diff --git a/ReceptionTrame_lib/receptionTrame_com.vhd b/ReceptionTrame_lib/receptionTrame_com.vhd
index dcfdbb8..a72fb93 100644
--- a/ReceptionTrame_lib/receptionTrame_com.vhd
+++ b/ReceptionTrame_lib/receptionTrame_com.vhd
@@ -32,7 +32,6 @@ ENTITY Command_Unit IS
     
     ErrorSet: OUT std_logic_vector(3 downto 1);
     MsgRcv_SET: OUT std_logic
-    DataNb_0: IN std_logic
   );
 END Command_Unit;
 
@@ -204,12 +203,9 @@ RCS : PROCESS(cState, LinSynchro, n_0)
 BEGIN
   BitNb_EN <= '0';
   nbData_EN <= '0';
-<<<<<<< HEAD
   RecByte_WR <= '0';
   MsgRcv_SET <= '0';
   
-=======
->>>>>>> refs/remotes/origin/master
   CASE cState IS
     WHEN waiting =>
       if(LinSynchro = '0') THEN
@@ -295,11 +291,7 @@ BEGIN
     WHEN syncFieldStop =>
       if(n_0 = '1') then
         if(LinSynchro = '1') then
-<<<<<<< HEAD
           RecByte_WR <= '1';
-=======
-          
->>>>>>> refs/remotes/origin/master
         else
           errs.ErrorStopBit <= '1';
         end if;
@@ -352,10 +344,7 @@ BEGIN
           nbData_LOAD <= '1';
           nbData_EN <= '1';
           IdentifierField_EN <= '1';
-<<<<<<< HEAD
           RecByte_WR <= '1';
-=======
->>>>>>> refs/remotes/origin/master
         else
           errs.ErrorStopBit <= '1';
         end if;