diff --git a/ReceptionTrame_lib/receptionTrame_com.vhd b/ReceptionTrame_lib/receptionTrame_com.vhd
index 05d6960..c2d5a6b 100644
--- a/ReceptionTrame_lib/receptionTrame_com.vhd
+++ b/ReceptionTrame_lib/receptionTrame_com.vhd
@@ -60,8 +60,8 @@ CASE cState IS
     END IF;
     
   WHEN syncBreak1 =>
-    if(LinSynchro = '0') THEN
-      if(n_0 = '1') THEN
+    if(n_0 = '1') THEN
+      if(LinSynchro = '1') THEN
         nState <= syncFieldWait;
       else
         nState <= waiting;
@@ -116,7 +116,7 @@ BEGIN
           n_LOAD <= '1';
           n_SELECT <= '0';
         else
-          -- ERROR sync
+          -- ERROR sync break
         end if;
       else
         if(n_0 = '1') then
@@ -130,6 +130,34 @@ BEGIN
         n_EN <= '1';
         nbBit_LOAD <= '0';
       end if;
+    WHEN syncBreak1 =>
+      if(n_0 = '1') then
+        if(LinSynchro = '0') then
+          -- ERROR sync stop
+        end if;
+      else
+        n_LOAD <= '0';
+        n_EN <= '1';
+      end if;
+    WHEN syncFieldWait =>
+      if(LinSynchro = '0') then
+          n_LOAD <= '1';
+          n_SELECT <= '1';
+      end if;
+    WHEN syncFieldStart =>
+      if(n_0 = '1') then
+        if(LinSynchro = '0') then
+          n_SELECT <= '0';
+          n_LOAD <= '1';
+          nbBit_SELECT <= '1';
+          nbBit_LOAD <= '1';
+        else
+          -- ERROR start bit
+        end if;
+      else
+        n_LOAD <= '0';
+        n_EN <= '1';
+      end if;
     WHEN others =>
       
   end CASE;
diff --git a/ReceptionTrame_lib/receptionTrame_tb.vhd b/ReceptionTrame_lib/receptionTrame_tb.vhd
index 2ff07f7..c226eb3 100644
--- a/ReceptionTrame_lib/receptionTrame_tb.vhd
+++ b/ReceptionTrame_lib/receptionTrame_tb.vhd
@@ -5,7 +5,7 @@ USE ieee.std_logic_arith.all;
 ENTITY receptionTrame_tb IS
   GENERIC(
     CLOCK_PERIOD: time := 52 us;
-    UC_CLK_PERIOD: time := 10 ns
+    UC_CLK_PERIOD: time := 40 ns
   );
 END receptionTrame_tb;