-- VHDL Entity RecepteurLIN_lib.decoder.interface
--
-- Created:
--          by - e208835u.UNKNOWN (irb121-06)
--          at - 16:35:13 19/09/2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2022.1 Built on 21 Jan 2022 at 13:00:30
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY decoder IS
   PORT( 
      RecByte          : IN     std_logic_vector (5 DOWNTO 4);
      DataFieldNb_INIT : OUT    std_logic_vector (2 DOWNTO 0)
   );

-- Declarations

END decoder ;

--
-- VHDL Architecture RecepteurLIN_lib.decoder.tbl
--
-- Created:
--          by - e208835u.UNKNOWN (irb121-06)
--          at - 16:41:56 19/09/2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2022.1 Built on 21 Jan 2022 at 13:00:30
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ARCHITECTURE tbl OF decoder IS
   
      -- Architecture declarations
    

BEGIN

   -----------------------------------------------------------------
   truth_process_proc: PROCESS(RecByte)
   -----------------------------------------------------------------
   BEGIN
      -- Block 1
      IF (RecByte(5 DOWNTO 4) = "00") THEN
         DataFieldNb_INIT <= "001";
      ELSIF (RecByte(5 DOWNTO 4) = "01") THEN
         DataFieldNb_INIT <= "001";
      ELSIF (RecByte(5 DOWNTO 4) = "10") THEN
         DataFieldNb_INIT <= "011";
      ELSIF (RecByte(5 DOWNTO 4) = "11") THEN
         DataFieldNb_INIT <= "111";
      END IF;

   END PROCESS truth_process_proc;

-- Architecture concurrent statements
 

END tbl;