-- VHDL Entity RecepteurLIN_lib.FrameReception_UnderTest.symbol
--
-- Created:
--          by - e208835U.UNKNOWN (irb121-02)
--          at - 11:35:03 26/09/2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2022.1 Built on 21 Jan 2022 at 13:00:30
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY FrameReception_UnderTest IS
-- Declarations

END FrameReception_UnderTest ;

--
-- VHDL Architecture RecepteurLIN_lib.FrameReception_UnderTest.struct
--
-- Created:
--          by - e208835u.UNKNOWN (irb013-09)
--          at - 10:39:28 10/10/2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2022.1 Built on 21 Jan 2022 at 13:00:30
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

-- LIBRARY LIN_Rec_Test_Env_2022_IP;
-- LIBRARY RecepteurLIN_lib;

ARCHITECTURE struct OF FrameReception_UnderTest IS

   -- Architecture declarations

   -- Internal signal declarations
   SIGNAL LIN        : std_logic;
   SIGNAL M_Received : std_logic;
   SIGNAL Master_Clk : std_logic;
   SIGNAL Reset_bar  : std_logic;


   -- Component Declarations
   COMPONENT LIN_Receiver_Env
   GENERIC (
      sur_ech : integer
   );
   PORT (
      M_Received : IN     std_logic;
      C_Dbar     : OUT    std_logic;
      Cs_bar     : OUT    std_logic;
      LIN        : OUT    std_logic;
      Master_Clk : OUT    std_logic;
      R_Wbar     : OUT    std_logic;
      Reset_bar  : OUT    std_logic;
      Data_Bus   : INOUT  std_logic_vector ( 7 DOWNTO 0 )
   );
   END COMPONENT;
   COMPONENT FrameReception
   PORT (
      H           : IN     std_logic ;
      Lin         : IN     std_logic ;
      nRST        : IN     std_logic ;
      RecByte     : OUT    std_logic_vector (7 DOWNTO 0);
      RecByte_RST : OUT    std_logic ;
      RecByte_WR  : OUT    std_logic 
   );
   END COMPONENT;

   -- Optional embedded configurations
   -- pragma synthesis_off
   -- FOR ALL : FrameReception USE ENTITY RecepteurLIN_lib.FrameReception;
   -- FOR ALL : LIN_Receiver_Env USE ENTITY LIN_Rec_Test_Env_2022_IP.LIN_Receiver_Env;
   -- pragma synthesis_on


BEGIN

   -- Instance port mappings.
   U_1 : LIN_Receiver_Env
      GENERIC MAP (
         sur_ech => 1024
      )
      PORT MAP (
         M_Received => M_Received,
         C_Dbar     => OPEN,
         Cs_bar     => OPEN,
         LIN        => LIN,
         Master_Clk => Master_Clk,
         R_Wbar     => OPEN,
         Reset_bar  => Reset_bar,
         Data_Bus   => OPEN
      );
   U_0 : FrameReception
      PORT MAP (
         H           => Master_Clk,
         Lin         => LIN,
         nRST        => Reset_bar,
         RecByte     => OPEN,
         RecByte_RST => OPEN,
         RecByte_WR  => OPEN
      );

END struct;