LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY D_FF_BANK IS
  PORT(
    H: IN std_logic;
    H_EN: IN std_logic;
    nRst : IN std_logic;
    D: IN std_logic_vector;
    Q: OUT std_logic_vector
  );
END D_FF_BANK;

ARCHITECTURE arch OF D_FF_BANK IS
COMPONENT D_FF
  PORT(
    H: IN std_logic;
    H_EN: IN std_logic;
    D: IN std_logic;
    nRst: IN std_logic;
    Q: OUT std_logic
  );
END COMPONENT;

BEGIN

bank_generate : for i in D'RANGE generate
  DFF_X : D_FF port map(
    H => H,
    H_EN => H_EN,
    D => D(i),
    nRst => nRst,
    Q => Q(i)
  );
end generate;

END ARCHITECTURE arch;