CAPI=2:
name: etn4:conceptionCircuit:recepteurLIN:1.0.0
description: A LIN receiver, ETN4 project

filesets:
  rtl:
    files:
      - recepteurlin_struct.vhd
      - internalstate_struct.vhd
    file_type: vhdlSource
    depend:
      - ETN4:conceptionCircuits:LIN_TB:1.0.0
      - ETN4:recepteurLIN:ReceptionTrame:1.0.0
      - ETN4:recepteurLIN:InterfaceMicroprocesseur:1.0.0

  tb:
    files:
      - recepteurlin_undertest_struct.vhd
    file_type: vhdlSource


targets:
  default: &default
    filesets:
      - rtl
    toplevel: RecepteurLIN
    parameters:

  sim:
    <<: *default
    description: Simulate the design
    default_tool: ghdl
    filesets_append:
      - tb
    toplevel: RecepteurLin_UnderTest
    tools:
      ghdl:
        analyze_options:
          - -fsynopsys
        run_options:
          - --wave=waveform.ghw --stop-time=25ms
    parameters:

  synth:
    <<: *default
    description: Synthesize the design
    default_tool: vivado
    filesets_append:
    tools:
      vivado:
        part: xc7a35tcpg236-1
        pnr: none
    parameters: