-- VHDL Entity RecepteurLIN_lib.FrameReception.symbol -- -- Created: -- by - e208835u.UNKNOWN (irb013-09) -- at - 12:46:30 17/10/2023 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2022.1 Built on 21 Jan 2022 at 13:00:30 -- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY FrameReception IS PORT( H : IN std_logic; Lin : IN std_logic; SelAdr : IN std_logic_vector (7 DOWNTO 0); nRST : IN std_logic; ErrorSet : OUT std_logic_vector (3 DOWNTO 1); MsgRcv_SET : OUT std_logic; NbRecByte_Inc : OUT std_logic; RecByte : OUT std_logic_vector (7 DOWNTO 0); RecByte_RST : OUT std_logic; RecByte_WR : OUT std_logic ); -- Declarations END FrameReception ; -- -- VHDL Architecture RecepteurLIN_lib.FrameReception.struct -- -- Created: -- by - e208835u.UNKNOWN (irb013-09) -- at - 12:46:30 17/10/2023 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2022.1 Built on 21 Jan 2022 at 13:00:30 -- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; -- LIBRARY RecepteurLIN_lib; ARCHITECTURE struct OF FrameReception IS -- Architecture declarations -- Internal signal declarations SIGNAL BitNb_EN : std_logic; SIGNAL BitNb_SELECT : std_logic; SIGNAL BitsNb_0 : std_logic; SIGNAL BitsNb_LOAD : std_logic; SIGNAL DataFieldNb : std_logic_vector(2 DOWNTO 0); SIGNAL DataFieldNb_0 : std_logic; SIGNAL DataFieldNb_LOAD : std_logic; SIGNAL IdentifierField : std_logic_vector(5 DOWNTO 0); SIGNAL LinSynchro : std_logic; SIGNAL dout : std_logic; SIGNAL identifier_EN : std_logic; SIGNAL n_0 : std_logic; SIGNAL n_EN : std_logic; SIGNAL n_LOAD : std_logic; SIGNAL n_SELECT : std_logic; SIGNAL nbData_EN : std_logic; SIGNAL octetRecu_EN : std_logic; SIGNAL RecByte_WR_int : std_logic; -- Component Declarations COMPONENT Command_Unit PORT ( BitNb_0 : IN std_logic; DataNb_0 : IN std_logic; H : IN std_logic; LinSynchro : IN std_logic; nRST : IN std_logic; n_0 : IN std_logic; BitNb_EN : OUT std_logic; BitNb_LOAD : OUT std_logic; BitNb_SELECT : OUT std_logic; ErrorSet : OUT std_logic_vector (3 DOWNTO 1); IdentifierField_EN : OUT std_logic; MsgRcv_SET : OUT std_logic; RecByte_RST : OUT std_logic := '0'; RecByte_WR : OUT std_logic; n_EN : OUT std_logic; n_LOAD : OUT std_logic; n_SELECT : OUT std_logic; nbData_EN : OUT std_logic; nbData_LOAD : OUT std_logic; octetRecu_EN : OUT std_logic ); END COMPONENT; COMPONENT FrameReceptionOP GENERIC ( N : std_logic_vector := "10000000000" ); PORT ( BitsNb_EN : IN std_logic ; BitsNb_LOAD : IN std_logic ; BitsNb_SELECT : IN std_logic ; DataFieldNb_EN : IN std_logic ; DataFieldNb_LOAD : IN std_logic ; H : IN std_logic ; IdentifierField_EN : IN std_logic ; Lin : IN std_logic ; RecByte_EN : IN std_logic ; nCLR : IN std_logic ; n_EN : IN std_logic ; n_LOAD : IN std_logic ; n_SELECT : IN std_logic ; BitsNb_0 : OUT std_logic ; DataFieldNb : OUT std_logic_vector (2 DOWNTO 0); DataFieldNb_0 : OUT std_logic ; IdentifierField : OUT std_logic_vector (5 DOWNTO 0); LinSynchro : OUT std_logic ; RecByte : OUT std_logic_vector (7 DOWNTO 0); n_0 : OUT std_logic ); END COMPONENT; -- Optional embedded configurations -- pragma synthesis_off -- FOR ALL : Command_Unit USE ENTITY RecepteurLIN_lib.Command_Unit; -- FOR ALL : FrameReceptionOP USE ENTITY RecepteurLIN_lib.FrameReceptionOP; -- pragma synthesis_on BEGIN NbRecByte_Inc <= RecByte_WR_int; RecByte_WR <= RecByte_WR_int; -- ModuleWare code(v1.12) for instance 'U_2' of 'pbuf' -- u_2seq_proc: PROCESS (octetRecu_EN) -- BEGIN -- IF (octetRecu_EN ='1' ) THEN -- NbRecByte_Inc <= '1'; -- ELSIF (octetRecu_EN ='H' ) THEN -- NbRecByte_Inc <= '1'; -- ELSIF (octetRecu_EN ='0' ) THEN -- NbRecByte_Inc <= '0'; -- ELSIF (octetRecu_EN ='L' ) THEN -- NbRecByte_Inc <= '0'; -- ELSIF (octetRecu_EN ='U' ) THEN -- NbRecByte_Inc <= 'U'; -- ELSIF (octetRecu_EN ='X' ) THEN -- NbRecByte_Inc <= 'X'; -- ELSIF (octetRecu_EN ='Z' ) THEN -- NbRecByte_Inc <= 'X'; -- END IF; -- END PROCESS u_2seq_proc; -- ModuleWare code(v1.12) for instance 'U_3' of 'pbuf' u_3seq_proc: PROCESS (octetRecu_EN) BEGIN IF (octetRecu_EN ='1' ) THEN dout <= '1'; ELSIF (octetRecu_EN ='H' ) THEN dout <= '1'; ELSIF (octetRecu_EN ='0' ) THEN dout <= '0'; ELSIF (octetRecu_EN ='L' ) THEN dout <= '0'; ELSIF (octetRecu_EN ='U' ) THEN dout <= 'U'; ELSIF (octetRecu_EN ='X' ) THEN dout <= 'X'; ELSIF (octetRecu_EN ='Z' ) THEN dout <= 'X'; END IF; END PROCESS u_3seq_proc; -- Instance port mappings. U_0 : Command_Unit PORT MAP ( H => H, nRST => nRST, LinSynchro => LinSynchro, octetRecu_EN => octetRecu_EN, n_SELECT => n_SELECT, n_LOAD => n_LOAD, n_EN => n_EN, BitNb_SELECT => BitNb_SELECT, BitNb_LOAD => BitsNb_LOAD, BitNb_EN => BitNb_EN, IdentifierField_EN => identifier_EN, nbData_LOAD => DataFieldNb_LOAD, nbData_EN => nbData_EN, n_0 => n_0, BitNb_0 => BitsNb_0, DataNb_0 => DataFieldNb_0, RecByte_WR => RecByte_WR_int, RecByte_RST => RecByte_RST, ErrorSet => ErrorSet, MsgRcv_SET => MsgRcv_SET ); U_1 : FrameReceptionOP GENERIC MAP ( N => "10000000000" ) PORT MAP ( BitsNb_EN => BitNb_EN, BitsNb_LOAD => BitsNb_LOAD, BitsNb_SELECT => BitNb_SELECT, DataFieldNb_EN => nbData_EN, DataFieldNb_LOAD => DataFieldNb_LOAD, H => H, IdentifierField_EN => identifier_EN, Lin => Lin, RecByte_EN => dout, nCLR => nRST, n_EN => n_EN, n_LOAD => n_LOAD, n_SELECT => n_SELECT, BitsNb_0 => BitsNb_0, DataFieldNb => DataFieldNb, DataFieldNb_0 => DataFieldNb_0, IdentifierField => IdentifierField, LinSynchro => LinSynchro, RecByte => RecByte, n_0 => n_0 ); END struct;