-- VHDL Entity RecepteurLIN_lib.FrameReceptionOP.symbol
--
-- Created:
--          by - e208835u.UNKNOWN (irb121-06)
--          at - 17:02:12 19/09/2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2022.1 Built on 21 Jan 2022 at 13:00:30
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY FrameReceptionOP IS
   GENERIC( 
      N : std_logic_vector := "10000000000"
   );
   PORT( 
      BitsNb_EN          : IN     std_logic;
      BitsNb_LOAD        : IN     std_logic;
      BitsNb_SELECT      : IN     std_logic;
      DataFieldNb_EN     : IN     std_logic;
      DataFieldNb_LOAD   : IN     std_logic;
      H                  : IN     std_logic;
      IdentifierField_EN : IN     std_logic;
      Lin                : IN     std_logic;
      RecByte_EN         : IN     std_logic;
      nCLR               : IN     std_logic;
      n_EN               : IN     std_logic;
      n_LOAD             : IN     std_logic;
      n_SELECT           : IN     std_logic;
      BitsNb_0           : OUT    std_logic;
      DataFieldNb        : OUT    std_logic_vector (2 DOWNTO 0);
      DataFieldNb_0      : OUT    std_logic;
      IdentifierField    : OUT    std_logic_vector (5 DOWNTO 0);
      LinSynchro         : OUT    std_logic;
      RecByte            : OUT    std_logic_vector (7 DOWNTO 0);
      n_0                : OUT    std_logic
   );

-- Declarations

END FrameReceptionOP ;

--
-- VHDL Architecture RecepteurLIN_lib.FrameReceptionOP.struct
--
-- Created:
--          by - e208835u.UNKNOWN (irb121-02)
--          at - 12:28:45 03/10/2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2022.1 Built on 21 Jan 2022 at 13:00:30
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

-- LIBRARY RecepteurLIN_lib;

ARCHITECTURE struct OF FrameReceptionOP IS

   -- Architecture declarations

   -- Internal signal declarations
   SIGNAL BitsNb           : std_logic_vector(3 DOWNTO 0);
   SIGNAL BitsNb_INIT      : std_logic_vector(3 DOWNTO 0);
   SIGNAL DataFieldNb_INIT : std_logic_vector(2 DOWNTO 0);
   SIGNAL dout             : std_logic;
   SIGNAL dout1            : std_logic_vector(3 DOWNTO 0);
   SIGNAL dout2            : std_logic_vector(3 DOWNTO 0);
   SIGNAL dout3            : std_logic_vector(10 DOWNTO 0);
   SIGNAL dout4            : std_logic_vector(10 DOWNTO 0);
   SIGNAL n_INIT           : std_logic_vector(10 DOWNTO 0);
   SIGNAL pas_n            : std_logic_vector(10 DOWNTO 0);

   -- Implicit buffer signal declarations
   SIGNAL LinSynchro_internal : std_logic;
   SIGNAL RecByte_internal    : std_logic_vector (7 DOWNTO 0);


   -- ModuleWare signal declarations(v1.12) for instance 'U_3' of 'cntr'
   SIGNAL mw_U_3n_cnt : std_logic_vector(10 DOWNTO 0);
   SIGNAL mw_U_3c_cnt : std_logic_vector(10 DOWNTO 0);

   -- ModuleWare signal declarations(v1.12) for instance 'U_7' of 'cntr'
   SIGNAL mw_U_7n_cnt : std_logic_vector(3 DOWNTO 0);
   SIGNAL mw_U_7c_cnt : std_logic_vector(3 DOWNTO 0);

   -- ModuleWare signal declarations(v1.12) for instance 'U_13' of 'cntr'
   SIGNAL mw_U_13n_cnt : std_logic_vector(2 DOWNTO 0);
   SIGNAL mw_U_13c_cnt : std_logic_vector(2 DOWNTO 0);

   -- ModuleWare signal declarations(v1.12) for instance 'U_0' of 'dff'
   SIGNAL mw_U_0reg_cval : std_logic;

   -- ModuleWare signal declarations(v1.12) for instance 'U_11' of 'dff'
   SIGNAL mw_U_11reg_cval : std_logic_vector(5 DOWNTO 0);

   -- ModuleWare signal declarations(v1.12) for instance 'U_1' of 'shiftsp'
   SIGNAL mw_U_1reg_cval : std_logic_vector(7 DOWNTO 0);
   SIGNAL mw_U_1reg_nval : std_logic_vector(7 DOWNTO 0);

   -- Component Declarations
   COMPONENT decoder
   PORT (
      RecByte          : IN     std_logic_vector (5 DOWNTO 4);
      DataFieldNb_INIT : OUT    std_logic_vector (2 DOWNTO 0)
   );
   END COMPONENT;

   -- Optional embedded configurations
   -- pragma synthesis_off
   -- FOR ALL : decoder USE ENTITY RecepteurLIN_lib.decoder;
   -- pragma synthesis_on


BEGIN

   -- ModuleWare code(v1.12) for instance 'U_3' of 'cntr'
   pas_n <= mw_U_3c_cnt;
   u_3clock_proc: PROCESS (H, nCLR)
   BEGIN
      IF (nCLR = '0') THEN
         mw_U_3c_cnt <= "00000000000";
      ELSIF (H'EVENT AND H='1') THEN
         IF (n_EN = '1') THEN
            mw_U_3c_cnt <= mw_U_3n_cnt;
         END IF;
      END IF;
   END PROCESS u_3clock_proc;
   u_3combo_proc: PROCESS (n_LOAD, n_INIT, mw_U_3c_cnt)
   BEGIN
      IF (n_LOAD = '1') THEN
         mw_U_3n_cnt <= n_INIT;
      ELSE
         IF (mw_U_3c_cnt = "00000000000") THEN
      mw_U_3n_cnt <= "11111111111";
         ELSE
            mw_U_3n_cnt <= (unsigned(mw_U_3c_cnt) - '1');
         END IF;
      END IF;
   END PROCESS u_3combo_proc;
   u_3max_drive_proc: PROCESS (mw_U_3c_cnt)
   BEGIN
      n_0 <= '0';
      IF (mw_U_3c_cnt = "00000000000") THEN
         n_0 <= '1';
      END IF;
   END PROCESS u_3max_drive_proc;

   -- ModuleWare code(v1.12) for instance 'U_7' of 'cntr'
   BitsNb <= mw_U_7c_cnt;
   u_7clock_proc: PROCESS (H, nCLR)
   BEGIN
      IF (nCLR = '0') THEN
         mw_U_7c_cnt <= "0000";
      ELSIF (H'EVENT AND H='1') THEN
         IF (BitsNb_EN = '1') THEN
            mw_U_7c_cnt <= mw_U_7n_cnt;
         END IF;
      END IF;
   END PROCESS u_7clock_proc;
   u_7combo_proc: PROCESS (BitsNb_LOAD, BitsNb_INIT, mw_U_7c_cnt)
   BEGIN
      IF (BitsNb_LOAD = '1') THEN
         mw_U_7n_cnt <= BitsNb_INIT;
      ELSE
         IF (mw_U_7c_cnt = "0000") THEN
      mw_U_7n_cnt <= "1111";
         ELSE
            mw_U_7n_cnt <= (unsigned(mw_U_7c_cnt) - '1');
         END IF;
      END IF;
   END PROCESS u_7combo_proc;
   u_7max_drive_proc: PROCESS (mw_U_7c_cnt)
   BEGIN
      BitsNb_0 <= '0';
      IF (mw_U_7c_cnt = "0000") THEN
         BitsNb_0 <= '1';
      END IF;
   END PROCESS u_7max_drive_proc;

   -- ModuleWare code(v1.12) for instance 'U_13' of 'cntr'
   DataFieldNb <= mw_U_13c_cnt;
   u_13clock_proc: PROCESS (H, nCLR)
   BEGIN
      IF (nCLR = '0') THEN
         mw_U_13c_cnt <= "000";
      ELSIF (H'EVENT AND H='1') THEN
         IF (DataFieldNb_EN = '1') THEN
            mw_U_13c_cnt <= mw_U_13n_cnt;
         END IF;
      END IF;
   END PROCESS u_13clock_proc;
   u_13combo_proc: PROCESS (DataFieldNb_LOAD, DataFieldNb_INIT, mw_U_13c_cnt)
   BEGIN
      IF (DataFieldNb_LOAD = '1') THEN
         mw_U_13n_cnt <= DataFieldNb_INIT;
      ELSE
         IF (mw_U_13c_cnt = "000") THEN
      mw_U_13n_cnt <= "111";
         ELSE
            mw_U_13n_cnt <= (unsigned(mw_U_13c_cnt) - '1');
         END IF;
      END IF;
   END PROCESS u_13combo_proc;
   u_13max_drive_proc: PROCESS (mw_U_13c_cnt)
   BEGIN
      DataFieldNb_0 <= '0';
      IF (mw_U_13c_cnt = "000") THEN
         DataFieldNb_0 <= '1';
      END IF;
   END PROCESS u_13max_drive_proc;

   -- ModuleWare code(v1.12) for instance 'U_5' of 'constval'
   dout4 <= "10000010001";

   -- ModuleWare code(v1.12) for instance 'U_6' of 'constval'
   dout3 <= "01000001001";

   -- ModuleWare code(v1.12) for instance 'U_9' of 'constval'
   dout2 <= "1100";

   -- ModuleWare code(v1.12) for instance 'U_10' of 'constval'
   dout1 <= "1000";

   -- ModuleWare code(v1.12) for instance 'U_0' of 'dff'
   LinSynchro_internal <= mw_U_0reg_cval;
   u_0seq_proc: PROCESS (H, nCLR)
   BEGIN
      IF (nCLR = '0') THEN
         mw_U_0reg_cval <= '0';
      ELSIF (H'EVENT AND H='1') THEN
         mw_U_0reg_cval <= Lin;
      END IF;
   END PROCESS u_0seq_proc;

   -- ModuleWare code(v1.12) for instance 'U_11' of 'dff'
   IdentifierField <= mw_U_11reg_cval;
   u_11seq_proc: PROCESS (H, nCLR)
   BEGIN
      IF (nCLR = '0') THEN
         mw_U_11reg_cval <= "000000";
      ELSIF (H'EVENT AND H='1') THEN
         IF (IdentifierField_EN = '1') THEN
            mw_U_11reg_cval <= RecByte_internal(5 DOWNTO 0);
         END IF;
      END IF;
   END PROCESS u_11seq_proc;

   -- ModuleWare code(v1.12) for instance 'U_2' of 'gnd'
   dout <= '0';

   -- ModuleWare code(v1.12) for instance 'U_4' of 'mux'
   u_4combo_proc: PROCESS(dout4, dout3, n_SELECT)
   BEGIN
      CASE n_SELECT IS
      WHEN '0' => n_INIT <= dout4;
      WHEN '1' => n_INIT <= dout3;
      WHEN OTHERS => n_INIT <= (OTHERS => 'X');
      END CASE;
   END PROCESS u_4combo_proc;

   -- ModuleWare code(v1.12) for instance 'U_8' of 'mux'
   u_8combo_proc: PROCESS(dout2, dout1, BitsNb_SELECT)
   BEGIN
      CASE BitsNb_SELECT IS
      WHEN '0' => BitsNb_INIT <= dout2;
      WHEN '1' => BitsNb_INIT <= dout1;
      WHEN OTHERS => BitsNb_INIT <= (OTHERS => 'X');
      END CASE;
   END PROCESS u_8combo_proc;

   -- ModuleWare code(v1.12) for instance 'U_1' of 'shiftsp'
   RecByte_internal <= mw_U_1reg_cval;
   u_1seq_proc: PROCESS (H, nCLR)
   BEGIN
      IF (nCLR = '0') THEN
         mw_U_1reg_cval <= "00000000";
      ELSIF (H'EVENT AND H='1') THEN
         IF (RecByte_EN = '1') THEN
            mw_U_1reg_cval <= mw_U_1reg_nval;
         END IF;
      END IF;
   END PROCESS u_1seq_proc;
   u_1combo_proc: PROCESS (dout, LinSynchro_internal, mw_U_1reg_cval)
   VARIABLE temp_dout : std_logic_vector(9 DOWNTO 0);
   BEGIN
      IF (dout = '0') THEN
         temp_dout := LinSynchro_internal & LinSynchro_internal & mw_U_1reg_cval;
      ELSIF (dout = '1') THEN
         temp_dout := mw_U_1reg_cval & LinSynchro_internal & LinSynchro_internal;
      ELSE
         temp_dout := (OTHERS => 'X');
      END IF;
   mw_U_1reg_nval <= temp_dout(8 DOWNTO 1);
   END PROCESS u_1combo_proc;

   -- Instance port mappings.
   U_12 : decoder
      PORT MAP (
         RecByte          => RecByte_internal(5 DOWNTO 4),
         DataFieldNb_INIT => DataFieldNb_INIT
      );

   -- Implicit buffered output assignments
   LinSynchro <= LinSynchro_internal;
   RecByte    <= RecByte_internal;

END struct;