-- VHDL generated by me

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY InterfaceMicroprocesseur_SousTest IS

END InterfaceMicroprocesseur_SousTest;

ARCHITECTURE struct OF InterfaceMicroprocesseur_SousTest IS
   SIGNAL D07        : std_logic_vector(7 DOWNTO 0);
   SIGNAL dout       : std_logic_vector(7 DOWNTO 0);
   SIGNAL dout1      : std_logic_vector(7 DOWNTO 0);
   SIGNAL H          : std_logic;
   SIGNAL CnD        : std_logic;
   SIGNAL M_Received : std_logic;
   SIGNAL RnW        : std_logic;
   SIGNAL nCS        : std_logic;
   SIGNAL nRST       : std_logic;

   COMPONENT EnvTest_InterfaceMicroprocesseur
     GENERIC (
        CLOCK_PERIOD   : time := 50 ns;
        RESET_OFFSET   : time := 500 ns;
        RESET_DURATION : time := 300 ns;
        ACCESS_TIME    : time := 40 ns;
        HOLD_TIME      : time := 70 ns
     );
     PORT (
        D07        : INOUT  std_logic_vector (7 DOWNTO 0);
        nRST       : OUT    std_logic;
        H          : OUT    std_logic;
        M_Received : IN     std_logic;
        CnD        : OUT    std_logic;
        RnW        : OUT    std_logic;
        nCS        : OUT    std_logic
     );
   END COMPONENT;

   COMPONENT InterfaceMicroprocesseur
     PORT (
        SelAdr     : OUT    std_logic_vector (7 DOWNTO 0);
        D07        : INOUT  std_logic_vector (7 DOWNTO 0);
        EtatLu     : IN     std_logic_vector (7 DOWNTO 0);
        OctetLu    : IN     std_logic_vector (7 DOWNTO 0);
        H          : IN     std_logic;
        nRST       : IN     std_logic;
        CnD        : IN     std_logic;
        RnW        : IN     std_logic;
        nCS        : IN     std_logic;
        DecNbOctet : OUT    std_logic;
        EtatLu_RST : OUT    std_logic;
        M_Received : OUT    std_logic;
        OctetLu_RD : OUT    std_logic
     );
   END COMPONENT;
BEGIN
  dout <= "00001000";
  dout1 <= "00001010";

  U_0 : EnvTest_InterfaceMicroprocesseur
    GENERIC MAP (
      CLOCK_PERIOD   => 50 ns,
      RESET_OFFSET   => 500 ns,
      RESET_DURATION => 300 ns,
      ACCESS_TIME    => 40 ns,
      HOLD_TIME      => 70 ns
    )
    PORT MAP (
      M_Received => M_Received,
      CnD        => CnD,
      H          => H,
      RnW        => RnW,
      nCS        => nCS,
      nRST       => nRST,
      D07        => D07
    );
  U_1 : InterfaceMicroprocesseur
    PORT MAP (
      CnD        => CnD,
      EtatLu     => dout1,
      H          => H,
      OctetLu    => dout,
      RnW        => RnW,
      nCS        => nCS,
      nRST       => nRST,
      DecNbOctet => OPEN,
      EtatLu_RST => OPEN,
      M_Received => M_Received,
      OctetLu_RD => OPEN,
      SelAdr     => OPEN,
      D07        => D07
    );

END struct;