-- VHDL Entity RecepteurLIN_lib.RecepteurLin_UnderTest.symbol
--
-- Created:
--          by - e208835u.UNKNOWN (irb013-09)
--          at - 10:50:04 10/10/2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2022.1 Built on 21 Jan 2022 at 13:00:30
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY RecepteurLin_UnderTest IS
-- Declarations

END RecepteurLin_UnderTest ;

--
-- VHDL Architecture RecepteurLIN_lib.RecepteurLin_UnderTest.struct
--
-- Created:
--          by - e208835u.UNKNOWN (irb013-09)
--          at - 10:39:26 17/10/2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2022.1 Built on 21 Jan 2022 at 13:00:30
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

-- LIBRARY LIN_Rec_Test_Env_2022_IP;
-- LIBRARY RecepteurLIN_lib;

ARCHITECTURE struct OF RecepteurLin_UnderTest IS

   -- Architecture declarations

   -- Internal signal declarations
   SIGNAL C_Dbar     : std_logic;
   SIGNAL Cs_bar     : std_logic;
   SIGNAL Data_Bus   : std_logic_vector( 7 DOWNTO 0 );
   SIGNAL LIN        : std_logic;
   SIGNAL M_Received : std_logic;
   SIGNAL Master_Clk : std_logic;
   SIGNAL R_Wbar     : std_logic;
   SIGNAL Reset_bar  : std_logic;


   -- Component Declarations
   COMPONENT LIN_Receiver_Env
   GENERIC (
      sur_ech : integer
   );
   PORT (
      M_Received : IN     std_logic;
      C_Dbar     : OUT    std_logic;
      Cs_bar     : OUT    std_logic;
      LIN        : OUT    std_logic;
      Master_Clk : OUT    std_logic;
      R_Wbar     : OUT    std_logic;
      Reset_bar  : OUT    std_logic;
      Data_Bus   : INOUT  std_logic_vector ( 7 DOWNTO 0 )
   );
   END COMPONENT;
   COMPONENT RecepteurLIN
   PORT (
      CnD        : IN     std_logic ;
      H          : IN     std_logic ;
      LIN        : IN     std_logic ;
      RnW        : IN     std_logic ;
      nCLR       : IN     std_logic ;
      nCS        : IN     std_logic ;
      M_Received : OUT    std_logic ;
      D07        : INOUT  std_logic_vector (7 DOWNTO 0)
   );
   END COMPONENT;

   -- Optional embedded configurations
   -- pragma synthesis_off
   -- FOR ALL : LIN_Receiver_Env USE ENTITY LIN_Rec_Test_Env_2022_IP.LIN_Receiver_Env;
   -- FOR ALL : RecepteurLIN USE ENTITY RecepteurLIN_lib.RecepteurLIN;
   -- pragma synthesis_on


BEGIN

   -- Instance port mappings.
   U_1 : LIN_Receiver_Env
      GENERIC MAP (
         sur_ech => 1024
      )
      PORT MAP (
         M_Received => M_Received,
         C_Dbar     => C_Dbar,
         Cs_bar     => Cs_bar,
         LIN        => LIN,
         Master_Clk => Master_Clk,
         R_Wbar     => R_Wbar,
         Reset_bar  => Reset_bar,
         Data_Bus   => Data_Bus
      );
   U_0 : RecepteurLIN
      PORT MAP (
         CnD        => C_Dbar,
         H          => Master_Clk,
         LIN        => LIN,
         RnW        => R_Wbar,
         nCLR       => Reset_bar,
         nCS        => Cs_bar,
         M_Received => M_Received,
         D07        => Data_Bus
      );

END struct;