LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY receptionTrame_tb IS
  GENERIC(
    CLOCK_PERIOD: time := 52 us;
    UC_CLK_PERIOD: time := 43 ns
  );
END receptionTrame_tb;

ARCHITECTURE arch of receptionTrame_tb IS
COMPONENT receptionTrame  
  PORT(
    H: IN std_logic;
    nCLR: IN std_logic;
    Lin: IN std_logic;

    AdrSel: IN std_logic_vector;

    RecByte: OUT std_logic_vector(7 downto 0);
    RecByte_WR: OUT std_logic;
    RecBytes_RST: OUT std_logic;

    Err_SET: OUT std_logic_vector(2 downto 0);
    NbByteInc: OUT std_logic;
    MsgReceived_SET: OUT std_logic;
    NbRecByte_RST: OUT std_logic
  );
END COMPONENT;

SIGNAL H: std_logic;
SIGNAL Lin: std_logic;

BEGIN

clkGen : PROCESS
BEGIN
  H <= '1';
  WAIT FOR UC_CLK_PERIOD / 2;
  H <= '0';
  WAIT FOR UC_CLK_PERIOD / 2;
END PROCESS clkGen;

linFrame : PROCESS
BEGIN
  Lin <= '1';
  WAIT FOR 100 us;
  -- Sync Break
  Lin <= '0';
  WAIT FOR 14 * CLOCK_PERIOD;
  Lin <= '1';
  WAIT FOR 2 * CLOCK_PERIOD;

  -- Sync field
  for i in 4 downto 0 loop
    Lin <= '0';
    WAIT FOR CLOCK_PERIOD;
    Lin <= '1';
    WAIT FOR CLOCK_PERIOD;
  end loop;

  -- ID field (0x0, 2 data byte)
  Lin <= '0';
  WAIT FOR CLOCK_PERIOD;
  Lin <= '0';
  WAIT FOR 8 * CLOCK_PERIOD;
  Lin <= '1';
  WAIT FOR CLOCK_PERIOD;

  -- data fields (both 0x00)
  Lin <= '0';
  WAIT FOR 9 * CLOCK_PERIOD;
  Lin <= '1';
  WAIT FOR CLOCK_PERIOD;

  Lin <= '0';
  WAIT FOR 9 * CLOCK_PERIOD;
  Lin <= '1';
  WAIT FOR CLOCK_PERIOD;

  -- checksum (0x0)
  Lin <= '0';
  WAIT FOR 9 * CLOCK_PERIOD;
  Lin <= '1';
  WAIT FOR CLOCK_PERIOD;

  report "Finished"  severity failure ;

END PROCESS;

U0 : receptionTrame
  PORT MAP(
    H => H,
    nCLR => '1',
    Lin => Lin,

    AdrSel => "000000",

    RecByte => OPEN,
    RecByte_WR => OPEN,
    RecBytes_RST => OPEN,

    Err_SET => OPEN,
    NbByteInc => OPEN,
    MsgReceived_SET => OPEN,
    NbRecByte_RST => OPEN
  );

END ARCHITECTURE arch;