LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- USE ieee.std_logic_arith.all;
USE ieee.numeric_std.all;

ENTITY receptionTrame_op IS
  GENERIC(
    N: integer := 1200;
    N_WIDTH : integer := 0
  );
  PORT(
    H: IN std_logic;
    nCLR: IN std_logic;
    Lin: IN std_logic;

    octetRecu_EN : IN std_logic;
    
    n_SELECT: IN std_logic;
    n_LOAD: IN std_logic;
    n_EN: IN std_logic;

    nbBit_SELECT: IN std_logic;
    nbBit_LOAD: IN std_logic;
    nbBit_EN: IN std_logic;

    identifier_EN: IN std_logic;

    nbData_LOAD: IN std_logic;
    nbData_EN: IN std_logic;

    LinSynchro: OUT std_logic;
    
    n_0: OUT std_logic;
    nbBit_0: OUT std_logic;
    nbData_0: OUT std_logic;

    identifier: OUT std_logic_vector(5 downto 0);
    octetRecu: OUT std_logic_vector(7 downto 0)
  );

END receptionTrame_op;

ARCHITECTURE arch OF receptionTrame_op IS
SIGNAL LinSynchro_int : std_logic;
SIGNAL octetRecu_int : std_logic_vector(7 downto 0);
SIGNAL nbDataField_INIT_int : integer := 0;
SIGNAL nbDataField_INIT : unsigned(2 downto 0);
SIGNAL n_INIT : unsigned(n_WIDTH - 1 downto 0);

COMPONENT D_FF
  PORT(
    H: IN std_logic;
    H_EN: IN std_logic;
    D: IN std_logic;
    nRst: IN std_logic;
    Q: OUT std_logic
  );
END COMPONENT;

COMPONENT D_FF_BANK IS
  PORT(
    H: IN std_logic;
    H_EN: IN std_logic;
    nRst : IN std_logic;
    D: IN std_logic_vector;
    Q: OUT std_logic_vector
  );
END COMPONENT;

COMPONENT shift_register
  GENERIC (
    WIDTH: integer
  );
  PORT(
    H: IN std_logic;
    H_EN: IN std_logic;
    nRst : IN std_logic;
    D: IN std_logic;
    Q: OUT std_logic_vector
  );
END COMPONENT;

COMPONENT counter
  GENERIC(
    WIDTH: integer;
    MAX_VAL: integer
  );
  PORT(
    H: IN std_logic;
    H_EN: IN std_logic;
    nRst: IN std_logic;
    INIT: IN unsigned(WIDTH-1 downto 0);
    LOAD: IN std_logic;
    upnDown: IN std_logic;

    val: OUT unsigned(WIDTH-1 downto 0);
    max: OUT std_logic
  );
END COMPONENT;
BEGIN

LinSynchro <= LinSynchro_int;
octetRecu <= octetRecu_int;

-- Lin sync D-FF, with asynchronous reset
Lin_in_sync : D_FF
  PORT MAP(
    H => H,
    H_EN => '1',
    D => Lin,
    nRst => nCLR,
    Q => LinSynchro_int
  );

-- Lin serial->parallel shift reg
Lin_para : shift_register
  GENERIC MAP(
    WIDTH => 8
  )
  PORT MAP(
    H => H,
    H_EN => octetRecu_EN,
    nRst => nCLR,
    D => LinSynchro_int,
    Q => octetRecu_int
  );

-- Decoder
WITH octetRecu_int(5 downto 4) SELECT
  nbDataField_INIT_int <= 
    1 when "00",
    1 when "01",
    3 when "10",
    7 when "11",
    0 when others;

nbDataField_INIT <= to_unsigned(nbDataField_INIT_int, 3);

-- nbDataField counter
nbDataField_cmp : counter
  GENERIC MAP(
    WIDTH => 3,
    MAX_VAL => 0
  )
  PORT MAP(
    H => H,
    H_EN => nbData_EN,
    nRst => nCLR,
    INIT => nbDataField_INIT,
    LOAD => nbData_LOAD,
    upnDown => '0',
    val => OPEN,
    max => nbData_0
  );

-- Identifier register
idReg : D_FF_BANK
  PORT MAP(
    H => H,
    H_EN => identifier_EN,
    nRst => nClr,
    D => octetRecu_int(5 downto 0),
    Q => identifier
  );

-- n_INIT mux
WITH n_SELECT SELECT
  n_INIT <= 
    to_unsigned(N - 1, N_WIDTH) when '0',
    to_unsigned(N / 2, N_WIDTH) when '1',
    (others => '0') when others;
  
END ARCHITECTURE arch;