LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY receptionTrame IS
  PORT(
    H: IN std_logic;
    nCLR: IN std_logic;
    Lin: IN std_logic
  );
END receptionTrame;

ARCHITECTURE arch OF receptionTrame IS
  COMPONENT receptionTrame_op
    GENERIC(
      N: integer := 1200;
      N_WIDTH : integer := 11
    );
    PORT(
      H: IN std_logic;
      nCLR: IN std_logic;
      Lin: IN std_logic;

      octetRecu_EN : IN std_logic;
    
      n_SELECT: IN std_logic;
      n_LOAD: IN std_logic;
      n_EN: IN std_logic;

      nbBit_SELECT: IN std_logic;
      nbBit_LOAD: IN std_logic;
      nbBit_EN: IN std_logic;

      identifier_EN: IN std_logic;

      nbData_LOAD: IN std_logic;
      nbData_EN: IN std_logic;

      LinSynchro: OUT std_logic;
    
      n_0: OUT std_logic;
      nbBit_0: OUT std_logic;
      nbData_0: OUT std_logic;

      identifier: OUT std_logic_vector(5 downto 0);
      octetRecu: OUT std_logic_vector(7 downto 0)
    );
  END COMPONENT;
BEGIN

END ARCHITECTURE arch;