LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY receptionTrame_op_tb IS
  GENERIC(
    CLOCK_PERIOD : time := 10 ns
  );
end receptionTrame_op_tb;

ARCHITECTURE arch OF receptionTrame_op_tb IS
SIGNAL H : std_logic;

COMPONENT receptionTrame_op
  GENERIC (
    N: integer
  );
  PORT (
    H: IN std_logic;
    nCLR: IN std_logic;
    Lin: IN std_logic;

    octetRecu_EN : IN std_logic;
    
    n_SELECT: IN std_logic;
    n_LOAD: IN std_logic;
    n_EN: IN std_logic;

    nbBit_SELECT: IN std_logic;
    nbBit_LOAD: IN std_logic;
    nbBit_EN: IN std_logic;

    identifier_EN: IN std_logic;

    nbData_LOAD: IN std_logic;
    nbData_EN: IN std_logic;

    LinSynchro: OUT std_logic;
    
    n_0: OUT std_logic;
    nbBit_0: OUT std_logic;
    nbData_0: OUT std_logic;

    identifier: OUT std_logic_vector(5 downto 0);
    octetRecu: OUT std_logic_vector(7 downto 0)
  );
  END COMPONENT;
BEGIN

CLK_gen : PROCESS
BEGIN
  H <= '0';
  WAIT FOR CLOCK_PERIOD/2;
  H <= '1';
  WAIT FOR CLOCK_PERIOD/2;
END PROCESS CLK_gen;

U0 : receptionTrame_op
  GENERIC MAP(
    N => 1200
  )
  PORT MAP(
    H => H,
    nCLR => '1',
    Lin => '1',
    octetRecu_EN => '1',
    n_SELECT => '0',
    n_LOAD => '1',
    n_EN => '1',
    nbBit_SELECT => '0',
    nbBit_LOAD => '1',
    nbBit_EN => '1',
    identifier_EN => '0',
    nbData_LOAD => '1',
    nbData_EN => '1'
  );
END ARCHITECTURE arch;