LIBRARY ieee;
USE ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;

ENTITY counter IS
  GENERIC(
    WIDTH: integer;
    MAX_VAL: integer
  );
  PORT(
    H: IN std_logic;
    H_EN: IN std_logic;
    nRst: IN std_logic;
    INIT: IN unsigned(WIDTH-1 downto 0);
    LOAD: IN std_logic;
    upnDown: IN std_logic;

    val: OUT unsigned(WIDTH-1 downto 0);
    max: OUT std_logic
  );
END counter;

ARCHITECTURE arch OF counter IS
SIGNAL cmp: unsigned(WIDTH-1 downto 0);
BEGIN

val <= cmp;
max <= '1' when cmp = MAX_VAL else '0';

main : PROCESS(H, nRst)
BEGIN
  if(nRst = '0') then
    cmp <= to_unsigned(0, WIDTH);
  elsif(rising_edge(H)) then
    if(LOAD = '1') then
      cmp <= INIT;
    elsif(H_EN = '1') then
      if(cmp /= MAX_VAL) then
        if(upnDown = '1') then
          cmp <= cmp + 1;
        else
          cmp <= cmp - 1;
        end if;
      end if;
    end if;
  end if;
END PROCESS main;

END ARCHITECTURE arch;