-- VHDL Entity Environnement_Test_lib.Testeur.symbol -- -- Created: -- by - lenours-s.None (LENOURS-S-PC) -- at - 08:38:40 10/03/16 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2013.1 (Build 6) -- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY Testeur IS -- Declarations END Testeur ; -- -- VHDL Architecture Environnement_Test_lib.Testeur.struct -- -- Created: -- by - lenours-s.None (LENOURS-S-PC) -- at - 08:39:56 10/03/16 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2013.1 (Build 6) -- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; -- LIBRARY Environnement_Test_lib; ARCHITECTURE struct OF Testeur IS -- Architecture declarations -- Internal signal declarations SIGNAL C_Dbar : std_logic; SIGNAL Cs_bar : std_logic; SIGNAL Data_Bus : std_logic_vector( 7 DOWNTO 0 ); SIGNAL LIN : std_logic; SIGNAL M_Received : std_logic; SIGNAL Master_Clk : std_logic; SIGNAL R_Wbar : std_logic; SIGNAL Reset_bar : std_logic; -- Component Declarations COMPONENT LIN_Receiver_Env GENERIC ( sur_ech : integer := 1024 ); PORT ( M_Received : IN std_logic; C_Dbar : OUT std_logic; Cs_bar : OUT std_logic; LIN : OUT std_logic; Master_Clk : OUT std_logic; R_Wbar : OUT std_logic; Reset_bar : OUT std_logic; Data_Bus : INOUT std_logic_vector ( 7 DOWNTO 0 ) ); END COMPONENT; -- Optional embedded configurations -- pragma synthesis_off FOR ALL : LIN_Receiver_Env USE ENTITY Environnement_Test_lib.LIN_Receiver_Env; -- pragma synthesis_on BEGIN -- Instance port mappings. U_0 : LIN_Receiver_Env GENERIC MAP ( sur_ech => 1024 ) PORT MAP ( M_Received => M_Received, C_Dbar => C_Dbar, Cs_bar => Cs_bar, LIN => LIN, Master_Clk => Master_Clk, R_Wbar => R_Wbar, Reset_bar => Reset_bar, Data_Bus => Data_Bus ); END struct;