LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY D_FF IS
  PORT(
    H: IN std_logic;
    D: IN std_logic;
    nRst: IN std_logic;
    Q: OUT std_logic
  );
END D_FF;
ARCHITECTURE arch of D_FF IS
BEGIN

dff: PROCESS(H, nRst)
BEGIN
  if(nRst = '0') THEN
    Q <= '0';
  ELSIF(rising_edge(H)) THEN
    Q <= D;
  END IF;
END PROCESS dff;

END ARCHITECTURE arch;