LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY stdlib_tb IS
  GENERIC(
    CLOCK_PERIOD : time := 10 ns
  );
END stdlib_tb;

ARCHITECTURE arch of stdlib_tb IS
SIGNAL CLK : std_logic;

SIGNAL D_FF_D : std_logic;
SIGNAL D_FF_Rst : std_logic;
SIGNAL D_FF_Q : std_logic;

SIGNAL D_FFb_D : std_logic_vector(7 downto 0);
SIGNAL D_FFb_Rst : std_logic;
SIGNAL D_FFb_Q : std_logic_vector(7 downto 0);

COMPONENT D_FF
  PORT(
    H: IN std_logic;
    D: IN std_logic;
    nRst: IN std_logic;
    Q: OUT std_logic
  );
END COMPONENT;

COMPONENT D_FF_BANK
  PORT(
    H: IN std_logic;
    D: IN std_logic_vector;
    nRst: IN std_logic;
    Q: OUT std_logic_vector
  );
END COMPONENT;

BEGIN

CLK_gen : PROCESS
BEGIN
  CLK <= '0';
  WAIT FOR CLOCK_PERIOD/2;
  CLK <= '1';
  WAIT FOR CLOCK_PERIOD/2;
END PROCESS CLK_gen;

D_FF_test : PROCESS
BEGIN
  D_FF_Rst <= '0';
  
  WAIT UNTIL CLK = '1';
  D_FF_Rst <= '1';
  D_FF_D <= '1';
  
  WAIT UNTIL CLK = '0';
  assert D_FF_Q = '0' report "D_FF set before clk" severity error;

  WAIT UNTIL CLK = '0';
  assert D_FF_Q = '1' report "D_FF not set" severity error;
  D_FF_Rst <= '0';
  
  WAIT UNTIL CLK = '0';
  assert D_FF_Q = '0' report "D_FF reset error" severity error;
END PROCESS D_FF_test;

D_FFb_test : PROCESS
BEGIN
  D_FFb_Rst <= '0';
  
  WAIT UNTIL CLK = '1';
  D_FFb_Rst <= '1';
  D_FFb_D <= "01010101";
  
  WAIT UNTIL CLK = '0';
  assert D_FFb_Q = "00000000" report "D_FF_bank set before clk" severity error;

  WAIT UNTIL CLK = '0';
  assert D_FFb_Q = "01010101" report "D_FF_bank not set" severity error;
  D_FFb_Rst <= '0';
  
  WAIT UNTIL CLK = '0';
  assert D_FFb_Q = "00000000" report "D_FF_bank reset error" severity error;
END PROCESS D_FFb_test;


U0 : D_FF
  PORT MAP (
    H => CLK,
    D => D_FF_D,
    nRst => D_FF_Rst,
    Q => D_FF_Q
  );

U1 : D_FF_BANK PORT MAP(
  H => CLK,
  D => D_FFb_D,
  nRst => D_FFb_Rst,
  Q => D_FFb_Q
);

END ARCHITECTURE arch;