LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY shift_register IS
  GENERIC(
    WIDTH: integer
  );
  PORT(
    H: IN std_logic;
    H_EN: IN std_logic;
    nRst : IN std_logic;
    D: IN std_logic;
    Q: OUT std_logic_vector
  );
END shift_register;

ARCHITECTURE arch of shift_register IS
SIGNAL data : std_logic_vector(WIDTH-1 downto 0) := (others => '0');
BEGIN

Q <= data;

sr: PROCESS(H, nRst)
BEGIN
  if(nRst = '0') THEN
    data <= (others => '0');
  ELSIF(rising_edge(H) and H_EN = '1') THEN
    data <= data(WIDTH-2 downto 0) & D;
  END IF;
END PROCESS sr;

END ARCHITECTURE arch;