-- VHDL Entity RecepteurLIN_lib.InterfaceMicroprocesseur_SousTest.symbol
--
-- Created:
--          by - e208835u.UNKNOWN (irb121-03)
--          at - 10:37:09 12/09/2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2022.1 Built on 21 Jan 2022 at 13:00:30
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY InterfaceMicroprocesseur_SousTest IS
-- Declarations

END InterfaceMicroprocesseur_SousTest ;

--
-- VHDL Architecture RecepteurLIN_lib.InterfaceMicroprocesseur_SousTest.struct
--
-- Created:
--          by - e208835u.UNKNOWN (irb121-03)
--          at - 10:59:28 12/09/2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2022.1 Built on 21 Jan 2022 at 13:00:30
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

-- LIBRARY RecepteurLIN_lib;

ARCHITECTURE struct OF InterfaceMicroprocesseur_SousTest IS

   -- Architecture declarations

   -- Internal signal declarations
   SIGNAL CnD        : std_logic;
   SIGNAL D07        : std_logic_vector(7 DOWNTO 0);
   SIGNAL H          : std_logic;
   SIGNAL M_Received : std_logic;
   SIGNAL RnW        : std_logic;
   SIGNAL dout       : std_logic_vector(7 DOWNTO 0);
   SIGNAL dout1      : std_logic_vector(7 DOWNTO 0);
   SIGNAL nCS        : std_logic;
   SIGNAL nRST       : std_logic;


   -- Component Declarations
   COMPONENT EnvTest_InterfaceMicroprocesseur
   GENERIC (
      CLOCK_PERIOD   : time := 50 ns;
      RESET_OFFSET   : time := 500 ns;
      RESET_DURATION : time := 300 ns;
      ACCESS_TIME    : time := 40 ns;
      HOLD_TIME      : time := 70 ns
   );
   PORT (
      M_Received : IN     std_logic ;
      CnD        : OUT    std_logic ;
      H          : OUT    std_logic ;
      RnW        : OUT    std_logic ;
      nCS        : OUT    std_logic ;
      nRST       : OUT    std_logic ;
      D07        : INOUT  std_logic_vector (7 DOWNTO 0)
   );
   END COMPONENT;
   COMPONENT InterfaceMicroprocesseur
   PORT (
      CnD        : IN     std_logic ;
      EtatLu     : IN     std_logic_vector (7 DOWNTO 0);
      H          : IN     std_logic ;
      OctetLu    : IN     std_logic_vector (7 DOWNTO 0);
      RnW        : IN     std_logic ;
      nCS        : IN     std_logic ;
      nRST       : IN     std_logic ;
      DecNbOctet : OUT    std_logic ;
      EtatLu_RST : OUT    std_logic ;
      M_Received : OUT    std_logic ;
      OctetLu_RD : OUT    std_logic ;
      SelAdr     : OUT    std_logic_vector (7 DOWNTO 0);
      D07        : INOUT  std_logic_vector (7 DOWNTO 0)
   );
   END COMPONENT;

   -- Optional embedded configurations
   -- pragma synthesis_off
   -- FOR ALL : EnvTest_InterfaceMicroprocesseur USE ENTITY RecepteurLIN_lib.EnvTest_InterfaceMicroprocesseur;
   -- FOR ALL : InterfaceMicroprocesseur USE ENTITY RecepteurLIN_lib.InterfaceMicroprocesseur;
   -- pragma synthesis_on


BEGIN

   -- ModuleWare code(v1.12) for instance 'U_2' of 'constval'
   dout <= "00001000";

   -- ModuleWare code(v1.12) for instance 'U_3' of 'constval'
   dout1 <= "00001010";

   -- Instance port mappings.
   U_0 : EnvTest_InterfaceMicroprocesseur
      GENERIC MAP (
         CLOCK_PERIOD   => 50 ns,
         RESET_OFFSET   => 500 ns,
         RESET_DURATION => 300 ns,
         ACCESS_TIME    => 40 ns,
         HOLD_TIME      => 70 ns
      )
      PORT MAP (
         M_Received => M_Received,
         CnD        => CnD,
         H          => H,
         RnW        => RnW,
         nCS        => nCS,
         nRST       => nRST,
         D07        => D07
      );
   U_1 : InterfaceMicroprocesseur
      PORT MAP (
         CnD        => CnD,
         EtatLu     => dout1,
         H          => H,
         OctetLu    => dout,
         RnW        => RnW,
         nCS        => nCS,
         nRST       => nRST,
         DecNbOctet => OPEN,
         EtatLu_RST => OPEN,
         M_Received => M_Received,
         OctetLu_RD => OPEN,
         SelAdr     => OPEN,
         D07        => D07
      );

END struct;