-- VHDL Entity RecepteurLIN_lib.RecepteurLIN.symbol -- -- Created: -- by - e208835u.UNKNOWN (irb013-09) -- at - 12:48:09 17/10/2023 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2022.1 Built on 21 Jan 2022 at 13:00:30 -- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY RecepteurLIN IS PORT( CnD : IN std_logic; H : IN std_logic; LIN : IN std_logic; RnW : IN std_logic; nCLR : IN std_logic; nCS : IN std_logic; M_Received : OUT std_logic; D07 : INOUT std_logic_vector (7 DOWNTO 0) ); -- Declarations END RecepteurLIN ; -- -- VHDL Architecture RecepteurLIN_lib.RecepteurLIN.struct -- -- Created: -- by - e208835u.UNKNOWN (irb013-09) -- at - 12:48:09 17/10/2023 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2022.1 Built on 21 Jan 2022 at 13:00:30 -- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; -- LIBRARY RecepteurLIN_lib; ARCHITECTURE struct OF RecepteurLIN IS -- Architecture declarations -- Internal signal declarations SIGNAL Errors_SET : std_logic_vector(3 DOWNTO 1); SIGNAL EtatLu : std_logic_vector(7 DOWNTO 0); SIGNAL EtatLu_RST : std_logic; SIGNAL MessageReceived_SET : std_logic; SIGNAL NbByteDec : std_logic; SIGNAL NbByteInc : std_logic; SIGNAL NbRecByte_RST : std_logic; SIGNAL RecByte : std_logic_vector(7 DOWNTO 0); SIGNAL RecByte_RST : std_logic; SIGNAL RecByte_WR : std_logic; SIGNAL SelAdr : std_logic_vector(7 DOWNTO 0); SIGNAL dout : std_logic; SIGNAL ffout : std_logic_vector(7 DOWNTO 0); SIGNAL rena : std_logic; -- ModuleWare signal declarations(v1.12) for instance 'U_1' of 'fifo' TYPE mw_U_1sreg IS ARRAY (11 DOWNTO 0) OF std_logic_vector(7 DOWNTO 0); SIGNAL mw_U_1addr_cval : INTEGER RANGE 0 TO 11; SIGNAL mw_U_1addr_nval : INTEGER RANGE 0 TO 11; SIGNAL mw_U_1reg_cval : mw_U_1sreg; SIGNAL mw_U_1reg_nval : mw_U_1sreg; -- Component Declarations COMPONENT FrameReception PORT ( H : IN std_logic ; Lin : IN std_logic ; SelAdr : IN std_logic_vector (7 DOWNTO 0); nRST : IN std_logic ; ErrorSet : OUT std_logic_vector (3 DOWNTO 1); MsgRcv_SET : OUT std_logic ; NbRecByte_Inc : OUT std_logic ; RecByte : OUT std_logic_vector (7 DOWNTO 0); RecByte_RST : OUT std_logic ; RecByte_WR : OUT std_logic ); END COMPONENT; COMPONENT InterfaceMicroprocesseur PORT ( CnD : IN std_logic ; EtatLu : IN std_logic_vector (7 DOWNTO 0); H : IN std_logic ; OctetLu : IN std_logic_vector (7 DOWNTO 0); RnW : IN std_logic ; nCS : IN std_logic ; nRST : IN std_logic ; DecNbOctet : OUT std_logic ; EtatLu_RST : OUT std_logic ; M_Received : OUT std_logic ; OctetLu_RD : OUT std_logic ; SelAdr : OUT std_logic_vector (7 DOWNTO 0); D07 : INOUT std_logic_vector (7 DOWNTO 0) ); END COMPONENT; COMPONENT InternalState PORT ( Errors_SET : IN std_logic_vector (3 DOWNTO 1); EtatLu_RST : IN std_logic ; H : IN std_logic ; MessageReceived_SET : IN std_logic ; NbByteDec : IN std_logic ; NbByteInc : IN std_logic ; NbRecByte_RST : IN std_logic ; nCLR : IN std_logic ; EtatLu : OUT std_logic_vector (7 DOWNTO 0) ); END COMPONENT; -- Optional embedded configurations -- pragma synthesis_off -- FOR ALL : FrameReception USE ENTITY RecepteurLIN_lib.FrameReception; -- FOR ALL : InterfaceMicroprocesseur USE ENTITY RecepteurLIN_lib.InterfaceMicroprocesseur; -- FOR ALL : InternalState USE ENTITY RecepteurLIN_lib.InternalState; -- pragma synthesis_on BEGIN -- ModuleWare code(v1.12) for instance 'U_1' of 'fifo' ffout <= mw_U_1reg_cval(0); u_1seq1_proc: PROCESS (H) BEGIN IF (H'EVENT AND H='1') THEN FOR i IN 0 TO 11 LOOP mw_U_1reg_cval(i)(7 DOWNTO 0) <= mw_U_1reg_nval(i)(7 DOWNTO 0); END LOOP; END IF; END PROCESS u_1seq1_proc; u_1seq2_proc: PROCESS (H, dout) BEGIN IF (dout = '1') THEN mw_U_1addr_cval <= 0; ELSIF (H'EVENT AND H='1') THEN mw_U_1addr_cval <= mw_U_1addr_nval; END IF; END PROCESS u_1seq2_proc; u_1combo_proc: PROCESS (dout, rena, RecByte_WR, mw_U_1addr_cval, mw_U_1reg_cval, RecByte) VARIABLE temp_rena : std_logic; VARIABLE temp_wena : std_logic; VARIABLE temp_full : std_logic; VARIABLE temp_empty : std_logic; BEGIN IF (mw_U_1addr_cval = 11) THEN temp_full := '1'; temp_empty := '0'; ELSIF (mw_U_1addr_cval = 0) THEN temp_full := '0'; temp_empty := '1'; ELSE temp_full := '0'; temp_empty := '0'; END IF; temp_rena := NOT(dout) AND rena AND NOT(temp_empty); temp_wena := NOT(dout) AND RecByte_WR AND NOT(temp_full); IF (temp_wena = '1') THEN mw_U_1addr_nval <= mw_U_1addr_cval + 1; ELSIF (temp_rena = '1') THEN mw_U_1addr_nval <= mw_U_1addr_cval - 1; ELSE mw_U_1addr_nval <= mw_U_1addr_cval; END IF; IF (temp_wena = '1') THEN mw_U_1reg_nval(0)(7 DOWNTO 0) <= mw_U_1reg_cval(0)(7 DOWNTO 0); FOR i IN 0 TO 10 LOOP IF (mw_U_1addr_cval = i) THEN mw_U_1reg_nval(i+1)(7 DOWNTO 0) <= RecByte; ELSE mw_U_1reg_nval(i+1)(7 DOWNTO 0) <= mw_U_1reg_cval(i+1)(7 DOWNTO 0); END IF; END LOOP; ELSIF (temp_wena = '0') THEN IF (temp_rena = '1') THEN FOR i IN 0 TO 10 LOOP mw_U_1reg_nval(i)(7 DOWNTO 0) <= mw_U_1reg_cval(i+1)(7 DOWNTO 0); END LOOP; mw_U_1reg_nval(11)(7 DOWNTO 0) <= mw_U_1reg_cval(11)(7 DOWNTO 0); ELSIF (temp_rena = '0') THEN FOR i IN 0 TO 11 LOOP mw_U_1reg_nval(i)(7 DOWNTO 0) <= mw_U_1reg_cval(i)(7 DOWNTO 0); END LOOP; ELSE FOR i IN 0 TO 11 LOOP mw_U_1reg_nval(i)(7 DOWNTO 0) <= (OTHERS => 'X'); END LOOP; END IF; ELSE FOR i IN 0 TO 11 LOOP mw_U_1reg_nval(i)(7 DOWNTO 0) <= (OTHERS => 'X'); END LOOP; END IF; END PROCESS u_1combo_proc; -- ModuleWare code(v1.12) for instance 'U_4' of 'pbuf' u_4seq_proc: PROCESS (RecByte_RST) BEGIN IF (RecByte_RST ='1' ) THEN dout <= '1'; ELSIF (RecByte_RST ='H' ) THEN dout <= '1'; ELSIF (RecByte_RST ='0' ) THEN dout <= '0'; ELSIF (RecByte_RST ='L' ) THEN dout <= '0'; ELSIF (RecByte_RST ='U' ) THEN dout <= 'U'; ELSIF (RecByte_RST ='X' ) THEN dout <= 'X'; ELSIF (RecByte_RST ='Z' ) THEN dout <= 'X'; END IF; END PROCESS u_4seq_proc; -- ModuleWare code(v1.12) for instance 'U_5' of 'pbuf' u_5seq_proc: PROCESS (RecByte_RST) BEGIN IF (RecByte_RST ='1' ) THEN NbRecByte_RST <= '1'; ELSIF (RecByte_RST ='H' ) THEN NbRecByte_RST <= '1'; ELSIF (RecByte_RST ='0' ) THEN NbRecByte_RST <= '0'; ELSIF (RecByte_RST ='L' ) THEN NbRecByte_RST <= '0'; ELSIF (RecByte_RST ='U' ) THEN NbRecByte_RST <= 'U'; ELSIF (RecByte_RST ='X' ) THEN NbRecByte_RST <= 'X'; ELSIF (RecByte_RST ='Z' ) THEN NbRecByte_RST <= 'X'; END IF; END PROCESS u_5seq_proc; -- Instance port mappings. U_2 : FrameReception PORT MAP ( H => H, Lin => LIN, SelAdr => SelAdr, nRST => nCLR, ErrorSet => Errors_SET, MsgRcv_SET => MessageReceived_SET, NbRecByte_Inc => NbByteInc, RecByte => RecByte, RecByte_RST => RecByte_RST, RecByte_WR => RecByte_WR ); U_0 : InterfaceMicroprocesseur PORT MAP ( CnD => CnD, EtatLu => EtatLu, H => H, OctetLu => ffout, RnW => RnW, nCS => nCS, nRST => nCLR, DecNbOctet => NbByteDec, EtatLu_RST => EtatLu_RST, M_Received => M_Received, OctetLu_RD => rena, SelAdr => SelAdr, D07 => D07 ); U_3 : InternalState PORT MAP ( Errors_SET => Errors_SET, EtatLu_RST => EtatLu_RST, H => H, MessageReceived_SET => MessageReceived_SET, NbByteDec => NbByteDec, NbByteInc => NbByteInc, NbRecByte_RST => NbRecByte_RST, nCLR => nCLR, EtatLu => EtatLu ); END struct;