### Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.

software_version_and_target_device
beta | FALSE | build_version | 2405991
date_generated | Tue Dec 7 12:44:52 2021 | os_platform | WIN64
product_version | Vivado v2018.3 (64-bit) | project_id | 5587c47a25864f30a941d919a4588f42
project_iteration | 43 | random_id | 5c5083d208095dd793a4532428ca92e6
registration_id | 5c5083d208095dd793a4532428ca92e6 | route_design | TRUE
target_device | xc7z010 | target_family | zynq
target_package | clg400 | target_speed | -1
tool_flow | Vivado

user_environment
cpu_name | Intel(R) Core(TM) i7-10700 CPU @ 2.90GHz | cpu_speed | 2904 MHz
os_name | Microsoft Windows 8 or later , 64-bit | os_release | major release (build 9200)
system_ram | 16.000 GB | total_processors | 1

vivado_usage

gui_handlers
abstractcombinedpanel_add_element=9 | abstractcombinedpanel_remove_selected_elements=2 | abstractfileview_close=1 | basedialog_cancel=45
basedialog_close=1 | basedialog_no=1 | basedialog_ok=396 | basedialog_yes=2
constraintschooserpanel_add_files=1 | coretreetablepanel_core_tree_table=18 | createsrcfiledialog_file_name=5 | definemodulesdialog_define_modules_and_specify_io_ports=95
filesetpanel_file_set_panel_tree=157 | flownavigatortreepanel_flow_navigator_tree=206 | fpgachooser_fpga_table=1 | gettingstartedview_create_new_project=1
hcodeeditor_blank_operations=17 | hcodeeditor_close=1 | hcodeeditor_commands_to_fold_text=2 | hcodeeditor_diff_with=8
hcodeeditor_search_text_combo_box=15 | hinputhandler_indent_selection=1 | hinputhandler_toggle_line_comments=37 | hinputhandler_unindent_selection=2
hpopuptitle_close=1 | logmonitor_monitor=3 | msgtreepanel_manage_suppression=1 | msgtreepanel_message_view_tree=79
msgview_clear_messages_resulting_from_user_executed=1 | msgview_critical_warnings=2 | msgview_error_messages=4 | msgview_information_messages=3
msgview_warning_messages=9 | numjobschooser_number_of_jobs=2 | pacommandnames_auto_connect_target=16 | pacommandnames_auto_update_hier=11
pacommandnames_goto_implemented_design=1 | pacommandnames_goto_netlist_design=1 | pacommandnames_log_window=1 | pacommandnames_open_hardware_manager=2
pacommandnames_recustomize_core=1 | pacommandnames_run_bitgen=42 | pacommandnames_run_implementation=8 | paviews_code=5
paviews_device=3 | paviews_ip_catalog=1 | paviews_project_summary=21 | paviews_schematic=9
programdebugtab_refresh_device=1 | programfpgadialog_program=45 | progressdialog_background=4 | progressdialog_cancel=5
projectnamechooser_project_name=1 | projecttab_reload=6 | rdicommands_delete=4 | rungadget_show_warning_and_error_messages_in_messages=2
saveprojectutils_dont_save=8 | saveprojectutils_save=5 | schematicview_previous=10 | simpleoutputproductdialog_generate_output_products_immediately=3
srcchooserpanel_add_hdl_and_netlist_files_to_your_project=1 | srcchooserpanel_add_or_create_source_file=1 | srcchooserpanel_create_file=6 | srcmenu_ip_documentation=5
srcmenu_ip_hierarchy=8 | stalerundialog_no=1 | syntheticagettingstartedview_recent_projects=4 | syntheticastatemonitor_cancel=5
taskbanner_close=16

java_command_handlers
addsources=6 | autoconnecttarget=16 | coreview=3 | customizecore=4
editdelete=4 | editpaste=2 | editundo=1 | launchprogramfpga=45
newproject=1 | openhardwaremanager=67 | openrecenttarget=21 | programdevice=45
recustomizecore=3 | runbitgen=45 | runimplementation=59 | runschematic=7
runsynthesis=92 | savefileproxyhandler=3 | showview=24 | viewtaskimplementation=8
viewtaskrtlanalysis=3 | viewtasksynthesis=2

other_data
guimode=5

project_data
constraintsetcount=1 | core_container=false | currentimplrun=impl_1 | currentsynthesisrun=synth_1
default_library=xil_defaultlib | designmode=RTL | export_simulation_activehdl=2 | export_simulation_ies=2
export_simulation_modelsim=2 | export_simulation_questa=2 | export_simulation_riviera=2 | export_simulation_vcs=2
export_simulation_xsim=2 | implstrategy=Vivado Implementation Defaults | launch_simulation_activehdl=0 | launch_simulation_ies=0
launch_simulation_modelsim=0 | launch_simulation_questa=0 | launch_simulation_riviera=0 | launch_simulation_vcs=0
launch_simulation_xsim=0 | simulator_language=VHDL | srcsetcount=8 | synthesisstrategy=Vivado Synthesis Defaults
target_language=VHDL | target_simulator=XSim | totalimplruns=1 | totalsynthesisruns=1

unisim_transformation

post_unisim_transformation
bufg=2 | carry4=34 | fdre=21 | gnd=2
ibuf=1 | lut1=4 | lut2=28 | lut3=7
lut4=62 | lut5=47 | lut6=65 | mmcme2_adv=1
obuf=18 | vcc=2

pre_unisim_transformation
bufg=2 | carry4=34 | fdre=21 | gnd=2
ibuf=1 | lut1=4 | lut2=28 | lut3=7
lut4=62 | lut5=47 | lut6=65 | mmcme2_adv=1
obuf=18 | vcc=2

ip_statistics

clk_wiz_v6_0_2_0_0/1
clkin1_period=8.000 | clkin2_period=10.000 | clock_mgr_type=NA | component_name=clk_wiz_1
core_container=NA | enable_axi=0 | feedback_source=FDBK_AUTO | feedback_type=SINGLE
iptotal=1 | manual_override=false | num_out_clk=1 | primitive=MMCM
use_dyn_phase_shift=false | use_dyn_reconfig=false | use_inclk_stopped=false | use_inclk_switchover=false
use_locked=false | use_max_i_jitter=false | use_min_o_jitter=false | use_phase_alignment=true
use_power_down=false | use_reset=false

report_drc

command_line_options
-append=default::[not_specified] | -checks=default::[not_specified] | -fail_on=default::[not_specified] | -force=default::[not_specified]
-format=default::[not_specified] | -internal=default::[not_specified] | -internal_only=default::[not_specified] | -messages=default::[not_specified]
-name=default::[not_specified] | -no_waivers=default::[not_specified] | -return_string=default::[not_specified] | -ruledecks=default::[not_specified]
-upgrade_cw=default::[not_specified] | -waived=default::[not_specified]

results
zps7-1=1

report_utilization

clocking
bufgctrl_available=32 | bufgctrl_fixed=0 | bufgctrl_used=2 | bufgctrl_util_percentage=6.25
bufhce_available=48 | bufhce_fixed=0 | bufhce_used=0 | bufhce_util_percentage=0.00
bufio_available=8 | bufio_fixed=0 | bufio_used=0 | bufio_util_percentage=0.00
bufmrce_available=4 | bufmrce_fixed=0 | bufmrce_used=0 | bufmrce_util_percentage=0.00
bufr_available=8 | bufr_fixed=0 | bufr_used=0 | bufr_util_percentage=0.00
mmcme2_adv_available=2 | mmcme2_adv_fixed=0 | mmcme2_adv_used=1 | mmcme2_adv_util_percentage=50.00
plle2_adv_available=2 | plle2_adv_fixed=0 | plle2_adv_used=0 | plle2_adv_util_percentage=0.00

dsp
dsps_available=80 | dsps_fixed=0 | dsps_used=0 | dsps_util_percentage=0.00

io_standard
blvds_25=0 | diff_hstl_i=0 | diff_hstl_i_18=0 | diff_hstl_ii=0
diff_hstl_ii_18=0 | diff_hsul_12=0 | diff_mobile_ddr=0 | diff_sstl135=0
diff_sstl135_r=0 | diff_sstl15=0 | diff_sstl15_r=0 | diff_sstl18_i=0
diff_sstl18_ii=0 | hstl_i=0 | hstl_i_18=0 | hstl_ii=0
hstl_ii_18=0 | hsul_12=0 | lvcmos12=0 | lvcmos15=0
lvcmos18=0 | lvcmos25=0 | lvcmos33=1 | lvds_25=0
lvttl=0 | mini_lvds_25=0 | mobile_ddr=0 | pci33_3=0
ppds_25=0 | rsds_25=0 | sstl135=0 | sstl135_r=0
sstl15=0 | sstl15_r=0 | sstl18_i=0 | sstl18_ii=0
tmds_33=0

memory
block_ram_tile_available=60 | block_ram_tile_fixed=0 | block_ram_tile_used=0 | block_ram_tile_util_percentage=0.00
ramb18_available=120 | ramb18_fixed=0 | ramb18_used=0 | ramb18_util_percentage=0.00
ramb36_fifo_available=60 | ramb36_fifo_fixed=0 | ramb36_fifo_used=0 | ramb36_fifo_util_percentage=0.00

primitives
bufg_functional_category=Clock | bufg_used=2 | carry4_functional_category=CarryLogic | carry4_used=34
fdre_functional_category=Flop & Latch | fdre_used=21 | ibuf_functional_category=IO | ibuf_used=1
lut1_functional_category=LUT | lut1_used=4 | lut2_functional_category=LUT | lut2_used=28
lut3_functional_category=LUT | lut3_used=7 | lut4_functional_category=LUT | lut4_used=64
lut5_functional_category=LUT | lut5_used=47 | lut6_functional_category=LUT | lut6_used=63
mmcme2_adv_functional_category=Clock | mmcme2_adv_used=1 | obuf_functional_category=IO | obuf_used=18

slice_logic
f7_muxes_available=8800 | f7_muxes_fixed=0 | f7_muxes_used=0 | f7_muxes_util_percentage=0.00
f8_muxes_available=4400 | f8_muxes_fixed=0 | f8_muxes_used=0 | f8_muxes_util_percentage=0.00
lut_as_logic_available=17600 | lut_as_logic_fixed=0 | lut_as_logic_used=168 | lut_as_logic_util_percentage=0.95
lut_as_memory_available=6000 | lut_as_memory_fixed=0 | lut_as_memory_used=0 | lut_as_memory_util_percentage=0.00
register_as_flip_flop_available=35200 | register_as_flip_flop_fixed=0 | register_as_flip_flop_used=21 | register_as_flip_flop_util_percentage=0.06
register_as_latch_available=35200 | register_as_latch_fixed=0 | register_as_latch_used=0 | register_as_latch_util_percentage=0.00
slice_luts_available=17600 | slice_luts_fixed=0 | slice_luts_used=168 | slice_luts_util_percentage=0.95
slice_registers_available=35200 | slice_registers_fixed=0 | slice_registers_used=21 | slice_registers_util_percentage=0.06
lut_as_distributed_ram_fixed=0 | lut_as_distributed_ram_used=0 | lut_as_logic_available=17600 | lut_as_logic_fixed=0
lut_as_logic_used=168 | lut_as_logic_util_percentage=0.95 | lut_as_memory_available=6000 | lut_as_memory_fixed=0
lut_as_memory_used=0 | lut_as_memory_util_percentage=0.00 | lut_as_shift_register_fixed=0 | lut_as_shift_register_used=0
lut_in_front_of_the_register_is_unused_fixed=0 | lut_in_front_of_the_register_is_unused_used=0 | lut_in_front_of_the_register_is_used_fixed=0 | lut_in_front_of_the_register_is_used_used=1
register_driven_from_outside_the_slice_fixed=1 | register_driven_from_outside_the_slice_used=1 | register_driven_from_within_the_slice_fixed=1 | register_driven_from_within_the_slice_used=20
slice_available=4400 | slice_fixed=0 | slice_registers_available=35200 | slice_registers_fixed=0
slice_registers_used=21 | slice_registers_util_percentage=0.06 | slice_used=61 | slice_util_percentage=1.39
slicel_fixed=0 | slicel_used=45 | slicem_fixed=0 | slicem_used=16
unique_control_sets_available=4400 | unique_control_sets_fixed=4400 | unique_control_sets_used=2 | unique_control_sets_util_percentage=0.05
using_o5_and_o6_fixed=0.05 | using_o5_and_o6_used=45 | using_o5_output_only_fixed=45 | using_o5_output_only_used=0
using_o6_output_only_fixed=0 | using_o6_output_only_used=123

specific_feature
bscane2_available=4 | bscane2_fixed=0 | bscane2_used=0 | bscane2_util_percentage=0.00
capturee2_available=1 | capturee2_fixed=0 | capturee2_used=0 | capturee2_util_percentage=0.00
dna_port_available=1 | dna_port_fixed=0 | dna_port_used=0 | dna_port_util_percentage=0.00
efuse_usr_available=1 | efuse_usr_fixed=0 | efuse_usr_used=0 | efuse_usr_util_percentage=0.00
frame_ecce2_available=1 | frame_ecce2_fixed=0 | frame_ecce2_used=0 | frame_ecce2_util_percentage=0.00
icape2_available=2 | icape2_fixed=0 | icape2_used=0 | icape2_util_percentage=0.00
startupe2_available=1 | startupe2_fixed=0 | startupe2_used=0 | startupe2_util_percentage=0.00
xadc_available=1 | xadc_fixed=0 | xadc_used=0 | xadc_util_percentage=0.00

synthesis

command_line_options
-assert=default::[not_specified] | -bufg=default::12 | -cascade_dsp=default::auto | -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto | -directive=default::default | -fanout_limit=default::10000 | -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto | -gated_clock_conversion=default::off | -generic=default::[not_specified] | -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] | -max_bram=default::-1 | -max_bram_cascade_height=default::-1 | -max_dsp=default::-1
-max_uram=default::-1 | -max_uram_cascade_height=default::-1 | -mode=default::default | -name=default::[not_specified]
-no_lc=default::[not_specified] | -no_srlextract=default::[not_specified] | -no_timing_driven=default::[not_specified] | -part=xc7z010clg400-1
-resource_sharing=default::auto | -retiming=default::[not_specified] | -rtl=default::[not_specified] | -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] | -seu_protect=default::none | -sfcu=default::[not_specified] | -shreg_min_size=default::3
-top=VGA_top | -verilog_define=default::[not_specified]

usage
elapsed=00:01:36s | hls_ip=0 | memory_gain=948.426MB | memory_peak=1310.512MB