#-----------------------------------------------------------
# Vivado v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec  6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec  7 01:43:56 MST 2018
# Start of session at: Tue Dec  7 12:30:30 2021
# Process ID: 4708
# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1
# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace
# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi
# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou
#-----------------------------------------------------------
source VGA_top.tcl -notrace
Command: link_design -top VGA_top -part xc7z010clg400-1
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Project 1-454] Reading design checkpoint 'c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.dcp' for cell 'U0'
INFO: [Netlist 29-17] Analyzing 11 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2018.3
INFO: [Device 21-403] Loading part xc7z010clg400-1
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst'
Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst'
Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst'
INFO: [Timing 38-35] Done setting XDC timing constraints. [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57]
INFO: [Timing 38-2] Deriving generated clocks [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57]
get_clocks: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1242.105 ; gain = 551.648
Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst'
Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc]
Finished Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1242.105 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:16 . Memory (MB): peak = 1242.105 ; gain = 878.844
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.511 . Memory (MB): peak = 1242.105 ; gain = 0.000

Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-2] Deriving generated clocks
Ending Cache Timing Information Task | Checksum: d2ac4cf6

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1259.926 ; gain = 17.820

Starting Logic Optimization Task

Phase 1 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 1f756781a

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1343.621 ; gain = 0.000
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 1 cells
INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 

Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 2 Constant propagation | Checksum: 1f756781a

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1343.621 ; gain = 0.000
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells

Phase 3 Sweep
Phase 3 Sweep | Checksum: 20f92b0fa

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 1343.621 ; gain = 0.000
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells

Phase 4 BUFG optimization
INFO: [Opt 31-194] Inserted BUFG U0/inst/clk_out1_clk_wiz_1_BUFG_inst to drive 0 load(s) on clock net U0/inst/clk_out1_clk_wiz_1_BUFG
INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets
Phase 4 BUFG optimization | Checksum: 19f2c89a4

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1343.621 ; gain = 0.000
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.

Phase 5 Shift Register Optimization
Phase 5 Shift Register Optimization | Checksum: 948878b4

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.036 . Memory (MB): peak = 1343.621 ; gain = 0.000
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells

Phase 6 Post Processing Netlist
Phase 6 Post Processing Netlist | Checksum: 10d0c29d4

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.037 . Memory (MB): peak = 1343.621 ; gain = 0.000
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Opt_design Change Summary
=========================


-------------------------------------------------------------------------------------------------------------------------
|  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
-------------------------------------------------------------------------------------------------------------------------
|  Retarget                     |               0  |               1  |                                              1  |
|  Constant propagation         |               0  |               0  |                                              0  |
|  Sweep                        |               0  |               0  |                                              0  |
|  BUFG optimization            |               0  |               0  |                                              0  |
|  Shift Register Optimization  |               0  |               0  |                                              0  |
|  Post Processing Netlist      |               0  |               0  |                                              0  |
-------------------------------------------------------------------------------------------------------------------------



Starting Connectivity Check Task

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1343.621 ; gain = 0.000
Ending Logic Optimization Task | Checksum: 1063f0394

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1343.621 ; gain = 0.000

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 1063f0394

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1343.621 ; gain = 0.000

Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 1063f0394

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1343.621 ; gain = 0.000

Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1343.621 ; gain = 0.000
Ending Netlist Obfuscation Task | Checksum: 1063f0394

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1343.621 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1343.621 ; gain = 0.000
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1343.621 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1343.621 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_opt.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx
Command: report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_opted.rpt.
report_drc completed successfully
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.

Starting Placer Task
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs

Phase 1 Placer Initialization

Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1343.621 ; gain = 0.000
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 73a34972

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1343.621 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1343.621 ; gain = 0.000

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1183e7dd3

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.259 . Memory (MB): peak = 1343.621 ; gain = 0.000

Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 1d9a96167

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.330 . Memory (MB): peak = 1343.621 ; gain = 0.000

Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 1d9a96167

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.331 . Memory (MB): peak = 1343.621 ; gain = 0.000
Phase 1 Placer Initialization | Checksum: 1d9a96167

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.331 . Memory (MB): peak = 1343.621 ; gain = 0.000

Phase 2 Global Placement

Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 207239471

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.384 . Memory (MB): peak = 1343.621 ; gain = 0.000

Phase 2.2 Physical Synthesis In Placer
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-670] No setup violation found.  DSP Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found.  Shift Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found.  BRAM Register Optimization was not performed.
INFO: [Physopt 32-949] No candidate nets found for HD net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1343.621 ; gain = 0.000

Summary of Physical Synthesis Optimizations
============================================


----------------------------------------------------------------------------------------------------------------------------------------
|  Optimization                  |  Added Cells  |  Removed Cells  |  Optimized Cells/Nets  |  Dont Touch  |  Iterations  |  Elapsed   |
----------------------------------------------------------------------------------------------------------------------------------------
|  Very High Fanout              |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  DSP Register                  |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  Shift Register                |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  BRAM Register                 |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  HD Interface Net Replication  |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Total                         |            0  |              0  |                     0  |           0  |           2  |  00:00:00  |
----------------------------------------------------------------------------------------------------------------------------------------


Phase 2.2 Physical Synthesis In Placer | Checksum: 1ec0f74d9

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1343.621 ; gain = 0.000
Phase 2 Global Placement | Checksum: 1db1d9ae8

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1343.621 ; gain = 0.000

Phase 3 Detail Placement

Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 1db1d9ae8

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1343.621 ; gain = 0.000

Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1b8be6344

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1343.621 ; gain = 0.000

Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 24618d2d2

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1343.621 ; gain = 0.000

Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 24618d2d2

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1343.621 ; gain = 0.000

Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: f3458c6a

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1343.621 ; gain = 0.000

Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: 1248ba3b4

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1343.621 ; gain = 0.000

Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: 1248ba3b4

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1343.621 ; gain = 0.000
Phase 3 Detail Placement | Checksum: 1248ba3b4

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1343.621 ; gain = 0.000

Phase 4 Post Placement Optimization and Clean-Up

Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.

Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 1635a43ad

Phase 4.1.1.1 BUFG Insertion
INFO: [Place 46-46] BUFG insertion identified 0 candidate nets, 0 success, 0 bufg driver replicated, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason
Phase 4.1.1.1 BUFG Insertion | Checksum: 1635a43ad

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1343.621 ; gain = 0.000
INFO: [Place 30-746] Post Placement Timing Summary WNS=36.020. For the most accurate timing information please run report_timing.
Phase 4.1.1 Post Placement Optimization | Checksum: 23bd24a0c

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1343.621 ; gain = 0.000
Phase 4.1 Post Commit Optimization | Checksum: 23bd24a0c

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1343.621 ; gain = 0.000

Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 23bd24a0c

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1343.621 ; gain = 0.000

Phase 4.3 Placer Reporting
Phase 4.3 Placer Reporting | Checksum: 23bd24a0c

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1343.621 ; gain = 0.000

Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1343.621 ; gain = 0.000
Phase 4.4 Final Placement Cleanup | Checksum: 219552bc9

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1343.621 ; gain = 0.000
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 219552bc9

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1343.621 ; gain = 0.000
Ending Placer Task | Checksum: 125980005

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1343.621 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
57 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1343.621 ; gain = 0.000
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.044 . Memory (MB): peak = 1343.621 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1343.621 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_placed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_io -file VGA_top_io_placed.rpt
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1343.621 ; gain = 0.000
INFO: [runtcl-4] Executing : report_utilization -file VGA_top_utilization_placed.rpt -pb VGA_top_utilization_placed.pb
INFO: [runtcl-4] Executing : report_control_sets -verbose -file VGA_top_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1343.621 ; gain = 0.000
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
Checksum: PlaceDB: af6487ab ConstDB: 0 ShapeSum: 7633785a RouteDB: 0

Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: c740a96f

Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1409.477 ; gain = 65.855
Post Restoration Checksum: NetGraph: 9566862e NumContArr: 31da2341 Constraints: 0 Timing: 0

Phase 2 Router Initialization

Phase 2.1 Create Timer
Phase 2.1 Create Timer | Checksum: c740a96f

Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1439.797 ; gain = 96.176

Phase 2.2 Fix Topology Constraints
Phase 2.2 Fix Topology Constraints | Checksum: c740a96f

Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1445.828 ; gain = 102.207

Phase 2.3 Pre Route Cleanup
Phase 2.3 Pre Route Cleanup | Checksum: c740a96f

Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1445.828 ; gain = 102.207
 Number of Nodes with overlaps = 0

Phase 2.4 Update Timing
Phase 2.4 Update Timing | Checksum: e75bf5ee

Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1448.480 ; gain = 104.859
INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.988 | TNS=0.000  | WHS=-0.304 | THS=-3.628 |

Phase 2 Router Initialization | Checksum: 43607781

Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1448.480 ; gain = 104.859

Phase 3 Initial Routing
Phase 3 Initial Routing | Checksum: 12c466190

Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1448.480 ; gain = 104.859

Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0
 Number of Nodes with overlaps = 10
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.445 | TNS=0.000  | WHS=N/A    | THS=N/A    |

Phase 4.1 Global Iteration 0 | Checksum: 210804e73

Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1448.480 ; gain = 104.859
Phase 4 Rip-up And Reroute | Checksum: 210804e73

Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1448.480 ; gain = 104.859

Phase 5 Delay and Skew Optimization

Phase 5.1 Delay CleanUp
Phase 5.1 Delay CleanUp | Checksum: 210804e73

Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1448.480 ; gain = 104.859

Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 210804e73

Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1448.480 ; gain = 104.859
Phase 5 Delay and Skew Optimization | Checksum: 210804e73

Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1448.480 ; gain = 104.859

Phase 6 Post Hold Fix

Phase 6.1 Hold Fix Iter

Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 14a89ec0d

Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1448.480 ; gain = 104.859
INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.560 | TNS=0.000  | WHS=0.076  | THS=0.000  |

Phase 6.1 Hold Fix Iter | Checksum: 14a89ec0d

Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1448.480 ; gain = 104.859
Phase 6 Post Hold Fix | Checksum: 14a89ec0d

Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1448.480 ; gain = 104.859

Phase 7 Route finalize

Router Utilization Summary
  Global Vertical Routing Utilization    = 0.0451858 %
  Global Horizontal Routing Utilization  = 0.0363051 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0

Phase 7 Route finalize | Checksum: 2224be1cd

Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1448.480 ; gain = 104.859

Phase 8 Verifying routed nets

 Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 2224be1cd

Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1450.207 ; gain = 106.586

Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 180a9d30f

Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1450.207 ; gain = 106.586

Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=35.560 | TNS=0.000  | WHS=0.076  | THS=0.000  |

INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 10 Post Router Timing | Checksum: 180a9d30f

Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1450.207 ; gain = 106.586
INFO: [Route 35-16] Router Completed Successfully

Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1450.207 ; gain = 106.586

Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
74 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:22 . Memory (MB): peak = 1450.207 ; gain = 106.586
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1450.207 ; gain = 0.000
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.045 . Memory (MB): peak = 1450.629 ; gain = 0.422
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1450.629 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_routed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx
Command: report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_routed.rpt.
report_drc completed successfully
INFO: [runtcl-4] Executing : report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx
Command: report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-133] Running Methodology with 2 threads
INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_methodology_drc_routed.rpt.
report_methodology completed successfully
INFO: [runtcl-4] Executing : report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx
Command: report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
86 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
INFO: [runtcl-4] Executing : report_route_status -file VGA_top_route_status.rpt -pb VGA_top_route_status.pb
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file VGA_top_timing_summary_routed.rpt -pb VGA_top_timing_summary_routed.pb -rpx VGA_top_timing_summary_routed.rpx -warn_on_violation 
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [runtcl-4] Executing : report_incremental_reuse -file VGA_top_incremental_reuse_routed.rpt
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
INFO: [runtcl-4] Executing : report_clock_utilization -file VGA_top_clock_utilization_routed.rpt
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file VGA_top_bus_skew_routed.rpt -pb VGA_top_bus_skew_routed.pb -rpx VGA_top_bus_skew_routed.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [Common 17-206] Exiting Vivado at Tue Dec  7 12:31:19 2021...
