Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec  6 23:38:27 MST 2018
| Date         : Tue Jan  4 12:21:22 2022
| Host         : irb121-12-w running 64-bit major release  (build 9200)
| Command      : report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx
| Design       : VGA_top
| Device       : xc7z010clg400-1
| Speed File   : -1
| Design State : Fully Routed
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Report DRC

Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS

1. REPORT SUMMARY
-----------------
            Netlist: netlist
          Floorplan: design_1
      Design limits: <entire design considered>
           Ruledeck: default
             Max violations: <unlimited>
             Violations found: 7
+----------+----------+--------------------+------------+
| Rule     | Severity | Description        | Violations |
+----------+----------+--------------------+------------+
| PDRC-153 | Warning  | Gated clock check  | 6          |
| ZPS7-1   | Warning  | PS7 block required | 1          |
+----------+----------+--------------------+------------+

2. REPORT DETAILS
-----------------
PDRC-153#1 Warning
Gated clock check  
Net UPD/dataOut_reg[18]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin UPD/dataOut_reg[18]_LDC_i_1/O, cell UPD/dataOut_reg[18]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
Related violations: <none>

PDRC-153#2 Warning
Gated clock check  
Net UPD/dataOut_reg[19]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin UPD/dataOut_reg[19]_LDC_i_1/O, cell UPD/dataOut_reg[19]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
Related violations: <none>

PDRC-153#3 Warning
Gated clock check  
Net UPD/dataOut_reg[1]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin UPD/dataOut_reg[1]_LDC_i_1/O, cell UPD/dataOut_reg[1]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
Related violations: <none>

PDRC-153#4 Warning
Gated clock check  
Net UPD/dataOut_reg[20]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin UPD/dataOut_reg[20]_LDC_i_1/O, cell UPD/dataOut_reg[20]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
Related violations: <none>

PDRC-153#5 Warning
Gated clock check  
Net UPD/dataOut_reg[21]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin UPD/dataOut_reg[21]_LDC_i_1/O, cell UPD/dataOut_reg[21]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
Related violations: <none>

PDRC-153#6 Warning
Gated clock check  
Net UPD/dataOut_reg[4]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin UPD/dataOut_reg[4]_LDC_i_1/O, cell UPD/dataOut_reg[4]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
Related violations: <none>

ZPS7-1#1 Warning
PS7 block required  
The PS7 cell must be used in this Zynq design in order to enable correct default configuration.
Related violations: <none>


