Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
| Date         : Tue Jan 11 11:43:30 2022
| Host         : LAPTOP-6KRNTV69 running 64-bit Ubuntu 20.04 LTS
| Command      : report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx
| Design       : VGA_top
| Device       : xc7z010clg400-1
| Speed File   : -1
| Design State : Fully Routed
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Report Methodology

Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS

1. REPORT SUMMARY
-----------------
            Netlist: netlist
          Floorplan: design_1
      Design limits: <entire design considered>
             Max violations: <unlimited>
             Violations found: 117
+-----------+------------------+--------------------------------------------+------------+
| Rule      | Severity         | Description                                | Violations |
+-----------+------------------+--------------------------------------------+------------+
| TIMING-17 | Critical Warning | Non-clocked sequential cell                | 1          |
| LUTAR-1   | Warning          | LUT drives async reset alert               | 5          |
| SYNTH-6   | Warning          | Timing of a RAM block might be sub-optimal | 27         |
| TIMING-16 | Warning          | Large setup violation                      | 75         |
| TIMING-18 | Warning          | Missing input or output delay              | 9          |
+-----------+------------------+--------------------------------------------+------------+

2. REPORT DETAILS
-----------------
TIMING-17#1 Critical Warning
Non-clocked sequential cell  
The clock pin UPD/isUpdating_reg/C is not reached by a timing clock
Related violations: <none>

LUTAR-1#1 Warning
LUT drives async reset alert  
LUT cell SNAKE/startUpdate_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) SNAKE/startUpdate_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
Related violations: <none>

LUTAR-1#2 Warning
LUT drives async reset alert  
LUT cell UPD/state[4]_i_3, with 2 or more inputs, drives asynchronous preset/clear pin(s) UPD/isUpdating_reg/CLR, UPD/state_reg[0]/CLR, UPD/state_reg[1]/CLR,
UPD/state_reg[2]/CLR, UPD/state_reg[3]/CLR, UPD/state_reg[4]/CLR,
UPD/updateIndex_reg[0]/CLR, UPD/updateIndex_reg[10]/CLR,
UPD/updateIndex_reg[1]/CLR, UPD/updateIndex_reg[2]/CLR,
UPD/updateIndex_reg[3]/CLR, UPD/updateIndex_reg[4]/CLR,
UPD/updateIndex_reg[5]/CLR, UPD/updateIndex_reg[6]/CLR,
UPD/updateIndex_reg[7]/CLR (the first 15 of 17 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
Related violations: <none>

LUTAR-1#3 Warning
LUT drives async reset alert  
LUT cell UPD/state_reg[3]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) APPLE/state_reg[0]_P/PRE, APPLE/state_reg[1]_P/PRE,
APPLE/state_reg[2]_P/PRE, APPLE/state_reg[3]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
Related violations: <none>

LUTAR-1#4 Warning
LUT drives async reset alert  
LUT cell UPD/state_reg[3]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) APPLE/state_reg[0]_C/CLR, APPLE/state_reg[1]_C/CLR,
APPLE/state_reg[2]_C/CLR, APPLE/state_reg[3]_C/CLR
APPLE/state_reg[3]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
Related violations: <none>

LUTAR-1#5 Warning
LUT drives async reset alert  
LUT cell UPD_CLK_DIV/temp[0]_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) UPD_CLK_DIV/temp_reg[0]/CLR, UPD_CLK_DIV/temp_reg[10]/CLR,
UPD_CLK_DIV/temp_reg[11]/CLR, UPD_CLK_DIV/temp_reg[12]/CLR,
UPD_CLK_DIV/temp_reg[13]/CLR, UPD_CLK_DIV/temp_reg[14]/CLR,
UPD_CLK_DIV/temp_reg[15]/CLR, UPD_CLK_DIV/temp_reg[16]/CLR,
UPD_CLK_DIV/temp_reg[17]/CLR, UPD_CLK_DIV/temp_reg[18]/CLR,
UPD_CLK_DIV/temp_reg[19]/CLR, UPD_CLK_DIV/temp_reg[1]/CLR,
UPD_CLK_DIV/temp_reg[20]/CLR, UPD_CLK_DIV/temp_reg[21]/CLR,
UPD_CLK_DIV/temp_reg[22]/CLR (the first 15 of 25 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
Related violations: <none>

SYNTH-6#1 Warning
Timing of a RAM block might be sub-optimal  
The timing for the instance RAMCTRL/MAT_RAM/mem_reg_1, implemented as a RAM block, might be sub-optimal as no output register was merged into the block.
Related violations: <none>

SYNTH-6#2 Warning
Timing of a RAM block might be sub-optimal  
The timing for the instance RAMCTRL/MAT_RAM/mem_reg_2, implemented as a RAM block, might be sub-optimal as no output register was merged into the block.
Related violations: <none>

SYNTH-6#3 Warning
Timing of a RAM block might be sub-optimal  
The timing for the instance RAMCTRL/MAT_RAM/mem_reg_3, implemented as a RAM block, might be sub-optimal as no output register was merged into the block.
Related violations: <none>

SYNTH-6#4 Warning
Timing of a RAM block might be sub-optimal  
The timing for the instance RAMCTRL/MAT_RAM/mem_reg_4, implemented as a RAM block, might be sub-optimal as no output register was merged into the block.
Related violations: <none>

SYNTH-6#5 Warning
Timing of a RAM block might be sub-optimal  
The timing for the instance RAMCTRL/MAT_RAM/mem_reg_5, implemented as a RAM block, might be sub-optimal as no output register was merged into the block.
Related violations: <none>

SYNTH-6#6 Warning
Timing of a RAM block might be sub-optimal  
The timing for the instance RAMCTRL/MAT_RAM/mem_reg_6, implemented as a RAM block, might be sub-optimal as no output register was merged into the block.
Related violations: <none>

SYNTH-6#7 Warning
Timing of a RAM block might be sub-optimal  
The timing for the instance RAMCTRL/MAT_RAM/mem_reg_7, implemented as a RAM block, might be sub-optimal as no output register was merged into the block.
Related violations: <none>

SYNTH-6#8 Warning
Timing of a RAM block might be sub-optimal  
The timing for the instance RAMCTRL/MAT_RAM/mem_reg_8, implemented as a RAM block, might be sub-optimal as no output register was merged into the block.
Related violations: <none>

SYNTH-6#9 Warning
Timing of a RAM block might be sub-optimal  
The timing for the instance RAMCTRL/MAT_RAM/mem_reg_9, implemented as a RAM block, might be sub-optimal as no output register was merged into the block.
Related violations: <none>

SYNTH-6#10 Warning
Timing of a RAM block might be sub-optimal  
The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_1_0, implemented as a RAM block, might be sub-optimal as no output register was merged into the block.
Related violations: <none>

SYNTH-6#11 Warning
Timing of a RAM block might be sub-optimal  
The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_1_1, implemented as a RAM block, might be sub-optimal as no output register was merged into the block.
Related violations: <none>

SYNTH-6#12 Warning
Timing of a RAM block might be sub-optimal  
The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_2_0, implemented as a RAM block, might be sub-optimal as no output register was merged into the block.
Related violations: <none>

SYNTH-6#13 Warning
Timing of a RAM block might be sub-optimal  
The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_2_1, implemented as a RAM block, might be sub-optimal as no output register was merged into the block.
Related violations: <none>

SYNTH-6#14 Warning
Timing of a RAM block might be sub-optimal  
The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_3_0, implemented as a RAM block, might be sub-optimal as no output register was merged into the block.
Related violations: <none>

SYNTH-6#15 Warning
Timing of a RAM block might be sub-optimal  
The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_3_1, implemented as a RAM block, might be sub-optimal as no output register was merged into the block.
Related violations: <none>

SYNTH-6#16 Warning
Timing of a RAM block might be sub-optimal  
The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_4_0, implemented as a RAM block, might be sub-optimal as no output register was merged into the block.
Related violations: <none>

SYNTH-6#17 Warning
Timing of a RAM block might be sub-optimal  
The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_4_1, implemented as a RAM block, might be sub-optimal as no output register was merged into the block.
Related violations: <none>

SYNTH-6#18 Warning
Timing of a RAM block might be sub-optimal  
The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_5_0, implemented as a RAM block, might be sub-optimal as no output register was merged into the block.
Related violations: <none>

SYNTH-6#19 Warning
Timing of a RAM block might be sub-optimal  
The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_5_1, implemented as a RAM block, might be sub-optimal as no output register was merged into the block.
Related violations: <none>

SYNTH-6#20 Warning
Timing of a RAM block might be sub-optimal  
The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_6_0, implemented as a RAM block, might be sub-optimal as no output register was merged into the block.
Related violations: <none>

SYNTH-6#21 Warning
Timing of a RAM block might be sub-optimal  
The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_6_1, implemented as a RAM block, might be sub-optimal as no output register was merged into the block.
Related violations: <none>

SYNTH-6#22 Warning
Timing of a RAM block might be sub-optimal  
The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_7_0, implemented as a RAM block, might be sub-optimal as no output register was merged into the block.
Related violations: <none>

SYNTH-6#23 Warning
Timing of a RAM block might be sub-optimal  
The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_7_1, implemented as a RAM block, might be sub-optimal as no output register was merged into the block.
Related violations: <none>

SYNTH-6#24 Warning
Timing of a RAM block might be sub-optimal  
The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_8_0, implemented as a RAM block, might be sub-optimal as no output register was merged into the block.
Related violations: <none>

SYNTH-6#25 Warning
Timing of a RAM block might be sub-optimal  
The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_8_1, implemented as a RAM block, might be sub-optimal as no output register was merged into the block.
Related violations: <none>

SYNTH-6#26 Warning
Timing of a RAM block might be sub-optimal  
The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_9_0, implemented as a RAM block, might be sub-optimal as no output register was merged into the block.
Related violations: <none>

SYNTH-6#27 Warning
Timing of a RAM block might be sub-optimal  
The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_9_1, implemented as a RAM block, might be sub-optimal as no output register was merged into the block.
Related violations: <none>

TIMING-16#1 Warning
Large setup violation  
There is a large setup violation of -1.182 ns between RAMCTRL/SNAKE_RAM/mem_reg_1_0/CLKARDCLK (clocked by sys_clk_pin) and UPD/state_reg[3]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#2 Warning
Large setup violation  
There is a large setup violation of -1.202 ns between APPLE/Xpos_reg[6]/C (clocked by sys_clk_pin) and APPLE/Ypos_reg[6]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#3 Warning
Large setup violation  
There is a large setup violation of -1.218 ns between APPLE/Xpos_reg[6]/C (clocked by sys_clk_pin) and APPLE/Ypos_reg[5]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#4 Warning
Large setup violation  
There is a large setup violation of -1.458 ns between RAMCTRL/SNAKE_RAM/mem_reg_9_1/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/snakeHere_reg/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#5 Warning
Large setup violation  
There is a large setup violation of -1.725 ns between RAMCTRL/SNAKE_RAM/mem_reg_1_0/CLKARDCLK (clocked by sys_clk_pin) and UPD/matAddress_reg[2]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#6 Warning
Large setup violation  
There is a large setup violation of -1.843 ns between RAMCTRL/SNAKE_RAM/mem_reg_1_0/CLKARDCLK (clocked by sys_clk_pin) and UPD/state_reg[1]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#7 Warning
Large setup violation  
There is a large setup violation of -1.934 ns between RAMCTRL/SNAKE_RAM/mem_reg_1_0/CLKARDCLK (clocked by sys_clk_pin) and UPD/matAddress_reg[3]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#8 Warning
Large setup violation  
There is a large setup violation of -2.259 ns between RAMCTRL/SNAKE_RAM/mem_reg_1_0/CLKARDCLK (clocked by sys_clk_pin) and UPD/matAddress_reg[4]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#9 Warning
Large setup violation  
There is a large setup violation of -2.279 ns between RAMCTRL/SNAKE_RAM/mem_reg_9_1/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[4]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#10 Warning
Large setup violation  
There is a large setup violation of -2.279 ns between RAMCTRL/SNAKE_RAM/mem_reg_9_1/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[5]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#11 Warning
Large setup violation  
There is a large setup violation of -2.279 ns between RAMCTRL/SNAKE_RAM/mem_reg_9_1/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[6]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#12 Warning
Large setup violation  
There is a large setup violation of -2.279 ns between RAMCTRL/SNAKE_RAM/mem_reg_9_1/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[7]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#13 Warning
Large setup violation  
There is a large setup violation of -2.311 ns between RAMCTRL/SNAKE_RAM/mem_reg_9_1/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[8]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#14 Warning
Large setup violation  
There is a large setup violation of -2.311 ns between RAMCTRL/SNAKE_RAM/mem_reg_9_1/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[9]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#15 Warning
Large setup violation  
There is a large setup violation of -2.323 ns between RAMCTRL/SNAKE_RAM/mem_reg_1_0/CLKARDCLK (clocked by sys_clk_pin) and UPD/dataOut_reg[4]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#16 Warning
Large setup violation  
There is a large setup violation of -2.362 ns between RAMCTRL/SNAKE_RAM/mem_reg_1_0/CLKARDCLK (clocked by sys_clk_pin) and UPD/dataOut_reg[21]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#17 Warning
Large setup violation  
There is a large setup violation of -2.362 ns between RAMCTRL/SNAKE_RAM/mem_reg_1_0/CLKARDCLK (clocked by sys_clk_pin) and UPD/dataOut_reg[22]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#18 Warning
Large setup violation  
There is a large setup violation of -2.375 ns between RAMCTRL/SNAKE_RAM/mem_reg_1_0/CLKARDCLK (clocked by sys_clk_pin) and UPD/dataOut_reg[8]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#19 Warning
Large setup violation  
There is a large setup violation of -2.375 ns between RAMCTRL/SNAKE_RAM/mem_reg_1_0/CLKARDCLK (clocked by sys_clk_pin) and UPD/state_reg[2]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#20 Warning
Large setup violation  
There is a large setup violation of -2.388 ns between RAMCTRL/SNAKE_RAM/mem_reg_1_0/CLKARDCLK (clocked by sys_clk_pin) and UPD/dataOut_reg[1]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#21 Warning
Large setup violation  
There is a large setup violation of -2.393 ns between RAMCTRL/SNAKE_RAM/mem_reg_1_0/CLKARDCLK (clocked by sys_clk_pin) and UPD/dataOut_reg[2]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#22 Warning
Large setup violation  
There is a large setup violation of -2.402 ns between RAMCTRL/SNAKE_RAM/mem_reg_1_0/CLKARDCLK (clocked by sys_clk_pin) and UPD/dataOut_reg[3]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#23 Warning
Large setup violation  
There is a large setup violation of -2.421 ns between RAMCTRL/SNAKE_RAM/mem_reg_9_1/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[0]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#24 Warning
Large setup violation  
There is a large setup violation of -2.421 ns between RAMCTRL/SNAKE_RAM/mem_reg_9_1/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[1]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#25 Warning
Large setup violation  
There is a large setup violation of -2.421 ns between RAMCTRL/SNAKE_RAM/mem_reg_9_1/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[2]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#26 Warning
Large setup violation  
There is a large setup violation of -2.421 ns between RAMCTRL/SNAKE_RAM/mem_reg_9_1/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[3]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#27 Warning
Large setup violation  
There is a large setup violation of -2.451 ns between RAMCTRL/SNAKE_RAM/mem_reg_1_0/CLKARDCLK (clocked by sys_clk_pin) and UPD/address_reg[10]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#28 Warning
Large setup violation  
There is a large setup violation of -2.451 ns between RAMCTRL/SNAKE_RAM/mem_reg_1_0/CLKARDCLK (clocked by sys_clk_pin) and UPD/address_reg[3]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#29 Warning
Large setup violation  
There is a large setup violation of -2.451 ns between RAMCTRL/SNAKE_RAM/mem_reg_1_0/CLKARDCLK (clocked by sys_clk_pin) and UPD/address_reg[6]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#30 Warning
Large setup violation  
There is a large setup violation of -2.488 ns between RAMCTRL/SNAKE_RAM/mem_reg_6_0/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[0]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#31 Warning
Large setup violation  
There is a large setup violation of -2.492 ns between RAMCTRL/SNAKE_RAM/mem_reg_1_0/CLKARDCLK (clocked by sys_clk_pin) and UPD/matAddress_reg[5]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#32 Warning
Large setup violation  
There is a large setup violation of -2.496 ns between RAMCTRL/SNAKE_RAM/mem_reg_1_0/CLKARDCLK (clocked by sys_clk_pin) and UPD/writeEnable_reg/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#33 Warning
Large setup violation  
There is a large setup violation of -2.511 ns between RAMCTRL/SNAKE_RAM/mem_reg_1_0/CLKARDCLK (clocked by sys_clk_pin) and UPD/dataOut_reg[18]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#34 Warning
Large setup violation  
There is a large setup violation of -2.511 ns between RAMCTRL/SNAKE_RAM/mem_reg_1_0/CLKARDCLK (clocked by sys_clk_pin) and UPD/dataOut_reg[19]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#35 Warning
Large setup violation  
There is a large setup violation of -2.511 ns between RAMCTRL/SNAKE_RAM/mem_reg_1_0/CLKARDCLK (clocked by sys_clk_pin) and UPD/dataOut_reg[20]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#36 Warning
Large setup violation  
There is a large setup violation of -2.524 ns between RAMCTRL/SNAKE_RAM/mem_reg_1_0/CLKARDCLK (clocked by sys_clk_pin) and UPD/dataOut_reg[7]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#37 Warning
Large setup violation  
There is a large setup violation of -2.576 ns between RAMCTRL/SNAKE_RAM/mem_reg_1_0/CLKARDCLK (clocked by sys_clk_pin) and UPD/address_reg[1]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#38 Warning
Large setup violation  
There is a large setup violation of -2.576 ns between RAMCTRL/SNAKE_RAM/mem_reg_1_0/CLKARDCLK (clocked by sys_clk_pin) and UPD/address_reg[8]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#39 Warning
Large setup violation  
There is a large setup violation of -2.576 ns between RAMCTRL/SNAKE_RAM/mem_reg_1_0/CLKARDCLK (clocked by sys_clk_pin) and UPD/address_reg[9]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#40 Warning
Large setup violation  
There is a large setup violation of -2.599 ns between RAMCTRL/SNAKE_RAM/mem_reg_1_0/CLKARDCLK (clocked by sys_clk_pin) and UPD/address_reg[2]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#41 Warning
Large setup violation  
There is a large setup violation of -2.611 ns between RAMCTRL/SNAKE_RAM/mem_reg_1_0/CLKARDCLK (clocked by sys_clk_pin) and UPD/dataOut_reg[14]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#42 Warning
Large setup violation  
There is a large setup violation of -2.639 ns between RAMCTRL/SNAKE_RAM/mem_reg_1_0/CLKARDCLK (clocked by sys_clk_pin) and UPD/address_reg[4]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#43 Warning
Large setup violation  
There is a large setup violation of -2.639 ns between RAMCTRL/SNAKE_RAM/mem_reg_1_0/CLKARDCLK (clocked by sys_clk_pin) and UPD/address_reg[5]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#44 Warning
Large setup violation  
There is a large setup violation of -2.641 ns between RAMCTRL/SNAKE_RAM/mem_reg_1_0/CLKARDCLK (clocked by sys_clk_pin) and UPD/matAddress_reg[8]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#45 Warning
Large setup violation  
There is a large setup violation of -2.648 ns between RAMCTRL/SNAKE_RAM/mem_reg_1_0/CLKARDCLK (clocked by sys_clk_pin) and UPD/dataOut_reg[10]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#46 Warning
Large setup violation  
There is a large setup violation of -2.648 ns between RAMCTRL/SNAKE_RAM/mem_reg_1_0/CLKARDCLK (clocked by sys_clk_pin) and UPD/matAddress_reg[6]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#47 Warning
Large setup violation  
There is a large setup violation of -2.658 ns between RAMCTRL/SNAKE_RAM/mem_reg_1_0/CLKARDCLK (clocked by sys_clk_pin) and UPD/dataOut_reg[17]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#48 Warning
Large setup violation  
There is a large setup violation of -2.658 ns between RAMCTRL/SNAKE_RAM/mem_reg_1_0/CLKARDCLK (clocked by sys_clk_pin) and UPD/matAddress_reg[7]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#49 Warning
Large setup violation  
There is a large setup violation of -2.664 ns between RAMCTRL/SNAKE_RAM/mem_reg_1_0/CLKARDCLK (clocked by sys_clk_pin) and UPD/dataOut_reg[9]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#50 Warning
Large setup violation  
There is a large setup violation of -2.673 ns between RAMCTRL/SNAKE_RAM/mem_reg_1_0/CLKARDCLK (clocked by sys_clk_pin) and UPD/dataOut_reg[15]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#51 Warning
Large setup violation  
There is a large setup violation of -2.673 ns between RAMCTRL/SNAKE_RAM/mem_reg_1_0/CLKARDCLK (clocked by sys_clk_pin) and UPD/dataOut_reg[2]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#52 Warning
Large setup violation  
There is a large setup violation of -2.673 ns between RAMCTRL/SNAKE_RAM/mem_reg_1_0/CLKARDCLK (clocked by sys_clk_pin) and UPD/dataOut_reg[5]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#53 Warning
Large setup violation  
There is a large setup violation of -2.673 ns between RAMCTRL/SNAKE_RAM/mem_reg_1_0/CLKARDCLK (clocked by sys_clk_pin) and UPD/dataOut_reg[6]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#54 Warning
Large setup violation  
There is a large setup violation of -2.675 ns between RAMCTRL/SNAKE_RAM/mem_reg_1_0/CLKARDCLK (clocked by sys_clk_pin) and UPD/dataOut_reg[16]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#55 Warning
Large setup violation  
There is a large setup violation of -2.679 ns between RAMCTRL/SNAKE_RAM/mem_reg_1_0/CLKARDCLK (clocked by sys_clk_pin) and UPD/dataOut_reg[1]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#56 Warning
Large setup violation  
There is a large setup violation of -2.679 ns between RAMCTRL/SNAKE_RAM/mem_reg_1_0/CLKARDCLK (clocked by sys_clk_pin) and UPD/dataOut_reg[3]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#57 Warning
Large setup violation  
There is a large setup violation of -2.679 ns between RAMCTRL/SNAKE_RAM/mem_reg_1_0/CLKARDCLK (clocked by sys_clk_pin) and UPD/dataOut_reg[4]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#58 Warning
Large setup violation  
There is a large setup violation of -2.704 ns between RAMCTRL/SNAKE_RAM/mem_reg_1_0/CLKARDCLK (clocked by sys_clk_pin) and UPD/dataOut_reg[12]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#59 Warning
Large setup violation  
There is a large setup violation of -2.719 ns between RAMCTRL/SNAKE_RAM/mem_reg_1_0/CLKARDCLK (clocked by sys_clk_pin) and UPD/matAddress_reg[9]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#60 Warning
Large setup violation  
There is a large setup violation of -2.724 ns between RAMCTRL/SNAKE_RAM/mem_reg_1_0/CLKARDCLK (clocked by sys_clk_pin) and UPD/matAddress_reg[10]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#61 Warning
Large setup violation  
There is a large setup violation of -2.736 ns between RAMCTRL/SNAKE_RAM/mem_reg_1_0/CLKARDCLK (clocked by sys_clk_pin) and UPD/address_reg[0]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#62 Warning
Large setup violation  
There is a large setup violation of -2.736 ns between RAMCTRL/SNAKE_RAM/mem_reg_1_0/CLKARDCLK (clocked by sys_clk_pin) and UPD/address_reg[7]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#63 Warning
Large setup violation  
There is a large setup violation of -2.749 ns between RAMCTRL/SNAKE_RAM/mem_reg_1_0/CLKARDCLK (clocked by sys_clk_pin) and UPD/dataOut_reg[11]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#64 Warning
Large setup violation  
There is a large setup violation of -2.749 ns between RAMCTRL/SNAKE_RAM/mem_reg_1_0/CLKARDCLK (clocked by sys_clk_pin) and UPD/dataOut_reg[13]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#65 Warning
Large setup violation  
There is a large setup violation of -2.775 ns between RAMCTRL/SNAKE_RAM/mem_reg_1_0/CLKARDCLK (clocked by sys_clk_pin) and UPD/dataOut_reg[0]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#66 Warning
Large setup violation  
There is a large setup violation of -2.777 ns between RAMCTRL/SNAKE_RAM/mem_reg_1_0/CLKARDCLK (clocked by sys_clk_pin) and UPD/dataOut_reg[23]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#67 Warning
Large setup violation  
There is a large setup violation of -2.784 ns between RAMCTRL/SNAKE_RAM/mem_reg_9_1/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[1]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#68 Warning
Large setup violation  
There is a large setup violation of -3.132 ns between RAMCTRL/SNAKE_RAM/mem_reg_9_1/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[2]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#69 Warning
Large setup violation  
There is a large setup violation of -3.197 ns between RAMCTRL/SNAKE_RAM/mem_reg_9_1/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[3]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#70 Warning
Large setup violation  
There is a large setup violation of -3.423 ns between RAMCTRL/SNAKE_RAM/mem_reg_4_0/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[4]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#71 Warning
Large setup violation  
There is a large setup violation of -3.516 ns between RAMCTRL/SNAKE_RAM/mem_reg_9_1/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[6]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#72 Warning
Large setup violation  
There is a large setup violation of -3.527 ns between RAMCTRL/SNAKE_RAM/mem_reg_4_0/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[5]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#73 Warning
Large setup violation  
There is a large setup violation of -3.921 ns between RAMCTRL/SNAKE_RAM/mem_reg_2_0/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[7]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#74 Warning
Large setup violation  
There is a large setup violation of -4.260 ns between RAMCTRL/SNAKE_RAM/mem_reg_2_0/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[8]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#75 Warning
Large setup violation  
There is a large setup violation of -4.368 ns between RAMCTRL/SNAKE_RAM/mem_reg_8_0/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[9]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-18#1 Warning
Missing input or output delay  
An input delay is missing on button_down relative to clock(s) sys_clk_pin
Related violations: <none>

TIMING-18#2 Warning
Missing input or output delay  
An input delay is missing on button_left relative to clock(s) sys_clk_pin
Related violations: <none>

TIMING-18#3 Warning
Missing input or output delay  
An input delay is missing on button_right relative to clock(s) sys_clk_pin
Related violations: <none>

TIMING-18#4 Warning
Missing input or output delay  
An input delay is missing on button_up relative to clock(s) sys_clk_pin
Related violations: <none>

TIMING-18#5 Warning
Missing input or output delay  
An input delay is missing on resetGeneral relative to clock(s) sys_clk_pin
Related violations: <none>

TIMING-18#6 Warning
Missing input or output delay  
An output delay is missing on led[0] relative to clock(s) sys_clk_pin
Related violations: <none>

TIMING-18#7 Warning
Missing input or output delay  
An output delay is missing on led[1] relative to clock(s) sys_clk_pin
Related violations: <none>

TIMING-18#8 Warning
Missing input or output delay  
An output delay is missing on led[2] relative to clock(s) sys_clk_pin
Related violations: <none>

TIMING-18#9 Warning
Missing input or output delay  
An output delay is missing on led[3] relative to clock(s) sys_clk_pin
Related violations: <none>


