# This file is automatically generated.
# It contains project source information necessary for synthesis and implementation.

# XDC: C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/ZYBO_Master.xdc

# IP: ip/clk_wiz_0_2/clk_wiz_0.xci
set_property DONT_TOUCH TRUE [get_cells -hier -filter {REF_NAME==clk_wiz_0 || ORIG_REF_NAME==clk_wiz_0} -quiet] -quiet
