Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
| Date         : Tue Jan 11 11:43:33 2022
| Host         : LAPTOP-6KRNTV69 running 64-bit Ubuntu 20.04 LTS
| Command      : report_timing_summary -max_paths 10 -file VGA_top_timing_summary_routed.rpt -pb VGA_top_timing_summary_routed.pb -rpx VGA_top_timing_summary_routed.rpx -warn_on_violation
| Design       : VGA_top
| Device       : 7z010-clg400
| Speed File   : -1  PRODUCTION 1.12 2019-11-22
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Timing Summary Report

------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

  Enable Multi Corner Analysis               :  Yes
  Enable Pessimism Removal                   :  Yes
  Pessimism Removal Resolution               :  Nearest Common Node
  Enable Input Delay Default Clock           :  No
  Enable Preset / Clear Arcs                 :  No
  Disable Flight Delays                      :  No
  Ignore I/O Paths                           :  No
  Timing Early Launch at Borrowing Latches   :  No
  Borrow Time for Max Delay Exceptions       :  Yes
  Merge Timing Exceptions                    :  Yes

  Corner  Analyze    Analyze    
  Name    Max Paths  Min Paths  
  ------  ---------  ---------  
  Slow    Yes        Yes        
  Fast    Yes        Yes        



check_timing report

Table of Contents
-----------------
1. checking no_clock (26)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (2)
5. checking no_input_delay (5)
6. checking no_output_delay (21)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)

1. checking no_clock (26)
-------------------------
 There is 1 register/latch pin with no clock driven by root clock pin: UPD/lost_reg/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: UPD_CLK_DIV/temp_reg[0]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: UPD_CLK_DIV/temp_reg[10]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: UPD_CLK_DIV/temp_reg[11]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: UPD_CLK_DIV/temp_reg[12]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: UPD_CLK_DIV/temp_reg[13]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: UPD_CLK_DIV/temp_reg[14]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: UPD_CLK_DIV/temp_reg[15]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: UPD_CLK_DIV/temp_reg[16]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: UPD_CLK_DIV/temp_reg[17]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: UPD_CLK_DIV/temp_reg[18]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: UPD_CLK_DIV/temp_reg[19]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: UPD_CLK_DIV/temp_reg[1]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: UPD_CLK_DIV/temp_reg[20]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: UPD_CLK_DIV/temp_reg[21]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: UPD_CLK_DIV/temp_reg[22]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: UPD_CLK_DIV/temp_reg[23]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: UPD_CLK_DIV/temp_reg[24]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: UPD_CLK_DIV/temp_reg[2]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: UPD_CLK_DIV/temp_reg[3]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: UPD_CLK_DIV/temp_reg[4]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: UPD_CLK_DIV/temp_reg[5]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: UPD_CLK_DIV/temp_reg[6]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: UPD_CLK_DIV/temp_reg[7]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: UPD_CLK_DIV/temp_reg[8]/Q (HIGH)

 There is 1 register/latch pin with no clock driven by root clock pin: UPD_CLK_DIV/temp_reg[9]/Q (HIGH)


2. checking constant_clock (0)
------------------------------
 There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock (0)
---------------------------------
 There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints (2)
------------------------------------------------
 There are 2 pins that are not constrained for maximum delay. (HIGH)

 There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay (5)
------------------------------
 There are 5 input ports with no input delay specified. (HIGH)

 There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay (21)
--------------------------------
 There are 21 ports with no output delay specified. (HIGH)

 There are 0 ports with no output delay but user has a false path constraint

 There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock (0)
------------------------------
 There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks (0)
--------------------------------
 There are 0 generated clocks that are not connected to a clock source.


9. checking loops (0)
---------------------
 There are 0 combinational loops in the design.


10. checking partial_input_delay (0)
------------------------------------
 There are 0 input ports with partial input delay specified.


11. checking partial_output_delay (0)
-------------------------------------
 There are 0 ports with partial output delay specified.


12. checking latch_loops (0)
----------------------------
 There are 0 combinational latch loops in the design through latch input



------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
     -4.368     -201.362                    103                 1629        0.086        0.000                      0                 1629        2.000        0.000                       0                   412  


Timing constraints are not met.


------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------

Clock                 Waveform(ns)         Period(ns)      Frequency(MHz)
-----                 ------------         ----------      --------------
sys_clk_pin           {0.000 4.000}        8.000           125.000         
  clk_out1_clk_wiz_0  {0.000 20.000}       40.000          25.000          
  clkfbout_clk_wiz_0  {0.000 20.000}       40.000          25.000          


------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock                     WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
-----                     -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
sys_clk_pin                -4.368     -201.362                    103                 1418        0.086        0.000                      0                 1418        2.000        0.000                       0                   328  
  clk_out1_clk_wiz_0       31.182        0.000                      0                  105        0.264        0.000                      0                  105       19.500        0.000                       0                    81  
  clkfbout_clk_wiz_0                                                                                                                                                   37.845        0.000                       0                     3  


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock          To Clock                WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------          --------                -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  
clk_out1_clk_wiz_0  sys_clk_pin              -4.144      -56.046                     21                   55        0.121        0.000                      0                   55  
sys_clk_pin         clk_out1_clk_wiz_0        1.409        0.000                      0                   37        0.091        0.000                      0                   37  


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group          From Clock          To Clock                WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------          ----------          --------                -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  
**async_default**   clk_out1_clk_wiz_0  clk_out1_clk_wiz_0       34.780        0.000                      0                   25        1.074        0.000                      0                   25  
**async_default**   sys_clk_pin         clk_out1_clk_wiz_0        1.294        0.000                      0                   26        0.537        0.000                      0                   26  
**async_default**   sys_clk_pin         sys_clk_pin               0.639        0.000                      0                   24        0.654        0.000                      0                   24  


------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------


---------------------------------------------------------------------------------------------------
From Clock:  sys_clk_pin
  To Clock:  sys_clk_pin

Setup :          103  Failing Endpoints,  Worst Slack       -4.368ns,  Total Violation     -201.362ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.086ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        2.000ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (VIOLATED) :        -4.368ns  (required time - arrival time)
  Source:                 RAMCTRL/SNAKE_RAM/mem_reg_8_0/CLKBWRCLK
                            (rising edge-triggered cell RAMB36E1 clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            SNAKE/ROMAddress_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             sys_clk_pin
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        12.246ns  (logic 5.434ns (44.375%)  route 6.812ns (55.625%))
  Logic Levels:           12  (CARRY4=3 LUT3=1 LUT5=2 LUT6=5 MUXF7=1)
  Clock Path Skew:        -0.196ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.897ns = ( 12.897 - 8.000 ) 
    Source Clock Delay      (SCD):    5.384ns
    Clock Pessimism Removal (CPR):    0.291ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491     1.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076     3.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101     3.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.715     5.384    RAMCTRL/SNAKE_RAM/H125MHz_IBUF_BUFG
    RAMB36_X1Y2          RAMB36E1                                     r  RAMCTRL/SNAKE_RAM/mem_reg_8_0/CLKBWRCLK
  -------------------------------------------------------------------    -------------------
    RAMB36_X1Y2          RAMB36E1 (Prop_ramb36e1_CLKBWRCLK_DOBDO[6])
                                                      2.454     7.838 r  RAMCTRL/SNAKE_RAM/mem_reg_8_0/DOBDO[6]
                         net (fo=11, routed)          1.563     9.401    SYNC/output_reg[1]_7[1]
    SLICE_X23Y21         LUT5 (Prop_lut5_I4_O)        0.124     9.525 r  SYNC/ROMAddress[3]_i_132/O
                         net (fo=1, routed)           0.000     9.525    SYNC/ROMAddress[3]_i_132_n_0
    SLICE_X23Y21         CARRY4 (Prop_carry4_S[1]_O[2])
                                                      0.580    10.105 r  SYNC/ROMAddress_reg[3]_i_52/O[2]
                         net (fo=5, routed)           0.833    10.939    RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_51_0[2]
    SLICE_X22Y22         LUT3 (Prop_lut3_I0_O)        0.332    11.271 r  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_124/O
                         net (fo=1, routed)           0.000    11.271    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_124_n_0
    SLICE_X22Y22         CARRY4 (Prop_carry4_DI[2]_O[3])
                                                      0.401    11.672 f  RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_51/O[3]
                         net (fo=2, routed)           0.591    12.263    RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_51_n_4
    SLICE_X23Y24         LUT6 (Prop_lut6_I5_O)        0.306    12.569 r  RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_80/O
                         net (fo=6, routed)           1.174    13.743    RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_80_n_0
    SLICE_X20Y28         LUT6 (Prop_lut6_I3_O)        0.124    13.867 r  RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_828/O
                         net (fo=1, routed)           0.000    13.867    RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_828_n_0
    SLICE_X20Y28         MUXF7 (Prop_muxf7_I1_O)      0.214    14.081 r  RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_657/O
                         net (fo=1, routed)           0.782    14.863    RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_657_n_0
    SLICE_X18Y32         LUT5 (Prop_lut5_I4_O)        0.297    15.160 f  RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_254/O
                         net (fo=1, routed)           0.754    15.914    RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_254_n_0
    SLICE_X11Y36         LUT6 (Prop_lut6_I5_O)        0.124    16.038 r  RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_70/O
                         net (fo=1, routed)           0.319    16.357    RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_70_n_0
    SLICE_X9Y36          LUT6 (Prop_lut6_I5_O)        0.124    16.481 r  RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_19/O
                         net (fo=1, routed)           0.794    17.275    RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_19_n_0
    SLICE_X8Y35          LUT6 (Prop_lut6_I3_O)        0.124    17.399 r  RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_5/O
                         net (fo=1, routed)           0.000    17.399    RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_5_n_0
    SLICE_X8Y35          CARRY4 (Prop_carry4_S[1]_O[1])
                                                      0.230    17.629 r  RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_2/O[1]
                         net (fo=1, routed)           0.000    17.629    SNAKE/D[9]
    SLICE_X8Y35          FDRE                                         r  SNAKE/ROMAddress_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      8.000     8.000 r  
    L16                                               0.000     8.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     8.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421     9.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    11.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    11.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.505    12.897    SNAKE/H125MHz_IBUF_BUFG
    SLICE_X8Y35          FDRE                                         r  SNAKE/ROMAddress_reg[9]/C
                         clock pessimism              0.291    13.188    
                         clock uncertainty           -0.035    13.152    
    SLICE_X8Y35          FDRE (Setup_fdre_C_D)        0.109    13.261    SNAKE/ROMAddress_reg[9]
  -------------------------------------------------------------------
                         required time                         13.261    
                         arrival time                         -17.629    
  -------------------------------------------------------------------
                         slack                                 -4.368    

Slack (VIOLATED) :        -4.260ns  (required time - arrival time)
  Source:                 RAMCTRL/SNAKE_RAM/mem_reg_2_0/CLKBWRCLK
                            (rising edge-triggered cell RAMB36E1 clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            SNAKE/ROMAddress_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             sys_clk_pin
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        12.148ns  (logic 5.537ns (45.578%)  route 6.611ns (54.422%))
  Logic Levels:           12  (CARRY4=5 LUT4=1 LUT5=3 LUT6=3)
  Clock Path Skew:        -0.185ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.897ns = ( 12.897 - 8.000 ) 
    Source Clock Delay      (SCD):    5.373ns
    Clock Pessimism Removal (CPR):    0.291ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491     1.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076     3.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101     3.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.704     5.373    RAMCTRL/SNAKE_RAM/H125MHz_IBUF_BUFG
    RAMB36_X1Y4          RAMB36E1                                     r  RAMCTRL/SNAKE_RAM/mem_reg_2_0/CLKBWRCLK
  -------------------------------------------------------------------    -------------------
    RAMB36_X1Y4          RAMB36E1 (Prop_ramb36e1_CLKBWRCLK_DOBDO[6])
                                                      2.454     7.827 r  RAMCTRL/SNAKE_RAM/mem_reg_2_0/DOBDO[6]
                         net (fo=11, routed)          1.312     9.138    SYNC/output_reg[7]_0[1]
    SLICE_X19Y22         LUT5 (Prop_lut5_I4_O)        0.124     9.262 r  SYNC/ROMAddress[3]_i_194/O
                         net (fo=1, routed)           0.000     9.262    SYNC/ROMAddress[3]_i_194_n_0
    SLICE_X19Y22         CARRY4 (Prop_carry4_S[1]_O[3])
                                                      0.640     9.902 r  SYNC/ROMAddress_reg[3]_i_77/O[3]
                         net (fo=5, routed)           0.970    10.873    RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_147_0[3]
    SLICE_X19Y25         LUT4 (Prop_lut4_I1_O)        0.306    11.179 r  RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_228/O
                         net (fo=1, routed)           0.000    11.179    RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_228_n_0
    SLICE_X19Y25         CARRY4 (Prop_carry4_S[3]_CO[3])
                                                      0.401    11.580 r  RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_147/CO[3]
                         net (fo=1, routed)           0.000    11.580    RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_147_n_0
    SLICE_X19Y26         CARRY4 (Prop_carry4_CI_O[0])
                                                      0.222    11.802 f  RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_202/O[0]
                         net (fo=5, routed)           1.496    13.298    RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_202_n_7
    SLICE_X5Y29          LUT5 (Prop_lut5_I4_O)        0.299    13.597 r  RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_201_comp/O
                         net (fo=1, routed)           0.660    14.257    RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_201_n_0
    SLICE_X4Y30          LUT6 (Prop_lut6_I4_O)        0.124    14.381 r  RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_51_comp_1/O
                         net (fo=1, routed)           1.090    15.471    RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_51_n_0
    SLICE_X7Y35          LUT6 (Prop_lut6_I2_O)        0.124    15.595 r  RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_14/O
                         net (fo=3, routed)           0.419    16.013    RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_14_n_0
    SLICE_X9Y34          LUT6 (Prop_lut6_I0_O)        0.124    16.137 r  RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_22/O
                         net (fo=1, routed)           0.665    16.802    RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_22_n_0
    SLICE_X8Y34          LUT5 (Prop_lut5_I3_O)        0.124    16.926 r  RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_6/O
                         net (fo=1, routed)           0.000    16.926    RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_6_n_0
    SLICE_X8Y34          CARRY4 (Prop_carry4_S[3]_CO[3])
                                                      0.376    17.302 r  RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_1/CO[3]
                         net (fo=1, routed)           0.000    17.302    RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_1_n_0
    SLICE_X8Y35          CARRY4 (Prop_carry4_CI_O[0])
                                                      0.219    17.521 r  RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_2/O[0]
                         net (fo=1, routed)           0.000    17.521    SNAKE/D[8]
    SLICE_X8Y35          FDRE                                         r  SNAKE/ROMAddress_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      8.000     8.000 r  
    L16                                               0.000     8.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     8.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421     9.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    11.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    11.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.505    12.897    SNAKE/H125MHz_IBUF_BUFG
    SLICE_X8Y35          FDRE                                         r  SNAKE/ROMAddress_reg[8]/C
                         clock pessimism              0.291    13.188    
                         clock uncertainty           -0.035    13.152    
    SLICE_X8Y35          FDRE (Setup_fdre_C_D)        0.109    13.261    SNAKE/ROMAddress_reg[8]
  -------------------------------------------------------------------
                         required time                         13.261    
                         arrival time                         -17.521    
  -------------------------------------------------------------------
                         slack                                 -4.260    

Slack (VIOLATED) :        -3.921ns  (required time - arrival time)
  Source:                 RAMCTRL/SNAKE_RAM/mem_reg_2_0/CLKBWRCLK
                            (rising edge-triggered cell RAMB36E1 clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            SNAKE/ROMAddress_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             sys_clk_pin
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        11.808ns  (logic 5.197ns (44.011%)  route 6.611ns (55.989%))
  Logic Levels:           11  (CARRY4=4 LUT4=1 LUT5=3 LUT6=3)
  Clock Path Skew:        -0.186ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.896ns = ( 12.896 - 8.000 ) 
    Source Clock Delay      (SCD):    5.373ns
    Clock Pessimism Removal (CPR):    0.291ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491     1.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076     3.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101     3.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.704     5.373    RAMCTRL/SNAKE_RAM/H125MHz_IBUF_BUFG
    RAMB36_X1Y4          RAMB36E1                                     r  RAMCTRL/SNAKE_RAM/mem_reg_2_0/CLKBWRCLK
  -------------------------------------------------------------------    -------------------
    RAMB36_X1Y4          RAMB36E1 (Prop_ramb36e1_CLKBWRCLK_DOBDO[6])
                                                      2.454     7.827 r  RAMCTRL/SNAKE_RAM/mem_reg_2_0/DOBDO[6]
                         net (fo=11, routed)          1.312     9.138    SYNC/output_reg[7]_0[1]
    SLICE_X19Y22         LUT5 (Prop_lut5_I4_O)        0.124     9.262 r  SYNC/ROMAddress[3]_i_194/O
                         net (fo=1, routed)           0.000     9.262    SYNC/ROMAddress[3]_i_194_n_0
    SLICE_X19Y22         CARRY4 (Prop_carry4_S[1]_O[3])
                                                      0.640     9.902 r  SYNC/ROMAddress_reg[3]_i_77/O[3]
                         net (fo=5, routed)           0.970    10.873    RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_147_0[3]
    SLICE_X19Y25         LUT4 (Prop_lut4_I1_O)        0.306    11.179 r  RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_228/O
                         net (fo=1, routed)           0.000    11.179    RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_228_n_0
    SLICE_X19Y25         CARRY4 (Prop_carry4_S[3]_CO[3])
                                                      0.401    11.580 r  RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_147/CO[3]
                         net (fo=1, routed)           0.000    11.580    RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_147_n_0
    SLICE_X19Y26         CARRY4 (Prop_carry4_CI_O[0])
                                                      0.222    11.802 f  RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_202/O[0]
                         net (fo=5, routed)           1.496    13.298    RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_202_n_7
    SLICE_X5Y29          LUT5 (Prop_lut5_I4_O)        0.299    13.597 r  RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_201_comp/O
                         net (fo=1, routed)           0.660    14.257    RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_201_n_0
    SLICE_X4Y30          LUT6 (Prop_lut6_I4_O)        0.124    14.381 r  RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_51_comp_1/O
                         net (fo=1, routed)           1.090    15.471    RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_51_n_0
    SLICE_X7Y35          LUT6 (Prop_lut6_I2_O)        0.124    15.595 r  RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_14/O
                         net (fo=3, routed)           0.419    16.013    RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_14_n_0
    SLICE_X9Y34          LUT6 (Prop_lut6_I0_O)        0.124    16.137 r  RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_22/O
                         net (fo=1, routed)           0.665    16.802    RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_22_n_0
    SLICE_X8Y34          LUT5 (Prop_lut5_I3_O)        0.124    16.926 r  RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_6/O
                         net (fo=1, routed)           0.000    16.926    RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_6_n_0
    SLICE_X8Y34          CARRY4 (Prop_carry4_S[3]_O[3])
                                                      0.255    17.181 r  RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_1/O[3]
                         net (fo=1, routed)           0.000    17.181    SNAKE/D[7]
    SLICE_X8Y34          FDRE                                         r  SNAKE/ROMAddress_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      8.000     8.000 r  
    L16                                               0.000     8.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     8.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421     9.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    11.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    11.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.504    12.896    SNAKE/H125MHz_IBUF_BUFG
    SLICE_X8Y34          FDRE                                         r  SNAKE/ROMAddress_reg[7]/C
                         clock pessimism              0.291    13.187    
                         clock uncertainty           -0.035    13.151    
    SLICE_X8Y34          FDRE (Setup_fdre_C_D)        0.109    13.260    SNAKE/ROMAddress_reg[7]
  -------------------------------------------------------------------
                         required time                         13.260    
                         arrival time                         -17.181    
  -------------------------------------------------------------------
                         slack                                 -3.921    

Slack (VIOLATED) :        -3.527ns  (required time - arrival time)
  Source:                 RAMCTRL/SNAKE_RAM/mem_reg_4_0/CLKBWRCLK
                            (rising edge-triggered cell RAMB36E1 clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            SNAKE/ROMAddress_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             sys_clk_pin
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        11.411ns  (logic 5.576ns (48.864%)  route 5.835ns (51.136%))
  Logic Levels:           12  (CARRY4=4 LUT4=2 LUT5=2 LUT6=3 MUXF7=1)
  Clock Path Skew:        -0.189ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.896ns = ( 12.896 - 8.000 ) 
    Source Clock Delay      (SCD):    5.376ns
    Clock Pessimism Removal (CPR):    0.291ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491     1.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076     3.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101     3.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.707     5.376    RAMCTRL/SNAKE_RAM/H125MHz_IBUF_BUFG
    RAMB36_X1Y6          RAMB36E1                                     r  RAMCTRL/SNAKE_RAM/mem_reg_4_0/CLKBWRCLK
  -------------------------------------------------------------------    -------------------
    RAMB36_X1Y6          RAMB36E1 (Prop_ramb36e1_CLKBWRCLK_DOBDO[5])
                                                      2.454     7.830 r  RAMCTRL/SNAKE_RAM/mem_reg_4_0/DOBDO[5]
                         net (fo=12, routed)          1.377     9.206    SYNC/output_reg[5]_4[0]
    SLICE_X21Y29         LUT5 (Prop_lut5_I3_O)        0.124     9.330 r  SYNC/ROMAddress[3]_i_307/O
                         net (fo=1, routed)           0.000     9.330    SYNC/ROMAddress[3]_i_307_n_0
    SLICE_X21Y29         CARRY4 (Prop_carry4_S[1]_O[2])
                                                      0.580     9.910 r  SYNC/ROMAddress_reg[3]_i_155/O[2]
                         net (fo=5, routed)           0.601    10.511    RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_244_0[2]
    SLICE_X22Y30         LUT4 (Prop_lut4_I3_O)        0.302    10.813 r  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_383/O
                         net (fo=1, routed)           0.000    10.813    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_383_n_0
    SLICE_X22Y30         CARRY4 (Prop_carry4_S[1]_O[1])
                                                      0.227    11.040 r  RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_244/O[1]
                         net (fo=5, routed)           0.651    11.691    RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_244_n_6
    SLICE_X18Y31         LUT4 (Prop_lut4_I0_O)        0.303    11.994 f  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_203/O
                         net (fo=2, routed)           1.794    13.788    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_203_n_0
    SLICE_X2Y29          LUT6 (Prop_lut6_I5_O)        0.124    13.912 f  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_97/O
                         net (fo=1, routed)           0.000    13.912    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_97_n_0
    SLICE_X2Y29          MUXF7 (Prop_muxf7_I0_O)      0.212    14.124 f  RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_40/O
                         net (fo=1, routed)           0.435    14.558    RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_40_n_0
    SLICE_X3Y31          LUT6 (Prop_lut6_I1_O)        0.299    14.857 f  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_16__0/O
                         net (fo=1, routed)           0.154    15.012    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_16__0_n_0
    SLICE_X3Y31          LUT6 (Prop_lut6_I2_O)        0.124    15.136 r  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_3_comp/O
                         net (fo=2, routed)           0.824    15.960    RAMCTRL/SNAKE_RAM/SNAKE/p_11_out[2]
    SLICE_X8Y33          LUT5 (Prop_lut5_I0_O)        0.124    16.084 r  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_7/O
                         net (fo=1, routed)           0.000    16.084    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_7_n_0
    SLICE_X8Y33          CARRY4 (Prop_carry4_S[2]_CO[3])
                                                      0.380    16.464 r  RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_1/CO[3]
                         net (fo=1, routed)           0.000    16.464    RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_1_n_0
    SLICE_X8Y34          CARRY4 (Prop_carry4_CI_O[1])
                                                      0.323    16.787 r  RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_1/O[1]
                         net (fo=1, routed)           0.000    16.787    SNAKE/D[5]
    SLICE_X8Y34          FDRE                                         r  SNAKE/ROMAddress_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      8.000     8.000 r  
    L16                                               0.000     8.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     8.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421     9.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    11.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    11.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.504    12.896    SNAKE/H125MHz_IBUF_BUFG
    SLICE_X8Y34          FDRE                                         r  SNAKE/ROMAddress_reg[5]/C
                         clock pessimism              0.291    13.187    
                         clock uncertainty           -0.035    13.151    
    SLICE_X8Y34          FDRE (Setup_fdre_C_D)        0.109    13.260    SNAKE/ROMAddress_reg[5]
  -------------------------------------------------------------------
                         required time                         13.260    
                         arrival time                         -16.787    
  -------------------------------------------------------------------
                         slack                                 -3.527    

Slack (VIOLATED) :        -3.516ns  (required time - arrival time)
  Source:                 RAMCTRL/SNAKE_RAM/mem_reg_9_1/CLKBWRCLK
                            (rising edge-triggered cell RAMB18E1 clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            SNAKE/ROMAddress_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             sys_clk_pin
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        11.397ns  (logic 4.647ns (40.772%)  route 6.750ns (59.228%))
  Logic Levels:           10  (CARRY4=3 LUT3=1 LUT5=3 LUT6=3)
  Clock Path Skew:        -0.192ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.896ns = ( 12.896 - 8.000 ) 
    Source Clock Delay      (SCD):    5.379ns
    Clock Pessimism Removal (CPR):    0.291ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491     1.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076     3.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101     3.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.710     5.379    RAMCTRL/SNAKE_RAM/H125MHz_IBUF_BUFG
    RAMB18_X1Y7          RAMB18E1                                     r  RAMCTRL/SNAKE_RAM/mem_reg_9_1/CLKBWRCLK
  -------------------------------------------------------------------    -------------------
    RAMB18_X1Y7          RAMB18E1 (Prop_ramb18e1_CLKBWRCLK_DOBDO[0])
                                                      2.454     7.833 f  RAMCTRL/SNAKE_RAM/mem_reg_9_1/DOBDO[0]
                         net (fo=12, routed)          1.320     9.153    RAMCTRL/SNAKE_RAM/output_reg[0]_1[13]
    SLICE_X14Y18         LUT3 (Prop_lut3_I0_O)        0.124     9.277 r  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_355/O
                         net (fo=1, routed)           0.695     9.971    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_355_n_0
    SLICE_X12Y20         LUT5 (Prop_lut5_I1_O)        0.124    10.095 r  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_213/O
                         net (fo=1, routed)           0.613    10.708    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_213_n_0
    SLICE_X13Y22         CARRY4 (Prop_carry4_DI[3]_CO[3])
                                                      0.385    11.093 r  RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_105/CO[3]
                         net (fo=1, routed)           0.000    11.093    RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_105_n_0
    SLICE_X13Y23         CARRY4 (Prop_carry4_CI_CO[1])
                                                      0.157    11.250 f  RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_45/CO[1]
                         net (fo=2, routed)           0.793    12.043    RAMCTRL/SNAKE_RAM/SNAKE/snakeHere519_in
    SLICE_X10Y25         LUT5 (Prop_lut5_I1_O)        0.329    12.372 f  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_18/O
                         net (fo=37, routed)          1.035    13.407    RAMCTRL/SNAKE_RAM/mem_reg_9_0_3
    SLICE_X2Y29          LUT6 (Prop_lut6_I2_O)        0.124    13.531 r  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_79_comp/O
                         net (fo=6, routed)           0.742    14.274    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_79_n_0
    SLICE_X6Y32          LUT6 (Prop_lut6_I3_O)        0.124    14.398 r  RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_39/O
                         net (fo=1, routed)           0.590    14.988    RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_39_n_0
    SLICE_X6Y33          LUT6 (Prop_lut6_I2_O)        0.124    15.112 r  RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_13/O
                         net (fo=4, routed)           0.963    16.074    RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_13_n_0
    SLICE_X8Y34          LUT5 (Prop_lut5_I0_O)        0.124    16.198 r  RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_8/O
                         net (fo=1, routed)           0.000    16.198    RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_8_n_0
    SLICE_X8Y34          CARRY4 (Prop_carry4_S[1]_O[2])
                                                      0.578    16.776 r  RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_1/O[2]
                         net (fo=1, routed)           0.000    16.776    SNAKE/D[6]
    SLICE_X8Y34          FDRE                                         r  SNAKE/ROMAddress_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      8.000     8.000 r  
    L16                                               0.000     8.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     8.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421     9.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    11.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    11.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.504    12.896    SNAKE/H125MHz_IBUF_BUFG
    SLICE_X8Y34          FDRE                                         r  SNAKE/ROMAddress_reg[6]/C
                         clock pessimism              0.291    13.187    
                         clock uncertainty           -0.035    13.151    
    SLICE_X8Y34          FDRE (Setup_fdre_C_D)        0.109    13.260    SNAKE/ROMAddress_reg[6]
  -------------------------------------------------------------------
                         required time                         13.260    
                         arrival time                         -16.776    
  -------------------------------------------------------------------
                         slack                                 -3.516    

Slack (VIOLATED) :        -3.423ns  (required time - arrival time)
  Source:                 RAMCTRL/SNAKE_RAM/mem_reg_4_0/CLKBWRCLK
                            (rising edge-triggered cell RAMB36E1 clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            SNAKE/ROMAddress_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             sys_clk_pin
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        11.307ns  (logic 5.472ns (48.394%)  route 5.835ns (51.606%))
  Logic Levels:           12  (CARRY4=4 LUT4=2 LUT5=2 LUT6=3 MUXF7=1)
  Clock Path Skew:        -0.189ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.896ns = ( 12.896 - 8.000 ) 
    Source Clock Delay      (SCD):    5.376ns
    Clock Pessimism Removal (CPR):    0.291ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491     1.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076     3.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101     3.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.707     5.376    RAMCTRL/SNAKE_RAM/H125MHz_IBUF_BUFG
    RAMB36_X1Y6          RAMB36E1                                     r  RAMCTRL/SNAKE_RAM/mem_reg_4_0/CLKBWRCLK
  -------------------------------------------------------------------    -------------------
    RAMB36_X1Y6          RAMB36E1 (Prop_ramb36e1_CLKBWRCLK_DOBDO[5])
                                                      2.454     7.830 r  RAMCTRL/SNAKE_RAM/mem_reg_4_0/DOBDO[5]
                         net (fo=12, routed)          1.377     9.206    SYNC/output_reg[5]_4[0]
    SLICE_X21Y29         LUT5 (Prop_lut5_I3_O)        0.124     9.330 r  SYNC/ROMAddress[3]_i_307/O
                         net (fo=1, routed)           0.000     9.330    SYNC/ROMAddress[3]_i_307_n_0
    SLICE_X21Y29         CARRY4 (Prop_carry4_S[1]_O[2])
                                                      0.580     9.910 r  SYNC/ROMAddress_reg[3]_i_155/O[2]
                         net (fo=5, routed)           0.601    10.511    RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_244_0[2]
    SLICE_X22Y30         LUT4 (Prop_lut4_I3_O)        0.302    10.813 r  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_383/O
                         net (fo=1, routed)           0.000    10.813    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_383_n_0
    SLICE_X22Y30         CARRY4 (Prop_carry4_S[1]_O[1])
                                                      0.227    11.040 r  RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_244/O[1]
                         net (fo=5, routed)           0.651    11.691    RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_244_n_6
    SLICE_X18Y31         LUT4 (Prop_lut4_I0_O)        0.303    11.994 f  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_203/O
                         net (fo=2, routed)           1.794    13.788    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_203_n_0
    SLICE_X2Y29          LUT6 (Prop_lut6_I5_O)        0.124    13.912 f  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_97/O
                         net (fo=1, routed)           0.000    13.912    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_97_n_0
    SLICE_X2Y29          MUXF7 (Prop_muxf7_I0_O)      0.212    14.124 f  RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_40/O
                         net (fo=1, routed)           0.435    14.558    RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_40_n_0
    SLICE_X3Y31          LUT6 (Prop_lut6_I1_O)        0.299    14.857 f  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_16__0/O
                         net (fo=1, routed)           0.154    15.012    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_16__0_n_0
    SLICE_X3Y31          LUT6 (Prop_lut6_I2_O)        0.124    15.136 r  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_3_comp/O
                         net (fo=2, routed)           0.824    15.960    RAMCTRL/SNAKE_RAM/SNAKE/p_11_out[2]
    SLICE_X8Y33          LUT5 (Prop_lut5_I0_O)        0.124    16.084 r  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_7/O
                         net (fo=1, routed)           0.000    16.084    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_7_n_0
    SLICE_X8Y33          CARRY4 (Prop_carry4_S[2]_CO[3])
                                                      0.380    16.464 r  RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_1/CO[3]
                         net (fo=1, routed)           0.000    16.464    RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_1_n_0
    SLICE_X8Y34          CARRY4 (Prop_carry4_CI_O[0])
                                                      0.219    16.683 r  RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_1/O[0]
                         net (fo=1, routed)           0.000    16.683    SNAKE/D[4]
    SLICE_X8Y34          FDRE                                         r  SNAKE/ROMAddress_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      8.000     8.000 r  
    L16                                               0.000     8.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     8.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421     9.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    11.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    11.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.504    12.896    SNAKE/H125MHz_IBUF_BUFG
    SLICE_X8Y34          FDRE                                         r  SNAKE/ROMAddress_reg[4]/C
                         clock pessimism              0.291    13.187    
                         clock uncertainty           -0.035    13.151    
    SLICE_X8Y34          FDRE (Setup_fdre_C_D)        0.109    13.260    SNAKE/ROMAddress_reg[4]
  -------------------------------------------------------------------
                         required time                         13.260    
                         arrival time                         -16.683    
  -------------------------------------------------------------------
                         slack                                 -3.423    

Slack (VIOLATED) :        -3.197ns  (required time - arrival time)
  Source:                 RAMCTRL/SNAKE_RAM/mem_reg_9_1/CLKBWRCLK
                            (rising edge-triggered cell RAMB18E1 clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            SNAKE/ROMAddress_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             sys_clk_pin
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        11.078ns  (logic 4.712ns (42.535%)  route 6.366ns (57.465%))
  Logic Levels:           10  (CARRY4=3 LUT3=1 LUT5=2 LUT6=4)
  Clock Path Skew:        -0.193ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.895ns = ( 12.895 - 8.000 ) 
    Source Clock Delay      (SCD):    5.379ns
    Clock Pessimism Removal (CPR):    0.291ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491     1.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076     3.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101     3.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.710     5.379    RAMCTRL/SNAKE_RAM/H125MHz_IBUF_BUFG
    RAMB18_X1Y7          RAMB18E1                                     r  RAMCTRL/SNAKE_RAM/mem_reg_9_1/CLKBWRCLK
  -------------------------------------------------------------------    -------------------
    RAMB18_X1Y7          RAMB18E1 (Prop_ramb18e1_CLKBWRCLK_DOBDO[0])
                                                      2.454     7.833 f  RAMCTRL/SNAKE_RAM/mem_reg_9_1/DOBDO[0]
                         net (fo=12, routed)          1.320     9.153    RAMCTRL/SNAKE_RAM/output_reg[0]_1[13]
    SLICE_X14Y18         LUT3 (Prop_lut3_I0_O)        0.124     9.277 r  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_355/O
                         net (fo=1, routed)           0.695     9.971    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_355_n_0
    SLICE_X12Y20         LUT5 (Prop_lut5_I1_O)        0.124    10.095 r  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_213/O
                         net (fo=1, routed)           0.613    10.708    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_213_n_0
    SLICE_X13Y22         CARRY4 (Prop_carry4_DI[3]_CO[3])
                                                      0.385    11.093 r  RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_105/CO[3]
                         net (fo=1, routed)           0.000    11.093    RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_105_n_0
    SLICE_X13Y23         CARRY4 (Prop_carry4_CI_CO[1])
                                                      0.157    11.250 f  RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_45/CO[1]
                         net (fo=2, routed)           0.793    12.043    RAMCTRL/SNAKE_RAM/SNAKE/snakeHere519_in
    SLICE_X10Y25         LUT5 (Prop_lut5_I1_O)        0.329    12.372 f  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_18/O
                         net (fo=37, routed)          1.035    13.407    RAMCTRL/SNAKE_RAM/mem_reg_9_0_3
    SLICE_X2Y29          LUT6 (Prop_lut6_I2_O)        0.124    13.531 r  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_79_comp/O
                         net (fo=6, routed)           0.494    14.025    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_79_n_0
    SLICE_X4Y29          LUT6 (Prop_lut6_I0_O)        0.124    14.149 r  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_72/O
                         net (fo=1, routed)           0.800    14.949    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_72_n_0
    SLICE_X4Y30          LUT6 (Prop_lut6_I3_O)        0.124    15.073 r  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_31/O
                         net (fo=1, routed)           0.617    15.690    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_31_n_0
    SLICE_X8Y33          LUT6 (Prop_lut6_I5_O)        0.124    15.814 r  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_8__0/O
                         net (fo=1, routed)           0.000    15.814    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_8__0_n_0
    SLICE_X8Y33          CARRY4 (Prop_carry4_S[1]_O[3])
                                                      0.643    16.457 r  RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_1/O[3]
                         net (fo=1, routed)           0.000    16.457    SNAKE/D[3]
    SLICE_X8Y33          FDRE                                         r  SNAKE/ROMAddress_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      8.000     8.000 r  
    L16                                               0.000     8.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     8.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421     9.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    11.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    11.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.503    12.895    SNAKE/H125MHz_IBUF_BUFG
    SLICE_X8Y33          FDRE                                         r  SNAKE/ROMAddress_reg[3]/C
                         clock pessimism              0.291    13.186    
                         clock uncertainty           -0.035    13.150    
    SLICE_X8Y33          FDRE (Setup_fdre_C_D)        0.109    13.259    SNAKE/ROMAddress_reg[3]
  -------------------------------------------------------------------
                         required time                         13.259    
                         arrival time                         -16.457    
  -------------------------------------------------------------------
                         slack                                 -3.197    

Slack (VIOLATED) :        -3.132ns  (required time - arrival time)
  Source:                 RAMCTRL/SNAKE_RAM/mem_reg_9_1/CLKBWRCLK
                            (rising edge-triggered cell RAMB18E1 clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            SNAKE/ROMAddress_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             sys_clk_pin
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        11.013ns  (logic 4.647ns (42.196%)  route 6.366ns (57.804%))
  Logic Levels:           10  (CARRY4=3 LUT3=1 LUT5=2 LUT6=4)
  Clock Path Skew:        -0.193ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.895ns = ( 12.895 - 8.000 ) 
    Source Clock Delay      (SCD):    5.379ns
    Clock Pessimism Removal (CPR):    0.291ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491     1.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076     3.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101     3.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.710     5.379    RAMCTRL/SNAKE_RAM/H125MHz_IBUF_BUFG
    RAMB18_X1Y7          RAMB18E1                                     r  RAMCTRL/SNAKE_RAM/mem_reg_9_1/CLKBWRCLK
  -------------------------------------------------------------------    -------------------
    RAMB18_X1Y7          RAMB18E1 (Prop_ramb18e1_CLKBWRCLK_DOBDO[0])
                                                      2.454     7.833 f  RAMCTRL/SNAKE_RAM/mem_reg_9_1/DOBDO[0]
                         net (fo=12, routed)          1.320     9.153    RAMCTRL/SNAKE_RAM/output_reg[0]_1[13]
    SLICE_X14Y18         LUT3 (Prop_lut3_I0_O)        0.124     9.277 r  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_355/O
                         net (fo=1, routed)           0.695     9.971    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_355_n_0
    SLICE_X12Y20         LUT5 (Prop_lut5_I1_O)        0.124    10.095 r  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_213/O
                         net (fo=1, routed)           0.613    10.708    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_213_n_0
    SLICE_X13Y22         CARRY4 (Prop_carry4_DI[3]_CO[3])
                                                      0.385    11.093 r  RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_105/CO[3]
                         net (fo=1, routed)           0.000    11.093    RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_105_n_0
    SLICE_X13Y23         CARRY4 (Prop_carry4_CI_CO[1])
                                                      0.157    11.250 f  RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_45/CO[1]
                         net (fo=2, routed)           0.793    12.043    RAMCTRL/SNAKE_RAM/SNAKE/snakeHere519_in
    SLICE_X10Y25         LUT5 (Prop_lut5_I1_O)        0.329    12.372 f  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_18/O
                         net (fo=37, routed)          1.035    13.407    RAMCTRL/SNAKE_RAM/mem_reg_9_0_3
    SLICE_X2Y29          LUT6 (Prop_lut6_I2_O)        0.124    13.531 r  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_79_comp/O
                         net (fo=6, routed)           0.494    14.025    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_79_n_0
    SLICE_X4Y29          LUT6 (Prop_lut6_I0_O)        0.124    14.149 r  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_72/O
                         net (fo=1, routed)           0.800    14.949    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_72_n_0
    SLICE_X4Y30          LUT6 (Prop_lut6_I3_O)        0.124    15.073 r  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_31/O
                         net (fo=1, routed)           0.617    15.690    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_31_n_0
    SLICE_X8Y33          LUT6 (Prop_lut6_I5_O)        0.124    15.814 r  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_8__0/O
                         net (fo=1, routed)           0.000    15.814    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_8__0_n_0
    SLICE_X8Y33          CARRY4 (Prop_carry4_S[1]_O[2])
                                                      0.578    16.392 r  RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_1/O[2]
                         net (fo=1, routed)           0.000    16.392    SNAKE/D[2]
    SLICE_X8Y33          FDRE                                         r  SNAKE/ROMAddress_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      8.000     8.000 r  
    L16                                               0.000     8.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     8.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421     9.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    11.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    11.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.503    12.895    SNAKE/H125MHz_IBUF_BUFG
    SLICE_X8Y33          FDRE                                         r  SNAKE/ROMAddress_reg[2]/C
                         clock pessimism              0.291    13.186    
                         clock uncertainty           -0.035    13.150    
    SLICE_X8Y33          FDRE (Setup_fdre_C_D)        0.109    13.259    SNAKE/ROMAddress_reg[2]
  -------------------------------------------------------------------
                         required time                         13.259    
                         arrival time                         -16.392    
  -------------------------------------------------------------------
                         slack                                 -3.132    

Slack (VIOLATED) :        -2.784ns  (required time - arrival time)
  Source:                 RAMCTRL/SNAKE_RAM/mem_reg_9_1/CLKBWRCLK
                            (rising edge-triggered cell RAMB18E1 clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            SNAKE/ROMAddress_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             sys_clk_pin
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        10.665ns  (logic 4.299ns (40.310%)  route 6.366ns (59.690%))
  Logic Levels:           10  (CARRY4=3 LUT3=1 LUT5=2 LUT6=4)
  Clock Path Skew:        -0.193ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.895ns = ( 12.895 - 8.000 ) 
    Source Clock Delay      (SCD):    5.379ns
    Clock Pessimism Removal (CPR):    0.291ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491     1.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076     3.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101     3.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.710     5.379    RAMCTRL/SNAKE_RAM/H125MHz_IBUF_BUFG
    RAMB18_X1Y7          RAMB18E1                                     r  RAMCTRL/SNAKE_RAM/mem_reg_9_1/CLKBWRCLK
  -------------------------------------------------------------------    -------------------
    RAMB18_X1Y7          RAMB18E1 (Prop_ramb18e1_CLKBWRCLK_DOBDO[0])
                                                      2.454     7.833 f  RAMCTRL/SNAKE_RAM/mem_reg_9_1/DOBDO[0]
                         net (fo=12, routed)          1.320     9.153    RAMCTRL/SNAKE_RAM/output_reg[0]_1[13]
    SLICE_X14Y18         LUT3 (Prop_lut3_I0_O)        0.124     9.277 r  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_355/O
                         net (fo=1, routed)           0.695     9.971    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_355_n_0
    SLICE_X12Y20         LUT5 (Prop_lut5_I1_O)        0.124    10.095 r  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_213/O
                         net (fo=1, routed)           0.613    10.708    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_213_n_0
    SLICE_X13Y22         CARRY4 (Prop_carry4_DI[3]_CO[3])
                                                      0.385    11.093 r  RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_105/CO[3]
                         net (fo=1, routed)           0.000    11.093    RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_105_n_0
    SLICE_X13Y23         CARRY4 (Prop_carry4_CI_CO[1])
                                                      0.157    11.250 f  RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_45/CO[1]
                         net (fo=2, routed)           0.793    12.043    RAMCTRL/SNAKE_RAM/SNAKE/snakeHere519_in
    SLICE_X10Y25         LUT5 (Prop_lut5_I1_O)        0.329    12.372 f  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_18/O
                         net (fo=37, routed)          1.035    13.407    RAMCTRL/SNAKE_RAM/mem_reg_9_0_3
    SLICE_X2Y29          LUT6 (Prop_lut6_I2_O)        0.124    13.531 r  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_79_comp/O
                         net (fo=6, routed)           0.494    14.025    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_79_n_0
    SLICE_X4Y29          LUT6 (Prop_lut6_I0_O)        0.124    14.149 r  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_72/O
                         net (fo=1, routed)           0.800    14.949    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_72_n_0
    SLICE_X4Y30          LUT6 (Prop_lut6_I3_O)        0.124    15.073 r  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_31/O
                         net (fo=1, routed)           0.617    15.690    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_31_n_0
    SLICE_X8Y33          LUT6 (Prop_lut6_I5_O)        0.124    15.814 r  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_8__0/O
                         net (fo=1, routed)           0.000    15.814    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_8__0_n_0
    SLICE_X8Y33          CARRY4 (Prop_carry4_S[1]_O[1])
                                                      0.230    16.044 r  RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_1/O[1]
                         net (fo=1, routed)           0.000    16.044    SNAKE/D[1]
    SLICE_X8Y33          FDRE                                         r  SNAKE/ROMAddress_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      8.000     8.000 r  
    L16                                               0.000     8.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     8.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421     9.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    11.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    11.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.503    12.895    SNAKE/H125MHz_IBUF_BUFG
    SLICE_X8Y33          FDRE                                         r  SNAKE/ROMAddress_reg[1]/C
                         clock pessimism              0.291    13.186    
                         clock uncertainty           -0.035    13.150    
    SLICE_X8Y33          FDRE (Setup_fdre_C_D)        0.109    13.259    SNAKE/ROMAddress_reg[1]
  -------------------------------------------------------------------
                         required time                         13.259    
                         arrival time                         -16.044    
  -------------------------------------------------------------------
                         slack                                 -2.784    

Slack (VIOLATED) :        -2.777ns  (required time - arrival time)
  Source:                 RAMCTRL/SNAKE_RAM/mem_reg_1_0/CLKARDCLK
                            (rising edge-triggered cell RAMB36E1 clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            UPD/dataOut_reg[23]/CE
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             sys_clk_pin
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        10.367ns  (logic 4.234ns (40.842%)  route 6.133ns (59.158%))
  Logic Levels:           9  (CARRY4=1 LUT4=2 LUT5=3 LUT6=3)
  Clock Path Skew:        -0.206ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.884ns = ( 12.884 - 8.000 ) 
    Source Clock Delay      (SCD):    5.381ns
    Clock Pessimism Removal (CPR):    0.291ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491     1.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076     3.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101     3.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.712     5.381    RAMCTRL/SNAKE_RAM/H125MHz_IBUF_BUFG
    RAMB36_X0Y5          RAMB36E1                                     r  RAMCTRL/SNAKE_RAM/mem_reg_1_0/CLKARDCLK
  -------------------------------------------------------------------    -------------------
    RAMB36_X0Y5          RAMB36E1 (Prop_ramb36e1_CLKARDCLK_DOADO[5])
                                                      2.454     7.835 r  RAMCTRL/SNAKE_RAM/mem_reg_1_0/DOADO[5]
                         net (fo=6, routed)           1.685     9.520    RAMCTRL/SNAKE_RAM/RAMDataIn[5]
    SLICE_X23Y30         LUT5 (Prop_lut5_I2_O)        0.124     9.644 r  RAMCTRL/SNAKE_RAM/cSnake[Y][3]_i_13/O
                         net (fo=1, routed)           0.433    10.077    RAMCTRL/SNAKE_RAM/cSnake[Y][3]_i_13_n_0
    SLICE_X23Y30         LUT6 (Prop_lut6_I5_O)        0.124    10.201 f  RAMCTRL/SNAKE_RAM/cSnake[Y][3]_i_11/O
                         net (fo=4, routed)           0.656    10.857    RAMCTRL/SNAKE_RAM/cSnake[Y][3]_i_11_n_0
    SLICE_X26Y29         LUT6 (Prop_lut6_I0_O)        0.124    10.981 r  RAMCTRL/SNAKE_RAM/lost_i_4/O
                         net (fo=2, routed)           0.413    11.394    RAMCTRL/SNAKE_RAM/mem_reg_1_0_6
    SLICE_X27Y29         LUT4 (Prop_lut4_I1_O)        0.124    11.518 r  RAMCTRL/SNAKE_RAM/cSnake[Y][3]_i_10/O
                         net (fo=1, routed)           0.000    11.518    RAMCTRL/SNAKE_RAM/cSnake[Y][3]_i_10_n_0
    SLICE_X27Y29         CARRY4 (Prop_carry4_S[0]_O[3])
                                                      0.606    12.124 f  RAMCTRL/SNAKE_RAM/cSnake_reg[Y][3]_i_2/O[3]
                         net (fo=3, routed)           0.637    12.761    UPD/dataOut_reg[8]_0[3]
    SLICE_X26Y28         LUT4 (Prop_lut4_I1_O)        0.306    13.067 f  UPD/state[3]_i_5/O
                         net (fo=2, routed)           0.468    13.535    UPD/state[3]_i_5_n_0
    SLICE_X30Y27         LUT5 (Prop_lut5_I4_O)        0.124    13.659 r  UPD/state[1]_i_5/O
                         net (fo=4, routed)           0.584    14.243    UPD/state[1]_i_5_n_0
    SLICE_X30Y28         LUT5 (Prop_lut5_I1_O)        0.124    14.367 r  UPD/dataOut[23]_i_3/O
                         net (fo=2, routed)           0.507    14.873    UPD/dataOut[23]_i_3_n_0
    SLICE_X30Y28         LUT6 (Prop_lut6_I2_O)        0.124    14.997 r  UPD/dataOut[23]_i_1/O
                         net (fo=24, routed)          0.750    15.747    UPD/dataOut[23]_i_1_n_0
    SLICE_X34Y30         FDRE                                         r  UPD/dataOut_reg[23]/CE
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      8.000     8.000 r  
    L16                                               0.000     8.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     8.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421     9.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    11.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    11.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.492    12.884    UPD/H125MHz_IBUF_BUFG
    SLICE_X34Y30         FDRE                                         r  UPD/dataOut_reg[23]/C
                         clock pessimism              0.291    13.175    
                         clock uncertainty           -0.035    13.139    
    SLICE_X34Y30         FDRE (Setup_fdre_C_CE)      -0.169    12.970    UPD/dataOut_reg[23]
  -------------------------------------------------------------------
                         required time                         12.970    
                         arrival time                         -15.747    
  -------------------------------------------------------------------
                         slack                                 -2.777    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.086ns  (arrival time - required time)
  Source:                 UPD/matDataOut_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            RAMCTRL/MAT_RAM/mem_reg_2/DIADI[8]
                            (rising edge-triggered cell RAMB36E1 clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             sys_clk_pin
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        0.456ns  (logic 0.141ns (30.934%)  route 0.315ns (69.066%))
  Logic Levels:           0  
  Clock Path Skew:        0.073ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.020ns
    Source Clock Delay      (SCD):    1.467ns
    Clock Pessimism Removal (CPR):    0.480ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.555     1.467    UPD/H125MHz_IBUF_BUFG
    SLICE_X35Y27         FDRE                                         r  UPD/matDataOut_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X35Y27         FDRE (Prop_fdre_C_Q)         0.141     1.608 r  UPD/matDataOut_reg[8]/Q
                         net (fo=9, routed)           0.315     1.923    RAMCTRL/MAT_RAM/mem_reg_1_4[8]
    RAMB36_X2Y4          RAMB36E1                                     r  RAMCTRL/MAT_RAM/mem_reg_2/DIADI[8]
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.861     2.020    RAMCTRL/MAT_RAM/H125MHz_IBUF_BUFG
    RAMB36_X2Y4          RAMB36E1                                     r  RAMCTRL/MAT_RAM/mem_reg_2/CLKARDCLK
                         clock pessimism             -0.480     1.540    
    RAMB36_X2Y4          RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[8])
                                                      0.296     1.836    RAMCTRL/MAT_RAM/mem_reg_2
  -------------------------------------------------------------------
                         required time                         -1.836    
                         arrival time                           1.923    
  -------------------------------------------------------------------
                         slack                                  0.086    

Slack (MET) :             0.090ns  (arrival time - required time)
  Source:                 UPD/dataOut_reg[9]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            RAMCTRL/SNAKE_RAM/mem_reg_2_0/DIADI[9]
                            (rising edge-triggered cell RAMB36E1 clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             sys_clk_pin
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        0.457ns  (logic 0.164ns (35.925%)  route 0.293ns (64.075%))
  Logic Levels:           0  
  Clock Path Skew:        0.070ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.019ns
    Source Clock Delay      (SCD):    1.469ns
    Clock Pessimism Removal (CPR):    0.480ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.557     1.469    UPD/H125MHz_IBUF_BUFG
    SLICE_X30Y30         FDRE                                         r  UPD/dataOut_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X30Y30         FDRE (Prop_fdre_C_Q)         0.164     1.633 r  UPD/dataOut_reg[9]/Q
                         net (fo=9, routed)           0.293     1.925    RAMCTRL/SNAKE_RAM/updateRAMDataOut[9]
    RAMB36_X1Y4          RAMB36E1                                     r  RAMCTRL/SNAKE_RAM/mem_reg_2_0/DIADI[9]
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.860     2.019    RAMCTRL/SNAKE_RAM/H125MHz_IBUF_BUFG
    RAMB36_X1Y4          RAMB36E1                                     r  RAMCTRL/SNAKE_RAM/mem_reg_2_0/CLKARDCLK
                         clock pessimism             -0.480     1.539    
    RAMB36_X1Y4          RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[9])
                                                      0.296     1.835    RAMCTRL/SNAKE_RAM/mem_reg_2_0
  -------------------------------------------------------------------
                         required time                         -1.835    
                         arrival time                           1.925    
  -------------------------------------------------------------------
                         slack                                  0.090    

Slack (MET) :             0.090ns  (arrival time - required time)
  Source:                 UPD/dataOut_reg[16]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            RAMCTRL/SNAKE_RAM/mem_reg_4_0/DIPADIP[0]
                            (rising edge-triggered cell RAMB36E1 clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             sys_clk_pin
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        0.467ns  (logic 0.164ns (35.147%)  route 0.303ns (64.853%))
  Logic Levels:           0  
  Clock Path Skew:        0.080ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.027ns
    Source Clock Delay      (SCD):    1.467ns
    Clock Pessimism Removal (CPR):    0.480ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.555     1.467    UPD/H125MHz_IBUF_BUFG
    SLICE_X30Y27         FDRE                                         r  UPD/dataOut_reg[16]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X30Y27         FDRE (Prop_fdre_C_Q)         0.164     1.631 r  UPD/dataOut_reg[16]/Q
                         net (fo=9, routed)           0.303     1.933    RAMCTRL/SNAKE_RAM/updateRAMDataOut[16]
    RAMB36_X1Y6          RAMB36E1                                     r  RAMCTRL/SNAKE_RAM/mem_reg_4_0/DIPADIP[0]
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.868     2.027    RAMCTRL/SNAKE_RAM/H125MHz_IBUF_BUFG
    RAMB36_X1Y6          RAMB36E1                                     r  RAMCTRL/SNAKE_RAM/mem_reg_4_0/CLKARDCLK
                         clock pessimism             -0.480     1.547    
    RAMB36_X1Y6          RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIPADIP[0])
                                                      0.296     1.843    RAMCTRL/SNAKE_RAM/mem_reg_4_0
  -------------------------------------------------------------------
                         required time                         -1.843    
                         arrival time                           1.933    
  -------------------------------------------------------------------
                         slack                                  0.090    

Slack (MET) :             0.094ns  (arrival time - required time)
  Source:                 UPD/matDataOut_reg[0]/C
                            (rising edge-triggered cell FDSE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            RAMCTRL/MAT_RAM/mem_reg_1/DIADI[0]
                            (rising edge-triggered cell RAMB36E1 clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             sys_clk_pin
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        0.447ns  (logic 0.164ns (36.695%)  route 0.283ns (63.305%))
  Logic Levels:           0  
  Clock Path Skew:        0.056ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.023ns
    Source Clock Delay      (SCD):    1.467ns
    Clock Pessimism Removal (CPR):    0.500ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.555     1.467    UPD/H125MHz_IBUF_BUFG
    SLICE_X34Y28         FDSE                                         r  UPD/matDataOut_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X34Y28         FDSE (Prop_fdse_C_Q)         0.164     1.631 r  UPD/matDataOut_reg[0]/Q
                         net (fo=9, routed)           0.283     1.914    RAMCTRL/MAT_RAM/mem_reg_1_4[0]
    RAMB36_X2Y5          RAMB36E1                                     r  RAMCTRL/MAT_RAM/mem_reg_1/DIADI[0]
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.864     2.023    RAMCTRL/MAT_RAM/H125MHz_IBUF_BUFG
    RAMB36_X2Y5          RAMB36E1                                     r  RAMCTRL/MAT_RAM/mem_reg_1/CLKARDCLK
                         clock pessimism             -0.500     1.523    
    RAMB36_X2Y5          RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[0])
                                                      0.296     1.819    RAMCTRL/MAT_RAM/mem_reg_1
  -------------------------------------------------------------------
                         required time                         -1.819    
                         arrival time                           1.914    
  -------------------------------------------------------------------
                         slack                                  0.094    

Slack (MET) :             0.097ns  (arrival time - required time)
  Source:                 UPD/dataOut_reg[15]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            RAMCTRL/SNAKE_RAM/mem_reg_2_0/DIADI[15]
                            (rising edge-triggered cell RAMB36E1 clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             sys_clk_pin
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        0.465ns  (logic 0.141ns (30.321%)  route 0.324ns (69.679%))
  Logic Levels:           0  
  Clock Path Skew:        0.072ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.019ns
    Source Clock Delay      (SCD):    1.467ns
    Clock Pessimism Removal (CPR):    0.480ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.555     1.467    UPD/H125MHz_IBUF_BUFG
    SLICE_X27Y27         FDRE                                         r  UPD/dataOut_reg[15]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X27Y27         FDRE (Prop_fdre_C_Q)         0.141     1.608 r  UPD/dataOut_reg[15]/Q
                         net (fo=9, routed)           0.324     1.932    RAMCTRL/SNAKE_RAM/updateRAMDataOut[15]
    RAMB36_X1Y4          RAMB36E1                                     r  RAMCTRL/SNAKE_RAM/mem_reg_2_0/DIADI[15]
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.860     2.019    RAMCTRL/SNAKE_RAM/H125MHz_IBUF_BUFG
    RAMB36_X1Y4          RAMB36E1                                     r  RAMCTRL/SNAKE_RAM/mem_reg_2_0/CLKARDCLK
                         clock pessimism             -0.480     1.539    
    RAMB36_X1Y4          RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[15])
                                                      0.296     1.835    RAMCTRL/SNAKE_RAM/mem_reg_2_0
  -------------------------------------------------------------------
                         required time                         -1.835    
                         arrival time                           1.932    
  -------------------------------------------------------------------
                         slack                                  0.097    

Slack (MET) :             0.100ns  (arrival time - required time)
  Source:                 UPD/matDataOut_reg[1]/C
                            (rising edge-triggered cell FDSE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            RAMCTRL/MAT_RAM/mem_reg_1/DIADI[1]
                            (rising edge-triggered cell RAMB36E1 clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             sys_clk_pin
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        0.452ns  (logic 0.164ns (36.266%)  route 0.288ns (63.734%))
  Logic Levels:           0  
  Clock Path Skew:        0.056ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.023ns
    Source Clock Delay      (SCD):    1.467ns
    Clock Pessimism Removal (CPR):    0.500ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.555     1.467    UPD/H125MHz_IBUF_BUFG
    SLICE_X34Y28         FDSE                                         r  UPD/matDataOut_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X34Y28         FDSE (Prop_fdse_C_Q)         0.164     1.631 r  UPD/matDataOut_reg[1]/Q
                         net (fo=9, routed)           0.288     1.919    RAMCTRL/MAT_RAM/mem_reg_1_4[1]
    RAMB36_X2Y5          RAMB36E1                                     r  RAMCTRL/MAT_RAM/mem_reg_1/DIADI[1]
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.864     2.023    RAMCTRL/MAT_RAM/H125MHz_IBUF_BUFG
    RAMB36_X2Y5          RAMB36E1                                     r  RAMCTRL/MAT_RAM/mem_reg_1/CLKARDCLK
                         clock pessimism             -0.500     1.523    
    RAMB36_X2Y5          RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[1])
                                                      0.296     1.819    RAMCTRL/MAT_RAM/mem_reg_1
  -------------------------------------------------------------------
                         required time                         -1.819    
                         arrival time                           1.919    
  -------------------------------------------------------------------
                         slack                                  0.100    

Slack (MET) :             0.102ns  (arrival time - required time)
  Source:                 UPD/dataOut_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            RAMCTRL/SNAKE_RAM/mem_reg_4_0/DIADI[0]
                            (rising edge-triggered cell RAMB36E1 clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             sys_clk_pin
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        0.477ns  (logic 0.164ns (34.364%)  route 0.313ns (65.636%))
  Logic Levels:           0  
  Clock Path Skew:        0.079ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.027ns
    Source Clock Delay      (SCD):    1.468ns
    Clock Pessimism Removal (CPR):    0.480ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.556     1.468    UPD/H125MHz_IBUF_BUFG
    SLICE_X34Y29         FDRE                                         r  UPD/dataOut_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X34Y29         FDRE (Prop_fdre_C_Q)         0.164     1.632 r  UPD/dataOut_reg[0]/Q
                         net (fo=9, routed)           0.313     1.945    RAMCTRL/SNAKE_RAM/updateRAMDataOut[0]
    RAMB36_X1Y6          RAMB36E1                                     r  RAMCTRL/SNAKE_RAM/mem_reg_4_0/DIADI[0]
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.868     2.027    RAMCTRL/SNAKE_RAM/H125MHz_IBUF_BUFG
    RAMB36_X1Y6          RAMB36E1                                     r  RAMCTRL/SNAKE_RAM/mem_reg_4_0/CLKARDCLK
                         clock pessimism             -0.480     1.547    
    RAMB36_X1Y6          RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[0])
                                                      0.296     1.843    RAMCTRL/SNAKE_RAM/mem_reg_4_0
  -------------------------------------------------------------------
                         required time                         -1.843    
                         arrival time                           1.945    
  -------------------------------------------------------------------
                         slack                                  0.102    

Slack (MET) :             0.119ns  (arrival time - required time)
  Source:                 UPD/dataOut_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            RAMCTRL/SNAKE_RAM/mem_reg_4_0/DIADI[1]
                            (rising edge-triggered cell RAMB36E1 clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             sys_clk_pin
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        0.479ns  (logic 0.141ns (29.457%)  route 0.338ns (70.543%))
  Logic Levels:           0  
  Clock Path Skew:        0.063ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.027ns
    Source Clock Delay      (SCD):    1.465ns
    Clock Pessimism Removal (CPR):    0.499ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.553     1.465    UPD/H125MHz_IBUF_BUFG
    SLICE_X26Y26         FDRE                                         r  UPD/dataOut_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X26Y26         FDRE (Prop_fdre_C_Q)         0.141     1.606 r  UPD/dataOut_reg[1]/Q
                         net (fo=9, routed)           0.338     1.943    RAMCTRL/SNAKE_RAM/updateRAMDataOut[1]
    RAMB36_X1Y6          RAMB36E1                                     r  RAMCTRL/SNAKE_RAM/mem_reg_4_0/DIADI[1]
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.868     2.027    RAMCTRL/SNAKE_RAM/H125MHz_IBUF_BUFG
    RAMB36_X1Y6          RAMB36E1                                     r  RAMCTRL/SNAKE_RAM/mem_reg_4_0/CLKARDCLK
                         clock pessimism             -0.499     1.528    
    RAMB36_X1Y6          RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[1])
                                                      0.296     1.824    RAMCTRL/SNAKE_RAM/mem_reg_4_0
  -------------------------------------------------------------------
                         required time                         -1.824    
                         arrival time                           1.943    
  -------------------------------------------------------------------
                         slack                                  0.119    

Slack (MET) :             0.132ns  (arrival time - required time)
  Source:                 UPD/dataOut_reg[23]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            RAMCTRL/SNAKE_RAM/mem_reg_5_1/DIADI[5]
                            (rising edge-triggered cell RAMB18E1 clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             sys_clk_pin
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        0.488ns  (logic 0.164ns (33.629%)  route 0.324ns (66.371%))
  Logic Levels:           0  
  Clock Path Skew:        0.059ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.028ns
    Source Clock Delay      (SCD):    1.469ns
    Clock Pessimism Removal (CPR):    0.500ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.557     1.469    UPD/H125MHz_IBUF_BUFG
    SLICE_X34Y30         FDRE                                         r  UPD/dataOut_reg[23]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X34Y30         FDRE (Prop_fdre_C_Q)         0.164     1.633 r  UPD/dataOut_reg[23]/Q
                         net (fo=9, routed)           0.324     1.956    RAMCTRL/SNAKE_RAM/updateRAMDataOut[23]
    RAMB18_X2Y13         RAMB18E1                                     r  RAMCTRL/SNAKE_RAM/mem_reg_5_1/DIADI[5]
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.869     2.028    RAMCTRL/SNAKE_RAM/H125MHz_IBUF_BUFG
    RAMB18_X2Y13         RAMB18E1                                     r  RAMCTRL/SNAKE_RAM/mem_reg_5_1/CLKARDCLK
                         clock pessimism             -0.500     1.528    
    RAMB18_X2Y13         RAMB18E1 (Hold_ramb18e1_CLKARDCLK_DIADI[5])
                                                      0.296     1.824    RAMCTRL/SNAKE_RAM/mem_reg_5_1
  -------------------------------------------------------------------
                         required time                         -1.824    
                         arrival time                           1.956    
  -------------------------------------------------------------------
                         slack                                  0.132    

Slack (MET) :             0.133ns  (arrival time - required time)
  Source:                 UPD/dataOut_reg[16]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            RAMCTRL/SNAKE_RAM/mem_reg_2_0/DIPADIP[0]
                            (rising edge-triggered cell RAMB36E1 clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             sys_clk_pin
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        0.501ns  (logic 0.164ns (32.705%)  route 0.337ns (67.295%))
  Logic Levels:           0  
  Clock Path Skew:        0.072ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.019ns
    Source Clock Delay      (SCD):    1.467ns
    Clock Pessimism Removal (CPR):    0.480ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.555     1.467    UPD/H125MHz_IBUF_BUFG
    SLICE_X30Y27         FDRE                                         r  UPD/dataOut_reg[16]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X30Y27         FDRE (Prop_fdre_C_Q)         0.164     1.631 r  UPD/dataOut_reg[16]/Q
                         net (fo=9, routed)           0.337     1.968    RAMCTRL/SNAKE_RAM/updateRAMDataOut[16]
    RAMB36_X1Y4          RAMB36E1                                     r  RAMCTRL/SNAKE_RAM/mem_reg_2_0/DIPADIP[0]
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.860     2.019    RAMCTRL/SNAKE_RAM/H125MHz_IBUF_BUFG
    RAMB36_X1Y4          RAMB36E1                                     r  RAMCTRL/SNAKE_RAM/mem_reg_2_0/CLKARDCLK
                         clock pessimism             -0.480     1.539    
    RAMB36_X1Y4          RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIPADIP[0])
                                                      0.296     1.835    RAMCTRL/SNAKE_RAM/mem_reg_2_0
  -------------------------------------------------------------------
                         required time                         -1.835    
                         arrival time                           1.968    
  -------------------------------------------------------------------
                         slack                                  0.133    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         sys_clk_pin
Waveform(ns):       { 0.000 4.000 }
Period(ns):         8.000
Sources:            { H125MHz }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period        n/a     RAMB18E1/CLKARDCLK  n/a            2.576         8.000       5.424      RAMB18_X1Y10     RAMCTRL/SNAKE_RAM/mem_reg_1_1/CLKARDCLK
Min Period        n/a     RAMB18E1/CLKBWRCLK  n/a            2.576         8.000       5.424      RAMB18_X1Y10     RAMCTRL/SNAKE_RAM/mem_reg_1_1/CLKBWRCLK
Min Period        n/a     RAMB18E1/CLKARDCLK  n/a            2.576         8.000       5.424      RAMB18_X0Y14     RAMCTRL/SNAKE_RAM/mem_reg_3_1/CLKARDCLK
Min Period        n/a     RAMB18E1/CLKBWRCLK  n/a            2.576         8.000       5.424      RAMB18_X0Y14     RAMCTRL/SNAKE_RAM/mem_reg_3_1/CLKBWRCLK
Min Period        n/a     RAMB18E1/CLKARDCLK  n/a            2.576         8.000       5.424      RAMB18_X2Y13     RAMCTRL/SNAKE_RAM/mem_reg_5_1/CLKARDCLK
Min Period        n/a     RAMB18E1/CLKBWRCLK  n/a            2.576         8.000       5.424      RAMB18_X2Y13     RAMCTRL/SNAKE_RAM/mem_reg_5_1/CLKBWRCLK
Min Period        n/a     RAMB18E1/CLKARDCLK  n/a            2.576         8.000       5.424      RAMB18_X0Y16     RAMCTRL/SNAKE_RAM/mem_reg_7_1/CLKARDCLK
Min Period        n/a     RAMB18E1/CLKBWRCLK  n/a            2.576         8.000       5.424      RAMB18_X0Y16     RAMCTRL/SNAKE_RAM/mem_reg_7_1/CLKBWRCLK
Min Period        n/a     RAMB18E1/CLKARDCLK  n/a            2.576         8.000       5.424      RAMB18_X1Y7      RAMCTRL/SNAKE_RAM/mem_reg_9_1/CLKARDCLK
Min Period        n/a     RAMB18E1/CLKBWRCLK  n/a            2.576         8.000       5.424      RAMB18_X1Y7      RAMCTRL/SNAKE_RAM/mem_reg_9_1/CLKBWRCLK
Max Period        n/a     MMCME2_ADV/CLKIN1   n/a            100.000       8.000       92.000     MMCME2_ADV_X0Y0  U0/inst/mmcm_adv_inst/CLKIN1
Low Pulse Width   Slow    MMCME2_ADV/CLKIN1   n/a            2.000         4.000       2.000      MMCME2_ADV_X0Y0  U0/inst/mmcm_adv_inst/CLKIN1
Low Pulse Width   Fast    MMCME2_ADV/CLKIN1   n/a            2.000         4.000       2.000      MMCME2_ADV_X0Y0  U0/inst/mmcm_adv_inst/CLKIN1
Low Pulse Width   Slow    FDRE/C              n/a            0.500         4.000       3.500      SLICE_X24Y51     APPLE/Xpos_reg[4]/C
Low Pulse Width   Fast    FDRE/C              n/a            0.500         4.000       3.500      SLICE_X24Y51     APPLE/Xpos_reg[4]/C
Low Pulse Width   Slow    FDRE/C              n/a            0.500         4.000       3.500      SLICE_X23Y52     APPLE/Xpos_reg[5]/C
Low Pulse Width   Fast    FDRE/C              n/a            0.500         4.000       3.500      SLICE_X23Y52     APPLE/Xpos_reg[5]/C
Low Pulse Width   Slow    FDRE/C              n/a            0.500         4.000       3.500      SLICE_X24Y50     APPLE/Xpos_reg[6]/C
Low Pulse Width   Fast    FDRE/C              n/a            0.500         4.000       3.500      SLICE_X24Y50     APPLE/Xpos_reg[6]/C
Low Pulse Width   Slow    FDRE/C              n/a            0.500         4.000       3.500      SLICE_X24Y46     APPLE/Xpos_reg[8]/C
Low Pulse Width   Slow    FDRE/C              n/a            0.500         4.000       3.500      SLICE_X24Y46     APPLE/Xpos_reg[9]/C
High Pulse Width  Fast    MMCME2_ADV/CLKIN1   n/a            2.000         4.000       2.000      MMCME2_ADV_X0Y0  U0/inst/mmcm_adv_inst/CLKIN1
High Pulse Width  Slow    MMCME2_ADV/CLKIN1   n/a            2.000         4.000       2.000      MMCME2_ADV_X0Y0  U0/inst/mmcm_adv_inst/CLKIN1
High Pulse Width  Fast    FDRE/C              n/a            0.500         4.000       3.500      SLICE_X38Y32     APPLE/Xpos_reg[3]/C
High Pulse Width  Slow    FDRE/C              n/a            0.500         4.000       3.500      SLICE_X27Y46     APPLE/Xpos_reg[7]/C
High Pulse Width  Fast    FDRE/C              n/a            0.500         4.000       3.500      SLICE_X27Y46     APPLE/Xpos_reg[7]/C
High Pulse Width  Slow    FDRE/C              n/a            0.500         4.000       3.500      SLICE_X22Y61     RAMCTRL/clkCount_reg[0]/C
High Pulse Width  Fast    FDRE/C              n/a            0.500         4.000       3.500      SLICE_X22Y61     RAMCTRL/clkCount_reg[0]/C
High Pulse Width  Slow    FDSE/C              n/a            0.500         4.000       3.500      SLICE_X35Y25     UPD/matDataOut_reg[10]/C
High Pulse Width  Fast    FDSE/C              n/a            0.500         4.000       3.500      SLICE_X35Y25     UPD/matDataOut_reg[10]/C
High Pulse Width  Slow    FDSE/C              n/a            0.500         4.000       3.500      SLICE_X35Y25     UPD/matDataOut_reg[2]/C



---------------------------------------------------------------------------------------------------
From Clock:  clk_out1_clk_wiz_0
  To Clock:  clk_out1_clk_wiz_0

Setup :            0  Failing Endpoints,  Worst Slack       31.182ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.264ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack       19.500ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             31.182ns  (required time - arrival time)
  Source:                 SYNC/comptX_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            APPLE/ROMAddress_reg[7]/CE
                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             clk_out1_clk_wiz_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            40.000ns  (clk_out1_clk_wiz_0 rise@40.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        8.299ns  (logic 1.699ns (20.472%)  route 6.600ns (79.528%))
  Logic Levels:           6  (CARRY4=2 LUT3=1 LUT4=1 LUT5=1 LUT6=1)
  Clock Path Skew:        -0.203ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.892ns = ( 44.892 - 40.000 ) 
    Source Clock Delay      (SCD):    5.385ns
    Clock Pessimism Removal (CPR):    0.291ns
  Clock Uncertainty:      0.147ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491     1.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076     3.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101     3.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.680     5.348    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.538     1.810 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.760     3.570    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.101     3.671 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.714     5.385    SYNC/clk_out1
    SLICE_X5Y28          FDRE                                         r  SYNC/comptX_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X5Y28          FDRE (Prop_fdre_C_Q)         0.456     5.841 r  SYNC/comptX_reg[6]/Q
                         net (fo=13, routed)          0.640     6.481    SYNC/comptX_reg[6]
    SLICE_X11Y28         LUT3 (Prop_lut3_I2_O)        0.124     6.605 r  SYNC/comptY[9]_i_4/O
                         net (fo=10, routed)          0.936     7.541    SYNC/comptY[9]_i_4_n_0
    SLICE_X4Y28          LUT5 (Prop_lut5_I4_O)        0.124     7.665 r  SYNC/cCaseX[3]_i_1/O
                         net (fo=70, routed)          2.900    10.565    APPLE/Xi[7]
    SLICE_X22Y39         LUT6 (Prop_lut6_I1_O)        0.124    10.689 r  APPLE/pommeHere_i_24/O
                         net (fo=1, routed)           0.591    11.281    APPLE/pommeHere_i_24_n_0
    SLICE_X23Y39         CARRY4 (Prop_carry4_DI[3]_CO[3])
                                                      0.385    11.666 r  APPLE/pommeHere_reg_i_6/CO[3]
                         net (fo=1, routed)           0.000    11.666    APPLE/pommeHere_reg_i_6_n_0
    SLICE_X23Y40         CARRY4 (Prop_carry4_CI_CO[1])
                                                      0.157    11.823 r  APPLE/pommeHere_reg_i_2/CO[1]
                         net (fo=1, routed)           0.715    12.538    APPLE/pommeHere30_in
    SLICE_X25Y39         LUT4 (Prop_lut4_I0_O)        0.329    12.867 r  APPLE/pommeHere_i_1/O
                         net (fo=9, routed)           0.818    13.684    APPLE/pommeHere0
    SLICE_X28Y40         FDRE                                         r  APPLE/ROMAddress_reg[7]/CE
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                     40.000    40.000 r  
    L16                                               0.000    40.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    40.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421    41.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    43.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    43.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.490    44.882    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.177    41.705 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.599    43.304    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    43.395 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.497    44.892    APPLE/clk_out1
    SLICE_X28Y40         FDRE                                         r  APPLE/ROMAddress_reg[7]/C
                         clock pessimism              0.291    45.183    
                         clock uncertainty           -0.147    45.035    
    SLICE_X28Y40         FDRE (Setup_fdre_C_CE)      -0.169    44.866    APPLE/ROMAddress_reg[7]
  -------------------------------------------------------------------
                         required time                         44.866    
                         arrival time                         -13.684    
  -------------------------------------------------------------------
                         slack                                 31.182    

Slack (MET) :             31.216ns  (required time - arrival time)
  Source:                 SYNC/comptX_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            APPLE/ROMAddress_reg[3]/CE
                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             clk_out1_clk_wiz_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            40.000ns  (clk_out1_clk_wiz_0 rise@40.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        8.265ns  (logic 1.699ns (20.555%)  route 6.566ns (79.445%))
  Logic Levels:           6  (CARRY4=2 LUT3=1 LUT4=1 LUT5=1 LUT6=1)
  Clock Path Skew:        -0.203ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.892ns = ( 44.892 - 40.000 ) 
    Source Clock Delay      (SCD):    5.385ns
    Clock Pessimism Removal (CPR):    0.291ns
  Clock Uncertainty:      0.147ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491     1.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076     3.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101     3.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.680     5.348    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.538     1.810 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.760     3.570    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.101     3.671 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.714     5.385    SYNC/clk_out1
    SLICE_X5Y28          FDRE                                         r  SYNC/comptX_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X5Y28          FDRE (Prop_fdre_C_Q)         0.456     5.841 r  SYNC/comptX_reg[6]/Q
                         net (fo=13, routed)          0.640     6.481    SYNC/comptX_reg[6]
    SLICE_X11Y28         LUT3 (Prop_lut3_I2_O)        0.124     6.605 r  SYNC/comptY[9]_i_4/O
                         net (fo=10, routed)          0.936     7.541    SYNC/comptY[9]_i_4_n_0
    SLICE_X4Y28          LUT5 (Prop_lut5_I4_O)        0.124     7.665 r  SYNC/cCaseX[3]_i_1/O
                         net (fo=70, routed)          2.900    10.565    APPLE/Xi[7]
    SLICE_X22Y39         LUT6 (Prop_lut6_I1_O)        0.124    10.689 r  APPLE/pommeHere_i_24/O
                         net (fo=1, routed)           0.591    11.281    APPLE/pommeHere_i_24_n_0
    SLICE_X23Y39         CARRY4 (Prop_carry4_DI[3]_CO[3])
                                                      0.385    11.666 r  APPLE/pommeHere_reg_i_6/CO[3]
                         net (fo=1, routed)           0.000    11.666    APPLE/pommeHere_reg_i_6_n_0
    SLICE_X23Y40         CARRY4 (Prop_carry4_CI_CO[1])
                                                      0.157    11.823 r  APPLE/pommeHere_reg_i_2/CO[1]
                         net (fo=1, routed)           0.715    12.538    APPLE/pommeHere30_in
    SLICE_X25Y39         LUT4 (Prop_lut4_I0_O)        0.329    12.867 r  APPLE/pommeHere_i_1/O
                         net (fo=9, routed)           0.784    13.651    APPLE/pommeHere0
    SLICE_X30Y39         FDRE                                         r  APPLE/ROMAddress_reg[3]/CE
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                     40.000    40.000 r  
    L16                                               0.000    40.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    40.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421    41.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    43.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    43.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.490    44.882    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.177    41.705 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.599    43.304    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    43.395 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.497    44.892    APPLE/clk_out1
    SLICE_X30Y39         FDRE                                         r  APPLE/ROMAddress_reg[3]/C
                         clock pessimism              0.291    45.183    
                         clock uncertainty           -0.147    45.035    
    SLICE_X30Y39         FDRE (Setup_fdre_C_CE)      -0.169    44.866    APPLE/ROMAddress_reg[3]
  -------------------------------------------------------------------
                         required time                         44.866    
                         arrival time                         -13.651    
  -------------------------------------------------------------------
                         slack                                 31.216    

Slack (MET) :             31.360ns  (required time - arrival time)
  Source:                 SYNC/comptX_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            APPLE/ROMAddress_reg[0]/CE
                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             clk_out1_clk_wiz_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            40.000ns  (clk_out1_clk_wiz_0 rise@40.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        8.085ns  (logic 1.699ns (21.013%)  route 6.386ns (78.987%))
  Logic Levels:           6  (CARRY4=2 LUT3=1 LUT4=1 LUT5=1 LUT6=1)
  Clock Path Skew:        -0.203ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.892ns = ( 44.892 - 40.000 ) 
    Source Clock Delay      (SCD):    5.385ns
    Clock Pessimism Removal (CPR):    0.291ns
  Clock Uncertainty:      0.147ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491     1.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076     3.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101     3.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.680     5.348    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.538     1.810 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.760     3.570    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.101     3.671 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.714     5.385    SYNC/clk_out1
    SLICE_X5Y28          FDRE                                         r  SYNC/comptX_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X5Y28          FDRE (Prop_fdre_C_Q)         0.456     5.841 r  SYNC/comptX_reg[6]/Q
                         net (fo=13, routed)          0.640     6.481    SYNC/comptX_reg[6]
    SLICE_X11Y28         LUT3 (Prop_lut3_I2_O)        0.124     6.605 r  SYNC/comptY[9]_i_4/O
                         net (fo=10, routed)          0.936     7.541    SYNC/comptY[9]_i_4_n_0
    SLICE_X4Y28          LUT5 (Prop_lut5_I4_O)        0.124     7.665 r  SYNC/cCaseX[3]_i_1/O
                         net (fo=70, routed)          2.900    10.565    APPLE/Xi[7]
    SLICE_X22Y39         LUT6 (Prop_lut6_I1_O)        0.124    10.689 r  APPLE/pommeHere_i_24/O
                         net (fo=1, routed)           0.591    11.281    APPLE/pommeHere_i_24_n_0
    SLICE_X23Y39         CARRY4 (Prop_carry4_DI[3]_CO[3])
                                                      0.385    11.666 r  APPLE/pommeHere_reg_i_6/CO[3]
                         net (fo=1, routed)           0.000    11.666    APPLE/pommeHere_reg_i_6_n_0
    SLICE_X23Y40         CARRY4 (Prop_carry4_CI_CO[1])
                                                      0.157    11.823 r  APPLE/pommeHere_reg_i_2/CO[1]
                         net (fo=1, routed)           0.715    12.538    APPLE/pommeHere30_in
    SLICE_X25Y39         LUT4 (Prop_lut4_I0_O)        0.329    12.867 r  APPLE/pommeHere_i_1/O
                         net (fo=9, routed)           0.604    13.471    APPLE/pommeHere0
    SLICE_X29Y39         FDRE                                         r  APPLE/ROMAddress_reg[0]/CE
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                     40.000    40.000 r  
    L16                                               0.000    40.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    40.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421    41.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    43.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    43.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.490    44.882    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.177    41.705 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.599    43.304    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    43.395 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.497    44.892    APPLE/clk_out1
    SLICE_X29Y39         FDRE                                         r  APPLE/ROMAddress_reg[0]/C
                         clock pessimism              0.291    45.183    
                         clock uncertainty           -0.147    45.035    
    SLICE_X29Y39         FDRE (Setup_fdre_C_CE)      -0.205    44.830    APPLE/ROMAddress_reg[0]
  -------------------------------------------------------------------
                         required time                         44.830    
                         arrival time                         -13.471    
  -------------------------------------------------------------------
                         slack                                 31.360    

Slack (MET) :             31.360ns  (required time - arrival time)
  Source:                 SYNC/comptX_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            APPLE/ROMAddress_reg[1]/CE
                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             clk_out1_clk_wiz_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            40.000ns  (clk_out1_clk_wiz_0 rise@40.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        8.085ns  (logic 1.699ns (21.013%)  route 6.386ns (78.987%))
  Logic Levels:           6  (CARRY4=2 LUT3=1 LUT4=1 LUT5=1 LUT6=1)
  Clock Path Skew:        -0.203ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.892ns = ( 44.892 - 40.000 ) 
    Source Clock Delay      (SCD):    5.385ns
    Clock Pessimism Removal (CPR):    0.291ns
  Clock Uncertainty:      0.147ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491     1.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076     3.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101     3.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.680     5.348    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.538     1.810 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.760     3.570    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.101     3.671 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.714     5.385    SYNC/clk_out1
    SLICE_X5Y28          FDRE                                         r  SYNC/comptX_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X5Y28          FDRE (Prop_fdre_C_Q)         0.456     5.841 r  SYNC/comptX_reg[6]/Q
                         net (fo=13, routed)          0.640     6.481    SYNC/comptX_reg[6]
    SLICE_X11Y28         LUT3 (Prop_lut3_I2_O)        0.124     6.605 r  SYNC/comptY[9]_i_4/O
                         net (fo=10, routed)          0.936     7.541    SYNC/comptY[9]_i_4_n_0
    SLICE_X4Y28          LUT5 (Prop_lut5_I4_O)        0.124     7.665 r  SYNC/cCaseX[3]_i_1/O
                         net (fo=70, routed)          2.900    10.565    APPLE/Xi[7]
    SLICE_X22Y39         LUT6 (Prop_lut6_I1_O)        0.124    10.689 r  APPLE/pommeHere_i_24/O
                         net (fo=1, routed)           0.591    11.281    APPLE/pommeHere_i_24_n_0
    SLICE_X23Y39         CARRY4 (Prop_carry4_DI[3]_CO[3])
                                                      0.385    11.666 r  APPLE/pommeHere_reg_i_6/CO[3]
                         net (fo=1, routed)           0.000    11.666    APPLE/pommeHere_reg_i_6_n_0
    SLICE_X23Y40         CARRY4 (Prop_carry4_CI_CO[1])
                                                      0.157    11.823 r  APPLE/pommeHere_reg_i_2/CO[1]
                         net (fo=1, routed)           0.715    12.538    APPLE/pommeHere30_in
    SLICE_X25Y39         LUT4 (Prop_lut4_I0_O)        0.329    12.867 r  APPLE/pommeHere_i_1/O
                         net (fo=9, routed)           0.604    13.471    APPLE/pommeHere0
    SLICE_X29Y39         FDRE                                         r  APPLE/ROMAddress_reg[1]/CE
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                     40.000    40.000 r  
    L16                                               0.000    40.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    40.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421    41.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    43.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    43.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.490    44.882    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.177    41.705 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.599    43.304    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    43.395 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.497    44.892    APPLE/clk_out1
    SLICE_X29Y39         FDRE                                         r  APPLE/ROMAddress_reg[1]/C
                         clock pessimism              0.291    45.183    
                         clock uncertainty           -0.147    45.035    
    SLICE_X29Y39         FDRE (Setup_fdre_C_CE)      -0.205    44.830    APPLE/ROMAddress_reg[1]
  -------------------------------------------------------------------
                         required time                         44.830    
                         arrival time                         -13.471    
  -------------------------------------------------------------------
                         slack                                 31.360    

Slack (MET) :             31.396ns  (required time - arrival time)
  Source:                 SYNC/comptX_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            APPLE/ROMAddress_reg[2]/CE
                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             clk_out1_clk_wiz_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            40.000ns  (clk_out1_clk_wiz_0 rise@40.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        8.085ns  (logic 1.699ns (21.013%)  route 6.386ns (78.987%))
  Logic Levels:           6  (CARRY4=2 LUT3=1 LUT4=1 LUT5=1 LUT6=1)
  Clock Path Skew:        -0.203ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.892ns = ( 44.892 - 40.000 ) 
    Source Clock Delay      (SCD):    5.385ns
    Clock Pessimism Removal (CPR):    0.291ns
  Clock Uncertainty:      0.147ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491     1.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076     3.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101     3.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.680     5.348    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.538     1.810 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.760     3.570    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.101     3.671 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.714     5.385    SYNC/clk_out1
    SLICE_X5Y28          FDRE                                         r  SYNC/comptX_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X5Y28          FDRE (Prop_fdre_C_Q)         0.456     5.841 r  SYNC/comptX_reg[6]/Q
                         net (fo=13, routed)          0.640     6.481    SYNC/comptX_reg[6]
    SLICE_X11Y28         LUT3 (Prop_lut3_I2_O)        0.124     6.605 r  SYNC/comptY[9]_i_4/O
                         net (fo=10, routed)          0.936     7.541    SYNC/comptY[9]_i_4_n_0
    SLICE_X4Y28          LUT5 (Prop_lut5_I4_O)        0.124     7.665 r  SYNC/cCaseX[3]_i_1/O
                         net (fo=70, routed)          2.900    10.565    APPLE/Xi[7]
    SLICE_X22Y39         LUT6 (Prop_lut6_I1_O)        0.124    10.689 r  APPLE/pommeHere_i_24/O
                         net (fo=1, routed)           0.591    11.281    APPLE/pommeHere_i_24_n_0
    SLICE_X23Y39         CARRY4 (Prop_carry4_DI[3]_CO[3])
                                                      0.385    11.666 r  APPLE/pommeHere_reg_i_6/CO[3]
                         net (fo=1, routed)           0.000    11.666    APPLE/pommeHere_reg_i_6_n_0
    SLICE_X23Y40         CARRY4 (Prop_carry4_CI_CO[1])
                                                      0.157    11.823 r  APPLE/pommeHere_reg_i_2/CO[1]
                         net (fo=1, routed)           0.715    12.538    APPLE/pommeHere30_in
    SLICE_X25Y39         LUT4 (Prop_lut4_I0_O)        0.329    12.867 r  APPLE/pommeHere_i_1/O
                         net (fo=9, routed)           0.604    13.471    APPLE/pommeHere0
    SLICE_X28Y39         FDRE                                         r  APPLE/ROMAddress_reg[2]/CE
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                     40.000    40.000 r  
    L16                                               0.000    40.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    40.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421    41.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    43.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    43.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.490    44.882    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.177    41.705 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.599    43.304    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    43.395 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.497    44.892    APPLE/clk_out1
    SLICE_X28Y39         FDRE                                         r  APPLE/ROMAddress_reg[2]/C
                         clock pessimism              0.291    45.183    
                         clock uncertainty           -0.147    45.035    
    SLICE_X28Y39         FDRE (Setup_fdre_C_CE)      -0.169    44.866    APPLE/ROMAddress_reg[2]
  -------------------------------------------------------------------
                         required time                         44.866    
                         arrival time                         -13.471    
  -------------------------------------------------------------------
                         slack                                 31.396    

Slack (MET) :             31.396ns  (required time - arrival time)
  Source:                 SYNC/comptX_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            APPLE/ROMAddress_reg[4]/CE
                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             clk_out1_clk_wiz_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            40.000ns  (clk_out1_clk_wiz_0 rise@40.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        8.085ns  (logic 1.699ns (21.013%)  route 6.386ns (78.987%))
  Logic Levels:           6  (CARRY4=2 LUT3=1 LUT4=1 LUT5=1 LUT6=1)
  Clock Path Skew:        -0.203ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.892ns = ( 44.892 - 40.000 ) 
    Source Clock Delay      (SCD):    5.385ns
    Clock Pessimism Removal (CPR):    0.291ns
  Clock Uncertainty:      0.147ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491     1.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076     3.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101     3.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.680     5.348    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.538     1.810 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.760     3.570    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.101     3.671 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.714     5.385    SYNC/clk_out1
    SLICE_X5Y28          FDRE                                         r  SYNC/comptX_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X5Y28          FDRE (Prop_fdre_C_Q)         0.456     5.841 r  SYNC/comptX_reg[6]/Q
                         net (fo=13, routed)          0.640     6.481    SYNC/comptX_reg[6]
    SLICE_X11Y28         LUT3 (Prop_lut3_I2_O)        0.124     6.605 r  SYNC/comptY[9]_i_4/O
                         net (fo=10, routed)          0.936     7.541    SYNC/comptY[9]_i_4_n_0
    SLICE_X4Y28          LUT5 (Prop_lut5_I4_O)        0.124     7.665 r  SYNC/cCaseX[3]_i_1/O
                         net (fo=70, routed)          2.900    10.565    APPLE/Xi[7]
    SLICE_X22Y39         LUT6 (Prop_lut6_I1_O)        0.124    10.689 r  APPLE/pommeHere_i_24/O
                         net (fo=1, routed)           0.591    11.281    APPLE/pommeHere_i_24_n_0
    SLICE_X23Y39         CARRY4 (Prop_carry4_DI[3]_CO[3])
                                                      0.385    11.666 r  APPLE/pommeHere_reg_i_6/CO[3]
                         net (fo=1, routed)           0.000    11.666    APPLE/pommeHere_reg_i_6_n_0
    SLICE_X23Y40         CARRY4 (Prop_carry4_CI_CO[1])
                                                      0.157    11.823 r  APPLE/pommeHere_reg_i_2/CO[1]
                         net (fo=1, routed)           0.715    12.538    APPLE/pommeHere30_in
    SLICE_X25Y39         LUT4 (Prop_lut4_I0_O)        0.329    12.867 r  APPLE/pommeHere_i_1/O
                         net (fo=9, routed)           0.604    13.471    APPLE/pommeHere0
    SLICE_X28Y39         FDRE                                         r  APPLE/ROMAddress_reg[4]/CE
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                     40.000    40.000 r  
    L16                                               0.000    40.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    40.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421    41.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    43.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    43.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.490    44.882    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.177    41.705 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.599    43.304    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    43.395 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.497    44.892    APPLE/clk_out1
    SLICE_X28Y39         FDRE                                         r  APPLE/ROMAddress_reg[4]/C
                         clock pessimism              0.291    45.183    
                         clock uncertainty           -0.147    45.035    
    SLICE_X28Y39         FDRE (Setup_fdre_C_CE)      -0.169    44.866    APPLE/ROMAddress_reg[4]
  -------------------------------------------------------------------
                         required time                         44.866    
                         arrival time                         -13.471    
  -------------------------------------------------------------------
                         slack                                 31.396    

Slack (MET) :             31.396ns  (required time - arrival time)
  Source:                 SYNC/comptX_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            APPLE/ROMAddress_reg[5]/CE
                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             clk_out1_clk_wiz_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            40.000ns  (clk_out1_clk_wiz_0 rise@40.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        8.085ns  (logic 1.699ns (21.013%)  route 6.386ns (78.987%))
  Logic Levels:           6  (CARRY4=2 LUT3=1 LUT4=1 LUT5=1 LUT6=1)
  Clock Path Skew:        -0.203ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.892ns = ( 44.892 - 40.000 ) 
    Source Clock Delay      (SCD):    5.385ns
    Clock Pessimism Removal (CPR):    0.291ns
  Clock Uncertainty:      0.147ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491     1.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076     3.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101     3.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.680     5.348    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.538     1.810 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.760     3.570    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.101     3.671 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.714     5.385    SYNC/clk_out1
    SLICE_X5Y28          FDRE                                         r  SYNC/comptX_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X5Y28          FDRE (Prop_fdre_C_Q)         0.456     5.841 r  SYNC/comptX_reg[6]/Q
                         net (fo=13, routed)          0.640     6.481    SYNC/comptX_reg[6]
    SLICE_X11Y28         LUT3 (Prop_lut3_I2_O)        0.124     6.605 r  SYNC/comptY[9]_i_4/O
                         net (fo=10, routed)          0.936     7.541    SYNC/comptY[9]_i_4_n_0
    SLICE_X4Y28          LUT5 (Prop_lut5_I4_O)        0.124     7.665 r  SYNC/cCaseX[3]_i_1/O
                         net (fo=70, routed)          2.900    10.565    APPLE/Xi[7]
    SLICE_X22Y39         LUT6 (Prop_lut6_I1_O)        0.124    10.689 r  APPLE/pommeHere_i_24/O
                         net (fo=1, routed)           0.591    11.281    APPLE/pommeHere_i_24_n_0
    SLICE_X23Y39         CARRY4 (Prop_carry4_DI[3]_CO[3])
                                                      0.385    11.666 r  APPLE/pommeHere_reg_i_6/CO[3]
                         net (fo=1, routed)           0.000    11.666    APPLE/pommeHere_reg_i_6_n_0
    SLICE_X23Y40         CARRY4 (Prop_carry4_CI_CO[1])
                                                      0.157    11.823 r  APPLE/pommeHere_reg_i_2/CO[1]
                         net (fo=1, routed)           0.715    12.538    APPLE/pommeHere30_in
    SLICE_X25Y39         LUT4 (Prop_lut4_I0_O)        0.329    12.867 r  APPLE/pommeHere_i_1/O
                         net (fo=9, routed)           0.604    13.471    APPLE/pommeHere0
    SLICE_X28Y39         FDRE                                         r  APPLE/ROMAddress_reg[5]/CE
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                     40.000    40.000 r  
    L16                                               0.000    40.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    40.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421    41.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    43.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    43.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.490    44.882    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.177    41.705 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.599    43.304    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    43.395 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.497    44.892    APPLE/clk_out1
    SLICE_X28Y39         FDRE                                         r  APPLE/ROMAddress_reg[5]/C
                         clock pessimism              0.291    45.183    
                         clock uncertainty           -0.147    45.035    
    SLICE_X28Y39         FDRE (Setup_fdre_C_CE)      -0.169    44.866    APPLE/ROMAddress_reg[5]
  -------------------------------------------------------------------
                         required time                         44.866    
                         arrival time                         -13.471    
  -------------------------------------------------------------------
                         slack                                 31.396    

Slack (MET) :             31.396ns  (required time - arrival time)
  Source:                 SYNC/comptX_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            APPLE/ROMAddress_reg[6]/CE
                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             clk_out1_clk_wiz_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            40.000ns  (clk_out1_clk_wiz_0 rise@40.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        8.085ns  (logic 1.699ns (21.013%)  route 6.386ns (78.987%))
  Logic Levels:           6  (CARRY4=2 LUT3=1 LUT4=1 LUT5=1 LUT6=1)
  Clock Path Skew:        -0.203ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.892ns = ( 44.892 - 40.000 ) 
    Source Clock Delay      (SCD):    5.385ns
    Clock Pessimism Removal (CPR):    0.291ns
  Clock Uncertainty:      0.147ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491     1.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076     3.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101     3.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.680     5.348    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.538     1.810 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.760     3.570    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.101     3.671 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.714     5.385    SYNC/clk_out1
    SLICE_X5Y28          FDRE                                         r  SYNC/comptX_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X5Y28          FDRE (Prop_fdre_C_Q)         0.456     5.841 r  SYNC/comptX_reg[6]/Q
                         net (fo=13, routed)          0.640     6.481    SYNC/comptX_reg[6]
    SLICE_X11Y28         LUT3 (Prop_lut3_I2_O)        0.124     6.605 r  SYNC/comptY[9]_i_4/O
                         net (fo=10, routed)          0.936     7.541    SYNC/comptY[9]_i_4_n_0
    SLICE_X4Y28          LUT5 (Prop_lut5_I4_O)        0.124     7.665 r  SYNC/cCaseX[3]_i_1/O
                         net (fo=70, routed)          2.900    10.565    APPLE/Xi[7]
    SLICE_X22Y39         LUT6 (Prop_lut6_I1_O)        0.124    10.689 r  APPLE/pommeHere_i_24/O
                         net (fo=1, routed)           0.591    11.281    APPLE/pommeHere_i_24_n_0
    SLICE_X23Y39         CARRY4 (Prop_carry4_DI[3]_CO[3])
                                                      0.385    11.666 r  APPLE/pommeHere_reg_i_6/CO[3]
                         net (fo=1, routed)           0.000    11.666    APPLE/pommeHere_reg_i_6_n_0
    SLICE_X23Y40         CARRY4 (Prop_carry4_CI_CO[1])
                                                      0.157    11.823 r  APPLE/pommeHere_reg_i_2/CO[1]
                         net (fo=1, routed)           0.715    12.538    APPLE/pommeHere30_in
    SLICE_X25Y39         LUT4 (Prop_lut4_I0_O)        0.329    12.867 r  APPLE/pommeHere_i_1/O
                         net (fo=9, routed)           0.604    13.471    APPLE/pommeHere0
    SLICE_X28Y39         FDRE                                         r  APPLE/ROMAddress_reg[6]/CE
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                     40.000    40.000 r  
    L16                                               0.000    40.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    40.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421    41.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    43.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    43.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.490    44.882    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.177    41.705 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.599    43.304    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    43.395 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.497    44.892    APPLE/clk_out1
    SLICE_X28Y39         FDRE                                         r  APPLE/ROMAddress_reg[6]/C
                         clock pessimism              0.291    45.183    
                         clock uncertainty           -0.147    45.035    
    SLICE_X28Y39         FDRE (Setup_fdre_C_CE)      -0.169    44.866    APPLE/ROMAddress_reg[6]
  -------------------------------------------------------------------
                         required time                         44.866    
                         arrival time                         -13.471    
  -------------------------------------------------------------------
                         slack                                 31.396    

Slack (MET) :             31.539ns  (required time - arrival time)
  Source:                 SYNC/comptX_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            APPLE/pommeHere_reg/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             clk_out1_clk_wiz_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            40.000ns  (clk_out1_clk_wiz_0 rise@40.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        8.080ns  (logic 1.699ns (21.026%)  route 6.381ns (78.974%))
  Logic Levels:           6  (CARRY4=2 LUT3=1 LUT4=1 LUT5=1 LUT6=1)
  Clock Path Skew:        -0.203ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.892ns = ( 44.892 - 40.000 ) 
    Source Clock Delay      (SCD):    5.385ns
    Clock Pessimism Removal (CPR):    0.291ns
  Clock Uncertainty:      0.147ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491     1.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076     3.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101     3.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.680     5.348    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.538     1.810 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.760     3.570    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.101     3.671 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.714     5.385    SYNC/clk_out1
    SLICE_X5Y28          FDRE                                         r  SYNC/comptX_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X5Y28          FDRE (Prop_fdre_C_Q)         0.456     5.841 r  SYNC/comptX_reg[6]/Q
                         net (fo=13, routed)          0.640     6.481    SYNC/comptX_reg[6]
    SLICE_X11Y28         LUT3 (Prop_lut3_I2_O)        0.124     6.605 r  SYNC/comptY[9]_i_4/O
                         net (fo=10, routed)          0.936     7.541    SYNC/comptY[9]_i_4_n_0
    SLICE_X4Y28          LUT5 (Prop_lut5_I4_O)        0.124     7.665 r  SYNC/cCaseX[3]_i_1/O
                         net (fo=70, routed)          2.900    10.565    APPLE/Xi[7]
    SLICE_X22Y39         LUT6 (Prop_lut6_I1_O)        0.124    10.689 r  APPLE/pommeHere_i_24/O
                         net (fo=1, routed)           0.591    11.281    APPLE/pommeHere_i_24_n_0
    SLICE_X23Y39         CARRY4 (Prop_carry4_DI[3]_CO[3])
                                                      0.385    11.666 r  APPLE/pommeHere_reg_i_6/CO[3]
                         net (fo=1, routed)           0.000    11.666    APPLE/pommeHere_reg_i_6_n_0
    SLICE_X23Y40         CARRY4 (Prop_carry4_CI_CO[1])
                                                      0.157    11.823 r  APPLE/pommeHere_reg_i_2/CO[1]
                         net (fo=1, routed)           0.715    12.538    APPLE/pommeHere30_in
    SLICE_X25Y39         LUT4 (Prop_lut4_I0_O)        0.329    12.867 r  APPLE/pommeHere_i_1/O
                         net (fo=9, routed)           0.599    13.466    APPLE/pommeHere0
    SLICE_X30Y40         FDRE                                         r  APPLE/pommeHere_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                     40.000    40.000 r  
    L16                                               0.000    40.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    40.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421    41.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    43.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    43.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.490    44.882    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.177    41.705 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.599    43.304    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    43.395 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.497    44.892    APPLE/clk_out1
    SLICE_X30Y40         FDRE                                         r  APPLE/pommeHere_reg/C
                         clock pessimism              0.291    45.183    
                         clock uncertainty           -0.147    45.035    
    SLICE_X30Y40         FDRE (Setup_fdre_C_D)       -0.031    45.004    APPLE/pommeHere_reg
  -------------------------------------------------------------------
                         required time                         45.004    
                         arrival time                         -13.466    
  -------------------------------------------------------------------
                         slack                                 31.539    

Slack (MET) :             32.251ns  (required time - arrival time)
  Source:                 SYNC/comptY_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            APPLE/ROMAddress_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             clk_out1_clk_wiz_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            40.000ns  (clk_out1_clk_wiz_0 rise@40.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        7.564ns  (logic 2.555ns (33.777%)  route 5.009ns (66.223%))
  Logic Levels:           6  (CARRY4=3 LUT2=1 LUT5=1 LUT6=1)
  Clock Path Skew:        -0.147ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.892ns = ( 44.892 - 40.000 ) 
    Source Clock Delay      (SCD):    5.329ns
    Clock Pessimism Removal (CPR):    0.291ns
  Clock Uncertainty:      0.147ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491     1.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076     3.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101     3.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.680     5.348    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.538     1.810 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.760     3.570    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.101     3.671 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.658     5.329    SYNC/clk_out1
    SLICE_X15Y23         FDRE                                         r  SYNC/comptY_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X15Y23         FDRE (Prop_fdre_C_Q)         0.419     5.748 r  SYNC/comptY_reg[8]/Q
                         net (fo=12, routed)          0.878     6.626    SYNC/comptY_reg[8]
    SLICE_X15Y24         LUT6 (Prop_lut6_I1_O)        0.299     6.925 r  SYNC/ROMAddress[3]_i_10/O
                         net (fo=58, routed)          2.430     9.355    SYNC/comptY_reg[9]_0[0]
    SLICE_X25Y35         CARRY4 (Prop_carry4_DI[0]_O[2])
                                                      0.556     9.911 r  SYNC/ROMAddress_reg[3]_i_3/O[2]
                         net (fo=2, routed)           1.098    11.009    APPLE/A[2]
    SLICE_X29Y39         LUT5 (Prop_lut5_I0_O)        0.302    11.311 r  APPLE/ROMAddress[7]_i_5/O
                         net (fo=1, routed)           0.000    11.311    APPLE/ROMAddress[7]_i_5_n_0
    SLICE_X29Y39         CARRY4 (Prop_carry4_S[0]_O[1])
                                                      0.424    11.735 r  APPLE/ROMAddress_reg[7]_i_3/O[1]
                         net (fo=1, routed)           0.604    12.339    SYNC/ROMAddress_reg[7][1]
    SLICE_X28Y40         LUT2 (Prop_lut2_I1_O)        0.303    12.642 r  SYNC/ROMAddress[7]_i_2__0/O
                         net (fo=1, routed)           0.000    12.642    SYNC/ROMAddress[7]_i_2__0_n_0
    SLICE_X28Y40         CARRY4 (Prop_carry4_S[0]_O[0])
                                                      0.252    12.894 r  SYNC/ROMAddress_reg[7]_i_1__0/O[0]
                         net (fo=1, routed)           0.000    12.894    APPLE/D[4]
    SLICE_X28Y40         FDRE                                         r  APPLE/ROMAddress_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                     40.000    40.000 r  
    L16                                               0.000    40.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    40.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421    41.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    43.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    43.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.490    44.882    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.177    41.705 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.599    43.304    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    43.395 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.497    44.892    APPLE/clk_out1
    SLICE_X28Y40         FDRE                                         r  APPLE/ROMAddress_reg[7]/C
                         clock pessimism              0.291    45.183    
                         clock uncertainty           -0.147    45.035    
    SLICE_X28Y40         FDRE (Setup_fdre_C_D)        0.109    45.144    APPLE/ROMAddress_reg[7]
  -------------------------------------------------------------------
                         required time                         45.144    
                         arrival time                         -12.894    
  -------------------------------------------------------------------
                         slack                                 32.251    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.264ns  (arrival time - required time)
  Source:                 UPD_CLK_DIV/temp_reg[11]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            UPD_CLK_DIV/temp_reg[11]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             clk_out1_clk_wiz_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        0.369ns  (logic 0.249ns (67.412%)  route 0.120ns (32.588%))
  Logic Levels:           1  (CARRY4=1)
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.986ns
    Source Clock Delay      (SCD):    1.471ns
    Clock Pessimism Removal (CPR):    0.515ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.548     1.460    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.053     0.406 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.482     0.888    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.914 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.557     1.471    UPD_CLK_DIV/clk_out1
    SLICE_X33Y63         FDCE                                         r  UPD_CLK_DIV/temp_reg[11]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X33Y63         FDCE (Prop_fdce_C_Q)         0.141     1.612 r  UPD_CLK_DIV/temp_reg[11]/Q
                         net (fo=4, routed)           0.120     1.732    UPD_CLK_DIV/temp_reg[11]
    SLICE_X33Y63         CARRY4 (Prop_carry4_S[3]_O[3])
                                                      0.108     1.840 r  UPD_CLK_DIV/temp_reg[8]_i_1/O[3]
                         net (fo=1, routed)           0.000     1.840    UPD_CLK_DIV/temp_reg[8]_i_1_n_4
    SLICE_X33Y63         FDCE                                         r  UPD_CLK_DIV/temp_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.814     1.973    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.369     0.604 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.528     1.132    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.161 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.825     1.986    UPD_CLK_DIV/clk_out1
    SLICE_X33Y63         FDCE                                         r  UPD_CLK_DIV/temp_reg[11]/C
                         clock pessimism             -0.515     1.471    
    SLICE_X33Y63         FDCE (Hold_fdce_C_D)         0.105     1.576    UPD_CLK_DIV/temp_reg[11]
  -------------------------------------------------------------------
                         required time                         -1.576    
                         arrival time                           1.840    
  -------------------------------------------------------------------
                         slack                                  0.264    

Slack (MET) :             0.264ns  (arrival time - required time)
  Source:                 UPD_CLK_DIV/temp_reg[19]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            UPD_CLK_DIV/temp_reg[19]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             clk_out1_clk_wiz_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        0.369ns  (logic 0.249ns (67.412%)  route 0.120ns (32.588%))
  Logic Levels:           1  (CARRY4=1)
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.985ns
    Source Clock Delay      (SCD):    1.471ns
    Clock Pessimism Removal (CPR):    0.514ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.548     1.460    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.053     0.406 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.482     0.888    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.914 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.557     1.471    UPD_CLK_DIV/clk_out1
    SLICE_X33Y65         FDCE                                         r  UPD_CLK_DIV/temp_reg[19]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X33Y65         FDCE (Prop_fdce_C_Q)         0.141     1.612 r  UPD_CLK_DIV/temp_reg[19]/Q
                         net (fo=4, routed)           0.120     1.732    UPD_CLK_DIV/temp_reg[19]
    SLICE_X33Y65         CARRY4 (Prop_carry4_S[3]_O[3])
                                                      0.108     1.840 r  UPD_CLK_DIV/temp_reg[16]_i_1/O[3]
                         net (fo=1, routed)           0.000     1.840    UPD_CLK_DIV/temp_reg[16]_i_1_n_4
    SLICE_X33Y65         FDCE                                         r  UPD_CLK_DIV/temp_reg[19]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.814     1.973    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.369     0.604 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.528     1.132    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.161 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.824     1.985    UPD_CLK_DIV/clk_out1
    SLICE_X33Y65         FDCE                                         r  UPD_CLK_DIV/temp_reg[19]/C
                         clock pessimism             -0.514     1.471    
    SLICE_X33Y65         FDCE (Hold_fdce_C_D)         0.105     1.576    UPD_CLK_DIV/temp_reg[19]
  -------------------------------------------------------------------
                         required time                         -1.576    
                         arrival time                           1.840    
  -------------------------------------------------------------------
                         slack                                  0.264    

Slack (MET) :             0.264ns  (arrival time - required time)
  Source:                 UPD_CLK_DIV/temp_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            UPD_CLK_DIV/temp_reg[3]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             clk_out1_clk_wiz_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        0.369ns  (logic 0.249ns (67.412%)  route 0.120ns (32.588%))
  Logic Levels:           1  (CARRY4=1)
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.989ns
    Source Clock Delay      (SCD):    1.473ns
    Clock Pessimism Removal (CPR):    0.516ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.548     1.460    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.053     0.406 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.482     0.888    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.914 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.559     1.473    UPD_CLK_DIV/clk_out1
    SLICE_X33Y61         FDCE                                         r  UPD_CLK_DIV/temp_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X33Y61         FDCE (Prop_fdce_C_Q)         0.141     1.614 r  UPD_CLK_DIV/temp_reg[3]/Q
                         net (fo=4, routed)           0.120     1.734    UPD_CLK_DIV/temp_reg[3]
    SLICE_X33Y61         CARRY4 (Prop_carry4_S[3]_O[3])
                                                      0.108     1.842 r  UPD_CLK_DIV/temp_reg[0]_i_1/O[3]
                         net (fo=1, routed)           0.000     1.842    UPD_CLK_DIV/temp_reg[0]_i_1_n_4
    SLICE_X33Y61         FDCE                                         r  UPD_CLK_DIV/temp_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.814     1.973    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.369     0.604 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.528     1.132    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.161 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.828     1.989    UPD_CLK_DIV/clk_out1
    SLICE_X33Y61         FDCE                                         r  UPD_CLK_DIV/temp_reg[3]/C
                         clock pessimism             -0.516     1.473    
    SLICE_X33Y61         FDCE (Hold_fdce_C_D)         0.105     1.578    UPD_CLK_DIV/temp_reg[3]
  -------------------------------------------------------------------
                         required time                         -1.578    
                         arrival time                           1.842    
  -------------------------------------------------------------------
                         slack                                  0.264    

Slack (MET) :             0.268ns  (arrival time - required time)
  Source:                 UPD_CLK_DIV/temp_reg[20]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            UPD_CLK_DIV/temp_reg[20]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             clk_out1_clk_wiz_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        0.373ns  (logic 0.256ns (68.576%)  route 0.117ns (31.424%))
  Logic Levels:           1  (CARRY4=1)
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.984ns
    Source Clock Delay      (SCD):    1.470ns
    Clock Pessimism Removal (CPR):    0.514ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.548     1.460    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.053     0.406 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.482     0.888    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.914 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.556     1.470    UPD_CLK_DIV/clk_out1
    SLICE_X33Y66         FDCE                                         r  UPD_CLK_DIV/temp_reg[20]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X33Y66         FDCE (Prop_fdce_C_Q)         0.141     1.611 r  UPD_CLK_DIV/temp_reg[20]/Q
                         net (fo=4, routed)           0.117     1.728    UPD_CLK_DIV/temp_reg[20]
    SLICE_X33Y66         CARRY4 (Prop_carry4_S[0]_O[0])
                                                      0.115     1.843 r  UPD_CLK_DIV/temp_reg[20]_i_1/O[0]
                         net (fo=1, routed)           0.000     1.843    UPD_CLK_DIV/temp_reg[20]_i_1_n_7
    SLICE_X33Y66         FDCE                                         r  UPD_CLK_DIV/temp_reg[20]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.814     1.973    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.369     0.604 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.528     1.132    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.161 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.823     1.984    UPD_CLK_DIV/clk_out1
    SLICE_X33Y66         FDCE                                         r  UPD_CLK_DIV/temp_reg[20]/C
                         clock pessimism             -0.514     1.470    
    SLICE_X33Y66         FDCE (Hold_fdce_C_D)         0.105     1.575    UPD_CLK_DIV/temp_reg[20]
  -------------------------------------------------------------------
                         required time                         -1.575    
                         arrival time                           1.843    
  -------------------------------------------------------------------
                         slack                                  0.268    

Slack (MET) :             0.269ns  (arrival time - required time)
  Source:                 UPD_CLK_DIV/temp_reg[22]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            UPD_CLK_DIV/temp_reg[22]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             clk_out1_clk_wiz_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        0.374ns  (logic 0.252ns (67.467%)  route 0.122ns (32.533%))
  Logic Levels:           1  (CARRY4=1)
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.984ns
    Source Clock Delay      (SCD):    1.470ns
    Clock Pessimism Removal (CPR):    0.514ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.548     1.460    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.053     0.406 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.482     0.888    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.914 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.556     1.470    UPD_CLK_DIV/clk_out1
    SLICE_X33Y66         FDCE                                         r  UPD_CLK_DIV/temp_reg[22]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X33Y66         FDCE (Prop_fdce_C_Q)         0.141     1.611 r  UPD_CLK_DIV/temp_reg[22]/Q
                         net (fo=4, routed)           0.122     1.732    UPD_CLK_DIV/temp_reg[22]
    SLICE_X33Y66         CARRY4 (Prop_carry4_S[2]_O[2])
                                                      0.111     1.843 r  UPD_CLK_DIV/temp_reg[20]_i_1/O[2]
                         net (fo=1, routed)           0.000     1.843    UPD_CLK_DIV/temp_reg[20]_i_1_n_5
    SLICE_X33Y66         FDCE                                         r  UPD_CLK_DIV/temp_reg[22]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.814     1.973    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.369     0.604 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.528     1.132    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.161 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.823     1.984    UPD_CLK_DIV/clk_out1
    SLICE_X33Y66         FDCE                                         r  UPD_CLK_DIV/temp_reg[22]/C
                         clock pessimism             -0.514     1.470    
    SLICE_X33Y66         FDCE (Hold_fdce_C_D)         0.105     1.575    UPD_CLK_DIV/temp_reg[22]
  -------------------------------------------------------------------
                         required time                         -1.575    
                         arrival time                           1.843    
  -------------------------------------------------------------------
                         slack                                  0.269    

Slack (MET) :             0.269ns  (arrival time - required time)
  Source:                 UPD_CLK_DIV/temp_reg[6]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            UPD_CLK_DIV/temp_reg[6]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             clk_out1_clk_wiz_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        0.374ns  (logic 0.252ns (67.467%)  route 0.122ns (32.533%))
  Logic Levels:           1  (CARRY4=1)
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.987ns
    Source Clock Delay      (SCD):    1.472ns
    Clock Pessimism Removal (CPR):    0.515ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.548     1.460    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.053     0.406 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.482     0.888    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.914 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.558     1.472    UPD_CLK_DIV/clk_out1
    SLICE_X33Y62         FDCE                                         r  UPD_CLK_DIV/temp_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X33Y62         FDCE (Prop_fdce_C_Q)         0.141     1.613 r  UPD_CLK_DIV/temp_reg[6]/Q
                         net (fo=4, routed)           0.122     1.734    UPD_CLK_DIV/temp_reg[6]
    SLICE_X33Y62         CARRY4 (Prop_carry4_S[2]_O[2])
                                                      0.111     1.845 r  UPD_CLK_DIV/temp_reg[4]_i_1/O[2]
                         net (fo=1, routed)           0.000     1.845    UPD_CLK_DIV/temp_reg[4]_i_1_n_5
    SLICE_X33Y62         FDCE                                         r  UPD_CLK_DIV/temp_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.814     1.973    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.369     0.604 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.528     1.132    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.161 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.826     1.987    UPD_CLK_DIV/clk_out1
    SLICE_X33Y62         FDCE                                         r  UPD_CLK_DIV/temp_reg[6]/C
                         clock pessimism             -0.515     1.472    
    SLICE_X33Y62         FDCE (Hold_fdce_C_D)         0.105     1.577    UPD_CLK_DIV/temp_reg[6]
  -------------------------------------------------------------------
                         required time                         -1.577    
                         arrival time                           1.845    
  -------------------------------------------------------------------
                         slack                                  0.269    

Slack (MET) :             0.274ns  (arrival time - required time)
  Source:                 UPD_CLK_DIV/temp_reg[23]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            UPD_CLK_DIV/temp_reg[23]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             clk_out1_clk_wiz_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        0.379ns  (logic 0.249ns (65.656%)  route 0.130ns (34.344%))
  Logic Levels:           1  (CARRY4=1)
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.984ns
    Source Clock Delay      (SCD):    1.470ns
    Clock Pessimism Removal (CPR):    0.514ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.548     1.460    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.053     0.406 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.482     0.888    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.914 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.556     1.470    UPD_CLK_DIV/clk_out1
    SLICE_X33Y66         FDCE                                         r  UPD_CLK_DIV/temp_reg[23]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X33Y66         FDCE (Prop_fdce_C_Q)         0.141     1.611 r  UPD_CLK_DIV/temp_reg[23]/Q
                         net (fo=4, routed)           0.130     1.741    UPD_CLK_DIV/temp_reg[23]
    SLICE_X33Y66         CARRY4 (Prop_carry4_S[3]_O[3])
                                                      0.108     1.849 r  UPD_CLK_DIV/temp_reg[20]_i_1/O[3]
                         net (fo=1, routed)           0.000     1.849    UPD_CLK_DIV/temp_reg[20]_i_1_n_4
    SLICE_X33Y66         FDCE                                         r  UPD_CLK_DIV/temp_reg[23]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.814     1.973    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.369     0.604 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.528     1.132    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.161 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.823     1.984    UPD_CLK_DIV/clk_out1
    SLICE_X33Y66         FDCE                                         r  UPD_CLK_DIV/temp_reg[23]/C
                         clock pessimism             -0.514     1.470    
    SLICE_X33Y66         FDCE (Hold_fdce_C_D)         0.105     1.575    UPD_CLK_DIV/temp_reg[23]
  -------------------------------------------------------------------
                         required time                         -1.575    
                         arrival time                           1.849    
  -------------------------------------------------------------------
                         slack                                  0.274    

Slack (MET) :             0.275ns  (arrival time - required time)
  Source:                 UPD_CLK_DIV/temp_reg[15]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            UPD_CLK_DIV/temp_reg[15]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             clk_out1_clk_wiz_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        0.380ns  (logic 0.249ns (65.445%)  route 0.131ns (34.555%))
  Logic Levels:           1  (CARRY4=1)
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.986ns
    Source Clock Delay      (SCD):    1.471ns
    Clock Pessimism Removal (CPR):    0.515ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.548     1.460    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.053     0.406 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.482     0.888    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.914 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.557     1.471    UPD_CLK_DIV/clk_out1
    SLICE_X33Y64         FDCE                                         r  UPD_CLK_DIV/temp_reg[15]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X33Y64         FDCE (Prop_fdce_C_Q)         0.141     1.612 r  UPD_CLK_DIV/temp_reg[15]/Q
                         net (fo=4, routed)           0.131     1.743    UPD_CLK_DIV/temp_reg[15]
    SLICE_X33Y64         CARRY4 (Prop_carry4_S[3]_O[3])
                                                      0.108     1.851 r  UPD_CLK_DIV/temp_reg[12]_i_1/O[3]
                         net (fo=1, routed)           0.000     1.851    UPD_CLK_DIV/temp_reg[12]_i_1_n_4
    SLICE_X33Y64         FDCE                                         r  UPD_CLK_DIV/temp_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.814     1.973    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.369     0.604 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.528     1.132    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.161 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.825     1.986    UPD_CLK_DIV/clk_out1
    SLICE_X33Y64         FDCE                                         r  UPD_CLK_DIV/temp_reg[15]/C
                         clock pessimism             -0.515     1.471    
    SLICE_X33Y64         FDCE (Hold_fdce_C_D)         0.105     1.576    UPD_CLK_DIV/temp_reg[15]
  -------------------------------------------------------------------
                         required time                         -1.576    
                         arrival time                           1.851    
  -------------------------------------------------------------------
                         slack                                  0.275    

Slack (MET) :             0.276ns  (arrival time - required time)
  Source:                 UPD_CLK_DIV/temp_reg[7]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            UPD_CLK_DIV/temp_reg[7]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             clk_out1_clk_wiz_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        0.381ns  (logic 0.249ns (65.279%)  route 0.132ns (34.721%))
  Logic Levels:           1  (CARRY4=1)
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.987ns
    Source Clock Delay      (SCD):    1.472ns
    Clock Pessimism Removal (CPR):    0.515ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.548     1.460    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.053     0.406 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.482     0.888    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.914 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.558     1.472    UPD_CLK_DIV/clk_out1
    SLICE_X33Y62         FDCE                                         r  UPD_CLK_DIV/temp_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X33Y62         FDCE (Prop_fdce_C_Q)         0.141     1.613 r  UPD_CLK_DIV/temp_reg[7]/Q
                         net (fo=4, routed)           0.132     1.745    UPD_CLK_DIV/temp_reg[7]
    SLICE_X33Y62         CARRY4 (Prop_carry4_S[3]_O[3])
                                                      0.108     1.853 r  UPD_CLK_DIV/temp_reg[4]_i_1/O[3]
                         net (fo=1, routed)           0.000     1.853    UPD_CLK_DIV/temp_reg[4]_i_1_n_4
    SLICE_X33Y62         FDCE                                         r  UPD_CLK_DIV/temp_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.814     1.973    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.369     0.604 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.528     1.132    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.161 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.826     1.987    UPD_CLK_DIV/clk_out1
    SLICE_X33Y62         FDCE                                         r  UPD_CLK_DIV/temp_reg[7]/C
                         clock pessimism             -0.515     1.472    
    SLICE_X33Y62         FDCE (Hold_fdce_C_D)         0.105     1.577    UPD_CLK_DIV/temp_reg[7]
  -------------------------------------------------------------------
                         required time                         -1.577    
                         arrival time                           1.853    
  -------------------------------------------------------------------
                         slack                                  0.276    

Slack (MET) :             0.277ns  (arrival time - required time)
  Source:                 UPD_CLK_DIV/temp_reg[12]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            UPD_CLK_DIV/temp_reg[12]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             clk_out1_clk_wiz_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        0.382ns  (logic 0.256ns (66.944%)  route 0.126ns (33.056%))
  Logic Levels:           1  (CARRY4=1)
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.986ns
    Source Clock Delay      (SCD):    1.471ns
    Clock Pessimism Removal (CPR):    0.515ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.548     1.460    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.053     0.406 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.482     0.888    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.914 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.557     1.471    UPD_CLK_DIV/clk_out1
    SLICE_X33Y64         FDCE                                         r  UPD_CLK_DIV/temp_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X33Y64         FDCE (Prop_fdce_C_Q)         0.141     1.612 r  UPD_CLK_DIV/temp_reg[12]/Q
                         net (fo=4, routed)           0.126     1.738    UPD_CLK_DIV/temp_reg[12]
    SLICE_X33Y64         CARRY4 (Prop_carry4_S[0]_O[0])
                                                      0.115     1.853 r  UPD_CLK_DIV/temp_reg[12]_i_1/O[0]
                         net (fo=1, routed)           0.000     1.853    UPD_CLK_DIV/temp_reg[12]_i_1_n_7
    SLICE_X33Y64         FDCE                                         r  UPD_CLK_DIV/temp_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.814     1.973    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.369     0.604 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.528     1.132    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.161 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.825     1.986    UPD_CLK_DIV/clk_out1
    SLICE_X33Y64         FDCE                                         r  UPD_CLK_DIV/temp_reg[12]/C
                         clock pessimism             -0.515     1.471    
    SLICE_X33Y64         FDCE (Hold_fdce_C_D)         0.105     1.576    UPD_CLK_DIV/temp_reg[12]
  -------------------------------------------------------------------
                         required time                         -1.576    
                         arrival time                           1.853    
  -------------------------------------------------------------------
                         slack                                  0.277    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clk_out1_clk_wiz_0
Waveform(ns):       { 0.000 20.000 }
Period(ns):         40.000
Sources:            { U0/inst/mmcm_adv_inst/CLKOUT0 }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period        n/a     BUFG/I              n/a            2.155         40.000      37.845     BUFGCTRL_X0Y0    U0/inst/clkout1_buf/I
Min Period        n/a     MMCME2_ADV/CLKOUT0  n/a            1.249         40.000      38.751     MMCME2_ADV_X0Y0  U0/inst/mmcm_adv_inst/CLKOUT0
Min Period        n/a     FDRE/C              n/a            1.000         40.000      39.000     SLICE_X29Y39     APPLE/ROMAddress_reg[0]/C
Min Period        n/a     FDRE/C              n/a            1.000         40.000      39.000     SLICE_X29Y39     APPLE/ROMAddress_reg[1]/C
Min Period        n/a     FDRE/C              n/a            1.000         40.000      39.000     SLICE_X28Y39     APPLE/ROMAddress_reg[2]/C
Min Period        n/a     FDRE/C              n/a            1.000         40.000      39.000     SLICE_X30Y39     APPLE/ROMAddress_reg[3]/C
Min Period        n/a     FDRE/C              n/a            1.000         40.000      39.000     SLICE_X28Y39     APPLE/ROMAddress_reg[4]/C
Min Period        n/a     FDRE/C              n/a            1.000         40.000      39.000     SLICE_X28Y39     APPLE/ROMAddress_reg[5]/C
Min Period        n/a     FDRE/C              n/a            1.000         40.000      39.000     SLICE_X28Y39     APPLE/ROMAddress_reg[6]/C
Min Period        n/a     FDRE/C              n/a            1.000         40.000      39.000     SLICE_X28Y40     APPLE/ROMAddress_reg[7]/C
Max Period        n/a     MMCME2_ADV/CLKOUT0  n/a            213.360       40.000      173.360    MMCME2_ADV_X0Y0  U0/inst/mmcm_adv_inst/CLKOUT0
Low Pulse Width   Fast    FDRE/C              n/a            0.500         20.000      19.500     SLICE_X29Y39     APPLE/ROMAddress_reg[0]/C
Low Pulse Width   Fast    FDRE/C              n/a            0.500         20.000      19.500     SLICE_X29Y39     APPLE/ROMAddress_reg[1]/C
Low Pulse Width   Fast    FDRE/C              n/a            0.500         20.000      19.500     SLICE_X28Y39     APPLE/ROMAddress_reg[2]/C
Low Pulse Width   Fast    FDRE/C              n/a            0.500         20.000      19.500     SLICE_X30Y39     APPLE/ROMAddress_reg[3]/C
Low Pulse Width   Fast    FDRE/C              n/a            0.500         20.000      19.500     SLICE_X28Y39     APPLE/ROMAddress_reg[4]/C
Low Pulse Width   Fast    FDRE/C              n/a            0.500         20.000      19.500     SLICE_X28Y39     APPLE/ROMAddress_reg[5]/C
Low Pulse Width   Fast    FDRE/C              n/a            0.500         20.000      19.500     SLICE_X28Y39     APPLE/ROMAddress_reg[6]/C
Low Pulse Width   Fast    FDRE/C              n/a            0.500         20.000      19.500     SLICE_X10Y29     SYNC/comptX_reg[8]/C
Low Pulse Width   Fast    FDCE/C              n/a            0.500         20.000      19.500     SLICE_X33Y61     UPD_CLK_DIV/temp_reg[0]/C
Low Pulse Width   Fast    FDRE/C              n/a            0.500         20.000      19.500     SLICE_X10Y29     SYNC/comptX_reg[9]/C
High Pulse Width  Slow    FDRE/C              n/a            0.500         20.000      19.500     SLICE_X10Y29     SYNC/comptX_reg[8]/C
High Pulse Width  Slow    FDRE/C              n/a            0.500         20.000      19.500     SLICE_X10Y29     SYNC/comptX_reg[9]/C
High Pulse Width  Slow    FDRE/C              n/a            0.500         20.000      19.500     SLICE_X29Y39     APPLE/ROMAddress_reg[0]/C
High Pulse Width  Slow    FDRE/C              n/a            0.500         20.000      19.500     SLICE_X29Y39     APPLE/ROMAddress_reg[1]/C
High Pulse Width  Slow    FDRE/C              n/a            0.500         20.000      19.500     SLICE_X28Y39     APPLE/ROMAddress_reg[2]/C
High Pulse Width  Slow    FDRE/C              n/a            0.500         20.000      19.500     SLICE_X30Y39     APPLE/ROMAddress_reg[3]/C
High Pulse Width  Slow    FDRE/C              n/a            0.500         20.000      19.500     SLICE_X28Y39     APPLE/ROMAddress_reg[4]/C
High Pulse Width  Slow    FDRE/C              n/a            0.500         20.000      19.500     SLICE_X28Y39     APPLE/ROMAddress_reg[5]/C
High Pulse Width  Slow    FDRE/C              n/a            0.500         20.000      19.500     SLICE_X28Y39     APPLE/ROMAddress_reg[6]/C
High Pulse Width  Slow    FDRE/C              n/a            0.500         20.000      19.500     SLICE_X28Y40     APPLE/ROMAddress_reg[7]/C



---------------------------------------------------------------------------------------------------
From Clock:  clkfbout_clk_wiz_0
  To Clock:  clkfbout_clk_wiz_0

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack       37.845ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clkfbout_clk_wiz_0
Waveform(ns):       { 0.000 20.000 }
Period(ns):         40.000
Sources:            { U0/inst/mmcm_adv_inst/CLKFBOUT }

Check Type  Corner  Lib Pin              Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period  n/a     BUFG/I               n/a            2.155         40.000      37.845     BUFGCTRL_X0Y1    U0/inst/clkf_buf/I
Min Period  n/a     MMCME2_ADV/CLKFBOUT  n/a            1.249         40.000      38.751     MMCME2_ADV_X0Y0  U0/inst/mmcm_adv_inst/CLKFBOUT
Min Period  n/a     MMCME2_ADV/CLKFBIN   n/a            1.249         40.000      38.751     MMCME2_ADV_X0Y0  U0/inst/mmcm_adv_inst/CLKFBIN
Max Period  n/a     MMCME2_ADV/CLKFBIN   n/a            100.000       40.000      60.000     MMCME2_ADV_X0Y0  U0/inst/mmcm_adv_inst/CLKFBIN
Max Period  n/a     MMCME2_ADV/CLKFBOUT  n/a            213.360       40.000      173.360    MMCME2_ADV_X0Y0  U0/inst/mmcm_adv_inst/CLKFBOUT



---------------------------------------------------------------------------------------------------
From Clock:  clk_out1_clk_wiz_0
  To Clock:  sys_clk_pin

Setup :           21  Failing Endpoints,  Worst Slack       -4.144ns,  Total Violation      -56.046ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.121ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (VIOLATED) :        -4.144ns  (required time - arrival time)
  Source:                 SYNC/comptX_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            SNAKE/ROMAddress_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             sys_clk_pin
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (sys_clk_pin rise@8.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        11.648ns  (logic 3.857ns (33.113%)  route 7.791ns (66.887%))
  Logic Levels:           14  (CARRY4=5 LUT2=1 LUT3=1 LUT4=1 LUT5=2 LUT6=4)
  Clock Path Skew:        -0.212ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.897ns = ( 12.897 - 8.000 ) 
    Source Clock Delay      (SCD):    5.385ns
    Clock Pessimism Removal (CPR):    0.277ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491     1.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076     3.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101     3.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.680     5.348    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.538     1.810 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.760     3.570    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.101     3.671 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.714     5.385    SYNC/clk_out1
    SLICE_X5Y28          FDRE                                         r  SYNC/comptX_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X5Y28          FDRE (Prop_fdre_C_Q)         0.456     5.841 r  SYNC/comptX_reg[6]/Q
                         net (fo=13, routed)          0.640     6.481    SYNC/comptX_reg[6]
    SLICE_X11Y28         LUT3 (Prop_lut3_I2_O)        0.124     6.605 r  SYNC/comptY[9]_i_4/O
                         net (fo=10, routed)          0.869     7.474    SYNC/comptY[9]_i_4_n_0
    SLICE_X11Y28         LUT6 (Prop_lut6_I4_O)        0.124     7.598 r  SYNC/ROMAddress[0]_i_1/O
                         net (fo=59, routed)          0.962     8.560    RAMCTRL/SNAKE_RAM/Xi[0]
    SLICE_X14Y25         LUT2 (Prop_lut2_I1_O)        0.124     8.684 r  RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_900/O
                         net (fo=1, routed)           0.000     8.684    SYNC/ROMAddress[7]_i_166[0]
    SLICE_X14Y25         CARRY4 (Prop_carry4_S[0]_O[3])
                                                      0.606     9.290 r  SYNC/ROMAddress_reg[9]_i_752/O[3]
                         net (fo=5, routed)           0.994    10.284    RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_91_0[2]
    SLICE_X14Y28         LUT4 (Prop_lut4_I1_O)        0.306    10.590 r  RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_164/O
                         net (fo=1, routed)           0.000    10.590    RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_164_n_0
    SLICE_X14Y28         CARRY4 (Prop_carry4_S[3]_CO[3])
                                                      0.401    10.991 r  RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_91/CO[3]
                         net (fo=1, routed)           0.000    10.991    RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_91_n_0
    SLICE_X14Y29         CARRY4 (Prop_carry4_CI_O[0])
                                                      0.222    11.213 r  RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_200/O[0]
                         net (fo=6, routed)           0.805    12.018    RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_200_n_7
    SLICE_X17Y26         LUT5 (Prop_lut5_I2_O)        0.299    12.317 r  RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_199_comp/O
                         net (fo=1, routed)           1.348    13.665    RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_199_n_0
    SLICE_X4Y30          LUT6 (Prop_lut6_I3_O)        0.124    13.789 r  RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_51_comp_1/O
                         net (fo=1, routed)           1.090    14.879    RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_51_n_0
    SLICE_X7Y35          LUT6 (Prop_lut6_I2_O)        0.124    15.003 r  RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_14/O
                         net (fo=3, routed)           0.419    15.421    RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_14_n_0
    SLICE_X9Y34          LUT6 (Prop_lut6_I0_O)        0.124    15.545 r  RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_22/O
                         net (fo=1, routed)           0.665    16.210    RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_22_n_0
    SLICE_X8Y34          LUT5 (Prop_lut5_I3_O)        0.124    16.334 r  RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_6/O
                         net (fo=1, routed)           0.000    16.334    RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_6_n_0
    SLICE_X8Y34          CARRY4 (Prop_carry4_S[3]_CO[3])
                                                      0.376    16.710 r  RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_1/CO[3]
                         net (fo=1, routed)           0.000    16.710    RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_1_n_0
    SLICE_X8Y35          CARRY4 (Prop_carry4_CI_O[1])
                                                      0.323    17.033 r  RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_2/O[1]
                         net (fo=1, routed)           0.000    17.033    SNAKE/D[9]
    SLICE_X8Y35          FDRE                                         r  SNAKE/ROMAddress_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      8.000     8.000 r  
    L16                                               0.000     8.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     8.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421     9.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    11.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    11.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.505    12.897    SNAKE/H125MHz_IBUF_BUFG
    SLICE_X8Y35          FDRE                                         r  SNAKE/ROMAddress_reg[9]/C
                         clock pessimism              0.277    13.174    
                         clock uncertainty           -0.393    12.781    
    SLICE_X8Y35          FDRE (Setup_fdre_C_D)        0.109    12.890    SNAKE/ROMAddress_reg[9]
  -------------------------------------------------------------------
                         required time                         12.890    
                         arrival time                         -17.033    
  -------------------------------------------------------------------
                         slack                                 -4.144    

Slack (VIOLATED) :        -4.040ns  (required time - arrival time)
  Source:                 SYNC/comptX_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            SNAKE/ROMAddress_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             sys_clk_pin
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (sys_clk_pin rise@8.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        11.544ns  (logic 3.753ns (32.510%)  route 7.791ns (67.490%))
  Logic Levels:           14  (CARRY4=5 LUT2=1 LUT3=1 LUT4=1 LUT5=2 LUT6=4)
  Clock Path Skew:        -0.212ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.897ns = ( 12.897 - 8.000 ) 
    Source Clock Delay      (SCD):    5.385ns
    Clock Pessimism Removal (CPR):    0.277ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491     1.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076     3.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101     3.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.680     5.348    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.538     1.810 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.760     3.570    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.101     3.671 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.714     5.385    SYNC/clk_out1
    SLICE_X5Y28          FDRE                                         r  SYNC/comptX_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X5Y28          FDRE (Prop_fdre_C_Q)         0.456     5.841 r  SYNC/comptX_reg[6]/Q
                         net (fo=13, routed)          0.640     6.481    SYNC/comptX_reg[6]
    SLICE_X11Y28         LUT3 (Prop_lut3_I2_O)        0.124     6.605 r  SYNC/comptY[9]_i_4/O
                         net (fo=10, routed)          0.869     7.474    SYNC/comptY[9]_i_4_n_0
    SLICE_X11Y28         LUT6 (Prop_lut6_I4_O)        0.124     7.598 r  SYNC/ROMAddress[0]_i_1/O
                         net (fo=59, routed)          0.962     8.560    RAMCTRL/SNAKE_RAM/Xi[0]
    SLICE_X14Y25         LUT2 (Prop_lut2_I1_O)        0.124     8.684 r  RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_900/O
                         net (fo=1, routed)           0.000     8.684    SYNC/ROMAddress[7]_i_166[0]
    SLICE_X14Y25         CARRY4 (Prop_carry4_S[0]_O[3])
                                                      0.606     9.290 r  SYNC/ROMAddress_reg[9]_i_752/O[3]
                         net (fo=5, routed)           0.994    10.284    RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_91_0[2]
    SLICE_X14Y28         LUT4 (Prop_lut4_I1_O)        0.306    10.590 r  RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_164/O
                         net (fo=1, routed)           0.000    10.590    RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_164_n_0
    SLICE_X14Y28         CARRY4 (Prop_carry4_S[3]_CO[3])
                                                      0.401    10.991 r  RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_91/CO[3]
                         net (fo=1, routed)           0.000    10.991    RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_91_n_0
    SLICE_X14Y29         CARRY4 (Prop_carry4_CI_O[0])
                                                      0.222    11.213 r  RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_200/O[0]
                         net (fo=6, routed)           0.805    12.018    RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_200_n_7
    SLICE_X17Y26         LUT5 (Prop_lut5_I2_O)        0.299    12.317 r  RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_199_comp/O
                         net (fo=1, routed)           1.348    13.665    RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_199_n_0
    SLICE_X4Y30          LUT6 (Prop_lut6_I3_O)        0.124    13.789 r  RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_51_comp_1/O
                         net (fo=1, routed)           1.090    14.879    RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_51_n_0
    SLICE_X7Y35          LUT6 (Prop_lut6_I2_O)        0.124    15.003 r  RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_14/O
                         net (fo=3, routed)           0.419    15.421    RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_14_n_0
    SLICE_X9Y34          LUT6 (Prop_lut6_I0_O)        0.124    15.545 r  RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_22/O
                         net (fo=1, routed)           0.665    16.210    RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_22_n_0
    SLICE_X8Y34          LUT5 (Prop_lut5_I3_O)        0.124    16.334 r  RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_6/O
                         net (fo=1, routed)           0.000    16.334    RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_6_n_0
    SLICE_X8Y34          CARRY4 (Prop_carry4_S[3]_CO[3])
                                                      0.376    16.710 r  RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_1/CO[3]
                         net (fo=1, routed)           0.000    16.710    RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_1_n_0
    SLICE_X8Y35          CARRY4 (Prop_carry4_CI_O[0])
                                                      0.219    16.929 r  RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_2/O[0]
                         net (fo=1, routed)           0.000    16.929    SNAKE/D[8]
    SLICE_X8Y35          FDRE                                         r  SNAKE/ROMAddress_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      8.000     8.000 r  
    L16                                               0.000     8.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     8.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421     9.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    11.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    11.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.505    12.897    SNAKE/H125MHz_IBUF_BUFG
    SLICE_X8Y35          FDRE                                         r  SNAKE/ROMAddress_reg[8]/C
                         clock pessimism              0.277    13.174    
                         clock uncertainty           -0.393    12.781    
    SLICE_X8Y35          FDRE (Setup_fdre_C_D)        0.109    12.890    SNAKE/ROMAddress_reg[8]
  -------------------------------------------------------------------
                         required time                         12.890    
                         arrival time                         -16.929    
  -------------------------------------------------------------------
                         slack                                 -4.040    

Slack (VIOLATED) :        -3.701ns  (required time - arrival time)
  Source:                 SYNC/comptX_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            SNAKE/ROMAddress_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             sys_clk_pin
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (sys_clk_pin rise@8.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        11.204ns  (logic 3.413ns (30.462%)  route 7.791ns (69.538%))
  Logic Levels:           13  (CARRY4=4 LUT2=1 LUT3=1 LUT4=1 LUT5=2 LUT6=4)
  Clock Path Skew:        -0.213ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.896ns = ( 12.896 - 8.000 ) 
    Source Clock Delay      (SCD):    5.385ns
    Clock Pessimism Removal (CPR):    0.277ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491     1.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076     3.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101     3.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.680     5.348    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.538     1.810 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.760     3.570    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.101     3.671 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.714     5.385    SYNC/clk_out1
    SLICE_X5Y28          FDRE                                         r  SYNC/comptX_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X5Y28          FDRE (Prop_fdre_C_Q)         0.456     5.841 r  SYNC/comptX_reg[6]/Q
                         net (fo=13, routed)          0.640     6.481    SYNC/comptX_reg[6]
    SLICE_X11Y28         LUT3 (Prop_lut3_I2_O)        0.124     6.605 r  SYNC/comptY[9]_i_4/O
                         net (fo=10, routed)          0.869     7.474    SYNC/comptY[9]_i_4_n_0
    SLICE_X11Y28         LUT6 (Prop_lut6_I4_O)        0.124     7.598 r  SYNC/ROMAddress[0]_i_1/O
                         net (fo=59, routed)          0.962     8.560    RAMCTRL/SNAKE_RAM/Xi[0]
    SLICE_X14Y25         LUT2 (Prop_lut2_I1_O)        0.124     8.684 r  RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_900/O
                         net (fo=1, routed)           0.000     8.684    SYNC/ROMAddress[7]_i_166[0]
    SLICE_X14Y25         CARRY4 (Prop_carry4_S[0]_O[3])
                                                      0.606     9.290 r  SYNC/ROMAddress_reg[9]_i_752/O[3]
                         net (fo=5, routed)           0.994    10.284    RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_91_0[2]
    SLICE_X14Y28         LUT4 (Prop_lut4_I1_O)        0.306    10.590 r  RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_164/O
                         net (fo=1, routed)           0.000    10.590    RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_164_n_0
    SLICE_X14Y28         CARRY4 (Prop_carry4_S[3]_CO[3])
                                                      0.401    10.991 r  RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_91/CO[3]
                         net (fo=1, routed)           0.000    10.991    RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_91_n_0
    SLICE_X14Y29         CARRY4 (Prop_carry4_CI_O[0])
                                                      0.222    11.213 r  RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_200/O[0]
                         net (fo=6, routed)           0.805    12.018    RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_200_n_7
    SLICE_X17Y26         LUT5 (Prop_lut5_I2_O)        0.299    12.317 r  RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_199_comp/O
                         net (fo=1, routed)           1.348    13.665    RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_199_n_0
    SLICE_X4Y30          LUT6 (Prop_lut6_I3_O)        0.124    13.789 r  RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_51_comp_1/O
                         net (fo=1, routed)           1.090    14.879    RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_51_n_0
    SLICE_X7Y35          LUT6 (Prop_lut6_I2_O)        0.124    15.003 r  RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_14/O
                         net (fo=3, routed)           0.419    15.421    RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_14_n_0
    SLICE_X9Y34          LUT6 (Prop_lut6_I0_O)        0.124    15.545 r  RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_22/O
                         net (fo=1, routed)           0.665    16.210    RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_22_n_0
    SLICE_X8Y34          LUT5 (Prop_lut5_I3_O)        0.124    16.334 r  RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_6/O
                         net (fo=1, routed)           0.000    16.334    RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_6_n_0
    SLICE_X8Y34          CARRY4 (Prop_carry4_S[3]_O[3])
                                                      0.255    16.589 r  RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_1/O[3]
                         net (fo=1, routed)           0.000    16.589    SNAKE/D[7]
    SLICE_X8Y34          FDRE                                         r  SNAKE/ROMAddress_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      8.000     8.000 r  
    L16                                               0.000     8.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     8.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421     9.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    11.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    11.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.504    12.896    SNAKE/H125MHz_IBUF_BUFG
    SLICE_X8Y34          FDRE                                         r  SNAKE/ROMAddress_reg[7]/C
                         clock pessimism              0.277    13.173    
                         clock uncertainty           -0.393    12.780    
    SLICE_X8Y34          FDRE (Setup_fdre_C_D)        0.109    12.889    SNAKE/ROMAddress_reg[7]
  -------------------------------------------------------------------
                         required time                         12.889    
                         arrival time                         -16.589    
  -------------------------------------------------------------------
                         slack                                 -3.701    

Slack (VIOLATED) :        -3.440ns  (required time - arrival time)
  Source:                 SYNC/comptX_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            SNAKE/ROMAddress_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             sys_clk_pin
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (sys_clk_pin rise@8.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        10.944ns  (logic 3.576ns (32.677%)  route 7.368ns (67.323%))
  Logic Levels:           14  (CARRY4=4 LUT2=1 LUT3=2 LUT4=1 LUT5=1 LUT6=5)
  Clock Path Skew:        -0.213ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.896ns = ( 12.896 - 8.000 ) 
    Source Clock Delay      (SCD):    5.385ns
    Clock Pessimism Removal (CPR):    0.277ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491     1.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076     3.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101     3.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.680     5.348    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.538     1.810 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.760     3.570    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.101     3.671 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.714     5.385    SYNC/clk_out1
    SLICE_X5Y28          FDRE                                         r  SYNC/comptX_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X5Y28          FDRE (Prop_fdre_C_Q)         0.456     5.841 r  SYNC/comptX_reg[6]/Q
                         net (fo=13, routed)          0.640     6.481    SYNC/comptX_reg[6]
    SLICE_X11Y28         LUT3 (Prop_lut3_I2_O)        0.124     6.605 r  SYNC/comptY[9]_i_4/O
                         net (fo=10, routed)          0.869     7.474    SYNC/comptY[9]_i_4_n_0
    SLICE_X11Y28         LUT6 (Prop_lut6_I4_O)        0.124     7.598 r  SYNC/ROMAddress[0]_i_1/O
                         net (fo=59, routed)          0.987     8.585    RAMCTRL/SNAKE_RAM/Xi[0]
    SLICE_X12Y26         LUT2 (Prop_lut2_I1_O)        0.124     8.709 r  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_300/O
                         net (fo=1, routed)           0.000     8.709    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_300_n_0
    SLICE_X12Y26         CARRY4 (Prop_carry4_S[0]_O[0])
                                                      0.252     8.961 r  RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_153/O[0]
                         net (fo=12, routed)          0.955     9.916    RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_153_n_7
    SLICE_X9Y27          LUT4 (Prop_lut4_I0_O)        0.295    10.211 r  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_418/O
                         net (fo=1, routed)           0.000    10.211    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_418_n_0
    SLICE_X9Y27          CARRY4 (Prop_carry4_S[1]_O[2])
                                                      0.580    10.791 r  RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_370/O[2]
                         net (fo=3, routed)           0.654    11.444    RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_370_n_5
    SLICE_X9Y26          LUT5 (Prop_lut5_I0_O)        0.302    11.746 f  RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_770/O
                         net (fo=2, routed)           0.571    12.317    RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_770_n_0
    SLICE_X4Y26          LUT3 (Prop_lut3_I2_O)        0.124    12.441 f  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_200/O
                         net (fo=1, routed)           1.037    13.478    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_200_n_0
    SLICE_X6Y39          LUT6 (Prop_lut6_I1_O)        0.124    13.602 f  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_96/O
                         net (fo=2, routed)           0.448    14.050    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_96_n_0
    SLICE_X7Y36          LUT6 (Prop_lut6_I0_O)        0.124    14.174 f  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_63/O
                         net (fo=1, routed)           0.501    14.674    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_63_n_0
    SLICE_X8Y36          LUT6 (Prop_lut6_I5_O)        0.124    14.798 r  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_25/O
                         net (fo=1, routed)           0.707    15.506    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_25_n_0
    SLICE_X8Y33          LUT6 (Prop_lut6_I0_O)        0.124    15.630 r  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_6/O
                         net (fo=1, routed)           0.000    15.630    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_6_n_0
    SLICE_X8Y33          CARRY4 (Prop_carry4_S[3]_CO[3])
                                                      0.376    16.006 r  RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_1/CO[3]
                         net (fo=1, routed)           0.000    16.006    RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_1_n_0
    SLICE_X8Y34          CARRY4 (Prop_carry4_CI_O[1])
                                                      0.323    16.329 r  RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_1/O[1]
                         net (fo=1, routed)           0.000    16.329    SNAKE/D[5]
    SLICE_X8Y34          FDRE                                         r  SNAKE/ROMAddress_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      8.000     8.000 r  
    L16                                               0.000     8.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     8.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421     9.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    11.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    11.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.504    12.896    SNAKE/H125MHz_IBUF_BUFG
    SLICE_X8Y34          FDRE                                         r  SNAKE/ROMAddress_reg[5]/C
                         clock pessimism              0.277    13.173    
                         clock uncertainty           -0.393    12.780    
    SLICE_X8Y34          FDRE (Setup_fdre_C_D)        0.109    12.889    SNAKE/ROMAddress_reg[5]
  -------------------------------------------------------------------
                         required time                         12.889    
                         arrival time                         -16.329    
  -------------------------------------------------------------------
                         slack                                 -3.440    

Slack (VIOLATED) :        -3.356ns  (required time - arrival time)
  Source:                 SYNC/comptX_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            SNAKE/ROMAddress_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             sys_clk_pin
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (sys_clk_pin rise@8.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        10.860ns  (logic 3.492ns (32.156%)  route 7.368ns (67.844%))
  Logic Levels:           14  (CARRY4=4 LUT2=1 LUT3=2 LUT4=1 LUT5=1 LUT6=5)
  Clock Path Skew:        -0.213ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.896ns = ( 12.896 - 8.000 ) 
    Source Clock Delay      (SCD):    5.385ns
    Clock Pessimism Removal (CPR):    0.277ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491     1.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076     3.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101     3.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.680     5.348    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.538     1.810 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.760     3.570    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.101     3.671 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.714     5.385    SYNC/clk_out1
    SLICE_X5Y28          FDRE                                         r  SYNC/comptX_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X5Y28          FDRE (Prop_fdre_C_Q)         0.456     5.841 r  SYNC/comptX_reg[6]/Q
                         net (fo=13, routed)          0.640     6.481    SYNC/comptX_reg[6]
    SLICE_X11Y28         LUT3 (Prop_lut3_I2_O)        0.124     6.605 r  SYNC/comptY[9]_i_4/O
                         net (fo=10, routed)          0.869     7.474    SYNC/comptY[9]_i_4_n_0
    SLICE_X11Y28         LUT6 (Prop_lut6_I4_O)        0.124     7.598 r  SYNC/ROMAddress[0]_i_1/O
                         net (fo=59, routed)          0.987     8.585    RAMCTRL/SNAKE_RAM/Xi[0]
    SLICE_X12Y26         LUT2 (Prop_lut2_I1_O)        0.124     8.709 r  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_300/O
                         net (fo=1, routed)           0.000     8.709    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_300_n_0
    SLICE_X12Y26         CARRY4 (Prop_carry4_S[0]_O[0])
                                                      0.252     8.961 r  RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_153/O[0]
                         net (fo=12, routed)          0.955     9.916    RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_153_n_7
    SLICE_X9Y27          LUT4 (Prop_lut4_I0_O)        0.295    10.211 r  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_418/O
                         net (fo=1, routed)           0.000    10.211    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_418_n_0
    SLICE_X9Y27          CARRY4 (Prop_carry4_S[1]_O[2])
                                                      0.580    10.791 r  RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_370/O[2]
                         net (fo=3, routed)           0.654    11.444    RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_370_n_5
    SLICE_X9Y26          LUT5 (Prop_lut5_I0_O)        0.302    11.746 f  RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_770/O
                         net (fo=2, routed)           0.571    12.317    RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_770_n_0
    SLICE_X4Y26          LUT3 (Prop_lut3_I2_O)        0.124    12.441 f  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_200/O
                         net (fo=1, routed)           1.037    13.478    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_200_n_0
    SLICE_X6Y39          LUT6 (Prop_lut6_I1_O)        0.124    13.602 f  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_96/O
                         net (fo=2, routed)           0.448    14.050    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_96_n_0
    SLICE_X7Y36          LUT6 (Prop_lut6_I0_O)        0.124    14.174 f  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_63/O
                         net (fo=1, routed)           0.501    14.674    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_63_n_0
    SLICE_X8Y36          LUT6 (Prop_lut6_I5_O)        0.124    14.798 r  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_25/O
                         net (fo=1, routed)           0.707    15.506    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_25_n_0
    SLICE_X8Y33          LUT6 (Prop_lut6_I0_O)        0.124    15.630 r  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_6/O
                         net (fo=1, routed)           0.000    15.630    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_6_n_0
    SLICE_X8Y33          CARRY4 (Prop_carry4_S[3]_CO[3])
                                                      0.376    16.006 r  RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_1/CO[3]
                         net (fo=1, routed)           0.000    16.006    RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_1_n_0
    SLICE_X8Y34          CARRY4 (Prop_carry4_CI_O[2])
                                                      0.239    16.245 r  RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_1/O[2]
                         net (fo=1, routed)           0.000    16.245    SNAKE/D[6]
    SLICE_X8Y34          FDRE                                         r  SNAKE/ROMAddress_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      8.000     8.000 r  
    L16                                               0.000     8.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     8.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421     9.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    11.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    11.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.504    12.896    SNAKE/H125MHz_IBUF_BUFG
    SLICE_X8Y34          FDRE                                         r  SNAKE/ROMAddress_reg[6]/C
                         clock pessimism              0.277    13.173    
                         clock uncertainty           -0.393    12.780    
    SLICE_X8Y34          FDRE (Setup_fdre_C_D)        0.109    12.889    SNAKE/ROMAddress_reg[6]
  -------------------------------------------------------------------
                         required time                         12.889    
                         arrival time                         -16.245    
  -------------------------------------------------------------------
                         slack                                 -3.356    

Slack (VIOLATED) :        -3.336ns  (required time - arrival time)
  Source:                 SYNC/comptX_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            SNAKE/ROMAddress_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             sys_clk_pin
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (sys_clk_pin rise@8.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        10.840ns  (logic 3.472ns (32.031%)  route 7.368ns (67.969%))
  Logic Levels:           14  (CARRY4=4 LUT2=1 LUT3=2 LUT4=1 LUT5=1 LUT6=5)
  Clock Path Skew:        -0.213ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.896ns = ( 12.896 - 8.000 ) 
    Source Clock Delay      (SCD):    5.385ns
    Clock Pessimism Removal (CPR):    0.277ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491     1.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076     3.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101     3.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.680     5.348    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.538     1.810 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.760     3.570    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.101     3.671 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.714     5.385    SYNC/clk_out1
    SLICE_X5Y28          FDRE                                         r  SYNC/comptX_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X5Y28          FDRE (Prop_fdre_C_Q)         0.456     5.841 r  SYNC/comptX_reg[6]/Q
                         net (fo=13, routed)          0.640     6.481    SYNC/comptX_reg[6]
    SLICE_X11Y28         LUT3 (Prop_lut3_I2_O)        0.124     6.605 r  SYNC/comptY[9]_i_4/O
                         net (fo=10, routed)          0.869     7.474    SYNC/comptY[9]_i_4_n_0
    SLICE_X11Y28         LUT6 (Prop_lut6_I4_O)        0.124     7.598 r  SYNC/ROMAddress[0]_i_1/O
                         net (fo=59, routed)          0.987     8.585    RAMCTRL/SNAKE_RAM/Xi[0]
    SLICE_X12Y26         LUT2 (Prop_lut2_I1_O)        0.124     8.709 r  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_300/O
                         net (fo=1, routed)           0.000     8.709    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_300_n_0
    SLICE_X12Y26         CARRY4 (Prop_carry4_S[0]_O[0])
                                                      0.252     8.961 r  RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_153/O[0]
                         net (fo=12, routed)          0.955     9.916    RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_153_n_7
    SLICE_X9Y27          LUT4 (Prop_lut4_I0_O)        0.295    10.211 r  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_418/O
                         net (fo=1, routed)           0.000    10.211    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_418_n_0
    SLICE_X9Y27          CARRY4 (Prop_carry4_S[1]_O[2])
                                                      0.580    10.791 r  RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_370/O[2]
                         net (fo=3, routed)           0.654    11.444    RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_370_n_5
    SLICE_X9Y26          LUT5 (Prop_lut5_I0_O)        0.302    11.746 f  RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_770/O
                         net (fo=2, routed)           0.571    12.317    RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_770_n_0
    SLICE_X4Y26          LUT3 (Prop_lut3_I2_O)        0.124    12.441 f  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_200/O
                         net (fo=1, routed)           1.037    13.478    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_200_n_0
    SLICE_X6Y39          LUT6 (Prop_lut6_I1_O)        0.124    13.602 f  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_96/O
                         net (fo=2, routed)           0.448    14.050    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_96_n_0
    SLICE_X7Y36          LUT6 (Prop_lut6_I0_O)        0.124    14.174 f  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_63/O
                         net (fo=1, routed)           0.501    14.674    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_63_n_0
    SLICE_X8Y36          LUT6 (Prop_lut6_I5_O)        0.124    14.798 r  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_25/O
                         net (fo=1, routed)           0.707    15.506    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_25_n_0
    SLICE_X8Y33          LUT6 (Prop_lut6_I0_O)        0.124    15.630 r  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_6/O
                         net (fo=1, routed)           0.000    15.630    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_6_n_0
    SLICE_X8Y33          CARRY4 (Prop_carry4_S[3]_CO[3])
                                                      0.376    16.006 r  RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_1/CO[3]
                         net (fo=1, routed)           0.000    16.006    RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_1_n_0
    SLICE_X8Y34          CARRY4 (Prop_carry4_CI_O[0])
                                                      0.219    16.225 r  RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_1/O[0]
                         net (fo=1, routed)           0.000    16.225    SNAKE/D[4]
    SLICE_X8Y34          FDRE                                         r  SNAKE/ROMAddress_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      8.000     8.000 r  
    L16                                               0.000     8.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     8.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421     9.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    11.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    11.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.504    12.896    SNAKE/H125MHz_IBUF_BUFG
    SLICE_X8Y34          FDRE                                         r  SNAKE/ROMAddress_reg[4]/C
                         clock pessimism              0.277    13.173    
                         clock uncertainty           -0.393    12.780    
    SLICE_X8Y34          FDRE (Setup_fdre_C_D)        0.109    12.889    SNAKE/ROMAddress_reg[4]
  -------------------------------------------------------------------
                         required time                         12.889    
                         arrival time                         -16.225    
  -------------------------------------------------------------------
                         slack                                 -3.336    

Slack (VIOLATED) :        -2.997ns  (required time - arrival time)
  Source:                 SYNC/comptX_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            SNAKE/ROMAddress_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             sys_clk_pin
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (sys_clk_pin rise@8.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        10.500ns  (logic 3.132ns (29.830%)  route 7.368ns (70.170%))
  Logic Levels:           13  (CARRY4=3 LUT2=1 LUT3=2 LUT4=1 LUT5=1 LUT6=5)
  Clock Path Skew:        -0.214ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.895ns = ( 12.895 - 8.000 ) 
    Source Clock Delay      (SCD):    5.385ns
    Clock Pessimism Removal (CPR):    0.277ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491     1.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076     3.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101     3.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.680     5.348    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.538     1.810 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.760     3.570    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.101     3.671 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.714     5.385    SYNC/clk_out1
    SLICE_X5Y28          FDRE                                         r  SYNC/comptX_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X5Y28          FDRE (Prop_fdre_C_Q)         0.456     5.841 r  SYNC/comptX_reg[6]/Q
                         net (fo=13, routed)          0.640     6.481    SYNC/comptX_reg[6]
    SLICE_X11Y28         LUT3 (Prop_lut3_I2_O)        0.124     6.605 r  SYNC/comptY[9]_i_4/O
                         net (fo=10, routed)          0.869     7.474    SYNC/comptY[9]_i_4_n_0
    SLICE_X11Y28         LUT6 (Prop_lut6_I4_O)        0.124     7.598 r  SYNC/ROMAddress[0]_i_1/O
                         net (fo=59, routed)          0.987     8.585    RAMCTRL/SNAKE_RAM/Xi[0]
    SLICE_X12Y26         LUT2 (Prop_lut2_I1_O)        0.124     8.709 r  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_300/O
                         net (fo=1, routed)           0.000     8.709    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_300_n_0
    SLICE_X12Y26         CARRY4 (Prop_carry4_S[0]_O[0])
                                                      0.252     8.961 r  RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_153/O[0]
                         net (fo=12, routed)          0.955     9.916    RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_153_n_7
    SLICE_X9Y27          LUT4 (Prop_lut4_I0_O)        0.295    10.211 r  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_418/O
                         net (fo=1, routed)           0.000    10.211    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_418_n_0
    SLICE_X9Y27          CARRY4 (Prop_carry4_S[1]_O[2])
                                                      0.580    10.791 r  RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_370/O[2]
                         net (fo=3, routed)           0.654    11.444    RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_370_n_5
    SLICE_X9Y26          LUT5 (Prop_lut5_I0_O)        0.302    11.746 f  RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_770/O
                         net (fo=2, routed)           0.571    12.317    RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_770_n_0
    SLICE_X4Y26          LUT3 (Prop_lut3_I2_O)        0.124    12.441 f  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_200/O
                         net (fo=1, routed)           1.037    13.478    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_200_n_0
    SLICE_X6Y39          LUT6 (Prop_lut6_I1_O)        0.124    13.602 f  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_96/O
                         net (fo=2, routed)           0.448    14.050    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_96_n_0
    SLICE_X7Y36          LUT6 (Prop_lut6_I0_O)        0.124    14.174 f  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_63/O
                         net (fo=1, routed)           0.501    14.674    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_63_n_0
    SLICE_X8Y36          LUT6 (Prop_lut6_I5_O)        0.124    14.798 r  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_25/O
                         net (fo=1, routed)           0.707    15.506    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_25_n_0
    SLICE_X8Y33          LUT6 (Prop_lut6_I0_O)        0.124    15.630 r  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_6/O
                         net (fo=1, routed)           0.000    15.630    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_6_n_0
    SLICE_X8Y33          CARRY4 (Prop_carry4_S[3]_O[3])
                                                      0.255    15.885 r  RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_1/O[3]
                         net (fo=1, routed)           0.000    15.885    SNAKE/D[3]
    SLICE_X8Y33          FDRE                                         r  SNAKE/ROMAddress_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      8.000     8.000 r  
    L16                                               0.000     8.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     8.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421     9.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    11.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    11.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.503    12.895    SNAKE/H125MHz_IBUF_BUFG
    SLICE_X8Y33          FDRE                                         r  SNAKE/ROMAddress_reg[3]/C
                         clock pessimism              0.277    13.172    
                         clock uncertainty           -0.393    12.779    
    SLICE_X8Y33          FDRE (Setup_fdre_C_D)        0.109    12.888    SNAKE/ROMAddress_reg[3]
  -------------------------------------------------------------------
                         required time                         12.888    
                         arrival time                         -15.885    
  -------------------------------------------------------------------
                         slack                                 -2.997    

Slack (VIOLATED) :        -2.724ns  (required time - arrival time)
  Source:                 SYNC/comptY_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            SNAKE/ROMAddress_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             sys_clk_pin
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (sys_clk_pin rise@8.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        10.282ns  (logic 3.041ns (29.575%)  route 7.241ns (70.425%))
  Logic Levels:           13  (CARRY4=3 LUT4=4 LUT5=2 LUT6=3 MUXF7=1)
  Clock Path Skew:        -0.158ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.895ns = ( 12.895 - 8.000 ) 
    Source Clock Delay      (SCD):    5.329ns
    Clock Pessimism Removal (CPR):    0.277ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491     1.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076     3.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101     3.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.680     5.348    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.538     1.810 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.760     3.570    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.101     3.671 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.658     5.329    SYNC/clk_out1
    SLICE_X15Y23         FDRE                                         r  SYNC/comptY_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X15Y23         FDRE (Prop_fdre_C_Q)         0.456     5.785 r  SYNC/comptY_reg[7]/Q
                         net (fo=13, routed)          0.935     6.720    SYNC/comptY_reg[7]
    SLICE_X17Y25         LUT5 (Prop_lut5_I2_O)        0.124     6.844 r  SYNC/cCaseY[0]_i_2/O
                         net (fo=61, routed)          0.828     7.672    SYNC/cCaseY[0]_i_2_n_0
    SLICE_X16Y22         LUT4 (Prop_lut4_I3_O)        0.124     7.796 r  SYNC/ROMAddress[7]_i_109/O
                         net (fo=58, routed)          1.020     8.816    RAMCTRL/SNAKE_RAM/Yi[1]
    SLICE_X21Y29         LUT4 (Prop_lut4_I0_O)        0.124     8.940 r  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_306/O
                         net (fo=1, routed)           0.000     8.940    SYNC/ROMAddress[3]_i_383[0]
    SLICE_X21Y29         CARRY4 (Prop_carry4_S[2]_O[2])
                                                      0.248     9.188 r  SYNC/ROMAddress_reg[3]_i_155/O[2]
                         net (fo=5, routed)           0.601     9.789    RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_244_0[2]
    SLICE_X22Y30         LUT4 (Prop_lut4_I3_O)        0.302    10.091 r  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_383/O
                         net (fo=1, routed)           0.000    10.091    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_383_n_0
    SLICE_X22Y30         CARRY4 (Prop_carry4_S[1]_O[1])
                                                      0.227    10.318 r  RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_244/O[1]
                         net (fo=5, routed)           0.651    10.969    RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_244_n_6
    SLICE_X18Y31         LUT4 (Prop_lut4_I0_O)        0.303    11.272 f  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_203/O
                         net (fo=2, routed)           1.794    13.065    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_203_n_0
    SLICE_X2Y29          LUT6 (Prop_lut6_I5_O)        0.124    13.189 f  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_97/O
                         net (fo=1, routed)           0.000    13.189    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_97_n_0
    SLICE_X2Y29          MUXF7 (Prop_muxf7_I0_O)      0.212    13.401 f  RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_40/O
                         net (fo=1, routed)           0.435    13.836    RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_40_n_0
    SLICE_X3Y31          LUT6 (Prop_lut6_I1_O)        0.299    14.135 f  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_16__0/O
                         net (fo=1, routed)           0.154    14.289    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_16__0_n_0
    SLICE_X3Y31          LUT6 (Prop_lut6_I2_O)        0.124    14.413 r  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_3_comp/O
                         net (fo=2, routed)           0.824    15.238    RAMCTRL/SNAKE_RAM/SNAKE/p_11_out[2]
    SLICE_X8Y33          LUT5 (Prop_lut5_I0_O)        0.124    15.362 r  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_7/O
                         net (fo=1, routed)           0.000    15.362    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_7_n_0
    SLICE_X8Y33          CARRY4 (Prop_carry4_S[2]_O[2])
                                                      0.250    15.612 r  RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_1/O[2]
                         net (fo=1, routed)           0.000    15.612    SNAKE/D[2]
    SLICE_X8Y33          FDRE                                         r  SNAKE/ROMAddress_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      8.000     8.000 r  
    L16                                               0.000     8.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     8.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421     9.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    11.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    11.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.503    12.895    SNAKE/H125MHz_IBUF_BUFG
    SLICE_X8Y33          FDRE                                         r  SNAKE/ROMAddress_reg[2]/C
                         clock pessimism              0.277    13.172    
                         clock uncertainty           -0.393    12.779    
    SLICE_X8Y33          FDRE (Setup_fdre_C_D)        0.109    12.888    SNAKE/ROMAddress_reg[2]
  -------------------------------------------------------------------
                         required time                         12.888    
                         arrival time                         -15.612    
  -------------------------------------------------------------------
                         slack                                 -2.724    

Slack (VIOLATED) :        -2.544ns  (required time - arrival time)
  Source:                 SYNC/comptX_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            SNAKE/ROMAddress_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             sys_clk_pin
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (sys_clk_pin rise@8.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        10.046ns  (logic 2.837ns (28.240%)  route 7.209ns (71.760%))
  Logic Levels:           11  (CARRY4=3 LUT3=1 LUT4=1 LUT5=2 LUT6=4)
  Clock Path Skew:        -0.214ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.895ns = ( 12.895 - 8.000 ) 
    Source Clock Delay      (SCD):    5.385ns
    Clock Pessimism Removal (CPR):    0.277ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491     1.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076     3.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101     3.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.680     5.348    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.538     1.810 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.760     3.570    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.101     3.671 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.714     5.385    SYNC/clk_out1
    SLICE_X5Y28          FDRE                                         r  SYNC/comptX_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X5Y28          FDRE (Prop_fdre_C_Q)         0.456     5.841 f  SYNC/comptX_reg[6]/Q
                         net (fo=13, routed)          0.640     6.481    SYNC/comptX_reg[6]
    SLICE_X11Y28         LUT3 (Prop_lut3_I2_O)        0.124     6.605 f  SYNC/comptY[9]_i_4/O
                         net (fo=10, routed)          1.212     7.817    SYNC/comptY[9]_i_4_n_0
    SLICE_X6Y27          LUT5 (Prop_lut5_I2_O)        0.124     7.941 r  SYNC/cCaseX[1]_i_2_comp/O
                         net (fo=1, routed)           0.441     8.382    SYNC/cCaseX[1]_i_2_n_0
    SLICE_X9Y26          LUT6 (Prop_lut6_I4_O)        0.124     8.506 r  SYNC/cCaseX[1]_i_1_comp/O
                         net (fo=71, routed)          1.242     9.748    RAMCTRL/SNAKE_RAM/Xi[5]
    SLICE_X17Y32         LUT4 (Prop_lut4_I3_O)        0.124     9.872 r  RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_189/O
                         net (fo=1, routed)           0.000     9.872    RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_189_n_0
    SLICE_X17Y32         CARRY4 (Prop_carry4_S[1]_CO[3])
                                                      0.550    10.422 r  RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_115/CO[3]
                         net (fo=1, routed)           0.000    10.422    RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_115_n_0
    SLICE_X17Y33         CARRY4 (Prop_carry4_CI_CO[2])
                                                      0.228    10.650 r  RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_51/CO[2]
                         net (fo=2, routed)           0.675    11.325    RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_51_n_1
    SLICE_X15Y34         LUT5 (Prop_lut5_I0_O)        0.313    11.638 f  RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_17/O
                         net (fo=29, routed)          0.563    12.201    RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_17_n_0
    SLICE_X12Y34         LUT6 (Prop_lut6_I5_O)        0.124    12.325 r  RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_11/O
                         net (fo=15, routed)          1.175    13.501    RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_11_n_0
    SLICE_X1Y34          LUT6 (Prop_lut6_I0_O)        0.124    13.625 r  RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_24_replica/O
                         net (fo=1, routed)           0.501    14.125    RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_24_n_0_repN
    SLICE_X3Y33          LUT6 (Prop_lut6_I5_O)        0.124    14.249 r  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_5/O
                         net (fo=2, routed)           0.760    15.009    RAMCTRL/SNAKE_RAM/SNAKE/p_11_out[0]
    SLICE_X8Y33          CARRY4 (Prop_carry4_DI[0]_O[1])
                                                      0.422    15.431 r  RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_1/O[1]
                         net (fo=1, routed)           0.000    15.431    SNAKE/D[1]
    SLICE_X8Y33          FDRE                                         r  SNAKE/ROMAddress_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      8.000     8.000 r  
    L16                                               0.000     8.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     8.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421     9.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    11.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    11.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.503    12.895    SNAKE/H125MHz_IBUF_BUFG
    SLICE_X8Y33          FDRE                                         r  SNAKE/ROMAddress_reg[1]/C
                         clock pessimism              0.277    13.172    
                         clock uncertainty           -0.393    12.779    
    SLICE_X8Y33          FDRE (Setup_fdre_C_D)        0.109    12.888    SNAKE/ROMAddress_reg[1]
  -------------------------------------------------------------------
                         required time                         12.888    
                         arrival time                         -15.431    
  -------------------------------------------------------------------
                         slack                                 -2.544    

Slack (VIOLATED) :        -2.294ns  (required time - arrival time)
  Source:                 SYNC/comptX_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            SNAKE/ROMAddress_reg[0]/CE
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             sys_clk_pin
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (sys_clk_pin rise@8.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        9.518ns  (logic 2.415ns (25.373%)  route 7.103ns (74.627%))
  Logic Levels:           10  (CARRY4=2 LUT3=2 LUT4=1 LUT5=2 LUT6=3)
  Clock Path Skew:        -0.214ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.895ns = ( 12.895 - 8.000 ) 
    Source Clock Delay      (SCD):    5.385ns
    Clock Pessimism Removal (CPR):    0.277ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491     1.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076     3.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101     3.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.680     5.348    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.538     1.810 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.760     3.570    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.101     3.671 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.714     5.385    SYNC/clk_out1
    SLICE_X5Y28          FDRE                                         r  SYNC/comptX_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X5Y28          FDRE (Prop_fdre_C_Q)         0.456     5.841 f  SYNC/comptX_reg[6]/Q
                         net (fo=13, routed)          0.640     6.481    SYNC/comptX_reg[6]
    SLICE_X11Y28         LUT3 (Prop_lut3_I2_O)        0.124     6.605 f  SYNC/comptY[9]_i_4/O
                         net (fo=10, routed)          1.212     7.817    SYNC/comptY[9]_i_4_n_0
    SLICE_X6Y27          LUT5 (Prop_lut5_I2_O)        0.124     7.941 r  SYNC/cCaseX[1]_i_2_comp/O
                         net (fo=1, routed)           0.441     8.382    SYNC/cCaseX[1]_i_2_n_0
    SLICE_X9Y26          LUT6 (Prop_lut6_I4_O)        0.124     8.506 r  SYNC/cCaseX[1]_i_1_comp/O
                         net (fo=71, routed)          1.179     9.685    RAMCTRL/SNAKE_RAM/Xi[5]
    SLICE_X18Y25         LUT4 (Prop_lut4_I3_O)        0.124     9.809 r  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_263/O
                         net (fo=1, routed)           0.000     9.809    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_263_n_0
    SLICE_X18Y25         CARRY4 (Prop_carry4_S[1]_CO[3])
                                                      0.550    10.359 r  RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_134/CO[3]
                         net (fo=1, routed)           0.000    10.359    RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_134_n_0
    SLICE_X18Y26         CARRY4 (Prop_carry4_CI_CO[2])
                                                      0.228    10.587 f  RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_54/CO[2]
                         net (fo=1, routed)           0.857    11.443    RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_54_n_1
    SLICE_X16Y29         LUT5 (Prop_lut5_I0_O)        0.313    11.756 r  RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_21/O
                         net (fo=35, routed)          0.841    12.598    RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_21_n_0
    SLICE_X13Y32         LUT6 (Prop_lut6_I0_O)        0.124    12.722 f  RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_10/O
                         net (fo=7, routed)           0.980    13.702    RAMCTRL/SNAKE_RAM/mem_reg_7_0_3
    SLICE_X12Y35         LUT6 (Prop_lut6_I3_O)        0.124    13.826 f  RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_3/O
                         net (fo=2, routed)           0.286    14.112    RAMCTRL/SNAKE_RAM/mem_reg_4_0_3
    SLICE_X12Y35         LUT3 (Prop_lut3_I2_O)        0.124    14.236 r  RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_1/O
                         net (fo=10, routed)          0.667    14.903    SNAKE/E[0]
    SLICE_X8Y33          FDRE                                         r  SNAKE/ROMAddress_reg[0]/CE
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      8.000     8.000 r  
    L16                                               0.000     8.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     8.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421     9.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    11.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    11.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.503    12.895    SNAKE/H125MHz_IBUF_BUFG
    SLICE_X8Y33          FDRE                                         r  SNAKE/ROMAddress_reg[0]/C
                         clock pessimism              0.277    13.172    
                         clock uncertainty           -0.393    12.779    
    SLICE_X8Y33          FDRE (Setup_fdre_C_CE)      -0.169    12.610    SNAKE/ROMAddress_reg[0]
  -------------------------------------------------------------------
                         required time                         12.610    
                         arrival time                         -14.903    
  -------------------------------------------------------------------
                         slack                                 -2.294    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.121ns  (arrival time - required time)
  Source:                 APPLE/ROMAddress_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            POMMEROM/data_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             sys_clk_pin
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        0.916ns  (logic 0.208ns (22.715%)  route 0.708ns (77.285%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.270ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.992ns
    Source Clock Delay      (SCD):    1.475ns
    Clock Pessimism Removal (CPR):    0.247ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.548     1.460    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.053     0.406 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.482     0.888    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.914 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.561     1.475    APPLE/clk_out1
    SLICE_X30Y39         FDRE                                         r  APPLE/ROMAddress_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X30Y39         FDRE (Prop_fdre_C_Q)         0.164     1.639 r  APPLE/ROMAddress_reg[3]/Q
                         net (fo=11, routed)          0.708     2.346    APPLE/pommeROMAddress[3]
    SLICE_X30Y45         LUT4 (Prop_lut4_I3_O)        0.044     2.390 r  APPLE/data[4]_i_1/O
                         net (fo=1, routed)           0.000     2.390    POMMEROM/D[4]
    SLICE_X30Y45         FDRE                                         r  POMMEROM/data_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.833     1.992    POMMEROM/H125MHz_IBUF_BUFG
    SLICE_X30Y45         FDRE                                         r  POMMEROM/data_reg[4]/C
                         clock pessimism             -0.247     1.745    
                         clock uncertainty            0.393     2.138    
    SLICE_X30Y45         FDRE (Hold_fdre_C_D)         0.131     2.269    POMMEROM/data_reg[4]
  -------------------------------------------------------------------
                         required time                         -2.269    
                         arrival time                           2.390    
  -------------------------------------------------------------------
                         slack                                  0.121    

Slack (MET) :             0.133ns  (arrival time - required time)
  Source:                 APPLE/ROMAddress_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            POMMEROM/data_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             sys_clk_pin
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        0.917ns  (logic 0.209ns (22.799%)  route 0.708ns (77.201%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.270ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.992ns
    Source Clock Delay      (SCD):    1.475ns
    Clock Pessimism Removal (CPR):    0.247ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.548     1.460    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.053     0.406 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.482     0.888    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.914 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.561     1.475    APPLE/clk_out1
    SLICE_X30Y39         FDRE                                         r  APPLE/ROMAddress_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X30Y39         FDRE (Prop_fdre_C_Q)         0.164     1.639 f  APPLE/ROMAddress_reg[3]/Q
                         net (fo=11, routed)          0.708     2.346    APPLE/pommeROMAddress[3]
    SLICE_X30Y45         LUT3 (Prop_lut3_I0_O)        0.045     2.391 r  APPLE/data[2]_i_1/O
                         net (fo=1, routed)           0.000     2.391    POMMEROM/D[2]
    SLICE_X30Y45         FDRE                                         r  POMMEROM/data_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.833     1.992    POMMEROM/H125MHz_IBUF_BUFG
    SLICE_X30Y45         FDRE                                         r  POMMEROM/data_reg[2]/C
                         clock pessimism             -0.247     1.745    
                         clock uncertainty            0.393     2.138    
    SLICE_X30Y45         FDRE (Hold_fdre_C_D)         0.120     2.258    POMMEROM/data_reg[2]
  -------------------------------------------------------------------
                         required time                         -2.258    
                         arrival time                           2.391    
  -------------------------------------------------------------------
                         slack                                  0.133    

Slack (MET) :             0.154ns  (arrival time - required time)
  Source:                 APPLE/ROMAddress_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            POMMEROM/data_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             sys_clk_pin
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        0.937ns  (logic 0.209ns (22.303%)  route 0.728ns (77.697%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        0.270ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.992ns
    Source Clock Delay      (SCD):    1.475ns
    Clock Pessimism Removal (CPR):    0.247ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.548     1.460    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.053     0.406 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.482     0.888    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.914 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.561     1.475    APPLE/clk_out1
    SLICE_X30Y39         FDRE                                         r  APPLE/ROMAddress_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X30Y39         FDRE (Prop_fdre_C_Q)         0.164     1.639 r  APPLE/ROMAddress_reg[3]/Q
                         net (fo=11, routed)          0.728     2.367    APPLE/pommeROMAddress[3]
    SLICE_X32Y44         LUT5 (Prop_lut5_I3_O)        0.045     2.412 r  APPLE/data[6]_i_1/O
                         net (fo=1, routed)           0.000     2.412    POMMEROM/D[6]
    SLICE_X32Y44         FDRE                                         r  POMMEROM/data_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.833     1.992    POMMEROM/H125MHz_IBUF_BUFG
    SLICE_X32Y44         FDRE                                         r  POMMEROM/data_reg[6]/C
                         clock pessimism             -0.247     1.745    
                         clock uncertainty            0.393     2.138    
    SLICE_X32Y44         FDRE (Hold_fdre_C_D)         0.120     2.258    POMMEROM/data_reg[6]
  -------------------------------------------------------------------
                         required time                         -2.258    
                         arrival time                           2.412    
  -------------------------------------------------------------------
                         slack                                  0.154    

Slack (MET) :             0.159ns  (arrival time - required time)
  Source:                 SNAKE/startUpdate_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            SNAKE/request_reg/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             sys_clk_pin
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        0.909ns  (logic 0.186ns (20.467%)  route 0.723ns (79.533%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.265ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.983ns
    Source Clock Delay      (SCD):    1.471ns
    Clock Pessimism Removal (CPR):    0.247ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.548     1.460    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.053     0.406 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.482     0.888    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.914 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.557     1.471    SNAKE/clk_out1
    SLICE_X22Y58         FDCE                                         r  SNAKE/startUpdate_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X22Y58         FDCE (Prop_fdce_C_Q)         0.141     1.612 r  SNAKE/startUpdate_reg/Q
                         net (fo=4, routed)           0.723     2.335    SNAKE/startUpdate
    SLICE_X22Y59         LUT4 (Prop_lut4_I2_O)        0.045     2.380 r  SNAKE/request_i_1/O
                         net (fo=1, routed)           0.000     2.380    SNAKE/request_i_1_n_0
    SLICE_X22Y59         FDRE                                         r  SNAKE/request_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.824     1.983    SNAKE/H125MHz_IBUF_BUFG
    SLICE_X22Y59         FDRE                                         r  SNAKE/request_reg/C
                         clock pessimism             -0.247     1.736    
                         clock uncertainty            0.393     2.129    
    SLICE_X22Y59         FDRE (Hold_fdre_C_D)         0.091     2.220    SNAKE/request_reg
  -------------------------------------------------------------------
                         required time                         -2.220    
                         arrival time                           2.380    
  -------------------------------------------------------------------
                         slack                                  0.159    

Slack (MET) :             0.177ns  (arrival time - required time)
  Source:                 APPLE/ROMAddress_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            POMMEROM/data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             sys_clk_pin
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        0.932ns  (logic 0.209ns (22.426%)  route 0.723ns (77.574%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.270ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.992ns
    Source Clock Delay      (SCD):    1.475ns
    Clock Pessimism Removal (CPR):    0.247ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.548     1.460    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.053     0.406 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.482     0.888    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.914 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.561     1.475    APPLE/clk_out1
    SLICE_X28Y39         FDRE                                         r  APPLE/ROMAddress_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X28Y39         FDRE (Prop_fdre_C_Q)         0.164     1.639 r  APPLE/ROMAddress_reg[2]/Q
                         net (fo=10, routed)          0.723     2.362    APPLE/pommeROMAddress[2]
    SLICE_X33Y46         LUT6 (Prop_lut6_I2_O)        0.045     2.407 r  APPLE/data[8]_i_1/O
                         net (fo=1, routed)           0.000     2.407    POMMEROM/D[8]
    SLICE_X33Y46         FDRE                                         r  POMMEROM/data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.833     1.992    POMMEROM/H125MHz_IBUF_BUFG
    SLICE_X33Y46         FDRE                                         r  POMMEROM/data_reg[8]/C
                         clock pessimism             -0.247     1.745    
                         clock uncertainty            0.393     2.138    
    SLICE_X33Y46         FDRE (Hold_fdre_C_D)         0.091     2.229    POMMEROM/data_reg[8]
  -------------------------------------------------------------------
                         required time                         -2.229    
                         arrival time                           2.407    
  -------------------------------------------------------------------
                         slack                                  0.177    

Slack (MET) :             0.195ns  (arrival time - required time)
  Source:                 APPLE/ROMAddress_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            POMMEROM/data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             sys_clk_pin
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        0.992ns  (logic 0.271ns (27.309%)  route 0.721ns (72.691%))
  Logic Levels:           2  (LUT6=1 MUXF7=1)
  Clock Path Skew:        0.270ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.992ns
    Source Clock Delay      (SCD):    1.475ns
    Clock Pessimism Removal (CPR):    0.247ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.548     1.460    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.053     0.406 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.482     0.888    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.914 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.561     1.475    APPLE/clk_out1
    SLICE_X28Y39         FDRE                                         r  APPLE/ROMAddress_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X28Y39         FDRE (Prop_fdre_C_Q)         0.164     1.639 f  APPLE/ROMAddress_reg[6]/Q
                         net (fo=26, routed)          0.721     2.360    APPLE/pommeROMAddress[6]
    SLICE_X30Y44         LUT6 (Prop_lut6_I5_O)        0.045     2.405 r  APPLE/data[9]_i_2__0/O
                         net (fo=1, routed)           0.000     2.405    APPLE/data[9]_i_2__0_n_0
    SLICE_X30Y44         MUXF7 (Prop_muxf7_I0_O)      0.062     2.467 r  APPLE/data_reg[9]_i_1__0/O
                         net (fo=1, routed)           0.000     2.467    POMMEROM/D[9]
    SLICE_X30Y44         FDRE                                         r  POMMEROM/data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.833     1.992    POMMEROM/H125MHz_IBUF_BUFG
    SLICE_X30Y44         FDRE                                         r  POMMEROM/data_reg[9]/C
                         clock pessimism             -0.247     1.745    
                         clock uncertainty            0.393     2.138    
    SLICE_X30Y44         FDRE (Hold_fdre_C_D)         0.134     2.272    POMMEROM/data_reg[9]
  -------------------------------------------------------------------
                         required time                         -2.272    
                         arrival time                           2.467    
  -------------------------------------------------------------------
                         slack                                  0.195    

Slack (MET) :             0.227ns  (arrival time - required time)
  Source:                 APPLE/ROMAddress_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            POMMEROM/data_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             sys_clk_pin
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        0.983ns  (logic 0.209ns (21.269%)  route 0.774ns (78.731%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.270ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.992ns
    Source Clock Delay      (SCD):    1.475ns
    Clock Pessimism Removal (CPR):    0.247ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.548     1.460    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.053     0.406 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.482     0.888    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.914 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.561     1.475    APPLE/clk_out1
    SLICE_X30Y39         FDRE                                         r  APPLE/ROMAddress_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X30Y39         FDRE (Prop_fdre_C_Q)         0.164     1.639 r  APPLE/ROMAddress_reg[3]/Q
                         net (fo=11, routed)          0.774     2.412    APPLE/pommeROMAddress[3]
    SLICE_X33Y45         LUT6 (Prop_lut6_I4_O)        0.045     2.457 r  APPLE/data[5]_i_1/O
                         net (fo=1, routed)           0.000     2.457    POMMEROM/D[5]
    SLICE_X33Y45         FDRE                                         r  POMMEROM/data_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.833     1.992    POMMEROM/H125MHz_IBUF_BUFG
    SLICE_X33Y45         FDRE                                         r  POMMEROM/data_reg[5]/C
                         clock pessimism             -0.247     1.745    
                         clock uncertainty            0.393     2.138    
    SLICE_X33Y45         FDRE (Hold_fdre_C_D)         0.092     2.230    POMMEROM/data_reg[5]
  -------------------------------------------------------------------
                         required time                         -2.230    
                         arrival time                           2.457    
  -------------------------------------------------------------------
                         slack                                  0.227    

Slack (MET) :             0.329ns  (arrival time - required time)
  Source:                 APPLE/ROMAddress_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            POMMEROM/data_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             sys_clk_pin
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        1.083ns  (logic 0.209ns (19.296%)  route 0.874ns (80.704%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.270ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.992ns
    Source Clock Delay      (SCD):    1.475ns
    Clock Pessimism Removal (CPR):    0.247ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.548     1.460    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.053     0.406 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.482     0.888    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.914 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.561     1.475    APPLE/clk_out1
    SLICE_X28Y39         FDRE                                         r  APPLE/ROMAddress_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X28Y39         FDRE (Prop_fdre_C_Q)         0.164     1.639 r  APPLE/ROMAddress_reg[2]/Q
                         net (fo=10, routed)          0.874     2.513    APPLE/pommeROMAddress[2]
    SLICE_X31Y45         LUT6 (Prop_lut6_I2_O)        0.045     2.558 r  APPLE/data[3]_i_1/O
                         net (fo=1, routed)           0.000     2.558    POMMEROM/D[3]
    SLICE_X31Y45         FDRE                                         r  POMMEROM/data_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.833     1.992    POMMEROM/H125MHz_IBUF_BUFG
    SLICE_X31Y45         FDRE                                         r  POMMEROM/data_reg[3]/C
                         clock pessimism             -0.247     1.745    
                         clock uncertainty            0.393     2.138    
    SLICE_X31Y45         FDRE (Hold_fdre_C_D)         0.091     2.229    POMMEROM/data_reg[3]
  -------------------------------------------------------------------
                         required time                         -2.229    
                         arrival time                           2.558    
  -------------------------------------------------------------------
                         slack                                  0.329    

Slack (MET) :             0.342ns  (arrival time - required time)
  Source:                 APPLE/ROMAddress_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            POMMEROM/data_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             sys_clk_pin
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        1.126ns  (logic 0.231ns (20.516%)  route 0.895ns (79.484%))
  Logic Levels:           2  (LUT6=2)
  Clock Path Skew:        0.270ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.992ns
    Source Clock Delay      (SCD):    1.475ns
    Clock Pessimism Removal (CPR):    0.247ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.548     1.460    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.053     0.406 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.482     0.888    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.914 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.561     1.475    APPLE/clk_out1
    SLICE_X29Y39         FDRE                                         r  APPLE/ROMAddress_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X29Y39         FDRE (Prop_fdre_C_Q)         0.141     1.616 r  APPLE/ROMAddress_reg[0]/Q
                         net (fo=26, routed)          0.481     2.096    APPLE/pommeROMAddress[0]
    SLICE_X31Y45         LUT6 (Prop_lut6_I0_O)        0.045     2.141 r  APPLE/data[1]_i_3/O
                         net (fo=1, routed)           0.414     2.556    APPLE/data[1]_i_3_n_0
    SLICE_X32Y45         LUT6 (Prop_lut6_I1_O)        0.045     2.601 r  APPLE/data[1]_i_1/O
                         net (fo=1, routed)           0.000     2.601    POMMEROM/D[1]
    SLICE_X32Y45         FDRE                                         r  POMMEROM/data_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.833     1.992    POMMEROM/H125MHz_IBUF_BUFG
    SLICE_X32Y45         FDRE                                         r  POMMEROM/data_reg[1]/C
                         clock pessimism             -0.247     1.745    
                         clock uncertainty            0.393     2.138    
    SLICE_X32Y45         FDRE (Hold_fdre_C_D)         0.120     2.258    POMMEROM/data_reg[1]
  -------------------------------------------------------------------
                         required time                         -2.258    
                         arrival time                           2.601    
  -------------------------------------------------------------------
                         slack                                  0.342    

Slack (MET) :             0.360ns  (arrival time - required time)
  Source:                 APPLE/ROMAddress_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            POMMEROM/data_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             sys_clk_pin
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        1.144ns  (logic 0.231ns (20.198%)  route 0.913ns (79.802%))
  Logic Levels:           2  (LUT5=1 LUT6=1)
  Clock Path Skew:        0.270ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.992ns
    Source Clock Delay      (SCD):    1.475ns
    Clock Pessimism Removal (CPR):    0.247ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.548     1.460    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.053     0.406 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.482     0.888    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.914 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.561     1.475    APPLE/clk_out1
    SLICE_X29Y39         FDRE                                         r  APPLE/ROMAddress_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X29Y39         FDRE (Prop_fdre_C_Q)         0.141     1.616 f  APPLE/ROMAddress_reg[1]/Q
                         net (fo=26, routed)          0.585     2.200    APPLE/pommeROMAddress[1]
    SLICE_X32Y43         LUT6 (Prop_lut6_I5_O)        0.045     2.245 r  APPLE/data[7]_i_3/O
                         net (fo=1, routed)           0.328     2.573    APPLE/data[7]_i_3_n_0
    SLICE_X32Y43         LUT5 (Prop_lut5_I2_O)        0.045     2.618 r  APPLE/data[7]_i_1__0/O
                         net (fo=1, routed)           0.000     2.618    POMMEROM/D[7]
    SLICE_X32Y43         FDRE                                         r  POMMEROM/data_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.833     1.992    POMMEROM/H125MHz_IBUF_BUFG
    SLICE_X32Y43         FDRE                                         r  POMMEROM/data_reg[7]/C
                         clock pessimism             -0.247     1.745    
                         clock uncertainty            0.393     2.138    
    SLICE_X32Y43         FDRE (Hold_fdre_C_D)         0.120     2.258    POMMEROM/data_reg[7]
  -------------------------------------------------------------------
                         required time                         -2.258    
                         arrival time                           2.618    
  -------------------------------------------------------------------
                         slack                                  0.360    





---------------------------------------------------------------------------------------------------
From Clock:  sys_clk_pin
  To Clock:  clk_out1_clk_wiz_0

Setup :            0  Failing Endpoints,  Worst Slack        1.409ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.091ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.409ns  (required time - arrival time)
  Source:                 APPLE/Xpos_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            APPLE/ROMAddress_reg[7]/CE
                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             clk_out1_clk_wiz_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (clk_out1_clk_wiz_0 rise@40.000ns - sys_clk_pin rise@32.000ns)
  Data Path Delay:        5.783ns  (logic 1.637ns (28.306%)  route 4.146ns (71.694%))
  Logic Levels:           5  (CARRY4=2 LUT2=1 LUT4=1 LUT6=1)
  Clock Path Skew:        -0.246ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.892ns = ( 44.892 - 40.000 ) 
    Source Clock Delay      (SCD):    5.414ns = ( 37.414 - 32.000 ) 
    Clock Pessimism Removal (CPR):    0.277ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                     32.000    32.000 r  
    L16                                               0.000    32.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    32.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491    33.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076    35.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101    35.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.746    37.414    APPLE/H125MHz_IBUF_BUFG
    SLICE_X38Y32         FDRE                                         r  APPLE/Xpos_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X38Y32         FDRE (Prop_fdre_C_Q)         0.518    37.932 r  APPLE/Xpos_reg[3]/Q
                         net (fo=28, routed)          1.556    39.488    APPLE/Xpos_reg[3]_0
    SLICE_X25Y40         LUT2 (Prop_lut2_I0_O)        0.124    39.612 r  APPLE/pommeHere_i_32/O
                         net (fo=4, routed)           0.466    40.078    APPLE/pommeHere_i_32_n_0
    SLICE_X22Y39         LUT6 (Prop_lut6_I3_O)        0.124    40.202 r  APPLE/pommeHere_i_24/O
                         net (fo=1, routed)           0.591    40.794    APPLE/pommeHere_i_24_n_0
    SLICE_X23Y39         CARRY4 (Prop_carry4_DI[3]_CO[3])
                                                      0.385    41.179 r  APPLE/pommeHere_reg_i_6/CO[3]
                         net (fo=1, routed)           0.000    41.179    APPLE/pommeHere_reg_i_6_n_0
    SLICE_X23Y40         CARRY4 (Prop_carry4_CI_CO[1])
                                                      0.157    41.336 r  APPLE/pommeHere_reg_i_2/CO[1]
                         net (fo=1, routed)           0.715    42.051    APPLE/pommeHere30_in
    SLICE_X25Y39         LUT4 (Prop_lut4_I0_O)        0.329    42.380 r  APPLE/pommeHere_i_1/O
                         net (fo=9, routed)           0.818    43.198    APPLE/pommeHere0
    SLICE_X28Y40         FDRE                                         r  APPLE/ROMAddress_reg[7]/CE
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                     40.000    40.000 r  
    L16                                               0.000    40.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    40.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421    41.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    43.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    43.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.490    44.882    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.177    41.705 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.599    43.304    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    43.395 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.497    44.892    APPLE/clk_out1
    SLICE_X28Y40         FDRE                                         r  APPLE/ROMAddress_reg[7]/C
                         clock pessimism              0.277    45.169    
                         clock uncertainty           -0.393    44.776    
    SLICE_X28Y40         FDRE (Setup_fdre_C_CE)      -0.169    44.607    APPLE/ROMAddress_reg[7]
  -------------------------------------------------------------------
                         required time                         44.607    
                         arrival time                         -43.198    
  -------------------------------------------------------------------
                         slack                                  1.409    

Slack (MET) :             1.443ns  (required time - arrival time)
  Source:                 APPLE/Xpos_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            APPLE/ROMAddress_reg[3]/CE
                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             clk_out1_clk_wiz_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (clk_out1_clk_wiz_0 rise@40.000ns - sys_clk_pin rise@32.000ns)
  Data Path Delay:        5.750ns  (logic 1.637ns (28.472%)  route 4.113ns (71.528%))
  Logic Levels:           5  (CARRY4=2 LUT2=1 LUT4=1 LUT6=1)
  Clock Path Skew:        -0.246ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.892ns = ( 44.892 - 40.000 ) 
    Source Clock Delay      (SCD):    5.414ns = ( 37.414 - 32.000 ) 
    Clock Pessimism Removal (CPR):    0.277ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                     32.000    32.000 r  
    L16                                               0.000    32.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    32.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491    33.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076    35.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101    35.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.746    37.414    APPLE/H125MHz_IBUF_BUFG
    SLICE_X38Y32         FDRE                                         r  APPLE/Xpos_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X38Y32         FDRE (Prop_fdre_C_Q)         0.518    37.932 r  APPLE/Xpos_reg[3]/Q
                         net (fo=28, routed)          1.556    39.488    APPLE/Xpos_reg[3]_0
    SLICE_X25Y40         LUT2 (Prop_lut2_I0_O)        0.124    39.612 r  APPLE/pommeHere_i_32/O
                         net (fo=4, routed)           0.466    40.078    APPLE/pommeHere_i_32_n_0
    SLICE_X22Y39         LUT6 (Prop_lut6_I3_O)        0.124    40.202 r  APPLE/pommeHere_i_24/O
                         net (fo=1, routed)           0.591    40.794    APPLE/pommeHere_i_24_n_0
    SLICE_X23Y39         CARRY4 (Prop_carry4_DI[3]_CO[3])
                                                      0.385    41.179 r  APPLE/pommeHere_reg_i_6/CO[3]
                         net (fo=1, routed)           0.000    41.179    APPLE/pommeHere_reg_i_6_n_0
    SLICE_X23Y40         CARRY4 (Prop_carry4_CI_CO[1])
                                                      0.157    41.336 r  APPLE/pommeHere_reg_i_2/CO[1]
                         net (fo=1, routed)           0.715    42.051    APPLE/pommeHere30_in
    SLICE_X25Y39         LUT4 (Prop_lut4_I0_O)        0.329    42.380 r  APPLE/pommeHere_i_1/O
                         net (fo=9, routed)           0.784    43.164    APPLE/pommeHere0
    SLICE_X30Y39         FDRE                                         r  APPLE/ROMAddress_reg[3]/CE
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                     40.000    40.000 r  
    L16                                               0.000    40.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    40.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421    41.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    43.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    43.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.490    44.882    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.177    41.705 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.599    43.304    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    43.395 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.497    44.892    APPLE/clk_out1
    SLICE_X30Y39         FDRE                                         r  APPLE/ROMAddress_reg[3]/C
                         clock pessimism              0.277    45.169    
                         clock uncertainty           -0.393    44.776    
    SLICE_X30Y39         FDRE (Setup_fdre_C_CE)      -0.169    44.607    APPLE/ROMAddress_reg[3]
  -------------------------------------------------------------------
                         required time                         44.607    
                         arrival time                         -43.164    
  -------------------------------------------------------------------
                         slack                                  1.443    

Slack (MET) :             1.587ns  (required time - arrival time)
  Source:                 APPLE/Xpos_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            APPLE/ROMAddress_reg[0]/CE
                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             clk_out1_clk_wiz_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (clk_out1_clk_wiz_0 rise@40.000ns - sys_clk_pin rise@32.000ns)
  Data Path Delay:        5.570ns  (logic 1.637ns (29.392%)  route 3.933ns (70.608%))
  Logic Levels:           5  (CARRY4=2 LUT2=1 LUT4=1 LUT6=1)
  Clock Path Skew:        -0.246ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.892ns = ( 44.892 - 40.000 ) 
    Source Clock Delay      (SCD):    5.414ns = ( 37.414 - 32.000 ) 
    Clock Pessimism Removal (CPR):    0.277ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                     32.000    32.000 r  
    L16                                               0.000    32.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    32.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491    33.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076    35.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101    35.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.746    37.414    APPLE/H125MHz_IBUF_BUFG
    SLICE_X38Y32         FDRE                                         r  APPLE/Xpos_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X38Y32         FDRE (Prop_fdre_C_Q)         0.518    37.932 r  APPLE/Xpos_reg[3]/Q
                         net (fo=28, routed)          1.556    39.488    APPLE/Xpos_reg[3]_0
    SLICE_X25Y40         LUT2 (Prop_lut2_I0_O)        0.124    39.612 r  APPLE/pommeHere_i_32/O
                         net (fo=4, routed)           0.466    40.078    APPLE/pommeHere_i_32_n_0
    SLICE_X22Y39         LUT6 (Prop_lut6_I3_O)        0.124    40.202 r  APPLE/pommeHere_i_24/O
                         net (fo=1, routed)           0.591    40.794    APPLE/pommeHere_i_24_n_0
    SLICE_X23Y39         CARRY4 (Prop_carry4_DI[3]_CO[3])
                                                      0.385    41.179 r  APPLE/pommeHere_reg_i_6/CO[3]
                         net (fo=1, routed)           0.000    41.179    APPLE/pommeHere_reg_i_6_n_0
    SLICE_X23Y40         CARRY4 (Prop_carry4_CI_CO[1])
                                                      0.157    41.336 r  APPLE/pommeHere_reg_i_2/CO[1]
                         net (fo=1, routed)           0.715    42.051    APPLE/pommeHere30_in
    SLICE_X25Y39         LUT4 (Prop_lut4_I0_O)        0.329    42.380 r  APPLE/pommeHere_i_1/O
                         net (fo=9, routed)           0.604    42.984    APPLE/pommeHere0
    SLICE_X29Y39         FDRE                                         r  APPLE/ROMAddress_reg[0]/CE
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                     40.000    40.000 r  
    L16                                               0.000    40.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    40.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421    41.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    43.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    43.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.490    44.882    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.177    41.705 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.599    43.304    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    43.395 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.497    44.892    APPLE/clk_out1
    SLICE_X29Y39         FDRE                                         r  APPLE/ROMAddress_reg[0]/C
                         clock pessimism              0.277    45.169    
                         clock uncertainty           -0.393    44.776    
    SLICE_X29Y39         FDRE (Setup_fdre_C_CE)      -0.205    44.571    APPLE/ROMAddress_reg[0]
  -------------------------------------------------------------------
                         required time                         44.571    
                         arrival time                         -42.984    
  -------------------------------------------------------------------
                         slack                                  1.587    

Slack (MET) :             1.587ns  (required time - arrival time)
  Source:                 APPLE/Xpos_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            APPLE/ROMAddress_reg[1]/CE
                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             clk_out1_clk_wiz_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (clk_out1_clk_wiz_0 rise@40.000ns - sys_clk_pin rise@32.000ns)
  Data Path Delay:        5.570ns  (logic 1.637ns (29.392%)  route 3.933ns (70.608%))
  Logic Levels:           5  (CARRY4=2 LUT2=1 LUT4=1 LUT6=1)
  Clock Path Skew:        -0.246ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.892ns = ( 44.892 - 40.000 ) 
    Source Clock Delay      (SCD):    5.414ns = ( 37.414 - 32.000 ) 
    Clock Pessimism Removal (CPR):    0.277ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                     32.000    32.000 r  
    L16                                               0.000    32.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    32.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491    33.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076    35.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101    35.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.746    37.414    APPLE/H125MHz_IBUF_BUFG
    SLICE_X38Y32         FDRE                                         r  APPLE/Xpos_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X38Y32         FDRE (Prop_fdre_C_Q)         0.518    37.932 r  APPLE/Xpos_reg[3]/Q
                         net (fo=28, routed)          1.556    39.488    APPLE/Xpos_reg[3]_0
    SLICE_X25Y40         LUT2 (Prop_lut2_I0_O)        0.124    39.612 r  APPLE/pommeHere_i_32/O
                         net (fo=4, routed)           0.466    40.078    APPLE/pommeHere_i_32_n_0
    SLICE_X22Y39         LUT6 (Prop_lut6_I3_O)        0.124    40.202 r  APPLE/pommeHere_i_24/O
                         net (fo=1, routed)           0.591    40.794    APPLE/pommeHere_i_24_n_0
    SLICE_X23Y39         CARRY4 (Prop_carry4_DI[3]_CO[3])
                                                      0.385    41.179 r  APPLE/pommeHere_reg_i_6/CO[3]
                         net (fo=1, routed)           0.000    41.179    APPLE/pommeHere_reg_i_6_n_0
    SLICE_X23Y40         CARRY4 (Prop_carry4_CI_CO[1])
                                                      0.157    41.336 r  APPLE/pommeHere_reg_i_2/CO[1]
                         net (fo=1, routed)           0.715    42.051    APPLE/pommeHere30_in
    SLICE_X25Y39         LUT4 (Prop_lut4_I0_O)        0.329    42.380 r  APPLE/pommeHere_i_1/O
                         net (fo=9, routed)           0.604    42.984    APPLE/pommeHere0
    SLICE_X29Y39         FDRE                                         r  APPLE/ROMAddress_reg[1]/CE
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                     40.000    40.000 r  
    L16                                               0.000    40.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    40.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421    41.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    43.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    43.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.490    44.882    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.177    41.705 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.599    43.304    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    43.395 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.497    44.892    APPLE/clk_out1
    SLICE_X29Y39         FDRE                                         r  APPLE/ROMAddress_reg[1]/C
                         clock pessimism              0.277    45.169    
                         clock uncertainty           -0.393    44.776    
    SLICE_X29Y39         FDRE (Setup_fdre_C_CE)      -0.205    44.571    APPLE/ROMAddress_reg[1]
  -------------------------------------------------------------------
                         required time                         44.571    
                         arrival time                         -42.984    
  -------------------------------------------------------------------
                         slack                                  1.587    

Slack (MET) :             1.623ns  (required time - arrival time)
  Source:                 APPLE/Xpos_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            APPLE/ROMAddress_reg[2]/CE
                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             clk_out1_clk_wiz_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (clk_out1_clk_wiz_0 rise@40.000ns - sys_clk_pin rise@32.000ns)
  Data Path Delay:        5.570ns  (logic 1.637ns (29.392%)  route 3.933ns (70.608%))
  Logic Levels:           5  (CARRY4=2 LUT2=1 LUT4=1 LUT6=1)
  Clock Path Skew:        -0.246ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.892ns = ( 44.892 - 40.000 ) 
    Source Clock Delay      (SCD):    5.414ns = ( 37.414 - 32.000 ) 
    Clock Pessimism Removal (CPR):    0.277ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                     32.000    32.000 r  
    L16                                               0.000    32.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    32.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491    33.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076    35.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101    35.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.746    37.414    APPLE/H125MHz_IBUF_BUFG
    SLICE_X38Y32         FDRE                                         r  APPLE/Xpos_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X38Y32         FDRE (Prop_fdre_C_Q)         0.518    37.932 r  APPLE/Xpos_reg[3]/Q
                         net (fo=28, routed)          1.556    39.488    APPLE/Xpos_reg[3]_0
    SLICE_X25Y40         LUT2 (Prop_lut2_I0_O)        0.124    39.612 r  APPLE/pommeHere_i_32/O
                         net (fo=4, routed)           0.466    40.078    APPLE/pommeHere_i_32_n_0
    SLICE_X22Y39         LUT6 (Prop_lut6_I3_O)        0.124    40.202 r  APPLE/pommeHere_i_24/O
                         net (fo=1, routed)           0.591    40.794    APPLE/pommeHere_i_24_n_0
    SLICE_X23Y39         CARRY4 (Prop_carry4_DI[3]_CO[3])
                                                      0.385    41.179 r  APPLE/pommeHere_reg_i_6/CO[3]
                         net (fo=1, routed)           0.000    41.179    APPLE/pommeHere_reg_i_6_n_0
    SLICE_X23Y40         CARRY4 (Prop_carry4_CI_CO[1])
                                                      0.157    41.336 r  APPLE/pommeHere_reg_i_2/CO[1]
                         net (fo=1, routed)           0.715    42.051    APPLE/pommeHere30_in
    SLICE_X25Y39         LUT4 (Prop_lut4_I0_O)        0.329    42.380 r  APPLE/pommeHere_i_1/O
                         net (fo=9, routed)           0.604    42.984    APPLE/pommeHere0
    SLICE_X28Y39         FDRE                                         r  APPLE/ROMAddress_reg[2]/CE
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                     40.000    40.000 r  
    L16                                               0.000    40.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    40.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421    41.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    43.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    43.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.490    44.882    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.177    41.705 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.599    43.304    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    43.395 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.497    44.892    APPLE/clk_out1
    SLICE_X28Y39         FDRE                                         r  APPLE/ROMAddress_reg[2]/C
                         clock pessimism              0.277    45.169    
                         clock uncertainty           -0.393    44.776    
    SLICE_X28Y39         FDRE (Setup_fdre_C_CE)      -0.169    44.607    APPLE/ROMAddress_reg[2]
  -------------------------------------------------------------------
                         required time                         44.607    
                         arrival time                         -42.984    
  -------------------------------------------------------------------
                         slack                                  1.623    

Slack (MET) :             1.623ns  (required time - arrival time)
  Source:                 APPLE/Xpos_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            APPLE/ROMAddress_reg[4]/CE
                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             clk_out1_clk_wiz_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (clk_out1_clk_wiz_0 rise@40.000ns - sys_clk_pin rise@32.000ns)
  Data Path Delay:        5.570ns  (logic 1.637ns (29.392%)  route 3.933ns (70.608%))
  Logic Levels:           5  (CARRY4=2 LUT2=1 LUT4=1 LUT6=1)
  Clock Path Skew:        -0.246ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.892ns = ( 44.892 - 40.000 ) 
    Source Clock Delay      (SCD):    5.414ns = ( 37.414 - 32.000 ) 
    Clock Pessimism Removal (CPR):    0.277ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                     32.000    32.000 r  
    L16                                               0.000    32.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    32.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491    33.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076    35.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101    35.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.746    37.414    APPLE/H125MHz_IBUF_BUFG
    SLICE_X38Y32         FDRE                                         r  APPLE/Xpos_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X38Y32         FDRE (Prop_fdre_C_Q)         0.518    37.932 r  APPLE/Xpos_reg[3]/Q
                         net (fo=28, routed)          1.556    39.488    APPLE/Xpos_reg[3]_0
    SLICE_X25Y40         LUT2 (Prop_lut2_I0_O)        0.124    39.612 r  APPLE/pommeHere_i_32/O
                         net (fo=4, routed)           0.466    40.078    APPLE/pommeHere_i_32_n_0
    SLICE_X22Y39         LUT6 (Prop_lut6_I3_O)        0.124    40.202 r  APPLE/pommeHere_i_24/O
                         net (fo=1, routed)           0.591    40.794    APPLE/pommeHere_i_24_n_0
    SLICE_X23Y39         CARRY4 (Prop_carry4_DI[3]_CO[3])
                                                      0.385    41.179 r  APPLE/pommeHere_reg_i_6/CO[3]
                         net (fo=1, routed)           0.000    41.179    APPLE/pommeHere_reg_i_6_n_0
    SLICE_X23Y40         CARRY4 (Prop_carry4_CI_CO[1])
                                                      0.157    41.336 r  APPLE/pommeHere_reg_i_2/CO[1]
                         net (fo=1, routed)           0.715    42.051    APPLE/pommeHere30_in
    SLICE_X25Y39         LUT4 (Prop_lut4_I0_O)        0.329    42.380 r  APPLE/pommeHere_i_1/O
                         net (fo=9, routed)           0.604    42.984    APPLE/pommeHere0
    SLICE_X28Y39         FDRE                                         r  APPLE/ROMAddress_reg[4]/CE
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                     40.000    40.000 r  
    L16                                               0.000    40.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    40.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421    41.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    43.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    43.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.490    44.882    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.177    41.705 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.599    43.304    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    43.395 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.497    44.892    APPLE/clk_out1
    SLICE_X28Y39         FDRE                                         r  APPLE/ROMAddress_reg[4]/C
                         clock pessimism              0.277    45.169    
                         clock uncertainty           -0.393    44.776    
    SLICE_X28Y39         FDRE (Setup_fdre_C_CE)      -0.169    44.607    APPLE/ROMAddress_reg[4]
  -------------------------------------------------------------------
                         required time                         44.607    
                         arrival time                         -42.984    
  -------------------------------------------------------------------
                         slack                                  1.623    

Slack (MET) :             1.623ns  (required time - arrival time)
  Source:                 APPLE/Xpos_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            APPLE/ROMAddress_reg[5]/CE
                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             clk_out1_clk_wiz_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (clk_out1_clk_wiz_0 rise@40.000ns - sys_clk_pin rise@32.000ns)
  Data Path Delay:        5.570ns  (logic 1.637ns (29.392%)  route 3.933ns (70.608%))
  Logic Levels:           5  (CARRY4=2 LUT2=1 LUT4=1 LUT6=1)
  Clock Path Skew:        -0.246ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.892ns = ( 44.892 - 40.000 ) 
    Source Clock Delay      (SCD):    5.414ns = ( 37.414 - 32.000 ) 
    Clock Pessimism Removal (CPR):    0.277ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                     32.000    32.000 r  
    L16                                               0.000    32.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    32.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491    33.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076    35.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101    35.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.746    37.414    APPLE/H125MHz_IBUF_BUFG
    SLICE_X38Y32         FDRE                                         r  APPLE/Xpos_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X38Y32         FDRE (Prop_fdre_C_Q)         0.518    37.932 r  APPLE/Xpos_reg[3]/Q
                         net (fo=28, routed)          1.556    39.488    APPLE/Xpos_reg[3]_0
    SLICE_X25Y40         LUT2 (Prop_lut2_I0_O)        0.124    39.612 r  APPLE/pommeHere_i_32/O
                         net (fo=4, routed)           0.466    40.078    APPLE/pommeHere_i_32_n_0
    SLICE_X22Y39         LUT6 (Prop_lut6_I3_O)        0.124    40.202 r  APPLE/pommeHere_i_24/O
                         net (fo=1, routed)           0.591    40.794    APPLE/pommeHere_i_24_n_0
    SLICE_X23Y39         CARRY4 (Prop_carry4_DI[3]_CO[3])
                                                      0.385    41.179 r  APPLE/pommeHere_reg_i_6/CO[3]
                         net (fo=1, routed)           0.000    41.179    APPLE/pommeHere_reg_i_6_n_0
    SLICE_X23Y40         CARRY4 (Prop_carry4_CI_CO[1])
                                                      0.157    41.336 r  APPLE/pommeHere_reg_i_2/CO[1]
                         net (fo=1, routed)           0.715    42.051    APPLE/pommeHere30_in
    SLICE_X25Y39         LUT4 (Prop_lut4_I0_O)        0.329    42.380 r  APPLE/pommeHere_i_1/O
                         net (fo=9, routed)           0.604    42.984    APPLE/pommeHere0
    SLICE_X28Y39         FDRE                                         r  APPLE/ROMAddress_reg[5]/CE
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                     40.000    40.000 r  
    L16                                               0.000    40.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    40.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421    41.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    43.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    43.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.490    44.882    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.177    41.705 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.599    43.304    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    43.395 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.497    44.892    APPLE/clk_out1
    SLICE_X28Y39         FDRE                                         r  APPLE/ROMAddress_reg[5]/C
                         clock pessimism              0.277    45.169    
                         clock uncertainty           -0.393    44.776    
    SLICE_X28Y39         FDRE (Setup_fdre_C_CE)      -0.169    44.607    APPLE/ROMAddress_reg[5]
  -------------------------------------------------------------------
                         required time                         44.607    
                         arrival time                         -42.984    
  -------------------------------------------------------------------
                         slack                                  1.623    

Slack (MET) :             1.623ns  (required time - arrival time)
  Source:                 APPLE/Xpos_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            APPLE/ROMAddress_reg[6]/CE
                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             clk_out1_clk_wiz_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (clk_out1_clk_wiz_0 rise@40.000ns - sys_clk_pin rise@32.000ns)
  Data Path Delay:        5.570ns  (logic 1.637ns (29.392%)  route 3.933ns (70.608%))
  Logic Levels:           5  (CARRY4=2 LUT2=1 LUT4=1 LUT6=1)
  Clock Path Skew:        -0.246ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.892ns = ( 44.892 - 40.000 ) 
    Source Clock Delay      (SCD):    5.414ns = ( 37.414 - 32.000 ) 
    Clock Pessimism Removal (CPR):    0.277ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                     32.000    32.000 r  
    L16                                               0.000    32.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    32.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491    33.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076    35.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101    35.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.746    37.414    APPLE/H125MHz_IBUF_BUFG
    SLICE_X38Y32         FDRE                                         r  APPLE/Xpos_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X38Y32         FDRE (Prop_fdre_C_Q)         0.518    37.932 r  APPLE/Xpos_reg[3]/Q
                         net (fo=28, routed)          1.556    39.488    APPLE/Xpos_reg[3]_0
    SLICE_X25Y40         LUT2 (Prop_lut2_I0_O)        0.124    39.612 r  APPLE/pommeHere_i_32/O
                         net (fo=4, routed)           0.466    40.078    APPLE/pommeHere_i_32_n_0
    SLICE_X22Y39         LUT6 (Prop_lut6_I3_O)        0.124    40.202 r  APPLE/pommeHere_i_24/O
                         net (fo=1, routed)           0.591    40.794    APPLE/pommeHere_i_24_n_0
    SLICE_X23Y39         CARRY4 (Prop_carry4_DI[3]_CO[3])
                                                      0.385    41.179 r  APPLE/pommeHere_reg_i_6/CO[3]
                         net (fo=1, routed)           0.000    41.179    APPLE/pommeHere_reg_i_6_n_0
    SLICE_X23Y40         CARRY4 (Prop_carry4_CI_CO[1])
                                                      0.157    41.336 r  APPLE/pommeHere_reg_i_2/CO[1]
                         net (fo=1, routed)           0.715    42.051    APPLE/pommeHere30_in
    SLICE_X25Y39         LUT4 (Prop_lut4_I0_O)        0.329    42.380 r  APPLE/pommeHere_i_1/O
                         net (fo=9, routed)           0.604    42.984    APPLE/pommeHere0
    SLICE_X28Y39         FDRE                                         r  APPLE/ROMAddress_reg[6]/CE
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                     40.000    40.000 r  
    L16                                               0.000    40.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    40.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421    41.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    43.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    43.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.490    44.882    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.177    41.705 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.599    43.304    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    43.395 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.497    44.892    APPLE/clk_out1
    SLICE_X28Y39         FDRE                                         r  APPLE/ROMAddress_reg[6]/C
                         clock pessimism              0.277    45.169    
                         clock uncertainty           -0.393    44.776    
    SLICE_X28Y39         FDRE (Setup_fdre_C_CE)      -0.169    44.607    APPLE/ROMAddress_reg[6]
  -------------------------------------------------------------------
                         required time                         44.607    
                         arrival time                         -42.984    
  -------------------------------------------------------------------
                         slack                                  1.623    

Slack (MET) :             1.766ns  (required time - arrival time)
  Source:                 APPLE/Xpos_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            APPLE/pommeHere_reg/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             clk_out1_clk_wiz_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (clk_out1_clk_wiz_0 rise@40.000ns - sys_clk_pin rise@32.000ns)
  Data Path Delay:        5.565ns  (logic 1.637ns (29.418%)  route 3.928ns (70.582%))
  Logic Levels:           5  (CARRY4=2 LUT2=1 LUT4=1 LUT6=1)
  Clock Path Skew:        -0.246ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.892ns = ( 44.892 - 40.000 ) 
    Source Clock Delay      (SCD):    5.414ns = ( 37.414 - 32.000 ) 
    Clock Pessimism Removal (CPR):    0.277ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                     32.000    32.000 r  
    L16                                               0.000    32.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    32.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491    33.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076    35.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101    35.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.746    37.414    APPLE/H125MHz_IBUF_BUFG
    SLICE_X38Y32         FDRE                                         r  APPLE/Xpos_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X38Y32         FDRE (Prop_fdre_C_Q)         0.518    37.932 r  APPLE/Xpos_reg[3]/Q
                         net (fo=28, routed)          1.556    39.488    APPLE/Xpos_reg[3]_0
    SLICE_X25Y40         LUT2 (Prop_lut2_I0_O)        0.124    39.612 r  APPLE/pommeHere_i_32/O
                         net (fo=4, routed)           0.466    40.078    APPLE/pommeHere_i_32_n_0
    SLICE_X22Y39         LUT6 (Prop_lut6_I3_O)        0.124    40.202 r  APPLE/pommeHere_i_24/O
                         net (fo=1, routed)           0.591    40.794    APPLE/pommeHere_i_24_n_0
    SLICE_X23Y39         CARRY4 (Prop_carry4_DI[3]_CO[3])
                                                      0.385    41.179 r  APPLE/pommeHere_reg_i_6/CO[3]
                         net (fo=1, routed)           0.000    41.179    APPLE/pommeHere_reg_i_6_n_0
    SLICE_X23Y40         CARRY4 (Prop_carry4_CI_CO[1])
                                                      0.157    41.336 r  APPLE/pommeHere_reg_i_2/CO[1]
                         net (fo=1, routed)           0.715    42.051    APPLE/pommeHere30_in
    SLICE_X25Y39         LUT4 (Prop_lut4_I0_O)        0.329    42.380 r  APPLE/pommeHere_i_1/O
                         net (fo=9, routed)           0.599    42.979    APPLE/pommeHere0
    SLICE_X30Y40         FDRE                                         r  APPLE/pommeHere_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                     40.000    40.000 r  
    L16                                               0.000    40.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    40.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421    41.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    43.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    43.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.490    44.882    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.177    41.705 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.599    43.304    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    43.395 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.497    44.892    APPLE/clk_out1
    SLICE_X30Y40         FDRE                                         r  APPLE/pommeHere_reg/C
                         clock pessimism              0.277    45.169    
                         clock uncertainty           -0.393    44.776    
    SLICE_X30Y40         FDRE (Setup_fdre_C_D)       -0.031    44.745    APPLE/pommeHere_reg
  -------------------------------------------------------------------
                         required time                         44.745    
                         arrival time                         -42.979    
  -------------------------------------------------------------------
                         slack                                  1.766    

Slack (MET) :             2.200ns  (required time - arrival time)
  Source:                 APPLE/Xpos_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            APPLE/ROMAddress_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             clk_out1_clk_wiz_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (clk_out1_clk_wiz_0 rise@40.000ns - sys_clk_pin rise@32.000ns)
  Data Path Delay:        5.271ns  (logic 1.978ns (37.530%)  route 3.293ns (62.470%))
  Logic Levels:           6  (CARRY4=3 LUT2=2 LUT6=1)
  Clock Path Skew:        -0.246ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.892ns = ( 44.892 - 40.000 ) 
    Source Clock Delay      (SCD):    5.414ns = ( 37.414 - 32.000 ) 
    Clock Pessimism Removal (CPR):    0.277ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                     32.000    32.000 r  
    L16                                               0.000    32.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    32.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491    33.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076    35.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101    35.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.746    37.414    APPLE/H125MHz_IBUF_BUFG
    SLICE_X38Y32         FDRE                                         r  APPLE/Xpos_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X38Y32         FDRE (Prop_fdre_C_Q)         0.518    37.932 r  APPLE/Xpos_reg[3]/Q
                         net (fo=28, routed)          1.749    39.681    APPLE/Xpos_reg[3]_0
    SLICE_X25Y35         LUT2 (Prop_lut2_I0_O)        0.124    39.805 r  APPLE/ROMAddress[3]_i_11__0/O
                         net (fo=1, routed)           0.000    39.805    SYNC/ROMAddress[3]_i_5__0[0]
    SLICE_X25Y35         CARRY4 (Prop_carry4_S[3]_O[3])
                                                      0.248    40.053 r  SYNC/ROMAddress_reg[3]_i_3/O[3]
                         net (fo=1, routed)           0.940    40.993    APPLE/A[3]
    SLICE_X29Y39         LUT6 (Prop_lut6_I0_O)        0.306    41.299 r  APPLE/ROMAddress[7]_i_4/O
                         net (fo=1, routed)           0.000    41.299    APPLE/ROMAddress[7]_i_4_n_0
    SLICE_X29Y39         CARRY4 (Prop_carry4_S[1]_O[1])
                                                      0.227    41.526 r  APPLE/ROMAddress_reg[7]_i_3/O[1]
                         net (fo=1, routed)           0.604    42.130    SYNC/ROMAddress_reg[7][1]
    SLICE_X28Y40         LUT2 (Prop_lut2_I1_O)        0.303    42.433 r  SYNC/ROMAddress[7]_i_2__0/O
                         net (fo=1, routed)           0.000    42.433    SYNC/ROMAddress[7]_i_2__0_n_0
    SLICE_X28Y40         CARRY4 (Prop_carry4_S[0]_O[0])
                                                      0.252    42.685 r  SYNC/ROMAddress_reg[7]_i_1__0/O[0]
                         net (fo=1, routed)           0.000    42.685    APPLE/D[4]
    SLICE_X28Y40         FDRE                                         r  APPLE/ROMAddress_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                     40.000    40.000 r  
    L16                                               0.000    40.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    40.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421    41.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    43.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    43.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.490    44.882    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.177    41.705 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.599    43.304    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    43.395 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.497    44.892    APPLE/clk_out1
    SLICE_X28Y40         FDRE                                         r  APPLE/ROMAddress_reg[7]/C
                         clock pessimism              0.277    45.169    
                         clock uncertainty           -0.393    44.776    
    SLICE_X28Y40         FDRE (Setup_fdre_C_D)        0.109    44.885    APPLE/ROMAddress_reg[7]
  -------------------------------------------------------------------
                         required time                         44.885    
                         arrival time                         -42.685    
  -------------------------------------------------------------------
                         slack                                  2.200    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.091ns  (arrival time - required time)
  Source:                 ROM/data_reg[17]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            SNAKE/snakeColor_reg[G][4]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             clk_out1_clk_wiz_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        0.864ns  (logic 0.207ns (23.956%)  route 0.657ns (76.044%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.273ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.992ns
    Source Clock Delay      (SCD):    1.472ns
    Clock Pessimism Removal (CPR):    0.247ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.560     1.472    ROM/H125MHz_IBUF_BUFG
    SLICE_X32Y51         FDRE                                         r  ROM/data_reg[17]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X32Y51         FDRE (Prop_fdre_C_Q)         0.164     1.636 r  ROM/data_reg[17]/Q
                         net (fo=1, routed)           0.657     2.293    SNAKE/spritesROMData[7]
    SLICE_X33Y50         LUT2 (Prop_lut2_I1_O)        0.043     2.336 r  SNAKE/snakeColor[G][4]_i_1/O
                         net (fo=1, routed)           0.000     2.336    SNAKE/snakeColor[G][4]_i_1_n_0
    SLICE_X33Y50         FDCE                                         r  SNAKE/snakeColor_reg[G][4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.814     1.973    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.369     0.604 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.528     1.132    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.161 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.831     1.992    SNAKE/clk_out1
    SLICE_X33Y50         FDCE                                         r  SNAKE/snakeColor_reg[G][4]/C
                         clock pessimism             -0.247     1.745    
                         clock uncertainty            0.393     2.138    
    SLICE_X33Y50         FDCE (Hold_fdce_C_D)         0.107     2.245    SNAKE/snakeColor_reg[G][4]
  -------------------------------------------------------------------
                         required time                         -2.245    
                         arrival time                           2.336    
  -------------------------------------------------------------------
                         slack                                  0.091    

Slack (MET) :             0.130ns  (arrival time - required time)
  Source:                 ROM/data_reg[22]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            SNAKE/snakeColor_reg[R][3]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             clk_out1_clk_wiz_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        0.903ns  (logic 0.209ns (23.138%)  route 0.694ns (76.862%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.273ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.992ns
    Source Clock Delay      (SCD):    1.472ns
    Clock Pessimism Removal (CPR):    0.247ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.560     1.472    ROM/H125MHz_IBUF_BUFG
    SLICE_X30Y52         FDRE                                         r  ROM/data_reg[22]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X30Y52         FDRE (Prop_fdre_C_Q)         0.164     1.636 r  ROM/data_reg[22]/Q
                         net (fo=1, routed)           0.694     2.330    SNAKE/spritesROMData[11]
    SLICE_X31Y50         LUT2 (Prop_lut2_I1_O)        0.045     2.375 r  SNAKE/snakeColor[R][3]_i_1/O
                         net (fo=1, routed)           0.000     2.375    SNAKE/snakeColor[R][3]_i_1_n_0
    SLICE_X31Y50         FDCE                                         r  SNAKE/snakeColor_reg[R][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.814     1.973    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.369     0.604 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.528     1.132    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.161 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.831     1.992    SNAKE/clk_out1
    SLICE_X31Y50         FDCE                                         r  SNAKE/snakeColor_reg[R][3]/C
                         clock pessimism             -0.247     1.745    
                         clock uncertainty            0.393     2.138    
    SLICE_X31Y50         FDCE (Hold_fdce_C_D)         0.107     2.245    SNAKE/snakeColor_reg[R][3]
  -------------------------------------------------------------------
                         required time                         -2.245    
                         arrival time                           2.375    
  -------------------------------------------------------------------
                         slack                                  0.130    

Slack (MET) :             0.140ns  (arrival time - required time)
  Source:                 ROM/data_reg[16]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            SNAKE/snakeColor_reg[G][3]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             clk_out1_clk_wiz_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        0.898ns  (logic 0.209ns (23.271%)  route 0.689ns (76.729%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.273ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.992ns
    Source Clock Delay      (SCD):    1.472ns
    Clock Pessimism Removal (CPR):    0.247ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.560     1.472    ROM/H125MHz_IBUF_BUFG
    SLICE_X32Y52         FDRE                                         r  ROM/data_reg[16]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X32Y52         FDRE (Prop_fdre_C_Q)         0.164     1.636 r  ROM/data_reg[16]/Q
                         net (fo=1, routed)           0.689     2.325    SNAKE/spritesROMData[6]
    SLICE_X33Y50         LUT2 (Prop_lut2_I1_O)        0.045     2.370 r  SNAKE/snakeColor[G][3]_i_1/O
                         net (fo=1, routed)           0.000     2.370    SNAKE/snakeColor[G][3]_i_1_n_0
    SLICE_X33Y50         FDCE                                         r  SNAKE/snakeColor_reg[G][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.814     1.973    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.369     0.604 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.528     1.132    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.161 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.831     1.992    SNAKE/clk_out1
    SLICE_X33Y50         FDCE                                         r  SNAKE/snakeColor_reg[G][3]/C
                         clock pessimism             -0.247     1.745    
                         clock uncertainty            0.393     2.138    
    SLICE_X33Y50         FDCE (Hold_fdce_C_D)         0.092     2.230    SNAKE/snakeColor_reg[G][3]
  -------------------------------------------------------------------
                         required time                         -2.230    
                         arrival time                           2.370    
  -------------------------------------------------------------------
                         slack                                  0.140    

Slack (MET) :             0.147ns  (arrival time - required time)
  Source:                 ROM/data_reg[9]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            SNAKE/snakeColor_reg[B][1]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             clk_out1_clk_wiz_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        0.904ns  (logic 0.209ns (23.115%)  route 0.695ns (76.885%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.273ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.992ns
    Source Clock Delay      (SCD):    1.472ns
    Clock Pessimism Removal (CPR):    0.247ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.560     1.472    ROM/H125MHz_IBUF_BUFG
    SLICE_X30Y50         FDRE                                         r  ROM/data_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X30Y50         FDRE (Prop_fdre_C_Q)         0.164     1.636 r  ROM/data_reg[9]/Q
                         net (fo=1, routed)           0.695     2.331    SNAKE/spritesROMData[1]
    SLICE_X31Y50         LUT2 (Prop_lut2_I1_O)        0.045     2.376 r  SNAKE/snakeColor[B][1]_i_1/O
                         net (fo=1, routed)           0.000     2.376    SNAKE/snakeColor[B][1]_i_1_n_0
    SLICE_X31Y50         FDCE                                         r  SNAKE/snakeColor_reg[B][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.814     1.973    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.369     0.604 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.528     1.132    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.161 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.831     1.992    SNAKE/clk_out1
    SLICE_X31Y50         FDCE                                         r  SNAKE/snakeColor_reg[B][1]/C
                         clock pessimism             -0.247     1.745    
                         clock uncertainty            0.393     2.138    
    SLICE_X31Y50         FDCE (Hold_fdce_C_D)         0.091     2.229    SNAKE/snakeColor_reg[B][1]
  -------------------------------------------------------------------
                         required time                         -2.229    
                         arrival time                           2.376    
  -------------------------------------------------------------------
                         slack                                  0.147    

Slack (MET) :             0.151ns  (arrival time - required time)
  Source:                 ROM/data_reg[13]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            SNAKE/snakeColor_reg[G][0]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             clk_out1_clk_wiz_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        0.903ns  (logic 0.209ns (23.141%)  route 0.694ns (76.859%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.268ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.993ns
    Source Clock Delay      (SCD):    1.478ns
    Clock Pessimism Removal (CPR):    0.247ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.566     1.478    ROM/H125MHz_IBUF_BUFG
    SLICE_X30Y49         FDRE                                         r  ROM/data_reg[13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X30Y49         FDRE (Prop_fdre_C_Q)         0.164     1.642 r  ROM/data_reg[13]/Q
                         net (fo=1, routed)           0.694     2.336    SNAKE/spritesROMData[3]
    SLICE_X31Y49         LUT2 (Prop_lut2_I1_O)        0.045     2.381 r  SNAKE/snakeColor[G][0]_i_1/O
                         net (fo=1, routed)           0.000     2.381    SNAKE/snakeColor[G][0]_i_1_n_0
    SLICE_X31Y49         FDCE                                         r  SNAKE/snakeColor_reg[G][0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.814     1.973    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.369     0.604 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.528     1.132    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.161 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.832     1.993    SNAKE/clk_out1
    SLICE_X31Y49         FDCE                                         r  SNAKE/snakeColor_reg[G][0]/C
                         clock pessimism             -0.247     1.746    
                         clock uncertainty            0.393     2.139    
    SLICE_X31Y49         FDCE (Hold_fdce_C_D)         0.091     2.230    SNAKE/snakeColor_reg[G][0]
  -------------------------------------------------------------------
                         required time                         -2.230    
                         arrival time                           2.381    
  -------------------------------------------------------------------
                         slack                                  0.151    

Slack (MET) :             0.157ns  (arrival time - required time)
  Source:                 ROM/data_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            SNAKE/snakeColor_reg[A][7]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             clk_out1_clk_wiz_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        0.915ns  (logic 0.186ns (20.331%)  route 0.729ns (79.669%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.273ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.992ns
    Source Clock Delay      (SCD):    1.472ns
    Clock Pessimism Removal (CPR):    0.247ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.560     1.472    ROM/H125MHz_IBUF_BUFG
    SLICE_X33Y52         FDRE                                         r  ROM/data_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X33Y52         FDRE (Prop_fdre_C_Q)         0.141     1.613 r  ROM/data_reg[7]/Q
                         net (fo=1, routed)           0.729     2.342    SNAKE/spritesROMData[0]
    SLICE_X33Y50         LUT2 (Prop_lut2_I1_O)        0.045     2.387 r  SNAKE/snakeColor[A][7]_i_1/O
                         net (fo=1, routed)           0.000     2.387    SNAKE/snakeColor[A][7]_i_1_n_0
    SLICE_X33Y50         FDCE                                         r  SNAKE/snakeColor_reg[A][7]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.814     1.973    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.369     0.604 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.528     1.132    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.161 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.831     1.992    SNAKE/clk_out1
    SLICE_X33Y50         FDCE                                         r  SNAKE/snakeColor_reg[A][7]/C
                         clock pessimism             -0.247     1.745    
                         clock uncertainty            0.393     2.138    
    SLICE_X33Y50         FDCE (Hold_fdce_C_D)         0.091     2.229    SNAKE/snakeColor_reg[A][7]
  -------------------------------------------------------------------
                         required time                         -2.229    
                         arrival time                           2.387    
  -------------------------------------------------------------------
                         slack                                  0.157    

Slack (MET) :             0.167ns  (arrival time - required time)
  Source:                 ROM/data_reg[15]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            SNAKE/snakeColor_reg[G][2]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             clk_out1_clk_wiz_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        0.936ns  (logic 0.183ns (19.552%)  route 0.753ns (80.448%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.268ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.993ns
    Source Clock Delay      (SCD):    1.478ns
    Clock Pessimism Removal (CPR):    0.247ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.566     1.478    ROM/H125MHz_IBUF_BUFG
    SLICE_X26Y48         FDRE                                         r  ROM/data_reg[15]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X26Y48         FDRE (Prop_fdre_C_Q)         0.141     1.619 r  ROM/data_reg[15]/Q
                         net (fo=1, routed)           0.753     2.372    SNAKE/spritesROMData[5]
    SLICE_X33Y49         LUT2 (Prop_lut2_I1_O)        0.042     2.414 r  SNAKE/snakeColor[G][2]_i_1/O
                         net (fo=1, routed)           0.000     2.414    SNAKE/snakeColor[G][2]_i_1_n_0
    SLICE_X33Y49         FDCE                                         r  SNAKE/snakeColor_reg[G][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.814     1.973    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.369     0.604 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.528     1.132    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.161 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.832     1.993    SNAKE/clk_out1
    SLICE_X33Y49         FDCE                                         r  SNAKE/snakeColor_reg[G][2]/C
                         clock pessimism             -0.247     1.746    
                         clock uncertainty            0.393     2.139    
    SLICE_X33Y49         FDCE (Hold_fdce_C_D)         0.107     2.246    SNAKE/snakeColor_reg[G][2]
  -------------------------------------------------------------------
                         required time                         -2.246    
                         arrival time                           2.414    
  -------------------------------------------------------------------
                         slack                                  0.167    

Slack (MET) :             0.177ns  (arrival time - required time)
  Source:                 POMMEROM/data_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            APPLE/colorOut_reg[G][3]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             clk_out1_clk_wiz_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        0.848ns  (logic 0.148ns (17.450%)  route 0.700ns (82.550%))
  Logic Levels:           0  
  Clock Path Skew:        0.268ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.992ns
    Source Clock Delay      (SCD):    1.477ns
    Clock Pessimism Removal (CPR):    0.247ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.565     1.477    POMMEROM/H125MHz_IBUF_BUFG
    SLICE_X30Y45         FDRE                                         r  POMMEROM/data_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X30Y45         FDRE (Prop_fdre_C_Q)         0.148     1.625 r  POMMEROM/data_reg[4]/Q
                         net (fo=1, routed)           0.700     2.325    APPLE/Q[4]
    SLICE_X32Y46         FDRE                                         r  APPLE/colorOut_reg[G][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.814     1.973    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.369     0.604 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.528     1.132    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.161 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.831     1.992    APPLE/clk_out1
    SLICE_X32Y46         FDRE                                         r  APPLE/colorOut_reg[G][3]/C
                         clock pessimism             -0.247     1.745    
                         clock uncertainty            0.393     2.138    
    SLICE_X32Y46         FDRE (Hold_fdre_C_D)         0.010     2.148    APPLE/colorOut_reg[G][3]
  -------------------------------------------------------------------
                         required time                         -2.148    
                         arrival time                           2.325    
  -------------------------------------------------------------------
                         slack                                  0.177    

Slack (MET) :             0.189ns  (arrival time - required time)
  Source:                 POMMEROM/data_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            APPLE/colorOut_reg[R][2]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             clk_out1_clk_wiz_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        0.917ns  (logic 0.164ns (17.893%)  route 0.753ns (82.107%))
  Logic Levels:           0  
  Clock Path Skew:        0.268ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.992ns
    Source Clock Delay      (SCD):    1.477ns
    Clock Pessimism Removal (CPR):    0.247ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.565     1.477    POMMEROM/H125MHz_IBUF_BUFG
    SLICE_X32Y43         FDRE                                         r  POMMEROM/data_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X32Y43         FDRE (Prop_fdre_C_Q)         0.164     1.641 r  POMMEROM/data_reg[7]/Q
                         net (fo=1, routed)           0.753     2.393    APPLE/Q[7]
    SLICE_X33Y44         FDRE                                         r  APPLE/colorOut_reg[R][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.814     1.973    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.369     0.604 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.528     1.132    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.161 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.831     1.992    APPLE/clk_out1
    SLICE_X33Y44         FDRE                                         r  APPLE/colorOut_reg[R][2]/C
                         clock pessimism             -0.247     1.745    
                         clock uncertainty            0.393     2.138    
    SLICE_X33Y44         FDRE (Hold_fdre_C_D)         0.066     2.204    APPLE/colorOut_reg[R][2]
  -------------------------------------------------------------------
                         required time                         -2.204    
                         arrival time                           2.393    
  -------------------------------------------------------------------
                         slack                                  0.189    

Slack (MET) :             0.191ns  (arrival time - required time)
  Source:                 POMMEROM/data_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            APPLE/colorOut_reg[R][1]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             clk_out1_clk_wiz_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        0.923ns  (logic 0.164ns (17.777%)  route 0.759ns (82.223%))
  Logic Levels:           0  
  Clock Path Skew:        0.268ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.992ns
    Source Clock Delay      (SCD):    1.477ns
    Clock Pessimism Removal (CPR):    0.247ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.565     1.477    POMMEROM/H125MHz_IBUF_BUFG
    SLICE_X32Y44         FDRE                                         r  POMMEROM/data_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X32Y44         FDRE (Prop_fdre_C_Q)         0.164     1.641 r  POMMEROM/data_reg[6]/Q
                         net (fo=1, routed)           0.759     2.399    APPLE/Q[6]
    SLICE_X33Y44         FDRE                                         r  APPLE/colorOut_reg[R][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.814     1.973    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.369     0.604 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.528     1.132    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.161 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.831     1.992    APPLE/clk_out1
    SLICE_X33Y44         FDRE                                         r  APPLE/colorOut_reg[R][1]/C
                         clock pessimism             -0.247     1.745    
                         clock uncertainty            0.393     2.138    
    SLICE_X33Y44         FDRE (Hold_fdre_C_D)         0.070     2.208    APPLE/colorOut_reg[R][1]
  -------------------------------------------------------------------
                         required time                         -2.208    
                         arrival time                           2.399    
  -------------------------------------------------------------------
                         slack                                  0.191    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  clk_out1_clk_wiz_0
  To Clock:  clk_out1_clk_wiz_0

Setup :            0  Failing Endpoints,  Worst Slack       34.780ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        1.074ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             34.780ns  (required time - arrival time)
  Source:                 UPD_CLK_DIV/temp_reg[5]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            UPD_CLK_DIV/temp_reg[0]/CLR
                            (recovery check against rising-edge clock clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            40.000ns  (clk_out1_clk_wiz_0 rise@40.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        4.644ns  (logic 1.888ns (40.655%)  route 2.756ns (59.345%))
  Logic Levels:           5  (CARRY4=3 LUT2=1 LUT4=1)
  Clock Path Skew:        -0.024ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.881ns = ( 44.881 - 40.000 ) 
    Source Clock Delay      (SCD):    5.330ns
    Clock Pessimism Removal (CPR):    0.425ns
  Clock Uncertainty:      0.147ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491     1.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076     3.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101     3.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.680     5.348    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.538     1.810 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.760     3.570    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.101     3.671 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.659     5.330    UPD_CLK_DIV/clk_out1
    SLICE_X33Y62         FDCE                                         r  UPD_CLK_DIV/temp_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X33Y62         FDCE (Prop_fdce_C_Q)         0.456     5.786 r  UPD_CLK_DIV/temp_reg[5]/Q
                         net (fo=4, routed)           1.108     6.895    UPD_CLK_DIV/temp_reg[5]
    SLICE_X31Y63         LUT4 (Prop_lut4_I2_O)        0.124     7.019 r  UPD_CLK_DIV/temp[0]_i_14/O
                         net (fo=1, routed)           0.000     7.019    UPD_CLK_DIV/temp[0]_i_14_n_0
    SLICE_X31Y63         CARRY4 (Prop_carry4_S[1]_CO[3])
                                                      0.550     7.569 r  UPD_CLK_DIV/temp_reg[0]_i_7/CO[3]
                         net (fo=1, routed)           0.000     7.569    UPD_CLK_DIV/temp_reg[0]_i_7_n_0
    SLICE_X31Y64         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     7.683 r  UPD_CLK_DIV/temp_reg[0]_i_5/CO[3]
                         net (fo=1, routed)           0.000     7.683    UPD_CLK_DIV/temp_reg[0]_i_5_n_0
    SLICE_X31Y65         CARRY4 (Prop_carry4_CI_CO[0])
                                                      0.271     7.954 f  UPD_CLK_DIV/temp_reg[0]_i_4/CO[0]
                         net (fo=1, routed)           0.405     8.358    UPD_CLK_DIV/temp_reg[0]_i_4_n_3
    SLICE_X31Y66         LUT2 (Prop_lut2_I0_O)        0.373     8.731 f  UPD_CLK_DIV/temp[0]_i_2/O
                         net (fo=25, routed)          1.243     9.974    UPD_CLK_DIV/temp[0]_i_2_n_0
    SLICE_X33Y61         FDCE                                         f  UPD_CLK_DIV/temp_reg[0]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                     40.000    40.000 r  
    L16                                               0.000    40.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    40.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421    41.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    43.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    43.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.490    44.882    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.177    41.705 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.599    43.304    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    43.395 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.487    44.881    UPD_CLK_DIV/clk_out1
    SLICE_X33Y61         FDCE                                         r  UPD_CLK_DIV/temp_reg[0]/C
                         clock pessimism              0.425    45.306    
                         clock uncertainty           -0.147    45.159    
    SLICE_X33Y61         FDCE (Recov_fdce_C_CLR)     -0.405    44.754    UPD_CLK_DIV/temp_reg[0]
  -------------------------------------------------------------------
                         required time                         44.754    
                         arrival time                          -9.974    
  -------------------------------------------------------------------
                         slack                                 34.780    

Slack (MET) :             34.780ns  (required time - arrival time)
  Source:                 UPD_CLK_DIV/temp_reg[5]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            UPD_CLK_DIV/temp_reg[1]/CLR
                            (recovery check against rising-edge clock clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            40.000ns  (clk_out1_clk_wiz_0 rise@40.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        4.644ns  (logic 1.888ns (40.655%)  route 2.756ns (59.345%))
  Logic Levels:           5  (CARRY4=3 LUT2=1 LUT4=1)
  Clock Path Skew:        -0.024ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.881ns = ( 44.881 - 40.000 ) 
    Source Clock Delay      (SCD):    5.330ns
    Clock Pessimism Removal (CPR):    0.425ns
  Clock Uncertainty:      0.147ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491     1.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076     3.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101     3.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.680     5.348    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.538     1.810 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.760     3.570    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.101     3.671 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.659     5.330    UPD_CLK_DIV/clk_out1
    SLICE_X33Y62         FDCE                                         r  UPD_CLK_DIV/temp_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X33Y62         FDCE (Prop_fdce_C_Q)         0.456     5.786 r  UPD_CLK_DIV/temp_reg[5]/Q
                         net (fo=4, routed)           1.108     6.895    UPD_CLK_DIV/temp_reg[5]
    SLICE_X31Y63         LUT4 (Prop_lut4_I2_O)        0.124     7.019 r  UPD_CLK_DIV/temp[0]_i_14/O
                         net (fo=1, routed)           0.000     7.019    UPD_CLK_DIV/temp[0]_i_14_n_0
    SLICE_X31Y63         CARRY4 (Prop_carry4_S[1]_CO[3])
                                                      0.550     7.569 r  UPD_CLK_DIV/temp_reg[0]_i_7/CO[3]
                         net (fo=1, routed)           0.000     7.569    UPD_CLK_DIV/temp_reg[0]_i_7_n_0
    SLICE_X31Y64         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     7.683 r  UPD_CLK_DIV/temp_reg[0]_i_5/CO[3]
                         net (fo=1, routed)           0.000     7.683    UPD_CLK_DIV/temp_reg[0]_i_5_n_0
    SLICE_X31Y65         CARRY4 (Prop_carry4_CI_CO[0])
                                                      0.271     7.954 f  UPD_CLK_DIV/temp_reg[0]_i_4/CO[0]
                         net (fo=1, routed)           0.405     8.358    UPD_CLK_DIV/temp_reg[0]_i_4_n_3
    SLICE_X31Y66         LUT2 (Prop_lut2_I0_O)        0.373     8.731 f  UPD_CLK_DIV/temp[0]_i_2/O
                         net (fo=25, routed)          1.243     9.974    UPD_CLK_DIV/temp[0]_i_2_n_0
    SLICE_X33Y61         FDCE                                         f  UPD_CLK_DIV/temp_reg[1]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                     40.000    40.000 r  
    L16                                               0.000    40.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    40.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421    41.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    43.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    43.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.490    44.882    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.177    41.705 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.599    43.304    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    43.395 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.487    44.881    UPD_CLK_DIV/clk_out1
    SLICE_X33Y61         FDCE                                         r  UPD_CLK_DIV/temp_reg[1]/C
                         clock pessimism              0.425    45.306    
                         clock uncertainty           -0.147    45.159    
    SLICE_X33Y61         FDCE (Recov_fdce_C_CLR)     -0.405    44.754    UPD_CLK_DIV/temp_reg[1]
  -------------------------------------------------------------------
                         required time                         44.754    
                         arrival time                          -9.974    
  -------------------------------------------------------------------
                         slack                                 34.780    

Slack (MET) :             34.780ns  (required time - arrival time)
  Source:                 UPD_CLK_DIV/temp_reg[5]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            UPD_CLK_DIV/temp_reg[2]/CLR
                            (recovery check against rising-edge clock clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            40.000ns  (clk_out1_clk_wiz_0 rise@40.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        4.644ns  (logic 1.888ns (40.655%)  route 2.756ns (59.345%))
  Logic Levels:           5  (CARRY4=3 LUT2=1 LUT4=1)
  Clock Path Skew:        -0.024ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.881ns = ( 44.881 - 40.000 ) 
    Source Clock Delay      (SCD):    5.330ns
    Clock Pessimism Removal (CPR):    0.425ns
  Clock Uncertainty:      0.147ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491     1.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076     3.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101     3.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.680     5.348    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.538     1.810 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.760     3.570    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.101     3.671 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.659     5.330    UPD_CLK_DIV/clk_out1
    SLICE_X33Y62         FDCE                                         r  UPD_CLK_DIV/temp_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X33Y62         FDCE (Prop_fdce_C_Q)         0.456     5.786 r  UPD_CLK_DIV/temp_reg[5]/Q
                         net (fo=4, routed)           1.108     6.895    UPD_CLK_DIV/temp_reg[5]
    SLICE_X31Y63         LUT4 (Prop_lut4_I2_O)        0.124     7.019 r  UPD_CLK_DIV/temp[0]_i_14/O
                         net (fo=1, routed)           0.000     7.019    UPD_CLK_DIV/temp[0]_i_14_n_0
    SLICE_X31Y63         CARRY4 (Prop_carry4_S[1]_CO[3])
                                                      0.550     7.569 r  UPD_CLK_DIV/temp_reg[0]_i_7/CO[3]
                         net (fo=1, routed)           0.000     7.569    UPD_CLK_DIV/temp_reg[0]_i_7_n_0
    SLICE_X31Y64         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     7.683 r  UPD_CLK_DIV/temp_reg[0]_i_5/CO[3]
                         net (fo=1, routed)           0.000     7.683    UPD_CLK_DIV/temp_reg[0]_i_5_n_0
    SLICE_X31Y65         CARRY4 (Prop_carry4_CI_CO[0])
                                                      0.271     7.954 f  UPD_CLK_DIV/temp_reg[0]_i_4/CO[0]
                         net (fo=1, routed)           0.405     8.358    UPD_CLK_DIV/temp_reg[0]_i_4_n_3
    SLICE_X31Y66         LUT2 (Prop_lut2_I0_O)        0.373     8.731 f  UPD_CLK_DIV/temp[0]_i_2/O
                         net (fo=25, routed)          1.243     9.974    UPD_CLK_DIV/temp[0]_i_2_n_0
    SLICE_X33Y61         FDCE                                         f  UPD_CLK_DIV/temp_reg[2]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                     40.000    40.000 r  
    L16                                               0.000    40.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    40.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421    41.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    43.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    43.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.490    44.882    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.177    41.705 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.599    43.304    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    43.395 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.487    44.881    UPD_CLK_DIV/clk_out1
    SLICE_X33Y61         FDCE                                         r  UPD_CLK_DIV/temp_reg[2]/C
                         clock pessimism              0.425    45.306    
                         clock uncertainty           -0.147    45.159    
    SLICE_X33Y61         FDCE (Recov_fdce_C_CLR)     -0.405    44.754    UPD_CLK_DIV/temp_reg[2]
  -------------------------------------------------------------------
                         required time                         44.754    
                         arrival time                          -9.974    
  -------------------------------------------------------------------
                         slack                                 34.780    

Slack (MET) :             34.780ns  (required time - arrival time)
  Source:                 UPD_CLK_DIV/temp_reg[5]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            UPD_CLK_DIV/temp_reg[3]/CLR
                            (recovery check against rising-edge clock clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            40.000ns  (clk_out1_clk_wiz_0 rise@40.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        4.644ns  (logic 1.888ns (40.655%)  route 2.756ns (59.345%))
  Logic Levels:           5  (CARRY4=3 LUT2=1 LUT4=1)
  Clock Path Skew:        -0.024ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.881ns = ( 44.881 - 40.000 ) 
    Source Clock Delay      (SCD):    5.330ns
    Clock Pessimism Removal (CPR):    0.425ns
  Clock Uncertainty:      0.147ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491     1.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076     3.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101     3.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.680     5.348    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.538     1.810 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.760     3.570    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.101     3.671 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.659     5.330    UPD_CLK_DIV/clk_out1
    SLICE_X33Y62         FDCE                                         r  UPD_CLK_DIV/temp_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X33Y62         FDCE (Prop_fdce_C_Q)         0.456     5.786 r  UPD_CLK_DIV/temp_reg[5]/Q
                         net (fo=4, routed)           1.108     6.895    UPD_CLK_DIV/temp_reg[5]
    SLICE_X31Y63         LUT4 (Prop_lut4_I2_O)        0.124     7.019 r  UPD_CLK_DIV/temp[0]_i_14/O
                         net (fo=1, routed)           0.000     7.019    UPD_CLK_DIV/temp[0]_i_14_n_0
    SLICE_X31Y63         CARRY4 (Prop_carry4_S[1]_CO[3])
                                                      0.550     7.569 r  UPD_CLK_DIV/temp_reg[0]_i_7/CO[3]
                         net (fo=1, routed)           0.000     7.569    UPD_CLK_DIV/temp_reg[0]_i_7_n_0
    SLICE_X31Y64         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     7.683 r  UPD_CLK_DIV/temp_reg[0]_i_5/CO[3]
                         net (fo=1, routed)           0.000     7.683    UPD_CLK_DIV/temp_reg[0]_i_5_n_0
    SLICE_X31Y65         CARRY4 (Prop_carry4_CI_CO[0])
                                                      0.271     7.954 f  UPD_CLK_DIV/temp_reg[0]_i_4/CO[0]
                         net (fo=1, routed)           0.405     8.358    UPD_CLK_DIV/temp_reg[0]_i_4_n_3
    SLICE_X31Y66         LUT2 (Prop_lut2_I0_O)        0.373     8.731 f  UPD_CLK_DIV/temp[0]_i_2/O
                         net (fo=25, routed)          1.243     9.974    UPD_CLK_DIV/temp[0]_i_2_n_0
    SLICE_X33Y61         FDCE                                         f  UPD_CLK_DIV/temp_reg[3]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                     40.000    40.000 r  
    L16                                               0.000    40.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    40.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421    41.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    43.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    43.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.490    44.882    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.177    41.705 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.599    43.304    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    43.395 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.487    44.881    UPD_CLK_DIV/clk_out1
    SLICE_X33Y61         FDCE                                         r  UPD_CLK_DIV/temp_reg[3]/C
                         clock pessimism              0.425    45.306    
                         clock uncertainty           -0.147    45.159    
    SLICE_X33Y61         FDCE (Recov_fdce_C_CLR)     -0.405    44.754    UPD_CLK_DIV/temp_reg[3]
  -------------------------------------------------------------------
                         required time                         44.754    
                         arrival time                          -9.974    
  -------------------------------------------------------------------
                         slack                                 34.780    

Slack (MET) :             34.900ns  (required time - arrival time)
  Source:                 UPD_CLK_DIV/temp_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            UPD_CLK_DIV/temp_reg[4]/CLR
                            (recovery check against rising-edge clock clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            40.000ns  (clk_out1_clk_wiz_0 rise@40.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        4.521ns  (logic 1.888ns (41.758%)  route 2.633ns (58.242%))
  Logic Levels:           5  (CARRY4=3 LUT2=1 LUT4=1)
  Clock Path Skew:        -0.026ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.880ns = ( 44.880 - 40.000 ) 
    Source Clock Delay      (SCD):    5.331ns
    Clock Pessimism Removal (CPR):    0.425ns
  Clock Uncertainty:      0.147ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491     1.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076     3.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101     3.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.680     5.348    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.538     1.810 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.760     3.570    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.101     3.671 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.660     5.331    UPD_CLK_DIV/clk_out1
    SLICE_X33Y61         FDCE                                         r  UPD_CLK_DIV/temp_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X33Y61         FDCE (Prop_fdce_C_Q)         0.456     5.787 f  UPD_CLK_DIV/temp_reg[3]/Q
                         net (fo=4, routed)           1.126     6.914    UPD_CLK_DIV/temp_reg[3]
    SLICE_X31Y63         LUT4 (Prop_lut4_I3_O)        0.124     7.038 r  UPD_CLK_DIV/temp[0]_i_14/O
                         net (fo=1, routed)           0.000     7.038    UPD_CLK_DIV/temp[0]_i_14_n_0
    SLICE_X31Y63         CARRY4 (Prop_carry4_S[1]_CO[3])
                                                      0.550     7.588 r  UPD_CLK_DIV/temp_reg[0]_i_7/CO[3]
                         net (fo=1, routed)           0.000     7.588    UPD_CLK_DIV/temp_reg[0]_i_7_n_0
    SLICE_X31Y64         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     7.702 r  UPD_CLK_DIV/temp_reg[0]_i_5/CO[3]
                         net (fo=1, routed)           0.000     7.702    UPD_CLK_DIV/temp_reg[0]_i_5_n_0
    SLICE_X31Y65         CARRY4 (Prop_carry4_CI_CO[0])
                                                      0.271     7.973 f  UPD_CLK_DIV/temp_reg[0]_i_4/CO[0]
                         net (fo=1, routed)           0.405     8.378    UPD_CLK_DIV/temp_reg[0]_i_4_n_3
    SLICE_X31Y66         LUT2 (Prop_lut2_I0_O)        0.373     8.751 f  UPD_CLK_DIV/temp[0]_i_2/O
                         net (fo=25, routed)          1.102     9.853    UPD_CLK_DIV/temp[0]_i_2_n_0
    SLICE_X33Y62         FDCE                                         f  UPD_CLK_DIV/temp_reg[4]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                     40.000    40.000 r  
    L16                                               0.000    40.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    40.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421    41.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    43.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    43.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.490    44.882    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.177    41.705 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.599    43.304    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    43.395 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.486    44.880    UPD_CLK_DIV/clk_out1
    SLICE_X33Y62         FDCE                                         r  UPD_CLK_DIV/temp_reg[4]/C
                         clock pessimism              0.425    45.305    
                         clock uncertainty           -0.147    45.158    
    SLICE_X33Y62         FDCE (Recov_fdce_C_CLR)     -0.405    44.753    UPD_CLK_DIV/temp_reg[4]
  -------------------------------------------------------------------
                         required time                         44.753    
                         arrival time                          -9.853    
  -------------------------------------------------------------------
                         slack                                 34.900    

Slack (MET) :             34.900ns  (required time - arrival time)
  Source:                 UPD_CLK_DIV/temp_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            UPD_CLK_DIV/temp_reg[5]/CLR
                            (recovery check against rising-edge clock clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            40.000ns  (clk_out1_clk_wiz_0 rise@40.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        4.521ns  (logic 1.888ns (41.758%)  route 2.633ns (58.242%))
  Logic Levels:           5  (CARRY4=3 LUT2=1 LUT4=1)
  Clock Path Skew:        -0.026ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.880ns = ( 44.880 - 40.000 ) 
    Source Clock Delay      (SCD):    5.331ns
    Clock Pessimism Removal (CPR):    0.425ns
  Clock Uncertainty:      0.147ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491     1.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076     3.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101     3.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.680     5.348    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.538     1.810 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.760     3.570    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.101     3.671 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.660     5.331    UPD_CLK_DIV/clk_out1
    SLICE_X33Y61         FDCE                                         r  UPD_CLK_DIV/temp_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X33Y61         FDCE (Prop_fdce_C_Q)         0.456     5.787 f  UPD_CLK_DIV/temp_reg[3]/Q
                         net (fo=4, routed)           1.126     6.914    UPD_CLK_DIV/temp_reg[3]
    SLICE_X31Y63         LUT4 (Prop_lut4_I3_O)        0.124     7.038 r  UPD_CLK_DIV/temp[0]_i_14/O
                         net (fo=1, routed)           0.000     7.038    UPD_CLK_DIV/temp[0]_i_14_n_0
    SLICE_X31Y63         CARRY4 (Prop_carry4_S[1]_CO[3])
                                                      0.550     7.588 r  UPD_CLK_DIV/temp_reg[0]_i_7/CO[3]
                         net (fo=1, routed)           0.000     7.588    UPD_CLK_DIV/temp_reg[0]_i_7_n_0
    SLICE_X31Y64         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     7.702 r  UPD_CLK_DIV/temp_reg[0]_i_5/CO[3]
                         net (fo=1, routed)           0.000     7.702    UPD_CLK_DIV/temp_reg[0]_i_5_n_0
    SLICE_X31Y65         CARRY4 (Prop_carry4_CI_CO[0])
                                                      0.271     7.973 f  UPD_CLK_DIV/temp_reg[0]_i_4/CO[0]
                         net (fo=1, routed)           0.405     8.378    UPD_CLK_DIV/temp_reg[0]_i_4_n_3
    SLICE_X31Y66         LUT2 (Prop_lut2_I0_O)        0.373     8.751 f  UPD_CLK_DIV/temp[0]_i_2/O
                         net (fo=25, routed)          1.102     9.853    UPD_CLK_DIV/temp[0]_i_2_n_0
    SLICE_X33Y62         FDCE                                         f  UPD_CLK_DIV/temp_reg[5]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                     40.000    40.000 r  
    L16                                               0.000    40.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    40.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421    41.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    43.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    43.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.490    44.882    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.177    41.705 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.599    43.304    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    43.395 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.486    44.880    UPD_CLK_DIV/clk_out1
    SLICE_X33Y62         FDCE                                         r  UPD_CLK_DIV/temp_reg[5]/C
                         clock pessimism              0.425    45.305    
                         clock uncertainty           -0.147    45.158    
    SLICE_X33Y62         FDCE (Recov_fdce_C_CLR)     -0.405    44.753    UPD_CLK_DIV/temp_reg[5]
  -------------------------------------------------------------------
                         required time                         44.753    
                         arrival time                          -9.853    
  -------------------------------------------------------------------
                         slack                                 34.900    

Slack (MET) :             34.900ns  (required time - arrival time)
  Source:                 UPD_CLK_DIV/temp_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            UPD_CLK_DIV/temp_reg[6]/CLR
                            (recovery check against rising-edge clock clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            40.000ns  (clk_out1_clk_wiz_0 rise@40.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        4.521ns  (logic 1.888ns (41.758%)  route 2.633ns (58.242%))
  Logic Levels:           5  (CARRY4=3 LUT2=1 LUT4=1)
  Clock Path Skew:        -0.026ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.880ns = ( 44.880 - 40.000 ) 
    Source Clock Delay      (SCD):    5.331ns
    Clock Pessimism Removal (CPR):    0.425ns
  Clock Uncertainty:      0.147ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491     1.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076     3.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101     3.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.680     5.348    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.538     1.810 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.760     3.570    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.101     3.671 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.660     5.331    UPD_CLK_DIV/clk_out1
    SLICE_X33Y61         FDCE                                         r  UPD_CLK_DIV/temp_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X33Y61         FDCE (Prop_fdce_C_Q)         0.456     5.787 f  UPD_CLK_DIV/temp_reg[3]/Q
                         net (fo=4, routed)           1.126     6.914    UPD_CLK_DIV/temp_reg[3]
    SLICE_X31Y63         LUT4 (Prop_lut4_I3_O)        0.124     7.038 r  UPD_CLK_DIV/temp[0]_i_14/O
                         net (fo=1, routed)           0.000     7.038    UPD_CLK_DIV/temp[0]_i_14_n_0
    SLICE_X31Y63         CARRY4 (Prop_carry4_S[1]_CO[3])
                                                      0.550     7.588 r  UPD_CLK_DIV/temp_reg[0]_i_7/CO[3]
                         net (fo=1, routed)           0.000     7.588    UPD_CLK_DIV/temp_reg[0]_i_7_n_0
    SLICE_X31Y64         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     7.702 r  UPD_CLK_DIV/temp_reg[0]_i_5/CO[3]
                         net (fo=1, routed)           0.000     7.702    UPD_CLK_DIV/temp_reg[0]_i_5_n_0
    SLICE_X31Y65         CARRY4 (Prop_carry4_CI_CO[0])
                                                      0.271     7.973 f  UPD_CLK_DIV/temp_reg[0]_i_4/CO[0]
                         net (fo=1, routed)           0.405     8.378    UPD_CLK_DIV/temp_reg[0]_i_4_n_3
    SLICE_X31Y66         LUT2 (Prop_lut2_I0_O)        0.373     8.751 f  UPD_CLK_DIV/temp[0]_i_2/O
                         net (fo=25, routed)          1.102     9.853    UPD_CLK_DIV/temp[0]_i_2_n_0
    SLICE_X33Y62         FDCE                                         f  UPD_CLK_DIV/temp_reg[6]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                     40.000    40.000 r  
    L16                                               0.000    40.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    40.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421    41.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    43.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    43.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.490    44.882    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.177    41.705 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.599    43.304    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    43.395 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.486    44.880    UPD_CLK_DIV/clk_out1
    SLICE_X33Y62         FDCE                                         r  UPD_CLK_DIV/temp_reg[6]/C
                         clock pessimism              0.425    45.305    
                         clock uncertainty           -0.147    45.158    
    SLICE_X33Y62         FDCE (Recov_fdce_C_CLR)     -0.405    44.753    UPD_CLK_DIV/temp_reg[6]
  -------------------------------------------------------------------
                         required time                         44.753    
                         arrival time                          -9.853    
  -------------------------------------------------------------------
                         slack                                 34.900    

Slack (MET) :             34.900ns  (required time - arrival time)
  Source:                 UPD_CLK_DIV/temp_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            UPD_CLK_DIV/temp_reg[7]/CLR
                            (recovery check against rising-edge clock clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            40.000ns  (clk_out1_clk_wiz_0 rise@40.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        4.521ns  (logic 1.888ns (41.758%)  route 2.633ns (58.242%))
  Logic Levels:           5  (CARRY4=3 LUT2=1 LUT4=1)
  Clock Path Skew:        -0.026ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.880ns = ( 44.880 - 40.000 ) 
    Source Clock Delay      (SCD):    5.331ns
    Clock Pessimism Removal (CPR):    0.425ns
  Clock Uncertainty:      0.147ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491     1.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076     3.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101     3.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.680     5.348    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.538     1.810 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.760     3.570    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.101     3.671 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.660     5.331    UPD_CLK_DIV/clk_out1
    SLICE_X33Y61         FDCE                                         r  UPD_CLK_DIV/temp_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X33Y61         FDCE (Prop_fdce_C_Q)         0.456     5.787 f  UPD_CLK_DIV/temp_reg[3]/Q
                         net (fo=4, routed)           1.126     6.914    UPD_CLK_DIV/temp_reg[3]
    SLICE_X31Y63         LUT4 (Prop_lut4_I3_O)        0.124     7.038 r  UPD_CLK_DIV/temp[0]_i_14/O
                         net (fo=1, routed)           0.000     7.038    UPD_CLK_DIV/temp[0]_i_14_n_0
    SLICE_X31Y63         CARRY4 (Prop_carry4_S[1]_CO[3])
                                                      0.550     7.588 r  UPD_CLK_DIV/temp_reg[0]_i_7/CO[3]
                         net (fo=1, routed)           0.000     7.588    UPD_CLK_DIV/temp_reg[0]_i_7_n_0
    SLICE_X31Y64         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     7.702 r  UPD_CLK_DIV/temp_reg[0]_i_5/CO[3]
                         net (fo=1, routed)           0.000     7.702    UPD_CLK_DIV/temp_reg[0]_i_5_n_0
    SLICE_X31Y65         CARRY4 (Prop_carry4_CI_CO[0])
                                                      0.271     7.973 f  UPD_CLK_DIV/temp_reg[0]_i_4/CO[0]
                         net (fo=1, routed)           0.405     8.378    UPD_CLK_DIV/temp_reg[0]_i_4_n_3
    SLICE_X31Y66         LUT2 (Prop_lut2_I0_O)        0.373     8.751 f  UPD_CLK_DIV/temp[0]_i_2/O
                         net (fo=25, routed)          1.102     9.853    UPD_CLK_DIV/temp[0]_i_2_n_0
    SLICE_X33Y62         FDCE                                         f  UPD_CLK_DIV/temp_reg[7]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                     40.000    40.000 r  
    L16                                               0.000    40.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    40.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421    41.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    43.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    43.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.490    44.882    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.177    41.705 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.599    43.304    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    43.395 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.486    44.880    UPD_CLK_DIV/clk_out1
    SLICE_X33Y62         FDCE                                         r  UPD_CLK_DIV/temp_reg[7]/C
                         clock pessimism              0.425    45.305    
                         clock uncertainty           -0.147    45.158    
    SLICE_X33Y62         FDCE (Recov_fdce_C_CLR)     -0.405    44.753    UPD_CLK_DIV/temp_reg[7]
  -------------------------------------------------------------------
                         required time                         44.753    
                         arrival time                          -9.853    
  -------------------------------------------------------------------
                         slack                                 34.900    

Slack (MET) :             35.050ns  (required time - arrival time)
  Source:                 UPD_CLK_DIV/temp_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            UPD_CLK_DIV/temp_reg[10]/CLR
                            (recovery check against rising-edge clock clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            40.000ns  (clk_out1_clk_wiz_0 rise@40.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        4.371ns  (logic 1.888ns (43.199%)  route 2.483ns (56.801%))
  Logic Levels:           5  (CARRY4=3 LUT2=1 LUT4=1)
  Clock Path Skew:        -0.027ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.879ns = ( 44.879 - 40.000 ) 
    Source Clock Delay      (SCD):    5.331ns
    Clock Pessimism Removal (CPR):    0.425ns
  Clock Uncertainty:      0.147ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491     1.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076     3.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101     3.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.680     5.348    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.538     1.810 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.760     3.570    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.101     3.671 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.660     5.331    UPD_CLK_DIV/clk_out1
    SLICE_X33Y61         FDCE                                         r  UPD_CLK_DIV/temp_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X33Y61         FDCE (Prop_fdce_C_Q)         0.456     5.787 f  UPD_CLK_DIV/temp_reg[3]/Q
                         net (fo=4, routed)           1.126     6.914    UPD_CLK_DIV/temp_reg[3]
    SLICE_X31Y63         LUT4 (Prop_lut4_I3_O)        0.124     7.038 r  UPD_CLK_DIV/temp[0]_i_14/O
                         net (fo=1, routed)           0.000     7.038    UPD_CLK_DIV/temp[0]_i_14_n_0
    SLICE_X31Y63         CARRY4 (Prop_carry4_S[1]_CO[3])
                                                      0.550     7.588 r  UPD_CLK_DIV/temp_reg[0]_i_7/CO[3]
                         net (fo=1, routed)           0.000     7.588    UPD_CLK_DIV/temp_reg[0]_i_7_n_0
    SLICE_X31Y64         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     7.702 r  UPD_CLK_DIV/temp_reg[0]_i_5/CO[3]
                         net (fo=1, routed)           0.000     7.702    UPD_CLK_DIV/temp_reg[0]_i_5_n_0
    SLICE_X31Y65         CARRY4 (Prop_carry4_CI_CO[0])
                                                      0.271     7.973 f  UPD_CLK_DIV/temp_reg[0]_i_4/CO[0]
                         net (fo=1, routed)           0.405     8.378    UPD_CLK_DIV/temp_reg[0]_i_4_n_3
    SLICE_X31Y66         LUT2 (Prop_lut2_I0_O)        0.373     8.751 f  UPD_CLK_DIV/temp[0]_i_2/O
                         net (fo=25, routed)          0.951     9.702    UPD_CLK_DIV/temp[0]_i_2_n_0
    SLICE_X33Y63         FDCE                                         f  UPD_CLK_DIV/temp_reg[10]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                     40.000    40.000 r  
    L16                                               0.000    40.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    40.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421    41.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    43.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    43.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.490    44.882    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.177    41.705 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.599    43.304    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    43.395 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.485    44.879    UPD_CLK_DIV/clk_out1
    SLICE_X33Y63         FDCE                                         r  UPD_CLK_DIV/temp_reg[10]/C
                         clock pessimism              0.425    45.304    
                         clock uncertainty           -0.147    45.157    
    SLICE_X33Y63         FDCE (Recov_fdce_C_CLR)     -0.405    44.752    UPD_CLK_DIV/temp_reg[10]
  -------------------------------------------------------------------
                         required time                         44.752    
                         arrival time                          -9.702    
  -------------------------------------------------------------------
                         slack                                 35.050    

Slack (MET) :             35.050ns  (required time - arrival time)
  Source:                 UPD_CLK_DIV/temp_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            UPD_CLK_DIV/temp_reg[11]/CLR
                            (recovery check against rising-edge clock clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            40.000ns  (clk_out1_clk_wiz_0 rise@40.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        4.371ns  (logic 1.888ns (43.199%)  route 2.483ns (56.801%))
  Logic Levels:           5  (CARRY4=3 LUT2=1 LUT4=1)
  Clock Path Skew:        -0.027ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.879ns = ( 44.879 - 40.000 ) 
    Source Clock Delay      (SCD):    5.331ns
    Clock Pessimism Removal (CPR):    0.425ns
  Clock Uncertainty:      0.147ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491     1.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076     3.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101     3.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.680     5.348    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.538     1.810 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.760     3.570    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.101     3.671 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.660     5.331    UPD_CLK_DIV/clk_out1
    SLICE_X33Y61         FDCE                                         r  UPD_CLK_DIV/temp_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X33Y61         FDCE (Prop_fdce_C_Q)         0.456     5.787 f  UPD_CLK_DIV/temp_reg[3]/Q
                         net (fo=4, routed)           1.126     6.914    UPD_CLK_DIV/temp_reg[3]
    SLICE_X31Y63         LUT4 (Prop_lut4_I3_O)        0.124     7.038 r  UPD_CLK_DIV/temp[0]_i_14/O
                         net (fo=1, routed)           0.000     7.038    UPD_CLK_DIV/temp[0]_i_14_n_0
    SLICE_X31Y63         CARRY4 (Prop_carry4_S[1]_CO[3])
                                                      0.550     7.588 r  UPD_CLK_DIV/temp_reg[0]_i_7/CO[3]
                         net (fo=1, routed)           0.000     7.588    UPD_CLK_DIV/temp_reg[0]_i_7_n_0
    SLICE_X31Y64         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     7.702 r  UPD_CLK_DIV/temp_reg[0]_i_5/CO[3]
                         net (fo=1, routed)           0.000     7.702    UPD_CLK_DIV/temp_reg[0]_i_5_n_0
    SLICE_X31Y65         CARRY4 (Prop_carry4_CI_CO[0])
                                                      0.271     7.973 f  UPD_CLK_DIV/temp_reg[0]_i_4/CO[0]
                         net (fo=1, routed)           0.405     8.378    UPD_CLK_DIV/temp_reg[0]_i_4_n_3
    SLICE_X31Y66         LUT2 (Prop_lut2_I0_O)        0.373     8.751 f  UPD_CLK_DIV/temp[0]_i_2/O
                         net (fo=25, routed)          0.951     9.702    UPD_CLK_DIV/temp[0]_i_2_n_0
    SLICE_X33Y63         FDCE                                         f  UPD_CLK_DIV/temp_reg[11]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                     40.000    40.000 r  
    L16                                               0.000    40.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    40.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421    41.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    43.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    43.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.490    44.882    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.177    41.705 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.599    43.304    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    43.395 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.485    44.879    UPD_CLK_DIV/clk_out1
    SLICE_X33Y63         FDCE                                         r  UPD_CLK_DIV/temp_reg[11]/C
                         clock pessimism              0.425    45.304    
                         clock uncertainty           -0.147    45.157    
    SLICE_X33Y63         FDCE (Recov_fdce_C_CLR)     -0.405    44.752    UPD_CLK_DIV/temp_reg[11]
  -------------------------------------------------------------------
                         required time                         44.752    
                         arrival time                          -9.702    
  -------------------------------------------------------------------
                         slack                                 35.050    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.074ns  (arrival time - required time)
  Source:                 UPD_CLK_DIV/temp_reg[24]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            UPD_CLK_DIV/temp_reg[20]/CLR
                            (removal check against rising-edge clock clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        0.997ns  (logic 0.411ns (41.215%)  route 0.586ns (58.785%))
  Logic Levels:           3  (CARRY4=1 LUT1=1 LUT2=1)
  Clock Path Skew:        0.015ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.984ns
    Source Clock Delay      (SCD):    1.469ns
    Clock Pessimism Removal (CPR):    0.500ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.548     1.460    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.053     0.406 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.482     0.888    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.914 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.555     1.469    UPD_CLK_DIV/clk_out1
    SLICE_X33Y67         FDCE                                         r  UPD_CLK_DIV/temp_reg[24]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X33Y67         FDCE (Prop_fdce_C_Q)         0.141     1.610 f  UPD_CLK_DIV/temp_reg[24]/Q
                         net (fo=4, routed)           0.251     1.860    UPD_CLK_DIV/temp_reg[24]
    SLICE_X31Y65         LUT1 (Prop_lut1_I0_O)        0.045     1.905 r  UPD_CLK_DIV/temp[0]_i_6/O
                         net (fo=1, routed)           0.000     1.905    UPD_CLK_DIV/temp[0]_i_6_n_0
    SLICE_X31Y65         CARRY4 (Prop_carry4_S[0]_CO[0])
                                                      0.099     2.004 f  UPD_CLK_DIV/temp_reg[0]_i_4/CO[0]
                         net (fo=1, routed)           0.140     2.144    UPD_CLK_DIV/temp_reg[0]_i_4_n_3
    SLICE_X31Y66         LUT2 (Prop_lut2_I0_O)        0.126     2.270 f  UPD_CLK_DIV/temp[0]_i_2/O
                         net (fo=25, routed)          0.196     2.466    UPD_CLK_DIV/temp[0]_i_2_n_0
    SLICE_X33Y66         FDCE                                         f  UPD_CLK_DIV/temp_reg[20]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.814     1.973    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.369     0.604 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.528     1.132    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.161 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.823     1.984    UPD_CLK_DIV/clk_out1
    SLICE_X33Y66         FDCE                                         r  UPD_CLK_DIV/temp_reg[20]/C
                         clock pessimism             -0.500     1.484    
    SLICE_X33Y66         FDCE (Remov_fdce_C_CLR)     -0.092     1.392    UPD_CLK_DIV/temp_reg[20]
  -------------------------------------------------------------------
                         required time                         -1.392    
                         arrival time                           2.466    
  -------------------------------------------------------------------
                         slack                                  1.074    

Slack (MET) :             1.074ns  (arrival time - required time)
  Source:                 UPD_CLK_DIV/temp_reg[24]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            UPD_CLK_DIV/temp_reg[21]/CLR
                            (removal check against rising-edge clock clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        0.997ns  (logic 0.411ns (41.215%)  route 0.586ns (58.785%))
  Logic Levels:           3  (CARRY4=1 LUT1=1 LUT2=1)
  Clock Path Skew:        0.015ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.984ns
    Source Clock Delay      (SCD):    1.469ns
    Clock Pessimism Removal (CPR):    0.500ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.548     1.460    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.053     0.406 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.482     0.888    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.914 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.555     1.469    UPD_CLK_DIV/clk_out1
    SLICE_X33Y67         FDCE                                         r  UPD_CLK_DIV/temp_reg[24]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X33Y67         FDCE (Prop_fdce_C_Q)         0.141     1.610 f  UPD_CLK_DIV/temp_reg[24]/Q
                         net (fo=4, routed)           0.251     1.860    UPD_CLK_DIV/temp_reg[24]
    SLICE_X31Y65         LUT1 (Prop_lut1_I0_O)        0.045     1.905 r  UPD_CLK_DIV/temp[0]_i_6/O
                         net (fo=1, routed)           0.000     1.905    UPD_CLK_DIV/temp[0]_i_6_n_0
    SLICE_X31Y65         CARRY4 (Prop_carry4_S[0]_CO[0])
                                                      0.099     2.004 f  UPD_CLK_DIV/temp_reg[0]_i_4/CO[0]
                         net (fo=1, routed)           0.140     2.144    UPD_CLK_DIV/temp_reg[0]_i_4_n_3
    SLICE_X31Y66         LUT2 (Prop_lut2_I0_O)        0.126     2.270 f  UPD_CLK_DIV/temp[0]_i_2/O
                         net (fo=25, routed)          0.196     2.466    UPD_CLK_DIV/temp[0]_i_2_n_0
    SLICE_X33Y66         FDCE                                         f  UPD_CLK_DIV/temp_reg[21]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.814     1.973    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.369     0.604 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.528     1.132    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.161 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.823     1.984    UPD_CLK_DIV/clk_out1
    SLICE_X33Y66         FDCE                                         r  UPD_CLK_DIV/temp_reg[21]/C
                         clock pessimism             -0.500     1.484    
    SLICE_X33Y66         FDCE (Remov_fdce_C_CLR)     -0.092     1.392    UPD_CLK_DIV/temp_reg[21]
  -------------------------------------------------------------------
                         required time                         -1.392    
                         arrival time                           2.466    
  -------------------------------------------------------------------
                         slack                                  1.074    

Slack (MET) :             1.074ns  (arrival time - required time)
  Source:                 UPD_CLK_DIV/temp_reg[24]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            UPD_CLK_DIV/temp_reg[22]/CLR
                            (removal check against rising-edge clock clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        0.997ns  (logic 0.411ns (41.215%)  route 0.586ns (58.785%))
  Logic Levels:           3  (CARRY4=1 LUT1=1 LUT2=1)
  Clock Path Skew:        0.015ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.984ns
    Source Clock Delay      (SCD):    1.469ns
    Clock Pessimism Removal (CPR):    0.500ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.548     1.460    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.053     0.406 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.482     0.888    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.914 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.555     1.469    UPD_CLK_DIV/clk_out1
    SLICE_X33Y67         FDCE                                         r  UPD_CLK_DIV/temp_reg[24]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X33Y67         FDCE (Prop_fdce_C_Q)         0.141     1.610 f  UPD_CLK_DIV/temp_reg[24]/Q
                         net (fo=4, routed)           0.251     1.860    UPD_CLK_DIV/temp_reg[24]
    SLICE_X31Y65         LUT1 (Prop_lut1_I0_O)        0.045     1.905 r  UPD_CLK_DIV/temp[0]_i_6/O
                         net (fo=1, routed)           0.000     1.905    UPD_CLK_DIV/temp[0]_i_6_n_0
    SLICE_X31Y65         CARRY4 (Prop_carry4_S[0]_CO[0])
                                                      0.099     2.004 f  UPD_CLK_DIV/temp_reg[0]_i_4/CO[0]
                         net (fo=1, routed)           0.140     2.144    UPD_CLK_DIV/temp_reg[0]_i_4_n_3
    SLICE_X31Y66         LUT2 (Prop_lut2_I0_O)        0.126     2.270 f  UPD_CLK_DIV/temp[0]_i_2/O
                         net (fo=25, routed)          0.196     2.466    UPD_CLK_DIV/temp[0]_i_2_n_0
    SLICE_X33Y66         FDCE                                         f  UPD_CLK_DIV/temp_reg[22]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.814     1.973    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.369     0.604 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.528     1.132    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.161 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.823     1.984    UPD_CLK_DIV/clk_out1
    SLICE_X33Y66         FDCE                                         r  UPD_CLK_DIV/temp_reg[22]/C
                         clock pessimism             -0.500     1.484    
    SLICE_X33Y66         FDCE (Remov_fdce_C_CLR)     -0.092     1.392    UPD_CLK_DIV/temp_reg[22]
  -------------------------------------------------------------------
                         required time                         -1.392    
                         arrival time                           2.466    
  -------------------------------------------------------------------
                         slack                                  1.074    

Slack (MET) :             1.074ns  (arrival time - required time)
  Source:                 UPD_CLK_DIV/temp_reg[24]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            UPD_CLK_DIV/temp_reg[23]/CLR
                            (removal check against rising-edge clock clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        0.997ns  (logic 0.411ns (41.215%)  route 0.586ns (58.785%))
  Logic Levels:           3  (CARRY4=1 LUT1=1 LUT2=1)
  Clock Path Skew:        0.015ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.984ns
    Source Clock Delay      (SCD):    1.469ns
    Clock Pessimism Removal (CPR):    0.500ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.548     1.460    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.053     0.406 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.482     0.888    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.914 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.555     1.469    UPD_CLK_DIV/clk_out1
    SLICE_X33Y67         FDCE                                         r  UPD_CLK_DIV/temp_reg[24]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X33Y67         FDCE (Prop_fdce_C_Q)         0.141     1.610 f  UPD_CLK_DIV/temp_reg[24]/Q
                         net (fo=4, routed)           0.251     1.860    UPD_CLK_DIV/temp_reg[24]
    SLICE_X31Y65         LUT1 (Prop_lut1_I0_O)        0.045     1.905 r  UPD_CLK_DIV/temp[0]_i_6/O
                         net (fo=1, routed)           0.000     1.905    UPD_CLK_DIV/temp[0]_i_6_n_0
    SLICE_X31Y65         CARRY4 (Prop_carry4_S[0]_CO[0])
                                                      0.099     2.004 f  UPD_CLK_DIV/temp_reg[0]_i_4/CO[0]
                         net (fo=1, routed)           0.140     2.144    UPD_CLK_DIV/temp_reg[0]_i_4_n_3
    SLICE_X31Y66         LUT2 (Prop_lut2_I0_O)        0.126     2.270 f  UPD_CLK_DIV/temp[0]_i_2/O
                         net (fo=25, routed)          0.196     2.466    UPD_CLK_DIV/temp[0]_i_2_n_0
    SLICE_X33Y66         FDCE                                         f  UPD_CLK_DIV/temp_reg[23]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.814     1.973    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.369     0.604 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.528     1.132    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.161 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.823     1.984    UPD_CLK_DIV/clk_out1
    SLICE_X33Y66         FDCE                                         r  UPD_CLK_DIV/temp_reg[23]/C
                         clock pessimism             -0.500     1.484    
    SLICE_X33Y66         FDCE (Remov_fdce_C_CLR)     -0.092     1.392    UPD_CLK_DIV/temp_reg[23]
  -------------------------------------------------------------------
                         required time                         -1.392    
                         arrival time                           2.466    
  -------------------------------------------------------------------
                         slack                                  1.074    

Slack (MET) :             1.127ns  (arrival time - required time)
  Source:                 UPD_CLK_DIV/temp_reg[24]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            UPD_CLK_DIV/temp_reg[16]/CLR
                            (removal check against rising-edge clock clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        1.051ns  (logic 0.411ns (39.103%)  route 0.640ns (60.897%))
  Logic Levels:           3  (CARRY4=1 LUT1=1 LUT2=1)
  Clock Path Skew:        0.016ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.985ns
    Source Clock Delay      (SCD):    1.469ns
    Clock Pessimism Removal (CPR):    0.500ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.548     1.460    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.053     0.406 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.482     0.888    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.914 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.555     1.469    UPD_CLK_DIV/clk_out1
    SLICE_X33Y67         FDCE                                         r  UPD_CLK_DIV/temp_reg[24]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X33Y67         FDCE (Prop_fdce_C_Q)         0.141     1.610 f  UPD_CLK_DIV/temp_reg[24]/Q
                         net (fo=4, routed)           0.251     1.860    UPD_CLK_DIV/temp_reg[24]
    SLICE_X31Y65         LUT1 (Prop_lut1_I0_O)        0.045     1.905 r  UPD_CLK_DIV/temp[0]_i_6/O
                         net (fo=1, routed)           0.000     1.905    UPD_CLK_DIV/temp[0]_i_6_n_0
    SLICE_X31Y65         CARRY4 (Prop_carry4_S[0]_CO[0])
                                                      0.099     2.004 f  UPD_CLK_DIV/temp_reg[0]_i_4/CO[0]
                         net (fo=1, routed)           0.140     2.144    UPD_CLK_DIV/temp_reg[0]_i_4_n_3
    SLICE_X31Y66         LUT2 (Prop_lut2_I0_O)        0.126     2.270 f  UPD_CLK_DIV/temp[0]_i_2/O
                         net (fo=25, routed)          0.250     2.520    UPD_CLK_DIV/temp[0]_i_2_n_0
    SLICE_X33Y65         FDCE                                         f  UPD_CLK_DIV/temp_reg[16]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.814     1.973    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.369     0.604 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.528     1.132    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.161 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.824     1.985    UPD_CLK_DIV/clk_out1
    SLICE_X33Y65         FDCE                                         r  UPD_CLK_DIV/temp_reg[16]/C
                         clock pessimism             -0.500     1.485    
    SLICE_X33Y65         FDCE (Remov_fdce_C_CLR)     -0.092     1.393    UPD_CLK_DIV/temp_reg[16]
  -------------------------------------------------------------------
                         required time                         -1.393    
                         arrival time                           2.520    
  -------------------------------------------------------------------
                         slack                                  1.127    

Slack (MET) :             1.127ns  (arrival time - required time)
  Source:                 UPD_CLK_DIV/temp_reg[24]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            UPD_CLK_DIV/temp_reg[17]/CLR
                            (removal check against rising-edge clock clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        1.051ns  (logic 0.411ns (39.103%)  route 0.640ns (60.897%))
  Logic Levels:           3  (CARRY4=1 LUT1=1 LUT2=1)
  Clock Path Skew:        0.016ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.985ns
    Source Clock Delay      (SCD):    1.469ns
    Clock Pessimism Removal (CPR):    0.500ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.548     1.460    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.053     0.406 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.482     0.888    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.914 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.555     1.469    UPD_CLK_DIV/clk_out1
    SLICE_X33Y67         FDCE                                         r  UPD_CLK_DIV/temp_reg[24]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X33Y67         FDCE (Prop_fdce_C_Q)         0.141     1.610 f  UPD_CLK_DIV/temp_reg[24]/Q
                         net (fo=4, routed)           0.251     1.860    UPD_CLK_DIV/temp_reg[24]
    SLICE_X31Y65         LUT1 (Prop_lut1_I0_O)        0.045     1.905 r  UPD_CLK_DIV/temp[0]_i_6/O
                         net (fo=1, routed)           0.000     1.905    UPD_CLK_DIV/temp[0]_i_6_n_0
    SLICE_X31Y65         CARRY4 (Prop_carry4_S[0]_CO[0])
                                                      0.099     2.004 f  UPD_CLK_DIV/temp_reg[0]_i_4/CO[0]
                         net (fo=1, routed)           0.140     2.144    UPD_CLK_DIV/temp_reg[0]_i_4_n_3
    SLICE_X31Y66         LUT2 (Prop_lut2_I0_O)        0.126     2.270 f  UPD_CLK_DIV/temp[0]_i_2/O
                         net (fo=25, routed)          0.250     2.520    UPD_CLK_DIV/temp[0]_i_2_n_0
    SLICE_X33Y65         FDCE                                         f  UPD_CLK_DIV/temp_reg[17]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.814     1.973    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.369     0.604 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.528     1.132    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.161 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.824     1.985    UPD_CLK_DIV/clk_out1
    SLICE_X33Y65         FDCE                                         r  UPD_CLK_DIV/temp_reg[17]/C
                         clock pessimism             -0.500     1.485    
    SLICE_X33Y65         FDCE (Remov_fdce_C_CLR)     -0.092     1.393    UPD_CLK_DIV/temp_reg[17]
  -------------------------------------------------------------------
                         required time                         -1.393    
                         arrival time                           2.520    
  -------------------------------------------------------------------
                         slack                                  1.127    

Slack (MET) :             1.127ns  (arrival time - required time)
  Source:                 UPD_CLK_DIV/temp_reg[24]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            UPD_CLK_DIV/temp_reg[18]/CLR
                            (removal check against rising-edge clock clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        1.051ns  (logic 0.411ns (39.103%)  route 0.640ns (60.897%))
  Logic Levels:           3  (CARRY4=1 LUT1=1 LUT2=1)
  Clock Path Skew:        0.016ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.985ns
    Source Clock Delay      (SCD):    1.469ns
    Clock Pessimism Removal (CPR):    0.500ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.548     1.460    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.053     0.406 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.482     0.888    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.914 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.555     1.469    UPD_CLK_DIV/clk_out1
    SLICE_X33Y67         FDCE                                         r  UPD_CLK_DIV/temp_reg[24]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X33Y67         FDCE (Prop_fdce_C_Q)         0.141     1.610 f  UPD_CLK_DIV/temp_reg[24]/Q
                         net (fo=4, routed)           0.251     1.860    UPD_CLK_DIV/temp_reg[24]
    SLICE_X31Y65         LUT1 (Prop_lut1_I0_O)        0.045     1.905 r  UPD_CLK_DIV/temp[0]_i_6/O
                         net (fo=1, routed)           0.000     1.905    UPD_CLK_DIV/temp[0]_i_6_n_0
    SLICE_X31Y65         CARRY4 (Prop_carry4_S[0]_CO[0])
                                                      0.099     2.004 f  UPD_CLK_DIV/temp_reg[0]_i_4/CO[0]
                         net (fo=1, routed)           0.140     2.144    UPD_CLK_DIV/temp_reg[0]_i_4_n_3
    SLICE_X31Y66         LUT2 (Prop_lut2_I0_O)        0.126     2.270 f  UPD_CLK_DIV/temp[0]_i_2/O
                         net (fo=25, routed)          0.250     2.520    UPD_CLK_DIV/temp[0]_i_2_n_0
    SLICE_X33Y65         FDCE                                         f  UPD_CLK_DIV/temp_reg[18]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.814     1.973    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.369     0.604 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.528     1.132    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.161 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.824     1.985    UPD_CLK_DIV/clk_out1
    SLICE_X33Y65         FDCE                                         r  UPD_CLK_DIV/temp_reg[18]/C
                         clock pessimism             -0.500     1.485    
    SLICE_X33Y65         FDCE (Remov_fdce_C_CLR)     -0.092     1.393    UPD_CLK_DIV/temp_reg[18]
  -------------------------------------------------------------------
                         required time                         -1.393    
                         arrival time                           2.520    
  -------------------------------------------------------------------
                         slack                                  1.127    

Slack (MET) :             1.127ns  (arrival time - required time)
  Source:                 UPD_CLK_DIV/temp_reg[24]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            UPD_CLK_DIV/temp_reg[19]/CLR
                            (removal check against rising-edge clock clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        1.051ns  (logic 0.411ns (39.103%)  route 0.640ns (60.897%))
  Logic Levels:           3  (CARRY4=1 LUT1=1 LUT2=1)
  Clock Path Skew:        0.016ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.985ns
    Source Clock Delay      (SCD):    1.469ns
    Clock Pessimism Removal (CPR):    0.500ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.548     1.460    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.053     0.406 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.482     0.888    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.914 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.555     1.469    UPD_CLK_DIV/clk_out1
    SLICE_X33Y67         FDCE                                         r  UPD_CLK_DIV/temp_reg[24]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X33Y67         FDCE (Prop_fdce_C_Q)         0.141     1.610 f  UPD_CLK_DIV/temp_reg[24]/Q
                         net (fo=4, routed)           0.251     1.860    UPD_CLK_DIV/temp_reg[24]
    SLICE_X31Y65         LUT1 (Prop_lut1_I0_O)        0.045     1.905 r  UPD_CLK_DIV/temp[0]_i_6/O
                         net (fo=1, routed)           0.000     1.905    UPD_CLK_DIV/temp[0]_i_6_n_0
    SLICE_X31Y65         CARRY4 (Prop_carry4_S[0]_CO[0])
                                                      0.099     2.004 f  UPD_CLK_DIV/temp_reg[0]_i_4/CO[0]
                         net (fo=1, routed)           0.140     2.144    UPD_CLK_DIV/temp_reg[0]_i_4_n_3
    SLICE_X31Y66         LUT2 (Prop_lut2_I0_O)        0.126     2.270 f  UPD_CLK_DIV/temp[0]_i_2/O
                         net (fo=25, routed)          0.250     2.520    UPD_CLK_DIV/temp[0]_i_2_n_0
    SLICE_X33Y65         FDCE                                         f  UPD_CLK_DIV/temp_reg[19]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.814     1.973    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.369     0.604 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.528     1.132    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.161 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.824     1.985    UPD_CLK_DIV/clk_out1
    SLICE_X33Y65         FDCE                                         r  UPD_CLK_DIV/temp_reg[19]/C
                         clock pessimism             -0.500     1.485    
    SLICE_X33Y65         FDCE (Remov_fdce_C_CLR)     -0.092     1.393    UPD_CLK_DIV/temp_reg[19]
  -------------------------------------------------------------------
                         required time                         -1.393    
                         arrival time                           2.520    
  -------------------------------------------------------------------
                         slack                                  1.127    

Slack (MET) :             1.143ns  (arrival time - required time)
  Source:                 UPD_CLK_DIV/temp_reg[24]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            UPD_CLK_DIV/temp_reg[24]/CLR
                            (removal check against rising-edge clock clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        1.051ns  (logic 0.411ns (39.120%)  route 0.640ns (60.880%))
  Logic Levels:           3  (CARRY4=1 LUT1=1 LUT2=1)
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.983ns
    Source Clock Delay      (SCD):    1.469ns
    Clock Pessimism Removal (CPR):    0.514ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.548     1.460    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.053     0.406 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.482     0.888    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.914 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.555     1.469    UPD_CLK_DIV/clk_out1
    SLICE_X33Y67         FDCE                                         r  UPD_CLK_DIV/temp_reg[24]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X33Y67         FDCE (Prop_fdce_C_Q)         0.141     1.610 f  UPD_CLK_DIV/temp_reg[24]/Q
                         net (fo=4, routed)           0.251     1.860    UPD_CLK_DIV/temp_reg[24]
    SLICE_X31Y65         LUT1 (Prop_lut1_I0_O)        0.045     1.905 r  UPD_CLK_DIV/temp[0]_i_6/O
                         net (fo=1, routed)           0.000     1.905    UPD_CLK_DIV/temp[0]_i_6_n_0
    SLICE_X31Y65         CARRY4 (Prop_carry4_S[0]_CO[0])
                                                      0.099     2.004 f  UPD_CLK_DIV/temp_reg[0]_i_4/CO[0]
                         net (fo=1, routed)           0.140     2.144    UPD_CLK_DIV/temp_reg[0]_i_4_n_3
    SLICE_X31Y66         LUT2 (Prop_lut2_I0_O)        0.126     2.270 f  UPD_CLK_DIV/temp[0]_i_2/O
                         net (fo=25, routed)          0.249     2.519    UPD_CLK_DIV/temp[0]_i_2_n_0
    SLICE_X33Y67         FDCE                                         f  UPD_CLK_DIV/temp_reg[24]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.814     1.973    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.369     0.604 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.528     1.132    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.161 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.822     1.983    UPD_CLK_DIV/clk_out1
    SLICE_X33Y67         FDCE                                         r  UPD_CLK_DIV/temp_reg[24]/C
                         clock pessimism             -0.514     1.469    
    SLICE_X33Y67         FDCE (Remov_fdce_C_CLR)     -0.092     1.377    UPD_CLK_DIV/temp_reg[24]
  -------------------------------------------------------------------
                         required time                         -1.377    
                         arrival time                           2.519    
  -------------------------------------------------------------------
                         slack                                  1.143    

Slack (MET) :             1.190ns  (arrival time - required time)
  Source:                 UPD_CLK_DIV/temp_reg[24]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Destination:            UPD_CLK_DIV/temp_reg[12]/CLR
                            (removal check against rising-edge clock clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
  Data Path Delay:        1.115ns  (logic 0.411ns (36.867%)  route 0.704ns (63.133%))
  Logic Levels:           3  (CARRY4=1 LUT1=1 LUT2=1)
  Clock Path Skew:        0.017ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.986ns
    Source Clock Delay      (SCD):    1.469ns
    Clock Pessimism Removal (CPR):    0.500ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.548     1.460    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.053     0.406 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.482     0.888    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.914 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.555     1.469    UPD_CLK_DIV/clk_out1
    SLICE_X33Y67         FDCE                                         r  UPD_CLK_DIV/temp_reg[24]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X33Y67         FDCE (Prop_fdce_C_Q)         0.141     1.610 f  UPD_CLK_DIV/temp_reg[24]/Q
                         net (fo=4, routed)           0.251     1.860    UPD_CLK_DIV/temp_reg[24]
    SLICE_X31Y65         LUT1 (Prop_lut1_I0_O)        0.045     1.905 r  UPD_CLK_DIV/temp[0]_i_6/O
                         net (fo=1, routed)           0.000     1.905    UPD_CLK_DIV/temp[0]_i_6_n_0
    SLICE_X31Y65         CARRY4 (Prop_carry4_S[0]_CO[0])
                                                      0.099     2.004 f  UPD_CLK_DIV/temp_reg[0]_i_4/CO[0]
                         net (fo=1, routed)           0.140     2.144    UPD_CLK_DIV/temp_reg[0]_i_4_n_3
    SLICE_X31Y66         LUT2 (Prop_lut2_I0_O)        0.126     2.270 f  UPD_CLK_DIV/temp[0]_i_2/O
                         net (fo=25, routed)          0.314     2.584    UPD_CLK_DIV/temp[0]_i_2_n_0
    SLICE_X33Y64         FDCE                                         f  UPD_CLK_DIV/temp_reg[12]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.814     1.973    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.369     0.604 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.528     1.132    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.161 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.825     1.986    UPD_CLK_DIV/clk_out1
    SLICE_X33Y64         FDCE                                         r  UPD_CLK_DIV/temp_reg[12]/C
                         clock pessimism             -0.500     1.486    
    SLICE_X33Y64         FDCE (Remov_fdce_C_CLR)     -0.092     1.394    UPD_CLK_DIV/temp_reg[12]
  -------------------------------------------------------------------
                         required time                         -1.394    
                         arrival time                           2.584    
  -------------------------------------------------------------------
                         slack                                  1.190    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  sys_clk_pin
  To Clock:  clk_out1_clk_wiz_0

Setup :            0  Failing Endpoints,  Worst Slack        1.294ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.537ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.294ns  (required time - arrival time)
  Source:                 UPD/lost_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            UPD_CLK_DIV/temp_reg[0]/CLR
                            (recovery check against rising-edge clock clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            8.000ns  (clk_out1_clk_wiz_0 rise@40.000ns - sys_clk_pin rise@32.000ns)
  Data Path Delay:        5.732ns  (logic 1.818ns (31.719%)  route 3.914ns (68.281%))
  Logic Levels:           4  (CARRY4=2 LUT2=1 LUT4=1)
  Clock Path Skew:        -0.176ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.881ns = ( 44.881 - 40.000 ) 
    Source Clock Delay      (SCD):    5.334ns = ( 37.334 - 32.000 ) 
    Clock Pessimism Removal (CPR):    0.277ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                     32.000    32.000 r  
    L16                                               0.000    32.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    32.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491    33.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076    35.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101    35.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.666    37.334    UPD/H125MHz_IBUF_BUFG
    SLICE_X34Y31         FDRE                                         r  UPD/lost_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X34Y31         FDRE (Prop_fdre_C_Q)         0.518    37.852 r  UPD/lost_reg/Q
                         net (fo=18, routed)          2.266    40.118    UPD_CLK_DIV/led_OBUF[1]
    SLICE_X31Y64         LUT4 (Prop_lut4_I0_O)        0.124    40.242 r  UPD_CLK_DIV/temp[0]_i_11/O
                         net (fo=1, routed)           0.000    40.242    UPD_CLK_DIV/temp[0]_i_11_n_0
    SLICE_X31Y64         CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.532    40.774 r  UPD_CLK_DIV/temp_reg[0]_i_5/CO[3]
                         net (fo=1, routed)           0.000    40.774    UPD_CLK_DIV/temp_reg[0]_i_5_n_0
    SLICE_X31Y65         CARRY4 (Prop_carry4_CI_CO[0])
                                                      0.271    41.045 f  UPD_CLK_DIV/temp_reg[0]_i_4/CO[0]
                         net (fo=1, routed)           0.405    41.450    UPD_CLK_DIV/temp_reg[0]_i_4_n_3
    SLICE_X31Y66         LUT2 (Prop_lut2_I0_O)        0.373    41.823 f  UPD_CLK_DIV/temp[0]_i_2/O
                         net (fo=25, routed)          1.243    43.066    UPD_CLK_DIV/temp[0]_i_2_n_0
    SLICE_X33Y61         FDCE                                         f  UPD_CLK_DIV/temp_reg[0]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                     40.000    40.000 r  
    L16                                               0.000    40.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    40.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421    41.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    43.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    43.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.490    44.882    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.177    41.705 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.599    43.304    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    43.395 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.487    44.881    UPD_CLK_DIV/clk_out1
    SLICE_X33Y61         FDCE                                         r  UPD_CLK_DIV/temp_reg[0]/C
                         clock pessimism              0.277    45.158    
                         clock uncertainty           -0.393    44.765    
    SLICE_X33Y61         FDCE (Recov_fdce_C_CLR)     -0.405    44.360    UPD_CLK_DIV/temp_reg[0]
  -------------------------------------------------------------------
                         required time                         44.360    
                         arrival time                         -43.066    
  -------------------------------------------------------------------
                         slack                                  1.294    

Slack (MET) :             1.294ns  (required time - arrival time)
  Source:                 UPD/lost_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            UPD_CLK_DIV/temp_reg[1]/CLR
                            (recovery check against rising-edge clock clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            8.000ns  (clk_out1_clk_wiz_0 rise@40.000ns - sys_clk_pin rise@32.000ns)
  Data Path Delay:        5.732ns  (logic 1.818ns (31.719%)  route 3.914ns (68.281%))
  Logic Levels:           4  (CARRY4=2 LUT2=1 LUT4=1)
  Clock Path Skew:        -0.176ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.881ns = ( 44.881 - 40.000 ) 
    Source Clock Delay      (SCD):    5.334ns = ( 37.334 - 32.000 ) 
    Clock Pessimism Removal (CPR):    0.277ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                     32.000    32.000 r  
    L16                                               0.000    32.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    32.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491    33.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076    35.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101    35.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.666    37.334    UPD/H125MHz_IBUF_BUFG
    SLICE_X34Y31         FDRE                                         r  UPD/lost_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X34Y31         FDRE (Prop_fdre_C_Q)         0.518    37.852 r  UPD/lost_reg/Q
                         net (fo=18, routed)          2.266    40.118    UPD_CLK_DIV/led_OBUF[1]
    SLICE_X31Y64         LUT4 (Prop_lut4_I0_O)        0.124    40.242 r  UPD_CLK_DIV/temp[0]_i_11/O
                         net (fo=1, routed)           0.000    40.242    UPD_CLK_DIV/temp[0]_i_11_n_0
    SLICE_X31Y64         CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.532    40.774 r  UPD_CLK_DIV/temp_reg[0]_i_5/CO[3]
                         net (fo=1, routed)           0.000    40.774    UPD_CLK_DIV/temp_reg[0]_i_5_n_0
    SLICE_X31Y65         CARRY4 (Prop_carry4_CI_CO[0])
                                                      0.271    41.045 f  UPD_CLK_DIV/temp_reg[0]_i_4/CO[0]
                         net (fo=1, routed)           0.405    41.450    UPD_CLK_DIV/temp_reg[0]_i_4_n_3
    SLICE_X31Y66         LUT2 (Prop_lut2_I0_O)        0.373    41.823 f  UPD_CLK_DIV/temp[0]_i_2/O
                         net (fo=25, routed)          1.243    43.066    UPD_CLK_DIV/temp[0]_i_2_n_0
    SLICE_X33Y61         FDCE                                         f  UPD_CLK_DIV/temp_reg[1]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                     40.000    40.000 r  
    L16                                               0.000    40.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    40.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421    41.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    43.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    43.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.490    44.882    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.177    41.705 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.599    43.304    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    43.395 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.487    44.881    UPD_CLK_DIV/clk_out1
    SLICE_X33Y61         FDCE                                         r  UPD_CLK_DIV/temp_reg[1]/C
                         clock pessimism              0.277    45.158    
                         clock uncertainty           -0.393    44.765    
    SLICE_X33Y61         FDCE (Recov_fdce_C_CLR)     -0.405    44.360    UPD_CLK_DIV/temp_reg[1]
  -------------------------------------------------------------------
                         required time                         44.360    
                         arrival time                         -43.066    
  -------------------------------------------------------------------
                         slack                                  1.294    

Slack (MET) :             1.294ns  (required time - arrival time)
  Source:                 UPD/lost_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            UPD_CLK_DIV/temp_reg[2]/CLR
                            (recovery check against rising-edge clock clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            8.000ns  (clk_out1_clk_wiz_0 rise@40.000ns - sys_clk_pin rise@32.000ns)
  Data Path Delay:        5.732ns  (logic 1.818ns (31.719%)  route 3.914ns (68.281%))
  Logic Levels:           4  (CARRY4=2 LUT2=1 LUT4=1)
  Clock Path Skew:        -0.176ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.881ns = ( 44.881 - 40.000 ) 
    Source Clock Delay      (SCD):    5.334ns = ( 37.334 - 32.000 ) 
    Clock Pessimism Removal (CPR):    0.277ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                     32.000    32.000 r  
    L16                                               0.000    32.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    32.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491    33.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076    35.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101    35.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.666    37.334    UPD/H125MHz_IBUF_BUFG
    SLICE_X34Y31         FDRE                                         r  UPD/lost_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X34Y31         FDRE (Prop_fdre_C_Q)         0.518    37.852 r  UPD/lost_reg/Q
                         net (fo=18, routed)          2.266    40.118    UPD_CLK_DIV/led_OBUF[1]
    SLICE_X31Y64         LUT4 (Prop_lut4_I0_O)        0.124    40.242 r  UPD_CLK_DIV/temp[0]_i_11/O
                         net (fo=1, routed)           0.000    40.242    UPD_CLK_DIV/temp[0]_i_11_n_0
    SLICE_X31Y64         CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.532    40.774 r  UPD_CLK_DIV/temp_reg[0]_i_5/CO[3]
                         net (fo=1, routed)           0.000    40.774    UPD_CLK_DIV/temp_reg[0]_i_5_n_0
    SLICE_X31Y65         CARRY4 (Prop_carry4_CI_CO[0])
                                                      0.271    41.045 f  UPD_CLK_DIV/temp_reg[0]_i_4/CO[0]
                         net (fo=1, routed)           0.405    41.450    UPD_CLK_DIV/temp_reg[0]_i_4_n_3
    SLICE_X31Y66         LUT2 (Prop_lut2_I0_O)        0.373    41.823 f  UPD_CLK_DIV/temp[0]_i_2/O
                         net (fo=25, routed)          1.243    43.066    UPD_CLK_DIV/temp[0]_i_2_n_0
    SLICE_X33Y61         FDCE                                         f  UPD_CLK_DIV/temp_reg[2]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                     40.000    40.000 r  
    L16                                               0.000    40.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    40.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421    41.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    43.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    43.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.490    44.882    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.177    41.705 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.599    43.304    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    43.395 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.487    44.881    UPD_CLK_DIV/clk_out1
    SLICE_X33Y61         FDCE                                         r  UPD_CLK_DIV/temp_reg[2]/C
                         clock pessimism              0.277    45.158    
                         clock uncertainty           -0.393    44.765    
    SLICE_X33Y61         FDCE (Recov_fdce_C_CLR)     -0.405    44.360    UPD_CLK_DIV/temp_reg[2]
  -------------------------------------------------------------------
                         required time                         44.360    
                         arrival time                         -43.066    
  -------------------------------------------------------------------
                         slack                                  1.294    

Slack (MET) :             1.294ns  (required time - arrival time)
  Source:                 UPD/lost_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            UPD_CLK_DIV/temp_reg[3]/CLR
                            (recovery check against rising-edge clock clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            8.000ns  (clk_out1_clk_wiz_0 rise@40.000ns - sys_clk_pin rise@32.000ns)
  Data Path Delay:        5.732ns  (logic 1.818ns (31.719%)  route 3.914ns (68.281%))
  Logic Levels:           4  (CARRY4=2 LUT2=1 LUT4=1)
  Clock Path Skew:        -0.176ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.881ns = ( 44.881 - 40.000 ) 
    Source Clock Delay      (SCD):    5.334ns = ( 37.334 - 32.000 ) 
    Clock Pessimism Removal (CPR):    0.277ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                     32.000    32.000 r  
    L16                                               0.000    32.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    32.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491    33.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076    35.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101    35.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.666    37.334    UPD/H125MHz_IBUF_BUFG
    SLICE_X34Y31         FDRE                                         r  UPD/lost_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X34Y31         FDRE (Prop_fdre_C_Q)         0.518    37.852 r  UPD/lost_reg/Q
                         net (fo=18, routed)          2.266    40.118    UPD_CLK_DIV/led_OBUF[1]
    SLICE_X31Y64         LUT4 (Prop_lut4_I0_O)        0.124    40.242 r  UPD_CLK_DIV/temp[0]_i_11/O
                         net (fo=1, routed)           0.000    40.242    UPD_CLK_DIV/temp[0]_i_11_n_0
    SLICE_X31Y64         CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.532    40.774 r  UPD_CLK_DIV/temp_reg[0]_i_5/CO[3]
                         net (fo=1, routed)           0.000    40.774    UPD_CLK_DIV/temp_reg[0]_i_5_n_0
    SLICE_X31Y65         CARRY4 (Prop_carry4_CI_CO[0])
                                                      0.271    41.045 f  UPD_CLK_DIV/temp_reg[0]_i_4/CO[0]
                         net (fo=1, routed)           0.405    41.450    UPD_CLK_DIV/temp_reg[0]_i_4_n_3
    SLICE_X31Y66         LUT2 (Prop_lut2_I0_O)        0.373    41.823 f  UPD_CLK_DIV/temp[0]_i_2/O
                         net (fo=25, routed)          1.243    43.066    UPD_CLK_DIV/temp[0]_i_2_n_0
    SLICE_X33Y61         FDCE                                         f  UPD_CLK_DIV/temp_reg[3]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                     40.000    40.000 r  
    L16                                               0.000    40.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    40.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421    41.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    43.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    43.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.490    44.882    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.177    41.705 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.599    43.304    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    43.395 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.487    44.881    UPD_CLK_DIV/clk_out1
    SLICE_X33Y61         FDCE                                         r  UPD_CLK_DIV/temp_reg[3]/C
                         clock pessimism              0.277    45.158    
                         clock uncertainty           -0.393    44.765    
    SLICE_X33Y61         FDCE (Recov_fdce_C_CLR)     -0.405    44.360    UPD_CLK_DIV/temp_reg[3]
  -------------------------------------------------------------------
                         required time                         44.360    
                         arrival time                         -43.066    
  -------------------------------------------------------------------
                         slack                                  1.294    

Slack (MET) :             1.434ns  (required time - arrival time)
  Source:                 UPD/lost_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            UPD_CLK_DIV/temp_reg[4]/CLR
                            (recovery check against rising-edge clock clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            8.000ns  (clk_out1_clk_wiz_0 rise@40.000ns - sys_clk_pin rise@32.000ns)
  Data Path Delay:        5.591ns  (logic 1.818ns (32.518%)  route 3.773ns (67.482%))
  Logic Levels:           4  (CARRY4=2 LUT2=1 LUT4=1)
  Clock Path Skew:        -0.177ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.880ns = ( 44.880 - 40.000 ) 
    Source Clock Delay      (SCD):    5.334ns = ( 37.334 - 32.000 ) 
    Clock Pessimism Removal (CPR):    0.277ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                     32.000    32.000 r  
    L16                                               0.000    32.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    32.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491    33.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076    35.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101    35.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.666    37.334    UPD/H125MHz_IBUF_BUFG
    SLICE_X34Y31         FDRE                                         r  UPD/lost_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X34Y31         FDRE (Prop_fdre_C_Q)         0.518    37.852 r  UPD/lost_reg/Q
                         net (fo=18, routed)          2.266    40.118    UPD_CLK_DIV/led_OBUF[1]
    SLICE_X31Y64         LUT4 (Prop_lut4_I0_O)        0.124    40.242 r  UPD_CLK_DIV/temp[0]_i_11/O
                         net (fo=1, routed)           0.000    40.242    UPD_CLK_DIV/temp[0]_i_11_n_0
    SLICE_X31Y64         CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.532    40.774 r  UPD_CLK_DIV/temp_reg[0]_i_5/CO[3]
                         net (fo=1, routed)           0.000    40.774    UPD_CLK_DIV/temp_reg[0]_i_5_n_0
    SLICE_X31Y65         CARRY4 (Prop_carry4_CI_CO[0])
                                                      0.271    41.045 f  UPD_CLK_DIV/temp_reg[0]_i_4/CO[0]
                         net (fo=1, routed)           0.405    41.450    UPD_CLK_DIV/temp_reg[0]_i_4_n_3
    SLICE_X31Y66         LUT2 (Prop_lut2_I0_O)        0.373    41.823 f  UPD_CLK_DIV/temp[0]_i_2/O
                         net (fo=25, routed)          1.102    42.925    UPD_CLK_DIV/temp[0]_i_2_n_0
    SLICE_X33Y62         FDCE                                         f  UPD_CLK_DIV/temp_reg[4]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                     40.000    40.000 r  
    L16                                               0.000    40.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    40.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421    41.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    43.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    43.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.490    44.882    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.177    41.705 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.599    43.304    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    43.395 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.486    44.880    UPD_CLK_DIV/clk_out1
    SLICE_X33Y62         FDCE                                         r  UPD_CLK_DIV/temp_reg[4]/C
                         clock pessimism              0.277    45.157    
                         clock uncertainty           -0.393    44.764    
    SLICE_X33Y62         FDCE (Recov_fdce_C_CLR)     -0.405    44.359    UPD_CLK_DIV/temp_reg[4]
  -------------------------------------------------------------------
                         required time                         44.359    
                         arrival time                         -42.925    
  -------------------------------------------------------------------
                         slack                                  1.434    

Slack (MET) :             1.434ns  (required time - arrival time)
  Source:                 UPD/lost_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            UPD_CLK_DIV/temp_reg[5]/CLR
                            (recovery check against rising-edge clock clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            8.000ns  (clk_out1_clk_wiz_0 rise@40.000ns - sys_clk_pin rise@32.000ns)
  Data Path Delay:        5.591ns  (logic 1.818ns (32.518%)  route 3.773ns (67.482%))
  Logic Levels:           4  (CARRY4=2 LUT2=1 LUT4=1)
  Clock Path Skew:        -0.177ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.880ns = ( 44.880 - 40.000 ) 
    Source Clock Delay      (SCD):    5.334ns = ( 37.334 - 32.000 ) 
    Clock Pessimism Removal (CPR):    0.277ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                     32.000    32.000 r  
    L16                                               0.000    32.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    32.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491    33.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076    35.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101    35.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.666    37.334    UPD/H125MHz_IBUF_BUFG
    SLICE_X34Y31         FDRE                                         r  UPD/lost_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X34Y31         FDRE (Prop_fdre_C_Q)         0.518    37.852 r  UPD/lost_reg/Q
                         net (fo=18, routed)          2.266    40.118    UPD_CLK_DIV/led_OBUF[1]
    SLICE_X31Y64         LUT4 (Prop_lut4_I0_O)        0.124    40.242 r  UPD_CLK_DIV/temp[0]_i_11/O
                         net (fo=1, routed)           0.000    40.242    UPD_CLK_DIV/temp[0]_i_11_n_0
    SLICE_X31Y64         CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.532    40.774 r  UPD_CLK_DIV/temp_reg[0]_i_5/CO[3]
                         net (fo=1, routed)           0.000    40.774    UPD_CLK_DIV/temp_reg[0]_i_5_n_0
    SLICE_X31Y65         CARRY4 (Prop_carry4_CI_CO[0])
                                                      0.271    41.045 f  UPD_CLK_DIV/temp_reg[0]_i_4/CO[0]
                         net (fo=1, routed)           0.405    41.450    UPD_CLK_DIV/temp_reg[0]_i_4_n_3
    SLICE_X31Y66         LUT2 (Prop_lut2_I0_O)        0.373    41.823 f  UPD_CLK_DIV/temp[0]_i_2/O
                         net (fo=25, routed)          1.102    42.925    UPD_CLK_DIV/temp[0]_i_2_n_0
    SLICE_X33Y62         FDCE                                         f  UPD_CLK_DIV/temp_reg[5]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                     40.000    40.000 r  
    L16                                               0.000    40.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    40.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421    41.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    43.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    43.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.490    44.882    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.177    41.705 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.599    43.304    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    43.395 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.486    44.880    UPD_CLK_DIV/clk_out1
    SLICE_X33Y62         FDCE                                         r  UPD_CLK_DIV/temp_reg[5]/C
                         clock pessimism              0.277    45.157    
                         clock uncertainty           -0.393    44.764    
    SLICE_X33Y62         FDCE (Recov_fdce_C_CLR)     -0.405    44.359    UPD_CLK_DIV/temp_reg[5]
  -------------------------------------------------------------------
                         required time                         44.359    
                         arrival time                         -42.925    
  -------------------------------------------------------------------
                         slack                                  1.434    

Slack (MET) :             1.434ns  (required time - arrival time)
  Source:                 UPD/lost_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            UPD_CLK_DIV/temp_reg[6]/CLR
                            (recovery check against rising-edge clock clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            8.000ns  (clk_out1_clk_wiz_0 rise@40.000ns - sys_clk_pin rise@32.000ns)
  Data Path Delay:        5.591ns  (logic 1.818ns (32.518%)  route 3.773ns (67.482%))
  Logic Levels:           4  (CARRY4=2 LUT2=1 LUT4=1)
  Clock Path Skew:        -0.177ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.880ns = ( 44.880 - 40.000 ) 
    Source Clock Delay      (SCD):    5.334ns = ( 37.334 - 32.000 ) 
    Clock Pessimism Removal (CPR):    0.277ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                     32.000    32.000 r  
    L16                                               0.000    32.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    32.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491    33.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076    35.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101    35.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.666    37.334    UPD/H125MHz_IBUF_BUFG
    SLICE_X34Y31         FDRE                                         r  UPD/lost_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X34Y31         FDRE (Prop_fdre_C_Q)         0.518    37.852 r  UPD/lost_reg/Q
                         net (fo=18, routed)          2.266    40.118    UPD_CLK_DIV/led_OBUF[1]
    SLICE_X31Y64         LUT4 (Prop_lut4_I0_O)        0.124    40.242 r  UPD_CLK_DIV/temp[0]_i_11/O
                         net (fo=1, routed)           0.000    40.242    UPD_CLK_DIV/temp[0]_i_11_n_0
    SLICE_X31Y64         CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.532    40.774 r  UPD_CLK_DIV/temp_reg[0]_i_5/CO[3]
                         net (fo=1, routed)           0.000    40.774    UPD_CLK_DIV/temp_reg[0]_i_5_n_0
    SLICE_X31Y65         CARRY4 (Prop_carry4_CI_CO[0])
                                                      0.271    41.045 f  UPD_CLK_DIV/temp_reg[0]_i_4/CO[0]
                         net (fo=1, routed)           0.405    41.450    UPD_CLK_DIV/temp_reg[0]_i_4_n_3
    SLICE_X31Y66         LUT2 (Prop_lut2_I0_O)        0.373    41.823 f  UPD_CLK_DIV/temp[0]_i_2/O
                         net (fo=25, routed)          1.102    42.925    UPD_CLK_DIV/temp[0]_i_2_n_0
    SLICE_X33Y62         FDCE                                         f  UPD_CLK_DIV/temp_reg[6]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                     40.000    40.000 r  
    L16                                               0.000    40.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    40.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421    41.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    43.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    43.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.490    44.882    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.177    41.705 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.599    43.304    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    43.395 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.486    44.880    UPD_CLK_DIV/clk_out1
    SLICE_X33Y62         FDCE                                         r  UPD_CLK_DIV/temp_reg[6]/C
                         clock pessimism              0.277    45.157    
                         clock uncertainty           -0.393    44.764    
    SLICE_X33Y62         FDCE (Recov_fdce_C_CLR)     -0.405    44.359    UPD_CLK_DIV/temp_reg[6]
  -------------------------------------------------------------------
                         required time                         44.359    
                         arrival time                         -42.925    
  -------------------------------------------------------------------
                         slack                                  1.434    

Slack (MET) :             1.434ns  (required time - arrival time)
  Source:                 UPD/lost_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            UPD_CLK_DIV/temp_reg[7]/CLR
                            (recovery check against rising-edge clock clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            8.000ns  (clk_out1_clk_wiz_0 rise@40.000ns - sys_clk_pin rise@32.000ns)
  Data Path Delay:        5.591ns  (logic 1.818ns (32.518%)  route 3.773ns (67.482%))
  Logic Levels:           4  (CARRY4=2 LUT2=1 LUT4=1)
  Clock Path Skew:        -0.177ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.880ns = ( 44.880 - 40.000 ) 
    Source Clock Delay      (SCD):    5.334ns = ( 37.334 - 32.000 ) 
    Clock Pessimism Removal (CPR):    0.277ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                     32.000    32.000 r  
    L16                                               0.000    32.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    32.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491    33.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076    35.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101    35.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.666    37.334    UPD/H125MHz_IBUF_BUFG
    SLICE_X34Y31         FDRE                                         r  UPD/lost_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X34Y31         FDRE (Prop_fdre_C_Q)         0.518    37.852 r  UPD/lost_reg/Q
                         net (fo=18, routed)          2.266    40.118    UPD_CLK_DIV/led_OBUF[1]
    SLICE_X31Y64         LUT4 (Prop_lut4_I0_O)        0.124    40.242 r  UPD_CLK_DIV/temp[0]_i_11/O
                         net (fo=1, routed)           0.000    40.242    UPD_CLK_DIV/temp[0]_i_11_n_0
    SLICE_X31Y64         CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.532    40.774 r  UPD_CLK_DIV/temp_reg[0]_i_5/CO[3]
                         net (fo=1, routed)           0.000    40.774    UPD_CLK_DIV/temp_reg[0]_i_5_n_0
    SLICE_X31Y65         CARRY4 (Prop_carry4_CI_CO[0])
                                                      0.271    41.045 f  UPD_CLK_DIV/temp_reg[0]_i_4/CO[0]
                         net (fo=1, routed)           0.405    41.450    UPD_CLK_DIV/temp_reg[0]_i_4_n_3
    SLICE_X31Y66         LUT2 (Prop_lut2_I0_O)        0.373    41.823 f  UPD_CLK_DIV/temp[0]_i_2/O
                         net (fo=25, routed)          1.102    42.925    UPD_CLK_DIV/temp[0]_i_2_n_0
    SLICE_X33Y62         FDCE                                         f  UPD_CLK_DIV/temp_reg[7]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                     40.000    40.000 r  
    L16                                               0.000    40.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    40.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421    41.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    43.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    43.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.490    44.882    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.177    41.705 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.599    43.304    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    43.395 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.486    44.880    UPD_CLK_DIV/clk_out1
    SLICE_X33Y62         FDCE                                         r  UPD_CLK_DIV/temp_reg[7]/C
                         clock pessimism              0.277    45.157    
                         clock uncertainty           -0.393    44.764    
    SLICE_X33Y62         FDCE (Recov_fdce_C_CLR)     -0.405    44.359    UPD_CLK_DIV/temp_reg[7]
  -------------------------------------------------------------------
                         required time                         44.359    
                         arrival time                         -42.925    
  -------------------------------------------------------------------
                         slack                                  1.434    

Slack (MET) :             1.584ns  (required time - arrival time)
  Source:                 UPD/lost_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            UPD_CLK_DIV/temp_reg[10]/CLR
                            (recovery check against rising-edge clock clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            8.000ns  (clk_out1_clk_wiz_0 rise@40.000ns - sys_clk_pin rise@32.000ns)
  Data Path Delay:        5.440ns  (logic 1.818ns (33.419%)  route 3.622ns (66.581%))
  Logic Levels:           4  (CARRY4=2 LUT2=1 LUT4=1)
  Clock Path Skew:        -0.178ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.879ns = ( 44.879 - 40.000 ) 
    Source Clock Delay      (SCD):    5.334ns = ( 37.334 - 32.000 ) 
    Clock Pessimism Removal (CPR):    0.277ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                     32.000    32.000 r  
    L16                                               0.000    32.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    32.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491    33.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076    35.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101    35.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.666    37.334    UPD/H125MHz_IBUF_BUFG
    SLICE_X34Y31         FDRE                                         r  UPD/lost_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X34Y31         FDRE (Prop_fdre_C_Q)         0.518    37.852 r  UPD/lost_reg/Q
                         net (fo=18, routed)          2.266    40.118    UPD_CLK_DIV/led_OBUF[1]
    SLICE_X31Y64         LUT4 (Prop_lut4_I0_O)        0.124    40.242 r  UPD_CLK_DIV/temp[0]_i_11/O
                         net (fo=1, routed)           0.000    40.242    UPD_CLK_DIV/temp[0]_i_11_n_0
    SLICE_X31Y64         CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.532    40.774 r  UPD_CLK_DIV/temp_reg[0]_i_5/CO[3]
                         net (fo=1, routed)           0.000    40.774    UPD_CLK_DIV/temp_reg[0]_i_5_n_0
    SLICE_X31Y65         CARRY4 (Prop_carry4_CI_CO[0])
                                                      0.271    41.045 f  UPD_CLK_DIV/temp_reg[0]_i_4/CO[0]
                         net (fo=1, routed)           0.405    41.450    UPD_CLK_DIV/temp_reg[0]_i_4_n_3
    SLICE_X31Y66         LUT2 (Prop_lut2_I0_O)        0.373    41.823 f  UPD_CLK_DIV/temp[0]_i_2/O
                         net (fo=25, routed)          0.951    42.774    UPD_CLK_DIV/temp[0]_i_2_n_0
    SLICE_X33Y63         FDCE                                         f  UPD_CLK_DIV/temp_reg[10]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                     40.000    40.000 r  
    L16                                               0.000    40.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    40.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421    41.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    43.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    43.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.490    44.882    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.177    41.705 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.599    43.304    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    43.395 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.485    44.879    UPD_CLK_DIV/clk_out1
    SLICE_X33Y63         FDCE                                         r  UPD_CLK_DIV/temp_reg[10]/C
                         clock pessimism              0.277    45.156    
                         clock uncertainty           -0.393    44.763    
    SLICE_X33Y63         FDCE (Recov_fdce_C_CLR)     -0.405    44.358    UPD_CLK_DIV/temp_reg[10]
  -------------------------------------------------------------------
                         required time                         44.358    
                         arrival time                         -42.774    
  -------------------------------------------------------------------
                         slack                                  1.584    

Slack (MET) :             1.584ns  (required time - arrival time)
  Source:                 UPD/lost_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            UPD_CLK_DIV/temp_reg[11]/CLR
                            (recovery check against rising-edge clock clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            8.000ns  (clk_out1_clk_wiz_0 rise@40.000ns - sys_clk_pin rise@32.000ns)
  Data Path Delay:        5.440ns  (logic 1.818ns (33.419%)  route 3.622ns (66.581%))
  Logic Levels:           4  (CARRY4=2 LUT2=1 LUT4=1)
  Clock Path Skew:        -0.178ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.879ns = ( 44.879 - 40.000 ) 
    Source Clock Delay      (SCD):    5.334ns = ( 37.334 - 32.000 ) 
    Clock Pessimism Removal (CPR):    0.277ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                     32.000    32.000 r  
    L16                                               0.000    32.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    32.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491    33.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076    35.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101    35.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.666    37.334    UPD/H125MHz_IBUF_BUFG
    SLICE_X34Y31         FDRE                                         r  UPD/lost_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X34Y31         FDRE (Prop_fdre_C_Q)         0.518    37.852 r  UPD/lost_reg/Q
                         net (fo=18, routed)          2.266    40.118    UPD_CLK_DIV/led_OBUF[1]
    SLICE_X31Y64         LUT4 (Prop_lut4_I0_O)        0.124    40.242 r  UPD_CLK_DIV/temp[0]_i_11/O
                         net (fo=1, routed)           0.000    40.242    UPD_CLK_DIV/temp[0]_i_11_n_0
    SLICE_X31Y64         CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.532    40.774 r  UPD_CLK_DIV/temp_reg[0]_i_5/CO[3]
                         net (fo=1, routed)           0.000    40.774    UPD_CLK_DIV/temp_reg[0]_i_5_n_0
    SLICE_X31Y65         CARRY4 (Prop_carry4_CI_CO[0])
                                                      0.271    41.045 f  UPD_CLK_DIV/temp_reg[0]_i_4/CO[0]
                         net (fo=1, routed)           0.405    41.450    UPD_CLK_DIV/temp_reg[0]_i_4_n_3
    SLICE_X31Y66         LUT2 (Prop_lut2_I0_O)        0.373    41.823 f  UPD_CLK_DIV/temp[0]_i_2/O
                         net (fo=25, routed)          0.951    42.774    UPD_CLK_DIV/temp[0]_i_2_n_0
    SLICE_X33Y63         FDCE                                         f  UPD_CLK_DIV/temp_reg[11]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                     40.000    40.000 r  
    L16                                               0.000    40.000 r  H125MHz (IN)
                         net (fo=0)                   0.000    40.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421    41.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    43.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    43.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.490    44.882    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.177    41.705 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.599    43.304    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    43.395 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          1.485    44.879    UPD_CLK_DIV/clk_out1
    SLICE_X33Y63         FDCE                                         r  UPD_CLK_DIV/temp_reg[11]/C
                         clock pessimism              0.277    45.156    
                         clock uncertainty           -0.393    44.763    
    SLICE_X33Y63         FDCE (Recov_fdce_C_CLR)     -0.405    44.358    UPD_CLK_DIV/temp_reg[11]
  -------------------------------------------------------------------
                         required time                         44.358    
                         arrival time                         -42.774    
  -------------------------------------------------------------------
                         slack                                  1.584    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.537ns  (arrival time - required time)
  Source:                 SNAKE/request_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            SNAKE/startUpdate_reg/CLR
                            (removal check against rising-edge clock clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        1.111ns  (logic 0.186ns (16.742%)  route 0.925ns (83.258%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.273ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.987ns
    Source Clock Delay      (SCD):    1.467ns
    Clock Pessimism Removal (CPR):    0.247ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.555     1.467    SNAKE/H125MHz_IBUF_BUFG
    SLICE_X22Y59         FDRE                                         r  SNAKE/request_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X22Y59         FDRE (Prop_fdre_C_Q)         0.141     1.608 f  SNAKE/request_reg/Q
                         net (fo=5, routed)           0.605     2.213    SNAKE/dataRequest
    SLICE_X22Y59         LUT2 (Prop_lut2_I1_O)        0.045     2.258 f  SNAKE/startUpdate_i_2/O
                         net (fo=1, routed)           0.320     2.578    SNAKE/startUpdate_i_2_n_0
    SLICE_X22Y58         FDCE                                         f  SNAKE/startUpdate_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.814     1.973    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.369     0.604 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.528     1.132    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.161 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.826     1.987    SNAKE/clk_out1
    SLICE_X22Y58         FDCE                                         r  SNAKE/startUpdate_reg/C
                         clock pessimism             -0.247     1.740    
                         clock uncertainty            0.393     2.133    
    SLICE_X22Y58         FDCE (Remov_fdce_C_CLR)     -0.092     2.041    SNAKE/startUpdate_reg
  -------------------------------------------------------------------
                         required time                         -2.041    
                         arrival time                           2.578    
  -------------------------------------------------------------------
                         slack                                  0.537    

Slack (MET) :             1.035ns  (arrival time - required time)
  Source:                 UPD/lost_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            UPD_CLK_DIV/temp_reg[20]/CLR
                            (removal check against rising-edge clock clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        1.604ns  (logic 0.526ns (32.800%)  route 1.078ns (67.200%))
  Logic Levels:           4  (CARRY4=2 LUT2=1 LUT4=1)
  Clock Path Skew:        0.267ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.984ns
    Source Clock Delay      (SCD):    1.470ns
    Clock Pessimism Removal (CPR):    0.247ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.558     1.470    UPD/H125MHz_IBUF_BUFG
    SLICE_X34Y31         FDRE                                         r  UPD/lost_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X34Y31         FDRE (Prop_fdre_C_Q)         0.164     1.634 r  UPD/lost_reg/Q
                         net (fo=18, routed)          0.742     2.376    UPD_CLK_DIV/led_OBUF[1]
    SLICE_X31Y64         LUT4 (Prop_lut4_I1_O)        0.045     2.421 r  UPD_CLK_DIV/temp[0]_i_9/O
                         net (fo=1, routed)           0.000     2.421    UPD_CLK_DIV/temp[0]_i_9_n_0
    SLICE_X31Y64         CARRY4 (Prop_carry4_S[2]_CO[3])
                                                      0.115     2.536 r  UPD_CLK_DIV/temp_reg[0]_i_5/CO[3]
                         net (fo=1, routed)           0.000     2.536    UPD_CLK_DIV/temp_reg[0]_i_5_n_0
    SLICE_X31Y65         CARRY4 (Prop_carry4_CI_CO[0])
                                                      0.076     2.612 f  UPD_CLK_DIV/temp_reg[0]_i_4/CO[0]
                         net (fo=1, routed)           0.140     2.752    UPD_CLK_DIV/temp_reg[0]_i_4_n_3
    SLICE_X31Y66         LUT2 (Prop_lut2_I0_O)        0.126     2.878 f  UPD_CLK_DIV/temp[0]_i_2/O
                         net (fo=25, routed)          0.196     3.073    UPD_CLK_DIV/temp[0]_i_2_n_0
    SLICE_X33Y66         FDCE                                         f  UPD_CLK_DIV/temp_reg[20]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.814     1.973    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.369     0.604 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.528     1.132    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.161 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.823     1.984    UPD_CLK_DIV/clk_out1
    SLICE_X33Y66         FDCE                                         r  UPD_CLK_DIV/temp_reg[20]/C
                         clock pessimism             -0.247     1.737    
                         clock uncertainty            0.393     2.130    
    SLICE_X33Y66         FDCE (Remov_fdce_C_CLR)     -0.092     2.038    UPD_CLK_DIV/temp_reg[20]
  -------------------------------------------------------------------
                         required time                         -2.038    
                         arrival time                           3.073    
  -------------------------------------------------------------------
                         slack                                  1.035    

Slack (MET) :             1.035ns  (arrival time - required time)
  Source:                 UPD/lost_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            UPD_CLK_DIV/temp_reg[21]/CLR
                            (removal check against rising-edge clock clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        1.604ns  (logic 0.526ns (32.800%)  route 1.078ns (67.200%))
  Logic Levels:           4  (CARRY4=2 LUT2=1 LUT4=1)
  Clock Path Skew:        0.267ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.984ns
    Source Clock Delay      (SCD):    1.470ns
    Clock Pessimism Removal (CPR):    0.247ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.558     1.470    UPD/H125MHz_IBUF_BUFG
    SLICE_X34Y31         FDRE                                         r  UPD/lost_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X34Y31         FDRE (Prop_fdre_C_Q)         0.164     1.634 r  UPD/lost_reg/Q
                         net (fo=18, routed)          0.742     2.376    UPD_CLK_DIV/led_OBUF[1]
    SLICE_X31Y64         LUT4 (Prop_lut4_I1_O)        0.045     2.421 r  UPD_CLK_DIV/temp[0]_i_9/O
                         net (fo=1, routed)           0.000     2.421    UPD_CLK_DIV/temp[0]_i_9_n_0
    SLICE_X31Y64         CARRY4 (Prop_carry4_S[2]_CO[3])
                                                      0.115     2.536 r  UPD_CLK_DIV/temp_reg[0]_i_5/CO[3]
                         net (fo=1, routed)           0.000     2.536    UPD_CLK_DIV/temp_reg[0]_i_5_n_0
    SLICE_X31Y65         CARRY4 (Prop_carry4_CI_CO[0])
                                                      0.076     2.612 f  UPD_CLK_DIV/temp_reg[0]_i_4/CO[0]
                         net (fo=1, routed)           0.140     2.752    UPD_CLK_DIV/temp_reg[0]_i_4_n_3
    SLICE_X31Y66         LUT2 (Prop_lut2_I0_O)        0.126     2.878 f  UPD_CLK_DIV/temp[0]_i_2/O
                         net (fo=25, routed)          0.196     3.073    UPD_CLK_DIV/temp[0]_i_2_n_0
    SLICE_X33Y66         FDCE                                         f  UPD_CLK_DIV/temp_reg[21]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.814     1.973    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.369     0.604 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.528     1.132    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.161 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.823     1.984    UPD_CLK_DIV/clk_out1
    SLICE_X33Y66         FDCE                                         r  UPD_CLK_DIV/temp_reg[21]/C
                         clock pessimism             -0.247     1.737    
                         clock uncertainty            0.393     2.130    
    SLICE_X33Y66         FDCE (Remov_fdce_C_CLR)     -0.092     2.038    UPD_CLK_DIV/temp_reg[21]
  -------------------------------------------------------------------
                         required time                         -2.038    
                         arrival time                           3.073    
  -------------------------------------------------------------------
                         slack                                  1.035    

Slack (MET) :             1.035ns  (arrival time - required time)
  Source:                 UPD/lost_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            UPD_CLK_DIV/temp_reg[22]/CLR
                            (removal check against rising-edge clock clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        1.604ns  (logic 0.526ns (32.800%)  route 1.078ns (67.200%))
  Logic Levels:           4  (CARRY4=2 LUT2=1 LUT4=1)
  Clock Path Skew:        0.267ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.984ns
    Source Clock Delay      (SCD):    1.470ns
    Clock Pessimism Removal (CPR):    0.247ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.558     1.470    UPD/H125MHz_IBUF_BUFG
    SLICE_X34Y31         FDRE                                         r  UPD/lost_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X34Y31         FDRE (Prop_fdre_C_Q)         0.164     1.634 r  UPD/lost_reg/Q
                         net (fo=18, routed)          0.742     2.376    UPD_CLK_DIV/led_OBUF[1]
    SLICE_X31Y64         LUT4 (Prop_lut4_I1_O)        0.045     2.421 r  UPD_CLK_DIV/temp[0]_i_9/O
                         net (fo=1, routed)           0.000     2.421    UPD_CLK_DIV/temp[0]_i_9_n_0
    SLICE_X31Y64         CARRY4 (Prop_carry4_S[2]_CO[3])
                                                      0.115     2.536 r  UPD_CLK_DIV/temp_reg[0]_i_5/CO[3]
                         net (fo=1, routed)           0.000     2.536    UPD_CLK_DIV/temp_reg[0]_i_5_n_0
    SLICE_X31Y65         CARRY4 (Prop_carry4_CI_CO[0])
                                                      0.076     2.612 f  UPD_CLK_DIV/temp_reg[0]_i_4/CO[0]
                         net (fo=1, routed)           0.140     2.752    UPD_CLK_DIV/temp_reg[0]_i_4_n_3
    SLICE_X31Y66         LUT2 (Prop_lut2_I0_O)        0.126     2.878 f  UPD_CLK_DIV/temp[0]_i_2/O
                         net (fo=25, routed)          0.196     3.073    UPD_CLK_DIV/temp[0]_i_2_n_0
    SLICE_X33Y66         FDCE                                         f  UPD_CLK_DIV/temp_reg[22]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.814     1.973    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.369     0.604 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.528     1.132    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.161 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.823     1.984    UPD_CLK_DIV/clk_out1
    SLICE_X33Y66         FDCE                                         r  UPD_CLK_DIV/temp_reg[22]/C
                         clock pessimism             -0.247     1.737    
                         clock uncertainty            0.393     2.130    
    SLICE_X33Y66         FDCE (Remov_fdce_C_CLR)     -0.092     2.038    UPD_CLK_DIV/temp_reg[22]
  -------------------------------------------------------------------
                         required time                         -2.038    
                         arrival time                           3.073    
  -------------------------------------------------------------------
                         slack                                  1.035    

Slack (MET) :             1.035ns  (arrival time - required time)
  Source:                 UPD/lost_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            UPD_CLK_DIV/temp_reg[23]/CLR
                            (removal check against rising-edge clock clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        1.604ns  (logic 0.526ns (32.800%)  route 1.078ns (67.200%))
  Logic Levels:           4  (CARRY4=2 LUT2=1 LUT4=1)
  Clock Path Skew:        0.267ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.984ns
    Source Clock Delay      (SCD):    1.470ns
    Clock Pessimism Removal (CPR):    0.247ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.558     1.470    UPD/H125MHz_IBUF_BUFG
    SLICE_X34Y31         FDRE                                         r  UPD/lost_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X34Y31         FDRE (Prop_fdre_C_Q)         0.164     1.634 r  UPD/lost_reg/Q
                         net (fo=18, routed)          0.742     2.376    UPD_CLK_DIV/led_OBUF[1]
    SLICE_X31Y64         LUT4 (Prop_lut4_I1_O)        0.045     2.421 r  UPD_CLK_DIV/temp[0]_i_9/O
                         net (fo=1, routed)           0.000     2.421    UPD_CLK_DIV/temp[0]_i_9_n_0
    SLICE_X31Y64         CARRY4 (Prop_carry4_S[2]_CO[3])
                                                      0.115     2.536 r  UPD_CLK_DIV/temp_reg[0]_i_5/CO[3]
                         net (fo=1, routed)           0.000     2.536    UPD_CLK_DIV/temp_reg[0]_i_5_n_0
    SLICE_X31Y65         CARRY4 (Prop_carry4_CI_CO[0])
                                                      0.076     2.612 f  UPD_CLK_DIV/temp_reg[0]_i_4/CO[0]
                         net (fo=1, routed)           0.140     2.752    UPD_CLK_DIV/temp_reg[0]_i_4_n_3
    SLICE_X31Y66         LUT2 (Prop_lut2_I0_O)        0.126     2.878 f  UPD_CLK_DIV/temp[0]_i_2/O
                         net (fo=25, routed)          0.196     3.073    UPD_CLK_DIV/temp[0]_i_2_n_0
    SLICE_X33Y66         FDCE                                         f  UPD_CLK_DIV/temp_reg[23]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.814     1.973    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.369     0.604 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.528     1.132    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.161 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.823     1.984    UPD_CLK_DIV/clk_out1
    SLICE_X33Y66         FDCE                                         r  UPD_CLK_DIV/temp_reg[23]/C
                         clock pessimism             -0.247     1.737    
                         clock uncertainty            0.393     2.130    
    SLICE_X33Y66         FDCE (Remov_fdce_C_CLR)     -0.092     2.038    UPD_CLK_DIV/temp_reg[23]
  -------------------------------------------------------------------
                         required time                         -2.038    
                         arrival time                           3.073    
  -------------------------------------------------------------------
                         slack                                  1.035    

Slack (MET) :             1.088ns  (arrival time - required time)
  Source:                 UPD/lost_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            UPD_CLK_DIV/temp_reg[16]/CLR
                            (removal check against rising-edge clock clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        1.658ns  (logic 0.526ns (31.734%)  route 1.132ns (68.266%))
  Logic Levels:           4  (CARRY4=2 LUT2=1 LUT4=1)
  Clock Path Skew:        0.268ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.985ns
    Source Clock Delay      (SCD):    1.470ns
    Clock Pessimism Removal (CPR):    0.247ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.558     1.470    UPD/H125MHz_IBUF_BUFG
    SLICE_X34Y31         FDRE                                         r  UPD/lost_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X34Y31         FDRE (Prop_fdre_C_Q)         0.164     1.634 r  UPD/lost_reg/Q
                         net (fo=18, routed)          0.742     2.376    UPD_CLK_DIV/led_OBUF[1]
    SLICE_X31Y64         LUT4 (Prop_lut4_I1_O)        0.045     2.421 r  UPD_CLK_DIV/temp[0]_i_9/O
                         net (fo=1, routed)           0.000     2.421    UPD_CLK_DIV/temp[0]_i_9_n_0
    SLICE_X31Y64         CARRY4 (Prop_carry4_S[2]_CO[3])
                                                      0.115     2.536 r  UPD_CLK_DIV/temp_reg[0]_i_5/CO[3]
                         net (fo=1, routed)           0.000     2.536    UPD_CLK_DIV/temp_reg[0]_i_5_n_0
    SLICE_X31Y65         CARRY4 (Prop_carry4_CI_CO[0])
                                                      0.076     2.612 f  UPD_CLK_DIV/temp_reg[0]_i_4/CO[0]
                         net (fo=1, routed)           0.140     2.752    UPD_CLK_DIV/temp_reg[0]_i_4_n_3
    SLICE_X31Y66         LUT2 (Prop_lut2_I0_O)        0.126     2.878 f  UPD_CLK_DIV/temp[0]_i_2/O
                         net (fo=25, routed)          0.250     3.127    UPD_CLK_DIV/temp[0]_i_2_n_0
    SLICE_X33Y65         FDCE                                         f  UPD_CLK_DIV/temp_reg[16]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.814     1.973    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.369     0.604 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.528     1.132    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.161 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.824     1.985    UPD_CLK_DIV/clk_out1
    SLICE_X33Y65         FDCE                                         r  UPD_CLK_DIV/temp_reg[16]/C
                         clock pessimism             -0.247     1.738    
                         clock uncertainty            0.393     2.131    
    SLICE_X33Y65         FDCE (Remov_fdce_C_CLR)     -0.092     2.039    UPD_CLK_DIV/temp_reg[16]
  -------------------------------------------------------------------
                         required time                         -2.039    
                         arrival time                           3.127    
  -------------------------------------------------------------------
                         slack                                  1.088    

Slack (MET) :             1.088ns  (arrival time - required time)
  Source:                 UPD/lost_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            UPD_CLK_DIV/temp_reg[17]/CLR
                            (removal check against rising-edge clock clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        1.658ns  (logic 0.526ns (31.734%)  route 1.132ns (68.266%))
  Logic Levels:           4  (CARRY4=2 LUT2=1 LUT4=1)
  Clock Path Skew:        0.268ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.985ns
    Source Clock Delay      (SCD):    1.470ns
    Clock Pessimism Removal (CPR):    0.247ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.558     1.470    UPD/H125MHz_IBUF_BUFG
    SLICE_X34Y31         FDRE                                         r  UPD/lost_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X34Y31         FDRE (Prop_fdre_C_Q)         0.164     1.634 r  UPD/lost_reg/Q
                         net (fo=18, routed)          0.742     2.376    UPD_CLK_DIV/led_OBUF[1]
    SLICE_X31Y64         LUT4 (Prop_lut4_I1_O)        0.045     2.421 r  UPD_CLK_DIV/temp[0]_i_9/O
                         net (fo=1, routed)           0.000     2.421    UPD_CLK_DIV/temp[0]_i_9_n_0
    SLICE_X31Y64         CARRY4 (Prop_carry4_S[2]_CO[3])
                                                      0.115     2.536 r  UPD_CLK_DIV/temp_reg[0]_i_5/CO[3]
                         net (fo=1, routed)           0.000     2.536    UPD_CLK_DIV/temp_reg[0]_i_5_n_0
    SLICE_X31Y65         CARRY4 (Prop_carry4_CI_CO[0])
                                                      0.076     2.612 f  UPD_CLK_DIV/temp_reg[0]_i_4/CO[0]
                         net (fo=1, routed)           0.140     2.752    UPD_CLK_DIV/temp_reg[0]_i_4_n_3
    SLICE_X31Y66         LUT2 (Prop_lut2_I0_O)        0.126     2.878 f  UPD_CLK_DIV/temp[0]_i_2/O
                         net (fo=25, routed)          0.250     3.127    UPD_CLK_DIV/temp[0]_i_2_n_0
    SLICE_X33Y65         FDCE                                         f  UPD_CLK_DIV/temp_reg[17]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.814     1.973    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.369     0.604 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.528     1.132    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.161 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.824     1.985    UPD_CLK_DIV/clk_out1
    SLICE_X33Y65         FDCE                                         r  UPD_CLK_DIV/temp_reg[17]/C
                         clock pessimism             -0.247     1.738    
                         clock uncertainty            0.393     2.131    
    SLICE_X33Y65         FDCE (Remov_fdce_C_CLR)     -0.092     2.039    UPD_CLK_DIV/temp_reg[17]
  -------------------------------------------------------------------
                         required time                         -2.039    
                         arrival time                           3.127    
  -------------------------------------------------------------------
                         slack                                  1.088    

Slack (MET) :             1.088ns  (arrival time - required time)
  Source:                 UPD/lost_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            UPD_CLK_DIV/temp_reg[18]/CLR
                            (removal check against rising-edge clock clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        1.658ns  (logic 0.526ns (31.734%)  route 1.132ns (68.266%))
  Logic Levels:           4  (CARRY4=2 LUT2=1 LUT4=1)
  Clock Path Skew:        0.268ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.985ns
    Source Clock Delay      (SCD):    1.470ns
    Clock Pessimism Removal (CPR):    0.247ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.558     1.470    UPD/H125MHz_IBUF_BUFG
    SLICE_X34Y31         FDRE                                         r  UPD/lost_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X34Y31         FDRE (Prop_fdre_C_Q)         0.164     1.634 r  UPD/lost_reg/Q
                         net (fo=18, routed)          0.742     2.376    UPD_CLK_DIV/led_OBUF[1]
    SLICE_X31Y64         LUT4 (Prop_lut4_I1_O)        0.045     2.421 r  UPD_CLK_DIV/temp[0]_i_9/O
                         net (fo=1, routed)           0.000     2.421    UPD_CLK_DIV/temp[0]_i_9_n_0
    SLICE_X31Y64         CARRY4 (Prop_carry4_S[2]_CO[3])
                                                      0.115     2.536 r  UPD_CLK_DIV/temp_reg[0]_i_5/CO[3]
                         net (fo=1, routed)           0.000     2.536    UPD_CLK_DIV/temp_reg[0]_i_5_n_0
    SLICE_X31Y65         CARRY4 (Prop_carry4_CI_CO[0])
                                                      0.076     2.612 f  UPD_CLK_DIV/temp_reg[0]_i_4/CO[0]
                         net (fo=1, routed)           0.140     2.752    UPD_CLK_DIV/temp_reg[0]_i_4_n_3
    SLICE_X31Y66         LUT2 (Prop_lut2_I0_O)        0.126     2.878 f  UPD_CLK_DIV/temp[0]_i_2/O
                         net (fo=25, routed)          0.250     3.127    UPD_CLK_DIV/temp[0]_i_2_n_0
    SLICE_X33Y65         FDCE                                         f  UPD_CLK_DIV/temp_reg[18]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.814     1.973    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.369     0.604 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.528     1.132    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.161 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.824     1.985    UPD_CLK_DIV/clk_out1
    SLICE_X33Y65         FDCE                                         r  UPD_CLK_DIV/temp_reg[18]/C
                         clock pessimism             -0.247     1.738    
                         clock uncertainty            0.393     2.131    
    SLICE_X33Y65         FDCE (Remov_fdce_C_CLR)     -0.092     2.039    UPD_CLK_DIV/temp_reg[18]
  -------------------------------------------------------------------
                         required time                         -2.039    
                         arrival time                           3.127    
  -------------------------------------------------------------------
                         slack                                  1.088    

Slack (MET) :             1.088ns  (arrival time - required time)
  Source:                 UPD/lost_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            UPD_CLK_DIV/temp_reg[19]/CLR
                            (removal check against rising-edge clock clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        1.658ns  (logic 0.526ns (31.734%)  route 1.132ns (68.266%))
  Logic Levels:           4  (CARRY4=2 LUT2=1 LUT4=1)
  Clock Path Skew:        0.268ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.985ns
    Source Clock Delay      (SCD):    1.470ns
    Clock Pessimism Removal (CPR):    0.247ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.558     1.470    UPD/H125MHz_IBUF_BUFG
    SLICE_X34Y31         FDRE                                         r  UPD/lost_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X34Y31         FDRE (Prop_fdre_C_Q)         0.164     1.634 r  UPD/lost_reg/Q
                         net (fo=18, routed)          0.742     2.376    UPD_CLK_DIV/led_OBUF[1]
    SLICE_X31Y64         LUT4 (Prop_lut4_I1_O)        0.045     2.421 r  UPD_CLK_DIV/temp[0]_i_9/O
                         net (fo=1, routed)           0.000     2.421    UPD_CLK_DIV/temp[0]_i_9_n_0
    SLICE_X31Y64         CARRY4 (Prop_carry4_S[2]_CO[3])
                                                      0.115     2.536 r  UPD_CLK_DIV/temp_reg[0]_i_5/CO[3]
                         net (fo=1, routed)           0.000     2.536    UPD_CLK_DIV/temp_reg[0]_i_5_n_0
    SLICE_X31Y65         CARRY4 (Prop_carry4_CI_CO[0])
                                                      0.076     2.612 f  UPD_CLK_DIV/temp_reg[0]_i_4/CO[0]
                         net (fo=1, routed)           0.140     2.752    UPD_CLK_DIV/temp_reg[0]_i_4_n_3
    SLICE_X31Y66         LUT2 (Prop_lut2_I0_O)        0.126     2.878 f  UPD_CLK_DIV/temp[0]_i_2/O
                         net (fo=25, routed)          0.250     3.127    UPD_CLK_DIV/temp[0]_i_2_n_0
    SLICE_X33Y65         FDCE                                         f  UPD_CLK_DIV/temp_reg[19]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.814     1.973    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.369     0.604 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.528     1.132    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.161 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.824     1.985    UPD_CLK_DIV/clk_out1
    SLICE_X33Y65         FDCE                                         r  UPD_CLK_DIV/temp_reg[19]/C
                         clock pessimism             -0.247     1.738    
                         clock uncertainty            0.393     2.131    
    SLICE_X33Y65         FDCE (Remov_fdce_C_CLR)     -0.092     2.039    UPD_CLK_DIV/temp_reg[19]
  -------------------------------------------------------------------
                         required time                         -2.039    
                         arrival time                           3.127    
  -------------------------------------------------------------------
                         slack                                  1.088    

Slack (MET) :             1.090ns  (arrival time - required time)
  Source:                 UPD/lost_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            UPD_CLK_DIV/temp_reg[24]/CLR
                            (removal check against rising-edge clock clk_out1_clk_wiz_0  {rise@0.000ns fall@20.000ns period=40.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_clk_wiz_0 rise@0.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        1.657ns  (logic 0.526ns (31.743%)  route 1.131ns (68.257%))
  Logic Levels:           4  (CARRY4=2 LUT2=1 LUT4=1)
  Clock Path Skew:        0.266ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.983ns
    Source Clock Delay      (SCD):    1.470ns
    Clock Pessimism Removal (CPR):    0.247ns
  Clock Uncertainty:      0.393ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.286ns
    Phase Error              (PE):    0.246ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.558     1.470    UPD/H125MHz_IBUF_BUFG
    SLICE_X34Y31         FDRE                                         r  UPD/lost_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X34Y31         FDRE (Prop_fdre_C_Q)         0.164     1.634 r  UPD/lost_reg/Q
                         net (fo=18, routed)          0.742     2.376    UPD_CLK_DIV/led_OBUF[1]
    SLICE_X31Y64         LUT4 (Prop_lut4_I1_O)        0.045     2.421 r  UPD_CLK_DIV/temp[0]_i_9/O
                         net (fo=1, routed)           0.000     2.421    UPD_CLK_DIV/temp[0]_i_9_n_0
    SLICE_X31Y64         CARRY4 (Prop_carry4_S[2]_CO[3])
                                                      0.115     2.536 r  UPD_CLK_DIV/temp_reg[0]_i_5/CO[3]
                         net (fo=1, routed)           0.000     2.536    UPD_CLK_DIV/temp_reg[0]_i_5_n_0
    SLICE_X31Y65         CARRY4 (Prop_carry4_CI_CO[0])
                                                      0.076     2.612 f  UPD_CLK_DIV/temp_reg[0]_i_4/CO[0]
                         net (fo=1, routed)           0.140     2.752    UPD_CLK_DIV/temp_reg[0]_i_4_n_3
    SLICE_X31Y66         LUT2 (Prop_lut2_I0_O)        0.126     2.878 f  UPD_CLK_DIV/temp[0]_i_2/O
                         net (fo=25, routed)          0.249     3.127    UPD_CLK_DIV/temp[0]_i_2_n_0
    SLICE_X33Y67         FDCE                                         f  UPD_CLK_DIV/temp_reg[24]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_clk_wiz_0 rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.814     1.973    U0/inst/clk_in1
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.369     0.604 r  U0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.528     1.132    U0/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.161 r  U0/inst/clkout1_buf/O
                         net (fo=79, routed)          0.822     1.983    UPD_CLK_DIV/clk_out1
    SLICE_X33Y67         FDCE                                         r  UPD_CLK_DIV/temp_reg[24]/C
                         clock pessimism             -0.247     1.736    
                         clock uncertainty            0.393     2.129    
    SLICE_X33Y67         FDCE (Remov_fdce_C_CLR)     -0.092     2.037    UPD_CLK_DIV/temp_reg[24]
  -------------------------------------------------------------------
                         required time                         -2.037    
                         arrival time                           3.127    
  -------------------------------------------------------------------
                         slack                                  1.090    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  sys_clk_pin
  To Clock:  sys_clk_pin

Setup :            0  Failing Endpoints,  Worst Slack        0.639ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.654ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.639ns  (required time - arrival time)
  Source:                 UPD/pommeCE_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            APPLE/state_reg[2]_P/PRE
                            (recovery check against rising-edge clock sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            8.000ns  (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        6.882ns  (logic 2.080ns (30.225%)  route 4.802ns (69.775%))
  Logic Levels:           5  (LDCE=1 LUT3=3 LUT6=1)
  Clock Path Skew:        -0.085ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.959ns = ( 12.959 - 8.000 ) 
    Source Clock Delay      (SCD):    5.334ns
    Clock Pessimism Removal (CPR):    0.291ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491     1.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076     3.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101     3.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.666     5.334    UPD/H125MHz_IBUF_BUFG
    SLICE_X18Y31         FDRE                                         r  UPD/pommeCE_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X18Y31         FDRE (Prop_fdre_C_Q)         0.456     5.790 f  UPD/pommeCE_reg/Q
                         net (fo=173, routed)         1.263     7.054    UPD/pommeCE
    SLICE_X38Y30         LUT3 (Prop_lut3_I2_O)        0.124     7.178 r  UPD/state_reg[3]_LDC_i_2/O
                         net (fo=5, routed)           0.588     7.766    APPLE/state_reg[3]_C_0
    SLICE_X38Y30         LDCE (SetClr_ldce_CLR_Q)     0.898     8.664 f  APPLE/state_reg[3]_LDC/Q
                         net (fo=5, routed)           0.827     9.491    APPLE/state_reg[3]_LDC_n_0
    SLICE_X41Y30         LUT3 (Prop_lut3_I1_O)        0.152     9.643 f  APPLE/randInd[10]_i_3/O
                         net (fo=9, routed)           0.495    10.138    APPLE/randInd[10]_i_3_n_0
    SLICE_X41Y30         LUT6 (Prop_lut6_I3_O)        0.326    10.464 r  APPLE/state_reg[3]_LDC_i_3/O
                         net (fo=2, routed)           0.797    11.262    UPD/state1
    SLICE_X38Y30         LUT3 (Prop_lut3_I1_O)        0.124    11.386 f  UPD/state_reg[3]_LDC_i_1/O
                         net (fo=5, routed)           0.830    12.216    APPLE/state_reg[3]_P_0
    SLICE_X39Y30         FDPE                                         f  APPLE/state_reg[2]_P/PRE
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      8.000     8.000 r  
    L16                                               0.000     8.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     8.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421     9.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    11.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    11.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.567    12.959    APPLE/H125MHz_IBUF_BUFG
    SLICE_X39Y30         FDPE                                         r  APPLE/state_reg[2]_P/C
                         clock pessimism              0.291    13.250    
                         clock uncertainty           -0.035    13.214    
    SLICE_X39Y30         FDPE (Recov_fdpe_C_PRE)     -0.359    12.855    APPLE/state_reg[2]_P
  -------------------------------------------------------------------
                         required time                         12.855    
                         arrival time                         -12.216    
  -------------------------------------------------------------------
                         slack                                  0.639    

Slack (MET) :             0.639ns  (required time - arrival time)
  Source:                 UPD/pommeCE_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            APPLE/state_reg[3]_P/PRE
                            (recovery check against rising-edge clock sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            8.000ns  (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        6.882ns  (logic 2.080ns (30.225%)  route 4.802ns (69.775%))
  Logic Levels:           5  (LDCE=1 LUT3=3 LUT6=1)
  Clock Path Skew:        -0.085ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.959ns = ( 12.959 - 8.000 ) 
    Source Clock Delay      (SCD):    5.334ns
    Clock Pessimism Removal (CPR):    0.291ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491     1.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076     3.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101     3.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.666     5.334    UPD/H125MHz_IBUF_BUFG
    SLICE_X18Y31         FDRE                                         r  UPD/pommeCE_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X18Y31         FDRE (Prop_fdre_C_Q)         0.456     5.790 f  UPD/pommeCE_reg/Q
                         net (fo=173, routed)         1.263     7.054    UPD/pommeCE
    SLICE_X38Y30         LUT3 (Prop_lut3_I2_O)        0.124     7.178 r  UPD/state_reg[3]_LDC_i_2/O
                         net (fo=5, routed)           0.588     7.766    APPLE/state_reg[3]_C_0
    SLICE_X38Y30         LDCE (SetClr_ldce_CLR_Q)     0.898     8.664 f  APPLE/state_reg[3]_LDC/Q
                         net (fo=5, routed)           0.827     9.491    APPLE/state_reg[3]_LDC_n_0
    SLICE_X41Y30         LUT3 (Prop_lut3_I1_O)        0.152     9.643 f  APPLE/randInd[10]_i_3/O
                         net (fo=9, routed)           0.495    10.138    APPLE/randInd[10]_i_3_n_0
    SLICE_X41Y30         LUT6 (Prop_lut6_I3_O)        0.326    10.464 r  APPLE/state_reg[3]_LDC_i_3/O
                         net (fo=2, routed)           0.797    11.262    UPD/state1
    SLICE_X38Y30         LUT3 (Prop_lut3_I1_O)        0.124    11.386 f  UPD/state_reg[3]_LDC_i_1/O
                         net (fo=5, routed)           0.830    12.216    APPLE/state_reg[3]_P_0
    SLICE_X39Y30         FDPE                                         f  APPLE/state_reg[3]_P/PRE
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      8.000     8.000 r  
    L16                                               0.000     8.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     8.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421     9.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    11.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    11.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.567    12.959    APPLE/H125MHz_IBUF_BUFG
    SLICE_X39Y30         FDPE                                         r  APPLE/state_reg[3]_P/C
                         clock pessimism              0.291    13.250    
                         clock uncertainty           -0.035    13.214    
    SLICE_X39Y30         FDPE (Recov_fdpe_C_PRE)     -0.359    12.855    APPLE/state_reg[3]_P
  -------------------------------------------------------------------
                         required time                         12.855    
                         arrival time                         -12.216    
  -------------------------------------------------------------------
                         slack                                  0.639    

Slack (MET) :             1.113ns  (required time - arrival time)
  Source:                 UPD/pommeCE_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            APPLE/state_reg[0]_P/PRE
                            (recovery check against rising-edge clock sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            8.000ns  (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        6.409ns  (logic 2.080ns (32.457%)  route 4.329ns (67.543%))
  Logic Levels:           5  (LDCE=1 LUT3=3 LUT6=1)
  Clock Path Skew:        -0.084ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.960ns = ( 12.960 - 8.000 ) 
    Source Clock Delay      (SCD):    5.334ns
    Clock Pessimism Removal (CPR):    0.291ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491     1.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076     3.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101     3.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.666     5.334    UPD/H125MHz_IBUF_BUFG
    SLICE_X18Y31         FDRE                                         r  UPD/pommeCE_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X18Y31         FDRE (Prop_fdre_C_Q)         0.456     5.790 f  UPD/pommeCE_reg/Q
                         net (fo=173, routed)         1.263     7.054    UPD/pommeCE
    SLICE_X38Y30         LUT3 (Prop_lut3_I2_O)        0.124     7.178 r  UPD/state_reg[3]_LDC_i_2/O
                         net (fo=5, routed)           0.588     7.766    APPLE/state_reg[3]_C_0
    SLICE_X38Y30         LDCE (SetClr_ldce_CLR_Q)     0.898     8.664 f  APPLE/state_reg[3]_LDC/Q
                         net (fo=5, routed)           0.827     9.491    APPLE/state_reg[3]_LDC_n_0
    SLICE_X41Y30         LUT3 (Prop_lut3_I1_O)        0.152     9.643 f  APPLE/randInd[10]_i_3/O
                         net (fo=9, routed)           0.495    10.138    APPLE/randInd[10]_i_3_n_0
    SLICE_X41Y30         LUT6 (Prop_lut6_I3_O)        0.326    10.464 r  APPLE/state_reg[3]_LDC_i_3/O
                         net (fo=2, routed)           0.797    11.262    UPD/state1
    SLICE_X38Y30         LUT3 (Prop_lut3_I1_O)        0.124    11.386 f  UPD/state_reg[3]_LDC_i_1/O
                         net (fo=5, routed)           0.357    11.743    APPLE/state_reg[3]_P_0
    SLICE_X41Y30         FDPE                                         f  APPLE/state_reg[0]_P/PRE
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      8.000     8.000 r  
    L16                                               0.000     8.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     8.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421     9.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    11.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    11.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.568    12.960    APPLE/H125MHz_IBUF_BUFG
    SLICE_X41Y30         FDPE                                         r  APPLE/state_reg[0]_P/C
                         clock pessimism              0.291    13.251    
                         clock uncertainty           -0.035    13.215    
    SLICE_X41Y30         FDPE (Recov_fdpe_C_PRE)     -0.359    12.856    APPLE/state_reg[0]_P
  -------------------------------------------------------------------
                         required time                         12.856    
                         arrival time                         -11.743    
  -------------------------------------------------------------------
                         slack                                  1.113    

Slack (MET) :             1.113ns  (required time - arrival time)
  Source:                 UPD/pommeCE_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            APPLE/state_reg[1]_P/PRE
                            (recovery check against rising-edge clock sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            8.000ns  (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        6.409ns  (logic 2.080ns (32.457%)  route 4.329ns (67.543%))
  Logic Levels:           5  (LDCE=1 LUT3=3 LUT6=1)
  Clock Path Skew:        -0.084ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.960ns = ( 12.960 - 8.000 ) 
    Source Clock Delay      (SCD):    5.334ns
    Clock Pessimism Removal (CPR):    0.291ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491     1.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076     3.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101     3.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.666     5.334    UPD/H125MHz_IBUF_BUFG
    SLICE_X18Y31         FDRE                                         r  UPD/pommeCE_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X18Y31         FDRE (Prop_fdre_C_Q)         0.456     5.790 f  UPD/pommeCE_reg/Q
                         net (fo=173, routed)         1.263     7.054    UPD/pommeCE
    SLICE_X38Y30         LUT3 (Prop_lut3_I2_O)        0.124     7.178 r  UPD/state_reg[3]_LDC_i_2/O
                         net (fo=5, routed)           0.588     7.766    APPLE/state_reg[3]_C_0
    SLICE_X38Y30         LDCE (SetClr_ldce_CLR_Q)     0.898     8.664 f  APPLE/state_reg[3]_LDC/Q
                         net (fo=5, routed)           0.827     9.491    APPLE/state_reg[3]_LDC_n_0
    SLICE_X41Y30         LUT3 (Prop_lut3_I1_O)        0.152     9.643 f  APPLE/randInd[10]_i_3/O
                         net (fo=9, routed)           0.495    10.138    APPLE/randInd[10]_i_3_n_0
    SLICE_X41Y30         LUT6 (Prop_lut6_I3_O)        0.326    10.464 r  APPLE/state_reg[3]_LDC_i_3/O
                         net (fo=2, routed)           0.797    11.262    UPD/state1
    SLICE_X38Y30         LUT3 (Prop_lut3_I1_O)        0.124    11.386 f  UPD/state_reg[3]_LDC_i_1/O
                         net (fo=5, routed)           0.357    11.743    APPLE/state_reg[3]_P_0
    SLICE_X41Y30         FDPE                                         f  APPLE/state_reg[1]_P/PRE
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      8.000     8.000 r  
    L16                                               0.000     8.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     8.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421     9.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    11.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    11.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.568    12.960    APPLE/H125MHz_IBUF_BUFG
    SLICE_X41Y30         FDPE                                         r  APPLE/state_reg[1]_P/C
                         clock pessimism              0.291    13.251    
                         clock uncertainty           -0.035    13.215    
    SLICE_X41Y30         FDPE (Recov_fdpe_C_PRE)     -0.359    12.856    APPLE/state_reg[1]_P
  -------------------------------------------------------------------
                         required time                         12.856    
                         arrival time                         -11.743    
  -------------------------------------------------------------------
                         slack                                  1.113    

Slack (MET) :             3.526ns  (required time - arrival time)
  Source:                 UPD/updateIndex_reg[10]/C
                            (rising edge-triggered cell FDCE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            UPD/state_reg[2]/CLR
                            (recovery check against rising-edge clock sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            8.000ns  (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        3.985ns  (logic 0.839ns (21.054%)  route 3.146ns (78.946%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.135ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.877ns = ( 12.877 - 8.000 ) 
    Source Clock Delay      (SCD):    5.403ns
    Clock Pessimism Removal (CPR):    0.391ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491     1.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076     3.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101     3.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.735     5.403    UPD/H125MHz_IBUF_BUFG
    SLICE_X39Y25         FDCE                                         r  UPD/updateIndex_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X39Y25         FDCE (Prop_fdce_C_Q)         0.419     5.822 f  UPD/updateIndex_reg[10]/Q
                         net (fo=5, routed)           0.855     6.677    UPD/updateIndex_reg[10]
    SLICE_X40Y26         LUT4 (Prop_lut4_I2_O)        0.296     6.973 r  UPD/state[4]_i_9/O
                         net (fo=1, routed)           0.870     7.844    UPD/state[4]_i_9_n_0
    SLICE_X41Y26         LUT6 (Prop_lut6_I1_O)        0.124     7.968 f  UPD/state[4]_i_3/O
                         net (fo=17, routed)          1.420     9.388    UPD/clear
    SLICE_X30Y25         FDCE                                         f  UPD/state_reg[2]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      8.000     8.000 r  
    L16                                               0.000     8.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     8.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421     9.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    11.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    11.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.485    12.877    UPD/H125MHz_IBUF_BUFG
    SLICE_X30Y25         FDCE                                         r  UPD/state_reg[2]/C
                         clock pessimism              0.391    13.268    
                         clock uncertainty           -0.035    13.233    
    SLICE_X30Y25         FDCE (Recov_fdce_C_CLR)     -0.319    12.914    UPD/state_reg[2]
  -------------------------------------------------------------------
                         required time                         12.914    
                         arrival time                          -9.388    
  -------------------------------------------------------------------
                         slack                                  3.526    

Slack (MET) :             3.833ns  (required time - arrival time)
  Source:                 UPD/updateIndex_reg[10]/C
                            (rising edge-triggered cell FDCE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            UPD/state_reg[3]/CLR
                            (recovery check against rising-edge clock sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            8.000ns  (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        3.685ns  (logic 0.839ns (22.768%)  route 2.846ns (77.232%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.128ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.884ns = ( 12.884 - 8.000 ) 
    Source Clock Delay      (SCD):    5.403ns
    Clock Pessimism Removal (CPR):    0.391ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491     1.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076     3.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101     3.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.735     5.403    UPD/H125MHz_IBUF_BUFG
    SLICE_X39Y25         FDCE                                         r  UPD/updateIndex_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X39Y25         FDCE (Prop_fdce_C_Q)         0.419     5.822 f  UPD/updateIndex_reg[10]/Q
                         net (fo=5, routed)           0.855     6.677    UPD/updateIndex_reg[10]
    SLICE_X40Y26         LUT4 (Prop_lut4_I2_O)        0.296     6.973 r  UPD/state[4]_i_9/O
                         net (fo=1, routed)           0.870     7.844    UPD/state[4]_i_9_n_0
    SLICE_X41Y26         LUT6 (Prop_lut6_I1_O)        0.124     7.968 f  UPD/state[4]_i_3/O
                         net (fo=17, routed)          1.120     9.088    UPD/clear
    SLICE_X32Y29         FDCE                                         f  UPD/state_reg[3]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      8.000     8.000 r  
    L16                                               0.000     8.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     8.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421     9.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    11.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    11.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.492    12.884    UPD/H125MHz_IBUF_BUFG
    SLICE_X32Y29         FDCE                                         r  UPD/state_reg[3]/C
                         clock pessimism              0.391    13.275    
                         clock uncertainty           -0.035    13.240    
    SLICE_X32Y29         FDCE (Recov_fdce_C_CLR)     -0.319    12.921    UPD/state_reg[3]
  -------------------------------------------------------------------
                         required time                         12.921    
                         arrival time                          -9.088    
  -------------------------------------------------------------------
                         slack                                  3.833    

Slack (MET) :             3.959ns  (required time - arrival time)
  Source:                 UPD/updateIndex_reg[10]/C
                            (rising edge-triggered cell FDCE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            UPD/state_reg[4]/CLR
                            (recovery check against rising-edge clock sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            8.000ns  (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        3.472ns  (logic 0.839ns (24.162%)  route 2.633ns (75.838%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.128ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.884ns = ( 12.884 - 8.000 ) 
    Source Clock Delay      (SCD):    5.403ns
    Clock Pessimism Removal (CPR):    0.391ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491     1.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076     3.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101     3.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.735     5.403    UPD/H125MHz_IBUF_BUFG
    SLICE_X39Y25         FDCE                                         r  UPD/updateIndex_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X39Y25         FDCE (Prop_fdce_C_Q)         0.419     5.822 f  UPD/updateIndex_reg[10]/Q
                         net (fo=5, routed)           0.855     6.677    UPD/updateIndex_reg[10]
    SLICE_X40Y26         LUT4 (Prop_lut4_I2_O)        0.296     6.973 r  UPD/state[4]_i_9/O
                         net (fo=1, routed)           0.870     7.844    UPD/state[4]_i_9_n_0
    SLICE_X41Y26         LUT6 (Prop_lut6_I1_O)        0.124     7.968 f  UPD/state[4]_i_3/O
                         net (fo=17, routed)          0.908     8.876    UPD/clear
    SLICE_X35Y29         FDCE                                         f  UPD/state_reg[4]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      8.000     8.000 r  
    L16                                               0.000     8.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     8.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421     9.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    11.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    11.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.492    12.884    UPD/H125MHz_IBUF_BUFG
    SLICE_X35Y29         FDCE                                         r  UPD/state_reg[4]/C
                         clock pessimism              0.391    13.275    
                         clock uncertainty           -0.035    13.240    
    SLICE_X35Y29         FDCE (Recov_fdce_C_CLR)     -0.405    12.835    UPD/state_reg[4]
  -------------------------------------------------------------------
                         required time                         12.835    
                         arrival time                          -8.876    
  -------------------------------------------------------------------
                         slack                                  3.959    

Slack (MET) :             4.024ns  (required time - arrival time)
  Source:                 UPD/updateIndex_reg[10]/C
                            (rising edge-triggered cell FDCE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            UPD/state_reg[1]/CLR
                            (recovery check against rising-edge clock sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            8.000ns  (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        3.492ns  (logic 0.839ns (24.024%)  route 2.653ns (75.976%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.129ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.883ns = ( 12.883 - 8.000 ) 
    Source Clock Delay      (SCD):    5.403ns
    Clock Pessimism Removal (CPR):    0.391ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491     1.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076     3.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101     3.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.735     5.403    UPD/H125MHz_IBUF_BUFG
    SLICE_X39Y25         FDCE                                         r  UPD/updateIndex_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X39Y25         FDCE (Prop_fdce_C_Q)         0.419     5.822 f  UPD/updateIndex_reg[10]/Q
                         net (fo=5, routed)           0.855     6.677    UPD/updateIndex_reg[10]
    SLICE_X40Y26         LUT4 (Prop_lut4_I2_O)        0.296     6.973 r  UPD/state[4]_i_9/O
                         net (fo=1, routed)           0.870     7.844    UPD/state[4]_i_9_n_0
    SLICE_X41Y26         LUT6 (Prop_lut6_I1_O)        0.124     7.968 f  UPD/state[4]_i_3/O
                         net (fo=17, routed)          0.928     8.896    UPD/clear
    SLICE_X32Y28         FDCE                                         f  UPD/state_reg[1]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      8.000     8.000 r  
    L16                                               0.000     8.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     8.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421     9.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    11.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    11.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.491    12.883    UPD/H125MHz_IBUF_BUFG
    SLICE_X32Y28         FDCE                                         r  UPD/state_reg[1]/C
                         clock pessimism              0.391    13.274    
                         clock uncertainty           -0.035    13.239    
    SLICE_X32Y28         FDCE (Recov_fdce_C_CLR)     -0.319    12.920    UPD/state_reg[1]
  -------------------------------------------------------------------
                         required time                         12.920    
                         arrival time                          -8.896    
  -------------------------------------------------------------------
                         slack                                  4.024    

Slack (MET) :             4.097ns  (required time - arrival time)
  Source:                 UPD/updateIndex_reg[10]/C
                            (rising edge-triggered cell FDCE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            UPD/state_reg[0]/CLR
                            (recovery check against rising-edge clock sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            8.000ns  (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        3.334ns  (logic 0.839ns (25.165%)  route 2.495ns (74.835%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.129ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.883ns = ( 12.883 - 8.000 ) 
    Source Clock Delay      (SCD):    5.403ns
    Clock Pessimism Removal (CPR):    0.391ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491     1.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076     3.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101     3.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.735     5.403    UPD/H125MHz_IBUF_BUFG
    SLICE_X39Y25         FDCE                                         r  UPD/updateIndex_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X39Y25         FDCE (Prop_fdce_C_Q)         0.419     5.822 f  UPD/updateIndex_reg[10]/Q
                         net (fo=5, routed)           0.855     6.677    UPD/updateIndex_reg[10]
    SLICE_X40Y26         LUT4 (Prop_lut4_I2_O)        0.296     6.973 r  UPD/state[4]_i_9/O
                         net (fo=1, routed)           0.870     7.844    UPD/state[4]_i_9_n_0
    SLICE_X41Y26         LUT6 (Prop_lut6_I1_O)        0.124     7.968 f  UPD/state[4]_i_3/O
                         net (fo=17, routed)          0.770     8.737    UPD/clear
    SLICE_X35Y28         FDCE                                         f  UPD/state_reg[0]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      8.000     8.000 r  
    L16                                               0.000     8.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     8.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421     9.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    11.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    11.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.491    12.883    UPD/H125MHz_IBUF_BUFG
    SLICE_X35Y28         FDCE                                         r  UPD/state_reg[0]/C
                         clock pessimism              0.391    13.274    
                         clock uncertainty           -0.035    13.239    
    SLICE_X35Y28         FDCE (Recov_fdce_C_CLR)     -0.405    12.834    UPD/state_reg[0]
  -------------------------------------------------------------------
                         required time                         12.834    
                         arrival time                          -8.737    
  -------------------------------------------------------------------
                         slack                                  4.097    

Slack (MET) :             4.207ns  (required time - arrival time)
  Source:                 UPD/updateIndex_reg[10]/C
                            (rising edge-triggered cell FDCE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            UPD/updateIndex_reg[7]/CLR
                            (recovery check against rising-edge clock sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            8.000ns  (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        3.330ns  (logic 0.839ns (25.193%)  route 2.491ns (74.807%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.022ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.953ns = ( 12.953 - 8.000 ) 
    Source Clock Delay      (SCD):    5.403ns
    Clock Pessimism Removal (CPR):    0.428ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.491     1.491 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           2.076     3.567    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.101     3.668 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.735     5.403    UPD/H125MHz_IBUF_BUFG
    SLICE_X39Y25         FDCE                                         r  UPD/updateIndex_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X39Y25         FDCE (Prop_fdce_C_Q)         0.419     5.822 f  UPD/updateIndex_reg[10]/Q
                         net (fo=5, routed)           0.855     6.677    UPD/updateIndex_reg[10]
    SLICE_X40Y26         LUT4 (Prop_lut4_I2_O)        0.296     6.973 r  UPD/state[4]_i_9/O
                         net (fo=1, routed)           0.870     7.844    UPD/state[4]_i_9_n_0
    SLICE_X41Y26         LUT6 (Prop_lut6_I1_O)        0.124     7.968 f  UPD/state[4]_i_3/O
                         net (fo=17, routed)          0.766     8.734    UPD/clear
    SLICE_X37Y25         FDCE                                         f  UPD/updateIndex_reg[7]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      8.000     8.000 r  
    L16                                               0.000     8.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     8.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         1.421     9.421 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           1.880    11.301    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    11.392 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         1.561    12.953    UPD/H125MHz_IBUF_BUFG
    SLICE_X37Y25         FDCE                                         r  UPD/updateIndex_reg[7]/C
                         clock pessimism              0.428    13.381    
                         clock uncertainty           -0.035    13.346    
    SLICE_X37Y25         FDCE (Recov_fdce_C_CLR)     -0.405    12.941    UPD/updateIndex_reg[7]
  -------------------------------------------------------------------
                         required time                         12.941    
                         arrival time                          -8.734    
  -------------------------------------------------------------------
                         slack                                  4.207    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.654ns  (arrival time - required time)
  Source:                 UPD/updateIndex_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            UPD/updateIndex_reg[1]/CLR
                            (removal check against rising-edge clock sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        0.575ns  (logic 0.186ns (32.338%)  route 0.389ns (67.662%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.013ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.007ns
    Source Clock Delay      (SCD):    1.494ns
    Clock Pessimism Removal (CPR):    0.500ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.582     1.494    UPD/H125MHz_IBUF_BUFG
    SLICE_X41Y26         FDCE                                         r  UPD/updateIndex_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y26         FDCE (Prop_fdce_C_Q)         0.141     1.635 r  UPD/updateIndex_reg[3]/Q
                         net (fo=9, routed)           0.243     1.878    UPD/updateIndex_reg[3]
    SLICE_X41Y26         LUT6 (Prop_lut6_I4_O)        0.045     1.923 f  UPD/state[4]_i_3/O
                         net (fo=17, routed)          0.146     2.069    UPD/clear
    SLICE_X40Y26         FDCE                                         f  UPD/updateIndex_reg[1]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.848     2.007    UPD/H125MHz_IBUF_BUFG
    SLICE_X40Y26         FDCE                                         r  UPD/updateIndex_reg[1]/C
                         clock pessimism             -0.500     1.507    
    SLICE_X40Y26         FDCE (Remov_fdce_C_CLR)     -0.092     1.415    UPD/updateIndex_reg[1]
  -------------------------------------------------------------------
                         required time                         -1.415    
                         arrival time                           2.069    
  -------------------------------------------------------------------
                         slack                                  0.654    

Slack (MET) :             0.663ns  (arrival time - required time)
  Source:                 UPD/updateIndex_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            UPD/updateIndex_reg[2]/CLR
                            (removal check against rising-edge clock sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        0.571ns  (logic 0.186ns (32.584%)  route 0.385ns (67.416%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.007ns
    Source Clock Delay      (SCD):    1.494ns
    Clock Pessimism Removal (CPR):    0.513ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.582     1.494    UPD/H125MHz_IBUF_BUFG
    SLICE_X41Y26         FDCE                                         r  UPD/updateIndex_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y26         FDCE (Prop_fdce_C_Q)         0.141     1.635 r  UPD/updateIndex_reg[3]/Q
                         net (fo=9, routed)           0.243     1.878    UPD/updateIndex_reg[3]
    SLICE_X41Y26         LUT6 (Prop_lut6_I4_O)        0.045     1.923 f  UPD/state[4]_i_3/O
                         net (fo=17, routed)          0.142     2.065    UPD/clear
    SLICE_X41Y26         FDCE                                         f  UPD/updateIndex_reg[2]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.848     2.007    UPD/H125MHz_IBUF_BUFG
    SLICE_X41Y26         FDCE                                         r  UPD/updateIndex_reg[2]/C
                         clock pessimism             -0.513     1.494    
    SLICE_X41Y26         FDCE (Remov_fdce_C_CLR)     -0.092     1.402    UPD/updateIndex_reg[2]
  -------------------------------------------------------------------
                         required time                         -1.402    
                         arrival time                           2.065    
  -------------------------------------------------------------------
                         slack                                  0.663    

Slack (MET) :             0.663ns  (arrival time - required time)
  Source:                 UPD/updateIndex_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            UPD/updateIndex_reg[3]/CLR
                            (removal check against rising-edge clock sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        0.571ns  (logic 0.186ns (32.584%)  route 0.385ns (67.416%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.007ns
    Source Clock Delay      (SCD):    1.494ns
    Clock Pessimism Removal (CPR):    0.513ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.582     1.494    UPD/H125MHz_IBUF_BUFG
    SLICE_X41Y26         FDCE                                         r  UPD/updateIndex_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y26         FDCE (Prop_fdce_C_Q)         0.141     1.635 r  UPD/updateIndex_reg[3]/Q
                         net (fo=9, routed)           0.243     1.878    UPD/updateIndex_reg[3]
    SLICE_X41Y26         LUT6 (Prop_lut6_I4_O)        0.045     1.923 f  UPD/state[4]_i_3/O
                         net (fo=17, routed)          0.142     2.065    UPD/clear
    SLICE_X41Y26         FDCE                                         f  UPD/updateIndex_reg[3]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.848     2.007    UPD/H125MHz_IBUF_BUFG
    SLICE_X41Y26         FDCE                                         r  UPD/updateIndex_reg[3]/C
                         clock pessimism             -0.513     1.494    
    SLICE_X41Y26         FDCE (Remov_fdce_C_CLR)     -0.092     1.402    UPD/updateIndex_reg[3]
  -------------------------------------------------------------------
                         required time                         -1.402    
                         arrival time                           2.065    
  -------------------------------------------------------------------
                         slack                                  0.663    

Slack (MET) :             0.663ns  (arrival time - required time)
  Source:                 UPD/updateIndex_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            UPD/updateIndex_reg[5]/CLR
                            (removal check against rising-edge clock sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        0.571ns  (logic 0.186ns (32.584%)  route 0.385ns (67.416%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.007ns
    Source Clock Delay      (SCD):    1.494ns
    Clock Pessimism Removal (CPR):    0.513ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.582     1.494    UPD/H125MHz_IBUF_BUFG
    SLICE_X41Y26         FDCE                                         r  UPD/updateIndex_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y26         FDCE (Prop_fdce_C_Q)         0.141     1.635 r  UPD/updateIndex_reg[3]/Q
                         net (fo=9, routed)           0.243     1.878    UPD/updateIndex_reg[3]
    SLICE_X41Y26         LUT6 (Prop_lut6_I4_O)        0.045     1.923 f  UPD/state[4]_i_3/O
                         net (fo=17, routed)          0.142     2.065    UPD/clear
    SLICE_X41Y26         FDCE                                         f  UPD/updateIndex_reg[5]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.848     2.007    UPD/H125MHz_IBUF_BUFG
    SLICE_X41Y26         FDCE                                         r  UPD/updateIndex_reg[5]/C
                         clock pessimism             -0.513     1.494    
    SLICE_X41Y26         FDCE (Remov_fdce_C_CLR)     -0.092     1.402    UPD/updateIndex_reg[5]
  -------------------------------------------------------------------
                         required time                         -1.402    
                         arrival time                           2.065    
  -------------------------------------------------------------------
                         slack                                  0.663    

Slack (MET) :             0.691ns  (arrival time - required time)
  Source:                 UPD/resetPomme_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            APPLE/state_reg[0]_C/CLR
                            (removal check against rising-edge clock sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        0.635ns  (logic 0.186ns (29.308%)  route 0.449ns (70.692%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.036ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.012ns
    Source Clock Delay      (SCD):    1.496ns
    Clock Pessimism Removal (CPR):    0.480ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.584     1.496    UPD/H125MHz_IBUF_BUFG
    SLICE_X37Y30         FDRE                                         r  UPD/resetPomme_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X37Y30         FDRE (Prop_fdre_C_Q)         0.141     1.637 r  UPD/resetPomme_reg/Q
                         net (fo=7, routed)           0.260     1.897    UPD/pommeReset
    SLICE_X38Y30         LUT3 (Prop_lut3_I0_O)        0.045     1.942 f  UPD/state_reg[3]_LDC_i_2/O
                         net (fo=5, routed)           0.188     2.130    APPLE/state_reg[3]_C_0
    SLICE_X40Y30         FDCE                                         f  APPLE/state_reg[0]_C/CLR
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.853     2.012    APPLE/H125MHz_IBUF_BUFG
    SLICE_X40Y30         FDCE                                         r  APPLE/state_reg[0]_C/C
                         clock pessimism             -0.480     1.532    
    SLICE_X40Y30         FDCE (Remov_fdce_C_CLR)     -0.092     1.440    APPLE/state_reg[0]_C
  -------------------------------------------------------------------
                         required time                         -1.440    
                         arrival time                           2.130    
  -------------------------------------------------------------------
                         slack                                  0.691    

Slack (MET) :             0.691ns  (arrival time - required time)
  Source:                 UPD/resetPomme_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            APPLE/state_reg[1]_C/CLR
                            (removal check against rising-edge clock sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        0.635ns  (logic 0.186ns (29.308%)  route 0.449ns (70.692%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.036ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.012ns
    Source Clock Delay      (SCD):    1.496ns
    Clock Pessimism Removal (CPR):    0.480ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.584     1.496    UPD/H125MHz_IBUF_BUFG
    SLICE_X37Y30         FDRE                                         r  UPD/resetPomme_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X37Y30         FDRE (Prop_fdre_C_Q)         0.141     1.637 r  UPD/resetPomme_reg/Q
                         net (fo=7, routed)           0.260     1.897    UPD/pommeReset
    SLICE_X38Y30         LUT3 (Prop_lut3_I0_O)        0.045     1.942 f  UPD/state_reg[3]_LDC_i_2/O
                         net (fo=5, routed)           0.188     2.130    APPLE/state_reg[3]_C_0
    SLICE_X40Y30         FDCE                                         f  APPLE/state_reg[1]_C/CLR
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.853     2.012    APPLE/H125MHz_IBUF_BUFG
    SLICE_X40Y30         FDCE                                         r  APPLE/state_reg[1]_C/C
                         clock pessimism             -0.480     1.532    
    SLICE_X40Y30         FDCE (Remov_fdce_C_CLR)     -0.092     1.440    APPLE/state_reg[1]_C
  -------------------------------------------------------------------
                         required time                         -1.440    
                         arrival time                           2.130    
  -------------------------------------------------------------------
                         slack                                  0.691    

Slack (MET) :             0.691ns  (arrival time - required time)
  Source:                 UPD/resetPomme_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            APPLE/state_reg[2]_C/CLR
                            (removal check against rising-edge clock sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        0.635ns  (logic 0.186ns (29.308%)  route 0.449ns (70.692%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.036ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.012ns
    Source Clock Delay      (SCD):    1.496ns
    Clock Pessimism Removal (CPR):    0.480ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.584     1.496    UPD/H125MHz_IBUF_BUFG
    SLICE_X37Y30         FDRE                                         r  UPD/resetPomme_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X37Y30         FDRE (Prop_fdre_C_Q)         0.141     1.637 r  UPD/resetPomme_reg/Q
                         net (fo=7, routed)           0.260     1.897    UPD/pommeReset
    SLICE_X38Y30         LUT3 (Prop_lut3_I0_O)        0.045     1.942 f  UPD/state_reg[3]_LDC_i_2/O
                         net (fo=5, routed)           0.188     2.130    APPLE/state_reg[3]_C_0
    SLICE_X40Y30         FDCE                                         f  APPLE/state_reg[2]_C/CLR
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.853     2.012    APPLE/H125MHz_IBUF_BUFG
    SLICE_X40Y30         FDCE                                         r  APPLE/state_reg[2]_C/C
                         clock pessimism             -0.480     1.532    
    SLICE_X40Y30         FDCE (Remov_fdce_C_CLR)     -0.092     1.440    APPLE/state_reg[2]_C
  -------------------------------------------------------------------
                         required time                         -1.440    
                         arrival time                           2.130    
  -------------------------------------------------------------------
                         slack                                  0.691    

Slack (MET) :             0.691ns  (arrival time - required time)
  Source:                 UPD/resetPomme_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            APPLE/state_reg[3]_C/CLR
                            (removal check against rising-edge clock sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        0.635ns  (logic 0.186ns (29.308%)  route 0.449ns (70.692%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.036ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.012ns
    Source Clock Delay      (SCD):    1.496ns
    Clock Pessimism Removal (CPR):    0.480ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.584     1.496    UPD/H125MHz_IBUF_BUFG
    SLICE_X37Y30         FDRE                                         r  UPD/resetPomme_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X37Y30         FDRE (Prop_fdre_C_Q)         0.141     1.637 r  UPD/resetPomme_reg/Q
                         net (fo=7, routed)           0.260     1.897    UPD/pommeReset
    SLICE_X38Y30         LUT3 (Prop_lut3_I0_O)        0.045     1.942 f  UPD/state_reg[3]_LDC_i_2/O
                         net (fo=5, routed)           0.188     2.130    APPLE/state_reg[3]_C_0
    SLICE_X40Y30         FDCE                                         f  APPLE/state_reg[3]_C/CLR
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.853     2.012    APPLE/H125MHz_IBUF_BUFG
    SLICE_X40Y30         FDCE                                         r  APPLE/state_reg[3]_C/C
                         clock pessimism             -0.480     1.532    
    SLICE_X40Y30         FDCE (Remov_fdce_C_CLR)     -0.092     1.440    APPLE/state_reg[3]_C
  -------------------------------------------------------------------
                         required time                         -1.440    
                         arrival time                           2.130    
  -------------------------------------------------------------------
                         slack                                  0.691    

Slack (MET) :             0.768ns  (arrival time - required time)
  Source:                 UPD/updateIndex_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            UPD/updateIndex_reg[4]/CLR
                            (removal check against rising-edge clock sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        0.731ns  (logic 0.186ns (25.434%)  route 0.545ns (74.566%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.030ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.004ns
    Source Clock Delay      (SCD):    1.494ns
    Clock Pessimism Removal (CPR):    0.480ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.582     1.494    UPD/H125MHz_IBUF_BUFG
    SLICE_X41Y26         FDCE                                         r  UPD/updateIndex_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y26         FDCE (Prop_fdce_C_Q)         0.141     1.635 r  UPD/updateIndex_reg[3]/Q
                         net (fo=9, routed)           0.243     1.878    UPD/updateIndex_reg[3]
    SLICE_X41Y26         LUT6 (Prop_lut6_I4_O)        0.045     1.923 f  UPD/state[4]_i_3/O
                         net (fo=17, routed)          0.302     2.225    UPD/clear
    SLICE_X38Y25         FDCE                                         f  UPD/updateIndex_reg[4]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.845     2.004    UPD/H125MHz_IBUF_BUFG
    SLICE_X38Y25         FDCE                                         r  UPD/updateIndex_reg[4]/C
                         clock pessimism             -0.480     1.524    
    SLICE_X38Y25         FDCE (Remov_fdce_C_CLR)     -0.067     1.457    UPD/updateIndex_reg[4]
  -------------------------------------------------------------------
                         required time                         -1.457    
                         arrival time                           2.225    
  -------------------------------------------------------------------
                         slack                                  0.768    

Slack (MET) :             0.768ns  (arrival time - required time)
  Source:                 UPD/updateIndex_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            UPD/updateIndex_reg[6]/CLR
                            (removal check against rising-edge clock sys_clk_pin  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
  Data Path Delay:        0.731ns  (logic 0.186ns (25.434%)  route 0.545ns (74.566%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.030ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.004ns
    Source Clock Delay      (SCD):    1.494ns
    Clock Pessimism Removal (CPR):    0.480ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.259     0.259 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.627     0.886    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     0.912 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.582     1.494    UPD/H125MHz_IBUF_BUFG
    SLICE_X41Y26         FDCE                                         r  UPD/updateIndex_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y26         FDCE (Prop_fdce_C_Q)         0.141     1.635 r  UPD/updateIndex_reg[3]/Q
                         net (fo=9, routed)           0.243     1.878    UPD/updateIndex_reg[3]
    SLICE_X41Y26         LUT6 (Prop_lut6_I4_O)        0.045     1.923 f  UPD/state[4]_i_3/O
                         net (fo=17, routed)          0.302     2.225    UPD/clear
    SLICE_X38Y25         FDCE                                         f  UPD/updateIndex_reg[6]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_pin rise edge)
                                                      0.000     0.000 r  
    L16                                               0.000     0.000 r  H125MHz (IN)
                         net (fo=0)                   0.000     0.000    H125MHz
    L16                  IBUF (Prop_ibuf_I_O)         0.447     0.447 r  H125MHz_IBUF_inst/O
                         net (fo=1, routed)           0.683     1.130    H125MHz_IBUF
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     1.159 r  H125MHz_IBUF_BUFG_inst/O
                         net (fo=327, routed)         0.845     2.004    UPD/H125MHz_IBUF_BUFG
    SLICE_X38Y25         FDCE                                         r  UPD/updateIndex_reg[6]/C
                         clock pessimism             -0.480     1.524    
    SLICE_X38Y25         FDCE (Remov_fdce_C_CLR)     -0.067     1.457    UPD/updateIndex_reg[6]
  -------------------------------------------------------------------
                         required time                         -1.457    
                         arrival time                           2.225    
  -------------------------------------------------------------------
                         slack                                  0.768    





