
*** Running vivado
    with args -log VGA_top.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace


****** Vivado v2018.3 (64-bit)
  **** SW Build 2405991 on Thu Dec  6 23:38:27 MST 2018
  **** IP Build 2404404 on Fri Dec  7 01:43:56 MST 2018
    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

source VGA_top.tcl -notrace
Command: link_design -top VGA_top -part xc7z010clg400-1
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Project 1-454] Reading design checkpoint 'c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0.dcp' for cell 'U0'
INFO: [Netlist 29-17] Analyzing 314 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2018.3
INFO: [Device 21-403] Loading part xc7z010clg400-1
INFO: [Project 1-570] Preparing netlist for logic optimization
WARNING: [Opt 31-35] Removing redundant IBUF, U0/inst/clkin1_ibufg, from the path connected to top-level port: H125MHz 
Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'U0/clk_in1' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0_board.xdc] for cell 'U0/inst'
Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0_board.xdc] for cell 'U0/inst'
Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0.xdc] for cell 'U0/inst'
INFO: [Timing 38-35] Done setting XDC timing constraints. [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0.xdc:57]
INFO: [Timing 38-2] Deriving generated clocks [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0.xdc:57]
get_clocks: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1251.785 ; gain = 552.953
Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0.xdc] for cell 'U0/inst'
Parsing XDC File [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/ZYBO_Master.xdc]
Finished Parsing XDC File [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/ZYBO_Master.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1251.785 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

10 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:25 . Memory (MB): peak = 1251.785 ; gain = 888.395
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.501 . Memory (MB): peak = 1251.785 ; gain = 0.000

Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 19f3e8d5f

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.092 . Memory (MB): peak = 1265.977 ; gain = 14.191

Starting Logic Optimization Task

Phase 1 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: c8a6b5ae

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.096 . Memory (MB): peak = 1346.285 ; gain = 0.000
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 

Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 2 Constant propagation | Checksum: 1409f9166

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.123 . Memory (MB): peak = 1346.285 ; gain = 0.000
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells

Phase 3 Sweep
Phase 3 Sweep | Checksum: 1b7440179

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.178 . Memory (MB): peak = 1346.285 ; gain = 0.000
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
INFO: [Opt 31-1021] In phase Sweep, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 

Phase 4 BUFG optimization
INFO: [Opt 31-194] Inserted BUFG U0/inst/clk_out1_clk_wiz_1_BUFG_inst to drive 0 load(s) on clock net U0/inst/clk_out1_clk_wiz_1_BUFG
INFO: [Opt 31-194] Inserted BUFG H125MHz_IBUF_BUFG_inst to drive 182 load(s) on clock net H125MHz_IBUF_BUFG
INFO: [Opt 31-193] Inserted 2 BUFG(s) on clock nets
Phase 4 BUFG optimization | Checksum: cecab300

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.259 . Memory (MB): peak = 1346.285 ; gain = 0.000
INFO: [Opt 31-662] Phase BUFG optimization created 1 cells of which 1 are BUFGs and removed 0 cells.

Phase 5 Shift Register Optimization
Phase 5 Shift Register Optimization | Checksum: 193828ea0

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.412 . Memory (MB): peak = 1346.285 ; gain = 0.000
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells

Phase 6 Post Processing Netlist
Phase 6 Post Processing Netlist | Checksum: 16ceef5f4

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.421 . Memory (MB): peak = 1346.285 ; gain = 0.000
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Opt_design Change Summary
=========================


-------------------------------------------------------------------------------------------------------------------------
|  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
-------------------------------------------------------------------------------------------------------------------------
|  Retarget                     |               0  |               0  |                                              1  |
|  Constant propagation         |               0  |               0  |                                              0  |
|  Sweep                        |               0  |               0  |                                              1  |
|  BUFG optimization            |               1  |               0  |                                              0  |
|  Shift Register Optimization  |               0  |               0  |                                              0  |
|  Post Processing Netlist      |               0  |               0  |                                              0  |
-------------------------------------------------------------------------------------------------------------------------



Starting Connectivity Check Task

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1346.285 ; gain = 0.000
Ending Logic Optimization Task | Checksum: 20356351c

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.429 . Memory (MB): peak = 1346.285 ; gain = 0.000

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-4.133 | TNS=-46.099 |
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
INFO: [Pwropt 34-9] Applying IDT optimizations ...
INFO: [Pwropt 34-10] Applying ODC optimizations ...


Starting PowerOpt Patch Enables Task
INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 27 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
INFO: [Pwropt 34-201] Structural ODC has moved 16 WE to EN ports
Number of BRAM Ports augmented: 0 newly gated: 25 Total Ports: 54
Number of Flops added for Enable Generation: 2

Ending PowerOpt Patch Enables Task | Checksum: 215f1437d

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.085 . Memory (MB): peak = 1500.016 ; gain = 0.000
Ending Power Optimization Task | Checksum: 215f1437d

Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1500.016 ; gain = 153.730

Starting Final Cleanup Task

Starting Logic Optimization Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Opt 31-194] Inserted BUFG U0/inst/clk_out1_clk_wiz_1_BUFG_inst to drive 0 load(s) on clock net U0/inst/clk_out1_clk_wiz_1_BUFG
INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets
Ending Logic Optimization Task | Checksum: 2182f781c

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.228 . Memory (MB): peak = 1500.016 ; gain = 0.000
Ending Final Cleanup Task | Checksum: 2182f781c

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.967 . Memory (MB): peak = 1500.016 ; gain = 0.000

Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1500.016 ; gain = 0.000
Ending Netlist Obfuscation Task | Checksum: 2182f781c

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1500.016 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
40 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1500.016 ; gain = 0.000
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.035 . Memory (MB): peak = 1500.016 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1500.016 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/impl_1/VGA_top_opt.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx
Command: report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/impl_1/VGA_top_drc_opted.rpt.
report_drc completed successfully
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.

Starting Placer Task
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs

Phase 1 Placer Initialization

Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1500.016 ; gain = 0.000
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 131936915

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1500.016 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1500.016 ; gain = 0.000

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: d8624408

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.459 . Memory (MB): peak = 1500.016 ; gain = 0.000

Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 1315496dd

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.837 . Memory (MB): peak = 1500.016 ; gain = 0.000

Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 1315496dd

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.840 . Memory (MB): peak = 1500.016 ; gain = 0.000
Phase 1 Placer Initialization | Checksum: 1315496dd

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.843 . Memory (MB): peak = 1500.016 ; gain = 0.000

Phase 2 Global Placement

Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 1a8bfe1e0

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.991 . Memory (MB): peak = 1500.016 ; gain = 0.000

Phase 2.2 Physical Synthesis In Placer
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-117] Net SNAKE/listRefs[8][0] could not be optimized because driver SNAKE/mem_reg_3_i_4 could not be replicated
INFO: [Physopt 32-117] Net SNAKE/listRefs[6][2] could not be optimized because driver SNAKE/mem_reg_1_i_4 could not be replicated
INFO: [Physopt 32-68] No nets found for critical-cell optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design.
INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-949] No candidate nets found for HD net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1500.016 ; gain = 0.000

Summary of Physical Synthesis Optimizations
============================================


----------------------------------------------------------------------------------------------------------------------------------------
|  Optimization                  |  Added Cells  |  Removed Cells  |  Optimized Cells/Nets  |  Dont Touch  |  Iterations  |  Elapsed   |
----------------------------------------------------------------------------------------------------------------------------------------
|  Very High Fanout              |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Critical Cell                 |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  DSP Register                  |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Shift Register                |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  BRAM Register                 |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  HD Interface Net Replication  |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Total                         |            0  |              0  |                     0  |           0  |           6  |  00:00:00  |
----------------------------------------------------------------------------------------------------------------------------------------


Phase 2.2 Physical Synthesis In Placer | Checksum: aaf1c87e

Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1500.016 ; gain = 0.000
Phase 2 Global Placement | Checksum: 17a0bd3eb

Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1500.016 ; gain = 0.000

Phase 3 Detail Placement

Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 17a0bd3eb

Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1500.016 ; gain = 0.000

Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 18c86a722

Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1500.016 ; gain = 0.000

Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 19f5ea993

Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1500.016 ; gain = 0.000

Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 1bfb8a901

Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1500.016 ; gain = 0.000

Phase 3.5 Fast Optimization
Phase 3.5 Fast Optimization | Checksum: 108c906c7

Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 1500.016 ; gain = 0.000

Phase 3.6 Small Shape Detail Placement
Phase 3.6 Small Shape Detail Placement | Checksum: 1f5ba145a

Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 1500.016 ; gain = 0.000

Phase 3.7 Re-assign LUT pins
Phase 3.7 Re-assign LUT pins | Checksum: 1ca5326f1

Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 1500.016 ; gain = 0.000

Phase 3.8 Pipeline Register Optimization
Phase 3.8 Pipeline Register Optimization | Checksum: 1aa2d2687

Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 1500.016 ; gain = 0.000

Phase 3.9 Fast Optimization
Phase 3.9 Fast Optimization | Checksum: a4f5789a

Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 1500.016 ; gain = 0.000
Phase 3 Detail Placement | Checksum: a4f5789a

Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 1500.016 ; gain = 0.000

Phase 4 Post Placement Optimization and Clean-Up

Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.

Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 100368e26

Phase 4.1.1.1 BUFG Insertion
INFO: [Place 46-46] BUFG insertion identified 0 candidate nets, 0 success, 0 bufg driver replicated, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason
Phase 4.1.1.1 BUFG Insertion | Checksum: 100368e26

Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 1500.016 ; gain = 0.000
INFO: [Place 30-746] Post Placement Timing Summary WNS=-3.374. For the most accurate timing information please run report_timing.
Phase 4.1.1 Post Placement Optimization | Checksum: be8bba9e

Time (s): cpu = 00:00:18 ; elapsed = 00:00:16 . Memory (MB): peak = 1500.016 ; gain = 0.000
Phase 4.1 Post Commit Optimization | Checksum: be8bba9e

Time (s): cpu = 00:00:18 ; elapsed = 00:00:17 . Memory (MB): peak = 1500.016 ; gain = 0.000

Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: be8bba9e

Time (s): cpu = 00:00:18 ; elapsed = 00:00:17 . Memory (MB): peak = 1500.016 ; gain = 0.000

Phase 4.3 Placer Reporting
Phase 4.3 Placer Reporting | Checksum: be8bba9e

Time (s): cpu = 00:00:18 ; elapsed = 00:00:17 . Memory (MB): peak = 1500.016 ; gain = 0.000

Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1500.016 ; gain = 0.000
Phase 4.4 Final Placement Cleanup | Checksum: 540ff3bc

Time (s): cpu = 00:00:18 ; elapsed = 00:00:17 . Memory (MB): peak = 1500.016 ; gain = 0.000
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 540ff3bc

Time (s): cpu = 00:00:18 ; elapsed = 00:00:17 . Memory (MB): peak = 1500.016 ; gain = 0.000
Ending Placer Task | Checksum: 531de2ac

Time (s): cpu = 00:00:18 ; elapsed = 00:00:17 . Memory (MB): peak = 1500.016 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
75 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:17 . Memory (MB): peak = 1500.016 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1500.016 ; gain = 0.000
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1500.016 ; gain = 0.000
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.200 . Memory (MB): peak = 1500.016 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/impl_1/VGA_top_placed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_io -file VGA_top_io_placed.rpt
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.040 . Memory (MB): peak = 1500.016 ; gain = 0.000
INFO: [runtcl-4] Executing : report_utilization -file VGA_top_utilization_placed.rpt -pb VGA_top_utilization_placed.pb
INFO: [runtcl-4] Executing : report_control_sets -verbose -file VGA_top_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1500.016 ; gain = 0.000
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
Checksum: PlaceDB: 3ad47cdf ConstDB: 0 ShapeSum: 184965cd RouteDB: 0

Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: 13e412dc8

Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1500.016 ; gain = 0.000
Post Restoration Checksum: NetGraph: 58741a68 NumContArr: e5cd1360 Constraints: 0 Timing: 0

Phase 2 Router Initialization

Phase 2.1 Create Timer
Phase 2.1 Create Timer | Checksum: 13e412dc8

Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1500.016 ; gain = 0.000

Phase 2.2 Fix Topology Constraints
Phase 2.2 Fix Topology Constraints | Checksum: 13e412dc8

Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1500.016 ; gain = 0.000

Phase 2.3 Pre Route Cleanup
Phase 2.3 Pre Route Cleanup | Checksum: 13e412dc8

Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1500.016 ; gain = 0.000
 Number of Nodes with overlaps = 0

Phase 2.4 Update Timing
Phase 2.4 Update Timing | Checksum: 1195a0f5b

Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1500.016 ; gain = 0.000
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-3.513 | TNS=-50.092| WHS=-1.636 | THS=-51.724|

Phase 2 Router Initialization | Checksum: 12ae7c807

Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1500.016 ; gain = 0.000

Phase 3 Initial Routing
Phase 3 Initial Routing | Checksum: 1b62d99da

Time (s): cpu = 00:00:24 ; elapsed = 00:00:17 . Memory (MB): peak = 1546.250 ; gain = 46.234

Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0
 Number of Nodes with overlaps = 954
 Number of Nodes with overlaps = 235
 Number of Nodes with overlaps = 66
 Number of Nodes with overlaps = 42
 Number of Nodes with overlaps = 19
 Number of Nodes with overlaps = 16
 Number of Nodes with overlaps = 15
 Number of Nodes with overlaps = 7
 Number of Nodes with overlaps = 1
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-5.639 | TNS=-90.744| WHS=N/A    | THS=N/A    |

Phase 4.1 Global Iteration 0 | Checksum: 1a754acba

Time (s): cpu = 00:01:24 ; elapsed = 00:01:06 . Memory (MB): peak = 1596.598 ; gain = 96.582

Phase 4.2 Global Iteration 1
 Number of Nodes with overlaps = 146
 Number of Nodes with overlaps = 24
 Number of Nodes with overlaps = 9
 Number of Nodes with overlaps = 8
 Number of Nodes with overlaps = 8
 Number of Nodes with overlaps = 5
 Number of Nodes with overlaps = 7
 Number of Nodes with overlaps = 5
 Number of Nodes with overlaps = 5
 Number of Nodes with overlaps = 2
 Number of Nodes with overlaps = 2
 Number of Nodes with overlaps = 1
 Number of Nodes with overlaps = 7
 Number of Nodes with overlaps = 1
 Number of Nodes with overlaps = 6
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-5.630 | TNS=-88.178| WHS=N/A    | THS=N/A    |

Phase 4.2 Global Iteration 1 | Checksum: 13f25b21c

Time (s): cpu = 00:02:20 ; elapsed = 00:01:46 . Memory (MB): peak = 1630.195 ; gain = 130.180
Phase 4 Rip-up And Reroute | Checksum: 13f25b21c

Time (s): cpu = 00:02:20 ; elapsed = 00:01:46 . Memory (MB): peak = 1630.195 ; gain = 130.180

Phase 5 Delay and Skew Optimization

Phase 5.1 Delay CleanUp

Phase 5.1.1 Update Timing
Phase 5.1.1 Update Timing | Checksum: 21c9bd585

Time (s): cpu = 00:02:20 ; elapsed = 00:01:46 . Memory (MB): peak = 1630.195 ; gain = 130.180
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-5.617 | TNS=-86.848| WHS=N/A    | THS=N/A    |

 Number of Nodes with overlaps = 0
Phase 5.1 Delay CleanUp | Checksum: e7e5e811

Time (s): cpu = 00:02:20 ; elapsed = 00:01:46 . Memory (MB): peak = 1630.195 ; gain = 130.180

Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: e7e5e811

Time (s): cpu = 00:02:20 ; elapsed = 00:01:46 . Memory (MB): peak = 1630.195 ; gain = 130.180
Phase 5 Delay and Skew Optimization | Checksum: e7e5e811

Time (s): cpu = 00:02:20 ; elapsed = 00:01:46 . Memory (MB): peak = 1630.195 ; gain = 130.180

Phase 6 Post Hold Fix

Phase 6.1 Hold Fix Iter

Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: ef9abc12

Time (s): cpu = 00:02:21 ; elapsed = 00:01:47 . Memory (MB): peak = 1630.195 ; gain = 130.180
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-5.617 | TNS=-86.439| WHS=-0.443 | THS=-0.849 |

Phase 6.1 Hold Fix Iter | Checksum: 151f6c881

Time (s): cpu = 00:02:22 ; elapsed = 00:01:48 . Memory (MB): peak = 1630.195 ; gain = 130.180
WARNING: [Route 35-468] The router encountered 388 pins that are both setup-critical and hold-critical and tried to fix hold violations at the expense of setup slack. Such pins are:
	RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_302/I0
	SYNC/ROMAddress_reg[3]_i_146/DI[3]
	SYNC/ROMAddress_reg[9]_i_237/DI[3]
	SYNC/ROMAddress[9]_i_588/I0
	SYNC/ROMAddress[9]_i_595/I0
	RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_589/I1
	RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_624/I1
	SYNC/ROMAddress_reg[9]_i_237/DI[2]
	SYNC/ROMAddress_reg[9]_i_266/DI[2]
	SYNC/ROMAddress[3]_i_103/I5
	.. and 378 more pins.

Phase 6 Post Hold Fix | Checksum: 197295544

Time (s): cpu = 00:02:22 ; elapsed = 00:01:48 . Memory (MB): peak = 1630.195 ; gain = 130.180

Phase 7 Route finalize

Router Utilization Summary
  Global Vertical Routing Utilization    = 2.83094 %
  Global Horizontal Routing Utilization  = 3.41935 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0

Congestion Report
North Dir 1x1 Area, Max Cong = 54.0541%, No Congested Regions.
South Dir 1x1 Area, Max Cong = 79.2793%, No Congested Regions.
East Dir 1x1 Area, Max Cong = 60.2941%, No Congested Regions.
West Dir 1x1 Area, Max Cong = 75%, No Congested Regions.

------------------------------
Reporting congestion hotspots
------------------------------
Direction: North
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: South
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: East
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: West
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0

Phase 7 Route finalize | Checksum: 1f1dffd6a

Time (s): cpu = 00:02:22 ; elapsed = 00:01:48 . Memory (MB): peak = 1630.195 ; gain = 130.180

Phase 8 Verifying routed nets

 Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 1f1dffd6a

Time (s): cpu = 00:02:22 ; elapsed = 00:01:48 . Memory (MB): peak = 1630.195 ; gain = 130.180

Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 238ddaa41

Time (s): cpu = 00:02:23 ; elapsed = 00:01:49 . Memory (MB): peak = 1630.195 ; gain = 130.180

Phase 10 Post Router Timing

Phase 10.1 Update Timing
Phase 10.1 Update Timing | Checksum: 1f42f7dac

Time (s): cpu = 00:02:23 ; elapsed = 00:01:49 . Memory (MB): peak = 1630.195 ; gain = 130.180
INFO: [Route 35-57] Estimated Timing Summary | WNS=-5.617 | TNS=-86.439| WHS=-0.027 | THS=-0.027 |

WARNING: [Route 35-328] Router estimated timing not met.
Resolution: For a complete and accurate timing signoff, report_timing_summary must be run after route_design. Alternatively, route_design can be run with the -timing_summary option to enable a complete timing signoff at the end of route_design.
Phase 10 Post Router Timing | Checksum: 1f42f7dac

Time (s): cpu = 00:02:23 ; elapsed = 00:01:49 . Memory (MB): peak = 1630.195 ; gain = 130.180
INFO: [Route 35-16] Router Completed Successfully

Time (s): cpu = 00:02:23 ; elapsed = 00:01:49 . Memory (MB): peak = 1630.195 ; gain = 130.180

Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
93 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:02:25 ; elapsed = 00:01:52 . Memory (MB): peak = 1630.195 ; gain = 130.180
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1630.195 ; gain = 0.000
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1630.195 ; gain = 0.000
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.257 . Memory (MB): peak = 1630.195 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/impl_1/VGA_top_routed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx
Command: report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/impl_1/VGA_top_drc_routed.rpt.
report_drc completed successfully
INFO: [runtcl-4] Executing : report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx
Command: report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-133] Running Methodology with 2 threads
INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/impl_1/VGA_top_methodology_drc_routed.rpt.
report_methodology completed successfully
INFO: [runtcl-4] Executing : report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx
Command: report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
105 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
INFO: [runtcl-4] Executing : report_route_status -file VGA_top_route_status.rpt -pb VGA_top_route_status.pb
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file VGA_top_timing_summary_routed.rpt -pb VGA_top_timing_summary_routed.pb -rpx VGA_top_timing_summary_routed.rpx -warn_on_violation 
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
CRITICAL WARNING: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.
INFO: [runtcl-4] Executing : report_incremental_reuse -file VGA_top_incremental_reuse_routed.rpt
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
INFO: [runtcl-4] Executing : report_clock_utilization -file VGA_top_clock_utilization_routed.rpt
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file VGA_top_bus_skew_routed.rpt -pb VGA_top_bus_skew_routed.pb -rpx VGA_top_bus_skew_routed.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
Command: write_bitstream -force VGA_top.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 2 threads
WARNING: [DRC PDRC-153] Gated clock check: Net UPD/dataOut_reg[18]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin UPD/dataOut_reg[18]_LDC_i_1/O, cell UPD/dataOut_reg[18]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
WARNING: [DRC PDRC-153] Gated clock check: Net UPD/dataOut_reg[19]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin UPD/dataOut_reg[19]_LDC_i_1/O, cell UPD/dataOut_reg[19]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
WARNING: [DRC PDRC-153] Gated clock check: Net UPD/dataOut_reg[1]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin UPD/dataOut_reg[1]_LDC_i_1/O, cell UPD/dataOut_reg[1]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
WARNING: [DRC PDRC-153] Gated clock check: Net UPD/dataOut_reg[20]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin UPD/dataOut_reg[20]_LDC_i_1/O, cell UPD/dataOut_reg[20]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
WARNING: [DRC PDRC-153] Gated clock check: Net UPD/dataOut_reg[21]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin UPD/dataOut_reg[21]_LDC_i_1/O, cell UPD/dataOut_reg[21]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
WARNING: [DRC PDRC-153] Gated clock check: Net UPD/dataOut_reg[4]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin UPD/dataOut_reg[4]_LDC_i_1/O, cell UPD/dataOut_reg[4]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 7 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 2 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Writing bitstream ./VGA_top.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-118] WebTalk data collection is enabled (User setting is ON. Install Setting is ON.).
INFO: [Common 17-83] Releasing license: Implementation
124 Infos, 11 Warnings, 1 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1942.887 ; gain = 312.691
INFO: [Common 17-206] Exiting Vivado at Tue Jan  4 12:21:36 2022...
