# Device Usage Statistics Report

### Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.

software_version_and_target_device
beta | FALSE | build_version | 3064766
date_generated | Tue Jan 11 11:43:56 2022 | os_platform | LIN64
product_version | Vivado v2020.2 (64-bit) | project_id | 9af971280c2f4a97bd669d4342d94e71
project_iteration | 294 | random_id | 71b3bd2e06bc5104aea64d7827d103e8
registration_id | 71b3bd2e06bc5104aea64d7827d103e8 | route_design | TRUE
target_device | xc7z010 | target_family | zynq
target_package | clg400 | target_speed | -1
tool_flow | Vivado

user_environment
cpu_name | AMD Ryzen 5 3500U with Radeon Vega Mobile Gfx | cpu_speed | 1400.000 MHz
os_name | Ubuntu | os_release | Ubuntu 20.04 LTS
system_ram | 6.000 GB | total_processors | 1

vivado_usage

gui_handlers
abstractcombinedpanel_add_element=1 | abstractfileview_reload=1 | addsrcwizard_specify_hdl_netlist_block_design=2 | basedialog_cancel=309
basedialog_no=7 | basedialog_ok=957 | basedialog_yes=361 | closeplanner_yes=3
cmdmsgdialog_ok=88 | constraintschooserpanel_add_existing_or_create_new_constraints=1 | constraintschooserpanel_add_files=2 | constraintschooserpanel_create_file=1
coretreetablepanel_core_tree_table=4 | createsrcfiledialog_file_location=3 | createsrcfiledialog_file_name=5 | definemodulesdialog_define_modules_and_specify_io_ports=37
designtimingsumsectionpanel_worst_negative_slack=6 | deviceview_show_cell_connections=2 | expruntreepanel_exp_run_tree_table=3 | filesetpanel_file_set_panel_tree=577
flownavigatortreepanel_flow_navigator_tree=796 | fpgachooser_fpga_table=4 | gettingstartedview_create_new_project=1 | hardwaretreepanel_hardware_tree_table=1
hcodeeditor_blank_operations=12 | hcodeeditor_close=9 | hcodeeditor_commands_to_fold_text=2 | hcodeeditor_diff_with=6
hcodeeditor_search_text_combo_box=8 | hinputhandler_indent_selection=1 | hinputhandler_toggle_block_comments=4 | hinputhandler_toggle_line_comments=127
hinputhandler_unindent_selection=17 | hpopuptitle_close=2 | languagetemplatesdialog_templates_tree=43 | mainmenumgr_edit=4
mainmenumgr_file=16 | mainmenumgr_flow=5 | mainmenumgr_help=4 | mainmenumgr_open_recent_project=5
mainmenumgr_project=7 | mainmenumgr_reports=2 | mainmenumgr_settings=1 | mainmenumgr_tools=3
mainmenumgr_view=8 | mainmenumgr_window=4 | maintoolbarmgr_open=3 | mainwinmenumgr_layout=4
msgtreepanel_message_severity=3 | msgtreepanel_message_view_tree=290 | msgview_clear_messages_resulting_from_user_executed=25 | msgview_error_messages=3
msgview_information_messages=10 | msgview_warning_messages=45 | navigabletimingreporttab_timing_report_navigation_tree=21 | netlistschmenuandmouse_view=2
netlisttreeview_netlist_tree=85 | numjobschooser_number_of_jobs=1 | pacommandnames_add_sources=14 | pacommandnames_auto_connect_target=48
pacommandnames_auto_update_hier=9 | pacommandnames_bel_const_mode=1 | pacommandnames_export_schematic=1 | pacommandnames_fed_toggle_routing_resources=4
pacommandnames_fileset_window=1 | pacommandnames_new_project=1 | pacommandnames_open_hardware_manager=72 | pacommandnames_project_summary=1
pacommandnames_recustomize_core=1 | pacommandnames_reports_window=2 | pacommandnames_run_bitgen=30 | pacommandnames_save_project_as=1
pacommandnames_set_used_in_prop=1 | pacommandnames_simulation_run_behavioral=1 | pacommandnames_src_replace_file=2 | pagraphicalviewutils_hide_all=1
pagraphicalviewutils_show_all=1 | pagraphicalviewutils_show_input_connections=1 | paviews_code=17 | paviews_device=41
paviews_project_summary=115 | paviews_schematic=9 | planaheadtab_show_flow_navigator=1 | programdebugtab_available_targets_on_server=2
programdebugtab_open_target=43 | programdebugtab_program_device=319 | programfpgadialog_program=323 | programfpgadialog_specify_bitstream_file=1
progressdialog_background=9 | progressdialog_cancel=6 | projectdashboardview_dashboard=3 | projectdashboardview_tabbed_pane=1
projectnamechooser_choose_project_location=5 | projectnamechooser_project_name=3 | projectsummarypowerpanel_tabbed_pane=2 | projectsummarytimingpanel_open_timing_summary_report=1
projectsummarytimingpanel_project_summary_timing_panel_tabbed=9 | projectsummaryutilizationgadget_project_summary_utilization_gadget_tabbed=4 | projectsummaryutilizationpanel_project_summary_utilization_panel_tabbed=5 | projectsummaryutilizationpanel_project_summary_utilization_table=7
projecttab_close_design=2 | projecttab_reload=58 | quickhelp_help=1 | rdicommands_copy=2
rdicommands_custom_commands=1 | rdicommands_delete=3 | rdicommands_settings=1 | rdicommands_undo=3
reportutiltab_report_utilization_navigation_tree=3 | rungadget_run_gadget_tabbed_pane=2 | rungadget_show_error_and_critical_warning_messages=1 | saveprojectutils_cancel=2
saveprojectutils_dont_save=2 | saveprojectutils_save=6 | saveschematicdialog_specify_output_pdf_file=1 | schematicview_previous=1
schmenuandmouse_save_as_pdf_file=1 | selectmenu_mark=1 | settingsdialog_options_tree=2 | settingsdialog_project_tree=1
simpleoutputproductdialog_generate_output_products_immediately=2 | specifylibrarydialog_library_name=1 | srcchooserpanel_add_hdl_and_netlist_files_to_your_project=9 | srcchooserpanel_add_or_create_source_file=3
srcchooserpanel_create_file=5 | srcfileproppanels_location=2 | srcfileproppanels_type=5 | srcfiletypecombobox_source_file_type=3
srcmenu_ip_hierarchy=4 | srcmenu_open_selected_source_files=1 | srcmenu_refresh_hierarchy=3 | srcmenu_set_library=1
stalemoreaction_out_of_date_details=1 | stalerundialog_no=1 | stalerundialog_yes=2 | statemonitor_reset_run=7
syntheticagettingstartedview_recent_projects=36 | syntheticastatemonitor_cancel=42 | taskbanner_close=29 | tclconsoleview_tcl_console_code_editor=1
tclobjecttreetable_treetable=1 | timingitemflattablepanel_table=21 | touchpointsurveydialog_remind_me_later=65 | touchpointsurveydialog_yes=1

java_command_handlers
addsources=14 | autoconnecttarget=47 | closeproject=1 | coreview=1
customizecore=1 | editdelete=8 | editpaste=4 | editproperties=1
editundo=3 | exitapp=33 | fedtoggleroutingresourcescmdhandler=4 | fliptoviewtaskrtlanalysis=16
launchprogramfpga=321 | newproject=2 | openhardwaremanager=111 | openrecenttarget=8
programdevice=5 | projectsummary=1 | recustomizecore=5 | reportclocknetworks=1
reportdrc=1 | reporttimingsummary=3 | reportutilization=7 | resetlayout=1
runbitgen=389 | runimplementation=51 | runschematic=6 | runsynthesis=157
savefileproxyhandler=35 | saveprojectas=1 | setsourceenabled=1 | showsource=1
showview=111 | simulationrun=1 | timingconstraintswizard=1 | toggleviewnavigator=1
toolssettings=1 | toolstemplates=2 | updatesourcefiles=3 | viewtaskimplementation=5
viewtaskprojectmanager=55 | viewtaskrtlanalysis=51 | viewtasksynthesis=2

other_data
guimode=37

project_data
constraintsetcount=1 | core_container=false | currentimplrun=impl_1 | currentsynthesisrun=synth_1
default_library=xil_defaultlib | designmode=RTL | export_simulation_activehdl=2 | export_simulation_ies=2
export_simulation_modelsim=2 | export_simulation_questa=2 | export_simulation_riviera=2 | export_simulation_vcs=2
export_simulation_xsim=2 | implstrategy=Vivado Implementation Defaults | launch_simulation_activehdl=0 | launch_simulation_ies=0
launch_simulation_modelsim=0 | launch_simulation_questa=0 | launch_simulation_riviera=0 | launch_simulation_vcs=0
launch_simulation_xsim=1 | simulator_language=Mixed | srcsetcount=13 | synthesisstrategy=Vivado Synthesis Defaults
target_language=VHDL | target_simulator=XSim | totalimplruns=2 | totalsynthesisruns=2

unisim_transformation

post_unisim_transformation
bufg=3 | carry4=307 | fdce=61 | fdpe=4
fdre=276 | fdse=9 | gnd=12 | ibuf=6
ldce=1 | lut1=33 | lut2=472 | lut3=399
lut4=495 | lut5=436 | lut6=606 | mmcme2_adv=1
muxf7=32 | muxf8=1 | obuf=22 | ramb18e1=9
ramb36e1=18 | vcc=13

pre_unisim_transformation
bufg=3 | carry4=307 | fdce=61 | fdpe=4
fdre=276 | fdse=9 | gnd=12 | ibuf=6
ldce=1 | lut1=33 | lut2=472 | lut3=399
lut4=495 | lut5=436 | lut6=606 | mmcme2_adv=1
muxf7=32 | muxf8=1 | obuf=22 | ramb18e1=9
ramb36e1=18 | vcc=13

phys_opt_design_post_place

command_line_options
-aggressive_hold_fix=default::[not_specified] | -bram_register_opt=default::[not_specified] | -clock_opt=default::[not_specified] | -critical_cell_opt=default::[not_specified]
-critical_pin_opt=default::[not_specified] | -directive=default::[not_specified] | -dsp_register_opt=default::[not_specified] | -effort_level=default::[not_specified]
-fanout_opt=default::[not_specified] | -hold_fix=default::[not_specified] | -insert_negative_edge_ffs=default::[not_specified] | -multi_clock_opt=default::[not_specified]
-placement_opt=default::[not_specified] | -restruct_opt=default::[not_specified] | -retime=default::[not_specified] | -rewire=default::[not_specified]
-shift_register_opt=default::[not_specified] | -uram_register_opt=default::[not_specified] | -verbose=default::[not_specified] | -vhfn=default::[not_specified]

usage
postths=0.000000 | posttns=-220.538226 | postwhs=0.000000 | postwns=-3.429840
preths=0.000000 | pretns=-224.136230 | prewhs=0.000000 | prewns=-4.399839

power_opt_design

command_line_options_spo
-cell_types=default::all | -clocks=default::[not_specified] | -exclude_cells=default::[not_specified] | -include_cells=default::[not_specified]

usage
bram_ports_augmented=0 | bram_ports_newly_gated=25 | bram_ports_total=54 | flow_state=default
slice_registers_augmented=0 | slice_registers_newly_gated=0 | slice_registers_total=350 | srls_augmented=0
srls_newly_gated=0 | srls_total=0

ip_statistics

clk_wiz_v6_0_6_0_0/1
clkin1_period=8.000 | clkin2_period=10.000 | clock_mgr_type=NA | component_name=clk_wiz_0
core_container=NA | enable_axi=0 | feedback_source=FDBK_AUTO | feedback_type=SINGLE
iptotal=1 | manual_override=false | num_out_clk=1 | primitive=MMCM
use_dyn_phase_shift=false | use_dyn_reconfig=false | use_inclk_stopped=false | use_inclk_switchover=false
use_locked=false | use_max_i_jitter=false | use_min_o_jitter=false | use_phase_alignment=true
use_power_down=false | use_reset=false

report_drc

command_line_options
-append=default::[not_specified] | -checks=default::[not_specified] | -fail_on=default::[not_specified] | -force=default::[not_specified]
-format=default::[not_specified] | -internal=default::[not_specified] | -internal_only=default::[not_specified] | -max_msgs_per_check=default::[not_specified]
-messages=default::[not_specified] | -name=default::[not_specified] | -no_waivers=default::[not_specified] | -return_string=default::[not_specified]
-ruledecks=default::[not_specified] | -upgrade_cw=default::[not_specified] | -waived=default::[not_specified]

results
pdrc-153=1 | zps7-1=1

report_methodology

command_line_options
-append=default::[not_specified] | -checks=default::[not_specified] | -fail_on=default::[not_specified] | -force=default::[not_specified]
-format=default::[not_specified] | -messages=default::[not_specified] | -name=default::[not_specified] | -return_string=default::[not_specified]
-slack_lesser_than=default::[not_specified] | -waived=default::[not_specified]

results
lutar-1=5 | synth-6=27 | timing-16=75 | timing-17=1
timing-18=9

report_power

command_line_options
-advisory=default::[not_specified] | -append=default::[not_specified] | -file=[specified] | -format=default::text
-hier=default::power | -hierarchical_depth=default::4 | -l=default::[not_specified] | -name=default::[not_specified]
-no_propagation=default::[not_specified] | -return_string=default::[not_specified] | -rpx=[specified] | -verbose=default::[not_specified]
-vid=default::[not_specified] | -xpe=default::[not_specified]

usage
airflow=250 (LFM) | ambient_temp=25.0 (C) | bi-dir_toggle=12.500000 | bidir_output_enable=1.000000
board_layers=8to11 (8 to 11 Layers) | board_selection=medium (10"x10") | bram=0.067657 | clocks=0.005035
confidence_level_clock_activity=High | confidence_level_design_state=High | confidence_level_device_models=High | confidence_level_internal_activity=Medium
confidence_level_io_activity=Low | confidence_level_overall=Low | customer=TBD | customer_class=TBD
devstatic=0.096515 | die=xc7z010clg400-1 | dsp_output_toggle=12.500000 | dynamic=0.201953
effective_thetaja=11.53 | enable_probability=0.990000 | family=zynq | ff_toggle=12.500000
flow_state=routed | heatsink=none | i/o=0.001682 | input_toggle=12.500000
junction_temp=28.4 (C) | logic=0.004873 | mgtavcc_dynamic_current=0.000000 | mgtavcc_static_current=0.000000
mgtavcc_total_current=0.000000 | mgtavcc_voltage=1.000000 | mgtavtt_dynamic_current=0.000000 | mgtavtt_static_current=0.000000
mgtavtt_total_current=0.000000 | mgtavtt_voltage=1.200000 | mgtvccaux_dynamic_current=0.000000 | mgtvccaux_static_current=0.000000
mgtvccaux_total_current=0.000000 | mgtvccaux_voltage=1.800000 | mmcm=0.115225 | netlist_net_matched=NA
off-chip_power=0.000000 | on-chip_power=0.298469 | output_enable=1.000000 | output_load=5.000000
output_toggle=12.500000 | package=clg400 | pct_clock_constrained=3.870000 | pct_inputs_defined=16
platform=lin64 | process=typical | ram_enable=50.000000 | ram_write=50.000000
read_saif=False | set/reset_probability=0.000000 | signal_rate=False | signals=0.007481
simulation_file=None | speedgrade=-1 | static_prob=False | temp_grade=commercial
thetajb=9.3 (C/W) | thetasa=0.0 (C/W) | toggle_rate=False | user_board_temp=25.0 (C)
user_effective_thetaja=11.53 | user_junc_temp=28.4 (C) | user_thetajb=9.3 (C/W) | user_thetasa=0.0 (C/W)
vccadc_dynamic_current=0.000000 | vccadc_static_current=0.020000 | vccadc_total_current=0.020000 | vccadc_voltage=1.800000
vccaux_dynamic_current=0.064014 | vccaux_io_dynamic_current=0.000000 | vccaux_io_static_current=0.000000 | vccaux_io_total_current=0.000000
vccaux_io_voltage=1.800000 | vccaux_static_current=0.005618 | vccaux_total_current=0.069632 | vccaux_voltage=1.800000
vccbram_dynamic_current=0.005701 | vccbram_static_current=0.001052 | vccbram_total_current=0.006753 | vccbram_voltage=1.000000
vccint_dynamic_current=0.079550 | vccint_static_current=0.004502 | vccint_total_current=0.084052 | vccint_voltage=1.000000
vcco12_dynamic_current=0.000000 | vcco12_static_current=0.000000 | vcco12_total_current=0.000000 | vcco12_voltage=1.200000
vcco135_dynamic_current=0.000000 | vcco135_static_current=0.000000 | vcco135_total_current=0.000000 | vcco135_voltage=1.350000
vcco15_dynamic_current=0.000000 | vcco15_static_current=0.000000 | vcco15_total_current=0.000000 | vcco15_voltage=1.500000
vcco18_dynamic_current=0.000000 | vcco18_static_current=0.000000 | vcco18_total_current=0.000000 | vcco18_voltage=1.800000
vcco25_dynamic_current=0.000000 | vcco25_static_current=0.000000 | vcco25_total_current=0.000000 | vcco25_voltage=2.500000
vcco33_dynamic_current=0.000448 | vcco33_static_current=0.001000 | vcco33_total_current=0.001448 | vcco33_voltage=3.300000
vcco_ddr_dynamic_current=0.000000 | vcco_ddr_static_current=0.000000 | vcco_ddr_total_current=0.000000 | vcco_ddr_voltage=1.500000
vcco_mio0_dynamic_current=0.000000 | vcco_mio0_static_current=0.000000 | vcco_mio0_total_current=0.000000 | vcco_mio0_voltage=1.800000
vcco_mio1_dynamic_current=0.000000 | vcco_mio1_static_current=0.000000 | vcco_mio1_total_current=0.000000 | vcco_mio1_voltage=1.800000
vccpaux_dynamic_current=0.000000 | vccpaux_static_current=0.010330 | vccpaux_total_current=0.010330 | vccpaux_voltage=1.800000
vccpint_dynamic_current=0.000000 | vccpint_static_current=0.017555 | vccpint_total_current=0.017555 | vccpint_voltage=1.000000
vccpll_dynamic_current=0.000000 | vccpll_static_current=0.003000 | vccpll_total_current=0.003000 | vccpll_voltage=1.800000
version=2020.2

report_utilization

clocking
bufgctrl_available=32 | bufgctrl_fixed=0 | bufgctrl_used=3 | bufgctrl_util_percentage=9.38
bufhce_available=48 | bufhce_fixed=0 | bufhce_used=0 | bufhce_util_percentage=0.00
bufio_available=8 | bufio_fixed=0 | bufio_used=0 | bufio_util_percentage=0.00
bufmrce_available=4 | bufmrce_fixed=0 | bufmrce_used=0 | bufmrce_util_percentage=0.00
bufr_available=8 | bufr_fixed=0 | bufr_used=0 | bufr_util_percentage=0.00
mmcme2_adv_available=2 | mmcme2_adv_fixed=0 | mmcme2_adv_used=1 | mmcme2_adv_util_percentage=50.00
plle2_adv_available=2 | plle2_adv_fixed=0 | plle2_adv_used=0 | plle2_adv_util_percentage=0.00

dsp
dsps_available=80 | dsps_fixed=0 | dsps_used=0 | dsps_util_percentage=0.00

io_standard
blvds_25=0 | diff_hstl_i=0 | diff_hstl_i_18=0 | diff_hstl_ii=0
diff_hstl_ii_18=0 | diff_hsul_12=0 | diff_mobile_ddr=0 | diff_sstl135=0
diff_sstl135_r=0 | diff_sstl15=0 | diff_sstl15_r=0 | diff_sstl18_i=0
diff_sstl18_ii=0 | hstl_i=0 | hstl_i_18=0 | hstl_ii=0
hstl_ii_18=0 | hsul_12=0 | lvcmos12=0 | lvcmos15=0
lvcmos18=0 | lvcmos25=0 | lvcmos33=1 | lvds_25=0
lvttl=0 | mini_lvds_25=0 | mobile_ddr=0 | pci33_3=0
ppds_25=0 | rsds_25=0 | sstl135=0 | sstl135_r=0
sstl15=0 | sstl15_r=0 | sstl18_i=0 | sstl18_ii=0
tmds_33=0

memory
block_ram_tile_available=60 | block_ram_tile_fixed=0 | block_ram_tile_used=22.5 | block_ram_tile_util_percentage=37.50
ramb18_available=120 | ramb18_fixed=0 | ramb18_used=9 | ramb18_util_percentage=7.50
ramb18e1_only_used=9 | ramb36_fifo_available=60 | ramb36_fifo_fixed=0 | ramb36_fifo_used=18
ramb36_fifo_util_percentage=30.00 | ramb36e1_only_used=18

primitives
bufg_functional_category=Clock | bufg_used=3 | carry4_functional_category=CarryLogic | carry4_used=307
fdce_functional_category=Flop & Latch | fdce_used=63 | fdpe_functional_category=Flop & Latch | fdpe_used=4
fdre_functional_category=Flop & Latch | fdre_used=276 | fdse_functional_category=Flop & Latch | fdse_used=9
ibuf_functional_category=IO | ibuf_used=6 | ldce_functional_category=Flop & Latch | ldce_used=1
lut1_functional_category=LUT | lut1_used=33 | lut2_functional_category=LUT | lut2_used=472
lut3_functional_category=LUT | lut3_used=408 | lut4_functional_category=LUT | lut4_used=495
lut5_functional_category=LUT | lut5_used=436 | lut6_functional_category=LUT | lut6_used=606
mmcme2_adv_functional_category=Clock | mmcme2_adv_used=1 | muxf7_functional_category=MuxFx | muxf7_used=32
muxf8_functional_category=MuxFx | muxf8_used=1 | obuf_functional_category=IO | obuf_used=22
ramb18e1_functional_category=Block Memory | ramb18e1_used=9 | ramb36e1_functional_category=Block Memory | ramb36e1_used=18

slice_logic
f7_muxes_available=8800 | f7_muxes_fixed=0 | f7_muxes_used=32 | f7_muxes_util_percentage=0.36
f8_muxes_available=4400 | f8_muxes_fixed=0 | f8_muxes_used=1 | f8_muxes_util_percentage=0.02
lut_as_logic_available=17600 | lut_as_logic_fixed=0 | lut_as_logic_used=1941 | lut_as_logic_util_percentage=11.03
lut_as_memory_available=6000 | lut_as_memory_fixed=0 | lut_as_memory_used=0 | lut_as_memory_util_percentage=0.00
register_as_flip_flop_available=35200 | register_as_flip_flop_fixed=0 | register_as_flip_flop_used=352 | register_as_flip_flop_util_percentage=1.00
register_as_latch_available=35200 | register_as_latch_fixed=0 | register_as_latch_used=1 | register_as_latch_util_percentage=<0.01
slice_luts_available=17600 | slice_luts_fixed=0 | slice_luts_used=1941 | slice_luts_util_percentage=11.03
slice_registers_available=35200 | slice_registers_fixed=0 | slice_registers_used=353 | slice_registers_util_percentage=1.00
lut_as_distributed_ram_fixed=0 | lut_as_distributed_ram_used=0 | lut_as_logic_available=17600 | lut_as_logic_fixed=0
lut_as_logic_used=1941 | lut_as_logic_util_percentage=11.03 | lut_as_memory_available=6000 | lut_as_memory_fixed=0
lut_as_memory_used=0 | lut_as_memory_util_percentage=0.00 | lut_as_shift_register_fixed=0 | lut_as_shift_register_used=0
lut_in_front_of_the_register_is_unused_fixed=0 | lut_in_front_of_the_register_is_unused_used=26 | lut_in_front_of_the_register_is_used_fixed=26 | lut_in_front_of_the_register_is_used_used=55
register_driven_from_outside_the_slice_fixed=55 | register_driven_from_outside_the_slice_used=81 | register_driven_from_within_the_slice_fixed=81 | register_driven_from_within_the_slice_used=272
slice_available=4400 | slice_fixed=0 | slice_registers_available=35200 | slice_registers_fixed=0
slice_registers_used=353 | slice_registers_util_percentage=1.00 | slice_used=670 | slice_util_percentage=15.23
slicel_fixed=0 | slicel_used=427 | slicem_fixed=0 | slicem_used=243
unique_control_sets_available=4400 | unique_control_sets_fixed=4400 | unique_control_sets_used=30 | unique_control_sets_util_percentage=0.68
using_o5_and_o6_fixed=0.68 | using_o5_and_o6_used=509 | using_o5_output_only_fixed=509 | using_o5_output_only_used=1
using_o6_output_only_fixed=1 | using_o6_output_only_used=1431

specific_feature
bscane2_available=4 | bscane2_fixed=0 | bscane2_used=0 | bscane2_util_percentage=0.00
capturee2_available=1 | capturee2_fixed=0 | capturee2_used=0 | capturee2_util_percentage=0.00
dna_port_available=1 | dna_port_fixed=0 | dna_port_used=0 | dna_port_util_percentage=0.00
efuse_usr_available=1 | efuse_usr_fixed=0 | efuse_usr_used=0 | efuse_usr_util_percentage=0.00
frame_ecce2_available=1 | frame_ecce2_fixed=0 | frame_ecce2_used=0 | frame_ecce2_util_percentage=0.00
icape2_available=2 | icape2_fixed=0 | icape2_used=0 | icape2_util_percentage=0.00
startupe2_available=1 | startupe2_fixed=0 | startupe2_used=0 | startupe2_util_percentage=0.00
xadc_available=1 | xadc_fixed=0 | xadc_used=0 | xadc_util_percentage=0.00

synthesis

command_line_options
-assert=default::[not_specified] | -bufg=default::12 | -cascade_dsp=default::auto | -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto | -debug_log=default::[not_specified] | -directive=default::default | -fanout_limit=default::10000
-flatten_hierarchy=default::rebuilt | -fsm_extraction=default::auto | -gated_clock_conversion=default::off | -generic=default::[not_specified]
-include_dirs=default::[not_specified] | -keep_equivalent_registers=default::[not_specified] | -lint=default::[not_specified] | -max_bram=default::-1
-max_bram_cascade_height=default::-1 | -max_dsp=default::-1 | -max_uram=default::-1 | -max_uram_cascade_height=default::-1
-mode=default::default | -name=default::[not_specified] | -no_lc=default::[not_specified] | -no_srlextract=default::[not_specified]
-no_timing_driven=default::[not_specified] | -os=default::[not_specified] | -part=xc7z010clg400-1 | -resource_sharing=default::auto
-retiming=default::[not_specified] | -rtl=default::[not_specified] | -rtl_skip_constraints=default::[not_specified] | -rtl_skip_ip=default::[not_specified]
-seu_protect=default::none | -sfcu=default::[not_specified] | -shreg_min_size=default::3 | -top=VGA_top
-verilog_define=default::[not_specified]

usage
elapsed=00:00:56s | hls_ip=0 | memory_gain=81.133MB | memory_peak=2284.512MB

xsim

command_line_options
-sim_mode=default::behavioral | -sim_type=default::