
*** Running vivado
    with args -log VGA_top.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace


****** Vivado v2020.2 (64-bit)
  **** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
  **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

source VGA_top.tcl -notrace
Command: link_design -top VGA_top -part xc7z010clg400-1
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Device 21-403] Loading part xc7z010clg400-1
INFO: [Project 1-454] Reading design checkpoint '/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.dcp' for cell 'U0'
Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2276.785 ; gain = 0.000 ; free physical = 429 ; free virtual = 5464
INFO: [Netlist 29-17] Analyzing 368 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2020.2
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'U0/inst'
Finished Parsing XDC File [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'U0/inst'
Parsing XDC File [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'U0/inst'
Finished Parsing XDC File [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'U0/inst'
Parsing XDC File [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/constrs_1/imports/projet_vga_etn_sources/ZYBO_Master.xdc]
Finished Parsing XDC File [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.srcs/constrs_1/imports/projet_vga_etn_sources/ZYBO_Master.xdc]
Parsing XDC File [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_late.xdc] for cell 'U0/inst'
Finished Parsing XDC File [/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_late.xdc] for cell 'U0/inst'
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2332.793 ; gain = 0.000 ; free physical = 93 ; free virtual = 4921
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

8 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 2332.793 ; gain = 56.027 ; free physical = 93 ; free virtual = 4921
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2396.824 ; gain = 64.031 ; free physical = 827 ; free virtual = 5274

Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-2] Deriving generated clocks
Ending Cache Timing Information Task | Checksum: 1f7452c13

Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2502.637 ; gain = 105.812 ; free physical = 562 ; free virtual = 5097

Starting Logic Optimization Task

Phase 1 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 1da4fc188

Time (s): cpu = 00:00:00.42 ; elapsed = 00:00:00.21 . Memory (MB): peak = 2675.574 ; gain = 0.000 ; free physical = 398 ; free virtual = 4934
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells

Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 2 Constant propagation | Checksum: 1627d3c1f

Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:00.26 . Memory (MB): peak = 2675.574 ; gain = 0.000 ; free physical = 398 ; free virtual = 4934
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells

Phase 3 Sweep
Phase 3 Sweep | Checksum: 174cd4735

Time (s): cpu = 00:00:00.56 ; elapsed = 00:00:00.36 . Memory (MB): peak = 2675.574 ; gain = 0.000 ; free physical = 397 ; free virtual = 4934
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells

Phase 4 BUFG optimization
Phase 4 BUFG optimization | Checksum: 174cd4735

Time (s): cpu = 00:00:00.64 ; elapsed = 00:00:00.45 . Memory (MB): peak = 2675.574 ; gain = 0.000 ; free physical = 397 ; free virtual = 4934
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.

Phase 5 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 5 Shift Register Optimization | Checksum: 174cd4735

Time (s): cpu = 00:00:00.65 ; elapsed = 00:00:00.45 . Memory (MB): peak = 2675.574 ; gain = 0.000 ; free physical = 397 ; free virtual = 4934
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells

Phase 6 Post Processing Netlist
Phase 6 Post Processing Netlist | Checksum: 174cd4735

Time (s): cpu = 00:00:00.66 ; elapsed = 00:00:00.47 . Memory (MB): peak = 2675.574 ; gain = 0.000 ; free physical = 397 ; free virtual = 4934
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Opt_design Change Summary
=========================


-------------------------------------------------------------------------------------------------------------------------
|  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
-------------------------------------------------------------------------------------------------------------------------
|  Retarget                     |               0  |               0  |                                              0  |
|  Constant propagation         |               0  |               0  |                                              0  |
|  Sweep                        |               0  |               0  |                                              0  |
|  BUFG optimization            |               0  |               0  |                                              0  |
|  Shift Register Optimization  |               0  |               0  |                                              0  |
|  Post Processing Netlist      |               0  |               0  |                                              0  |
-------------------------------------------------------------------------------------------------------------------------



Starting Connectivity Check Task

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2675.574 ; gain = 0.000 ; free physical = 397 ; free virtual = 4934
Ending Logic Optimization Task | Checksum: 1bdd283c3

Time (s): cpu = 00:00:00.78 ; elapsed = 00:00:00.59 . Memory (MB): peak = 2675.574 ; gain = 0.000 ; free physical = 397 ; free virtual = 4934

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
INFO: [Pwropt 34-9] Applying IDT optimizations ...
INFO: [Pwropt 34-10] Applying ODC optimizations ...


Starting PowerOpt Patch Enables Task
INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 27 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
INFO: [Pwropt 34-201] Structural ODC has moved 16 WE to EN ports
Number of BRAM Ports augmented: 0 newly gated: 25 Total Ports: 54
Number of Flops added for Enable Generation: 2

Ending PowerOpt Patch Enables Task | Checksum: 1ad2a399a

Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 364 ; free virtual = 4911
Ending Power Optimization Task | Checksum: 1ad2a399a

Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2970.512 ; gain = 294.938 ; free physical = 369 ; free virtual = 4917

Starting Final Cleanup Task

Starting Logic Optimization Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Logic Optimization Task | Checksum: 18c429c7b

Time (s): cpu = 00:00:00.70 ; elapsed = 00:00:00.32 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 367 ; free virtual = 4915
Ending Final Cleanup Task | Checksum: 18c429c7b

Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 367 ; free virtual = 4914

Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 367 ; free virtual = 4914
Ending Netlist Obfuscation Task | Checksum: 18c429c7b

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 367 ; free virtual = 4914
INFO: [Common 17-83] Releasing license: Implementation
32 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:18 . Memory (MB): peak = 2970.512 ; gain = 637.719 ; free physical = 367 ; free virtual = 4914
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 361 ; free virtual = 4911
INFO: [Common 17-1381] The checkpoint '/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.runs/impl_1/VGA_top_opt.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx
Command: report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Coretcl 2-168] The results of DRC are in file /home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.runs/impl_1/VGA_top_drc_opted.rpt.
report_drc completed successfully
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.

Starting Placer Task
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs

Phase 1 Placer Initialization

Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 257 ; free virtual = 4823
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 12b493a13

Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.08 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 257 ; free virtual = 4823
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 257 ; free virtual = 4823

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: e35db202

Time (s): cpu = 00:00:00.54 ; elapsed = 00:00:00.63 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 279 ; free virtual = 4848

Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 175364624

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 279 ; free virtual = 4850

Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 175364624

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 279 ; free virtual = 4850
Phase 1 Placer Initialization | Checksum: 175364624

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 278 ; free virtual = 4849

Phase 2 Global Placement

Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 13261e3b6

Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 271 ; free virtual = 4842

Phase 2.2 Update Timing before SLR Path Opt
Phase 2.2 Update Timing before SLR Path Opt | Checksum: 18cc5423c

Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 269 ; free virtual = 4840

Phase 2.3 Global Placement Core

Phase 2.3.1 Physical Synthesis In Placer
INFO: [Physopt 32-1035] Found 40 LUTNM shape to break, 48 LUT instances to create LUTNM shape
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 17, two critical 23, total 40, new lutff created 8
INFO: [Physopt 32-775] End 1 Pass. Optimized 61 nets or cells. Created 40 new cells, deleted 21 existing cells and moved 0 existing cell
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design.
INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 216 ; free virtual = 4811

Summary of Physical Synthesis Optimizations
============================================


-----------------------------------------------------------------------------------------------------------------------------------------------------------
|  Optimization                                     |  Added Cells  |  Removed Cells  |  Optimized Cells/Nets  |  Dont Touch  |  Iterations  |  Elapsed   |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
|  LUT Combining                                    |           40  |             21  |                    61  |           0  |           1  |  00:00:00  |
|  Very High Fanout                                 |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  DSP Register                                     |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Shift Register to Pipeline                       |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Shift Register                                   |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  BRAM Register                                    |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  URAM Register                                    |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Dynamic/Static Region Interface Net Replication  |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Total                                            |           40  |             21  |                    61  |           0  |           8  |  00:00:00  |
-----------------------------------------------------------------------------------------------------------------------------------------------------------


Phase 2.3.1 Physical Synthesis In Placer | Checksum: 1b76e4ec8

Time (s): cpu = 00:00:15 ; elapsed = 00:00:07 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 216 ; free virtual = 4812
Phase 2.3 Global Placement Core | Checksum: 1c34d07e2

Time (s): cpu = 00:00:17 ; elapsed = 00:00:07 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 214 ; free virtual = 4811
Phase 2 Global Placement | Checksum: 1c34d07e2

Time (s): cpu = 00:00:17 ; elapsed = 00:00:07 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 215 ; free virtual = 4811

Phase 3 Detail Placement

Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 1b3fbaa71

Time (s): cpu = 00:00:17 ; elapsed = 00:00:07 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 213 ; free virtual = 4810

Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 193d31e7b

Time (s): cpu = 00:00:19 ; elapsed = 00:00:08 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 208 ; free virtual = 4809

Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 1a35df298

Time (s): cpu = 00:00:19 ; elapsed = 00:00:08 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 208 ; free virtual = 4809

Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 1f3df6129

Time (s): cpu = 00:00:19 ; elapsed = 00:00:08 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 208 ; free virtual = 4809

Phase 3.5 Fast Optimization
Phase 3.5 Fast Optimization | Checksum: 17b5282b8

Time (s): cpu = 00:00:22 ; elapsed = 00:00:10 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 176 ; free virtual = 4777

Phase 3.6 Small Shape Detail Placement
Phase 3.6 Small Shape Detail Placement | Checksum: 1b6de8d33

Time (s): cpu = 00:00:23 ; elapsed = 00:00:11 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 197 ; free virtual = 4800

Phase 3.7 Re-assign LUT pins
Phase 3.7 Re-assign LUT pins | Checksum: 19f762ab5

Time (s): cpu = 00:00:23 ; elapsed = 00:00:11 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 197 ; free virtual = 4800

Phase 3.8 Pipeline Register Optimization
Phase 3.8 Pipeline Register Optimization | Checksum: 12ecf9d46

Time (s): cpu = 00:00:23 ; elapsed = 00:00:11 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 197 ; free virtual = 4800

Phase 3.9 Fast Optimization
Phase 3.9 Fast Optimization | Checksum: 1aeb9bb91

Time (s): cpu = 00:00:29 ; elapsed = 00:00:16 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 99 ; free virtual = 4449
Phase 3 Detail Placement | Checksum: 1aeb9bb91

Time (s): cpu = 00:00:29 ; elapsed = 00:00:16 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 92 ; free virtual = 4446

Phase 4 Post Placement Optimization and Clean-Up

Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.

Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 2084b0e14

Phase 4.1.1.1 BUFG Insertion

Starting Physical Synthesis Task

Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-5.119 | TNS=-226.735 |
Phase 1 Physical Synthesis Initialization | Checksum: 1ba891144

Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 117 ; free virtual = 4398
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0.
Ending Physical Synthesis Task | Checksum: 19b5bb111

Time (s): cpu = 00:00:00.34 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 120 ; free virtual = 4396
Phase 4.1.1.1 BUFG Insertion | Checksum: 2084b0e14

Time (s): cpu = 00:00:31 ; elapsed = 00:00:17 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 115 ; free virtual = 4394
INFO: [Place 30-746] Post Placement Timing Summary WNS=-4.400. For the most accurate timing information please run report_timing.

Time (s): cpu = 00:00:40 ; elapsed = 00:00:25 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 755 ; free virtual = 4702
Phase 4.1 Post Commit Optimization | Checksum: 14ab57cb3

Time (s): cpu = 00:00:40 ; elapsed = 00:00:25 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 810 ; free virtual = 4757

Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 14ab57cb3

Time (s): cpu = 00:00:40 ; elapsed = 00:00:25 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 808 ; free virtual = 4756

Phase 4.3 Placer Reporting

Phase 4.3.1 Print Estimated Congestion
INFO: [Place 30-612] Post-Placement Estimated Congestion 
 ____________________________________________________
|           | Global Congestion | Short Congestion  |
| Direction | Region Size       | Region Size       |
|___________|___________________|___________________|
|      North|                1x1|                2x2|
|___________|___________________|___________________|
|      South|                1x1|                1x1|
|___________|___________________|___________________|
|       East|                1x1|                1x1|
|___________|___________________|___________________|
|       West|                1x1|                1x1|
|___________|___________________|___________________|

Phase 4.3.1 Print Estimated Congestion | Checksum: 14ab57cb3

Time (s): cpu = 00:00:40 ; elapsed = 00:00:25 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 807 ; free virtual = 4755
Phase 4.3 Placer Reporting | Checksum: 14ab57cb3

Time (s): cpu = 00:00:40 ; elapsed = 00:00:25 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 805 ; free virtual = 4755

Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 805 ; free virtual = 4756

Time (s): cpu = 00:00:40 ; elapsed = 00:00:25 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 805 ; free virtual = 4756
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1698d3664

Time (s): cpu = 00:00:40 ; elapsed = 00:00:25 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 802 ; free virtual = 4753
Ending Placer Task | Checksum: bf5d0325

Time (s): cpu = 00:00:40 ; elapsed = 00:00:26 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 739 ; free virtual = 4699
INFO: [Common 17-83] Releasing license: Implementation
72 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:27 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 739 ; free virtual = 4700
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.99 ; elapsed = 00:00:00.32 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 768 ; free virtual = 4745
INFO: [Common 17-1381] The checkpoint '/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.runs/impl_1/VGA_top_placed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_io -file VGA_top_io_placed.rpt
report_io: Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:01 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 748 ; free virtual = 4735
INFO: [runtcl-4] Executing : report_utilization -file VGA_top_utilization_placed.rpt -pb VGA_top_utilization_placed.pb
INFO: [runtcl-4] Executing : report_control_sets -verbose -file VGA_top_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 745 ; free virtual = 4733
Command: phys_opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 716 ; free virtual = 4707

Starting Physical Synthesis Task

Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-4.400 | TNS=-224.136 |
Phase 1 Physical Synthesis Initialization | Checksum: 1446c420d

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.48 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 716 ; free virtual = 4713
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-4.400 | TNS=-224.136 |

Phase 2 DSP Register Optimization
INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design.
INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Phase 2 DSP Register Optimization | Checksum: 1446c420d

Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.67 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 715 ; free virtual = 4714

Phase 3 Critical Path Optimization
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-4.400 | TNS=-224.136 |
INFO: [Physopt 32-702] Processed net SNAKE/ROMAddress_reg[9]_0[0]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/output_reg[7]_0[9]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_1_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_6_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-4.206 | TNS=-223.554 |
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_6_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_22_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_22
INFO: [Physopt 32-134] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_22_n_0. Rewiring did not optimize the net.
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_22_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_14_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_14
INFO: [Physopt 32-572] Net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_14_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_14_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-4.085 | TNS=-223.256 |
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_14_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_14
INFO: [Physopt 32-572] Net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_14_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_14_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_51_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_51
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_51_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_199_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_199
INFO: [Physopt 32-710] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_51_n_0. Critical path length was reduced through logic transformation on cell RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_51_comp.
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_199_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-4.013 | TNS=-223.112 |
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/output_reg[7]_0[0]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-663] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_201_n_0.  Re-placed instance RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_201
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_201_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.972 | TNS=-222.977 |
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_5_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.919 | TNS=-222.924 |
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/output_reg[6]_5[0]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_8_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.884 | TNS=-222.616 |
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_10_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_10
INFO: [Physopt 32-572] Net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_10_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_10_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.853 | TNS=-222.554 |
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_201_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_201
INFO: [Physopt 32-710] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_51_n_0. Critical path length was reduced through logic transformation on cell RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_51_comp_1.
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_201_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.852 | TNS=-222.552 |
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/output_reg[5]_4[9]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_11_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_11
INFO: [Physopt 32-572] Net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_11_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_11_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_31_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_31
INFO: [Physopt 32-710] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_11_n_0. Critical path length was reduced through logic transformation on cell RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_11_comp.
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_31_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.803 | TNS=-222.457 |
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/output_reg[5]_4[0]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_13_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_13
INFO: [Physopt 32-572] Net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_13_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_13_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_47_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_47
INFO: [Physopt 32-710] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_13_n_0. Critical path length was reduced through logic transformation on cell RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_13_comp.
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_47_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.800 | TNS=-222.462 |
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/output_reg[7]_0[3]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_8_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-663] Processed net RAMCTRL/SNAKE_RAM/SNAKE/p_0_out[4].  Re-placed instance RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_23
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/SNAKE/p_0_out[4]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.755 | TNS=-222.239 |
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_5_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_20_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_20
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_20_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_74_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_74
INFO: [Physopt 32-710] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_20_n_0. Critical path length was reduced through logic transformation on cell RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_20_comp.
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_74_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.752 | TNS=-222.237 |
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_90_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_90
INFO: [Physopt 32-572] Net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_90_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_90_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.748 | TNS=-222.199 |
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_3_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_3
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_3_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.745 | TNS=-222.193 |
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_3_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_3
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_3_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_15_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_15
INFO: [Physopt 32-710] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_3_n_0. Critical path length was reduced through logic transformation on cell RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_3_comp.
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_15_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.736 | TNS=-222.167 |
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_6_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.726 | TNS=-222.157 |
INFO: [Physopt 32-702] Processed net U0/inst/clk_out1_clk_wiz_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_31_n_0_repN.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_31_comp_1
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_31_n_0_repN. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_79_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_79
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_79_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.720 | TNS=-222.144 |
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_12_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_12
INFO: [Physopt 32-572] Net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_12_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_12_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_36_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_36
INFO: [Physopt 32-710] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_12_n_0. Critical path length was reduced through logic transformation on cell RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_12_comp.
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_36_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.720 | TNS=-222.145 |
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_21_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_21
INFO: [Physopt 32-572] Net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_21_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_21_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.715 | TNS=-222.109 |
INFO: [Physopt 32-663] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_201_n_0.  Re-placed instance RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_201_comp
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_201_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.713 | TNS=-222.101 |
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/output_reg[1]_7[10]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_18_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_67_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_246_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_246
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_246_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_649_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_649
INFO: [Physopt 32-710] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_246_n_0. Critical path length was reduced through logic transformation on cell RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_246_comp.
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_649_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.709 | TNS=-222.097 |
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/output_reg[3]_8[0]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_36_n_0_repN.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_36_comp_1
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_36_n_0_repN. Optimizations did not improve timing on the net.
INFO: [Physopt 32-663] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_35_n_0.  Re-placed instance RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_35
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_35_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.708 | TNS=-222.095 |
INFO: [Physopt 32-663] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_199_n_0.  Re-placed instance RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_199_comp
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_199_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.707 | TNS=-222.093 |
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_15_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_15
INFO: [Physopt 32-572] Net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_15_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_15_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_47_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_47
INFO: [Physopt 32-710] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_15_n_0. Critical path length was reduced through logic transformation on cell RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_15_comp_1.
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_47_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.705 | TNS=-222.070 |
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/output_reg[3]_8[9]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_47_n_0_repN.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_47_comp
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_47_n_0_repN. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_49_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_49
INFO: [Physopt 32-710] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_47_n_0_repN. Critical path length was reduced through logic transformation on cell RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_47_comp_2.
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_49_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.704 | TNS=-222.068 |
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/output_reg[4]_3[13]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_24_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_24
INFO: [Physopt 32-134] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_24_n_0. Rewiring did not optimize the net.
INFO: [Physopt 32-81] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_24_n_0. Replicated 1 times.
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_24_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.698 | TNS=-222.516 |
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_49_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_49_comp
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_49_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-663] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_192_n_0.  Re-placed instance RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_192
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_192_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.697 | TNS=-222.514 |
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_24_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_24
INFO: [Physopt 32-242] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_24_n_0. Rewired (signal push) RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_11_n_0 to 3 loads. Replicated 1 times.
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_24_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.688 | TNS=-222.678 |
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/output_reg[2]_2[4]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-663] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_37_n_0.  Re-placed instance RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_37
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_37_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.686 | TNS=-222.674 |
INFO: [Physopt 32-663] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_194_n_0.  Re-placed instance RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_194
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_194_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.686 | TNS=-222.674 |
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_14_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_14
INFO: [Physopt 32-572] Net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_14_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_14_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_43_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_96_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.682 | TNS=-222.658 |
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_13_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_13
INFO: [Physopt 32-572] Net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_13_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_13_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_39_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_39
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_39_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.669 | TNS=-222.540 |
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_192_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_192
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_192_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.660 | TNS=-222.523 |
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_201_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_201_comp
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_201_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.652 | TNS=-222.490 |
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/output_reg[6]_5[5]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_16_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_16
INFO: [Physopt 32-572] Net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_16_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_16_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_59_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_59
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_59_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_223_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_223
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_223_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.636 | TNS=-222.474 |
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/SNAKE/p_0_out[4].  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_23
INFO: [Physopt 32-572] Net RAMCTRL/SNAKE_RAM/SNAKE/p_0_out[4] was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/SNAKE/p_0_out[4]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_20_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_20
INFO: [Physopt 32-710] Processed net RAMCTRL/SNAKE_RAM/SNAKE/p_0_out[4]. Critical path length was reduced through logic transformation on cell RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_23_comp.
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_20_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.623 | TNS=-222.430 |
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_201_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_201_comp
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_201_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_200_n_5. Optimizations did not improve timing on the net.
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_550_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.619 | TNS=-222.421 |
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_39_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_39
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_39_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-663] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_92_n_0.  Re-placed instance RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_92
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_92_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.618 | TNS=-222.408 |
INFO: [Physopt 32-663] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_194_n_0.  Re-placed instance RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_194
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_194_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.615 | TNS=-222.403 |
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_551_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net SYNC/comptX_reg[10]_1[1]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net SYNC/ROMAddress[9]_i_896_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-81] Processed net SYNC/Xi[4]. Replicated 1 times.
INFO: [Physopt 32-735] Processed net SYNC/Xi[4]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.611 | TNS=-222.394 |
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_194_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_194
INFO: [Physopt 32-710] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_47_n_0_repN. Critical path length was reduced through logic transformation on cell RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_47_comp.
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_194_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.601 | TNS=-222.374 |
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_21_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_21
INFO: [Physopt 32-572] Net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_21_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_21_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_61_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_61
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_61_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.586 | TNS=-222.344 |
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_10_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_10
INFO: [Physopt 32-572] Net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_10_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_10_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_27_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_27
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_27_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.585 | TNS=-222.342 |
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_199_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_199_comp
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_199_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_202_n_5. Optimizations did not improve timing on the net.
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_558_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.584 | TNS=-222.340 |
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_200_n_7. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_91_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_166_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.584 | TNS=-222.117 |
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_42_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_42
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_42_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.580 | TNS=-222.071 |
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_79_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_79
INFO: [Physopt 32-81] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_79_n_0. Replicated 1 times.
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_79_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.568 | TNS=-222.048 |
INFO: [Physopt 32-81] Processed net SYNC/Xi[4]_repN. Replicated 1 times.
INFO: [Physopt 32-735] Processed net SYNC/Xi[4]_repN. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.565 | TNS=-222.041 |
INFO: [Physopt 32-663] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_24_n_0_repN.  Re-placed instance RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_24_replica
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_24_n_0_repN. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.553 | TNS=-222.321 |
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_559_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net SYNC/comptY_reg[5]_0[1]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net SYNC/ROMAddress_reg[3]_i_77_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/mem_reg_2_0_1[1]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.543 | TNS=-222.298 |
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/output_reg[7]_0[13]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_6_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.540 | TNS=-222.295 |
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/output_reg[7]_0[1]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/mem_reg_2_0_1[0]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.540 | TNS=-222.295 |
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_96_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-663] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_168_n_0.  Re-placed instance RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_168
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_168_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.536 | TNS=-222.287 |
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_1_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_7_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/SNAKE/p_11_out[2].  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_3
INFO: [Physopt 32-572] Net RAMCTRL/SNAKE_RAM/SNAKE/p_11_out[2] was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/SNAKE/p_11_out[2]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-663] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_24_n_0_repN.  Re-placed instance RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_24_replica
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_24_n_0_repN. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.531 | TNS=-221.997 |
INFO: [Physopt 32-702] Processed net SYNC/comptY_reg[5]_0[2]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/S[1]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.528 | TNS=-221.991 |
INFO: [Physopt 32-663] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_33_n_0.  Re-placed instance RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_33
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_33_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.523 | TNS=-221.982 |
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/mem_reg_2_0_1[1]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-81] Processed net SYNC/comptY_reg[9]_0[2]. Replicated 3 times.
INFO: [Physopt 32-735] Processed net SYNC/comptY_reg[9]_0[2]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.520 | TNS=-221.975 |
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/output_reg[4]_3[9]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_53_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_53
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_53_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.516 | TNS=-221.967 |
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/output_reg[4]_3[0]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_53_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_53
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_53_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_209_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_209
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_209_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_274_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_274
INFO: [Physopt 32-81] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_274_n_0. Replicated 1 times.
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_274_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.516 | TNS=-221.967 |
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_170_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_170
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_170_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_781_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_781
INFO: [Physopt 32-710] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_170_n_0. Critical path length was reduced through logic transformation on cell RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_170_comp.
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_781_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.515 | TNS=-221.965 |
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_274_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_274
INFO: [Physopt 32-81] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_274_n_0. Replicated 1 times.
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_274_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.515 | TNS=-221.965 |
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_274_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_274
INFO: [Physopt 32-572] Net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_274_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_274_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.514 | TNS=-221.963 |
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_168_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_168
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_168_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.501 | TNS=-221.937 |
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/output_reg[1]_7[3]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/mem_reg_7_0_3.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_10
INFO: [Physopt 32-81] Processed net RAMCTRL/SNAKE_RAM/mem_reg_7_0_3. Replicated 1 times.
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/mem_reg_7_0_3. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.499 | TNS=-221.273 |
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_202_n_6. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_147_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_228_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net SYNC/comptY_reg[3]_0[3]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-735] Processed net SYNC/ROMAddress[3]_i_194_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.498 | TNS=-221.271 |
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_79_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_79
INFO: [Physopt 32-572] Net RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_79_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_79_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-572] Net RAMCTRL/SNAKE_RAM/mem_reg_2_0_2 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/mem_reg_2_0_2.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_9
INFO: [Physopt 32-710] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_79_n_0. Critical path length was reduced through logic transformation on cell RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_79_comp.
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/mem_reg_2_0_2. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.495 | TNS=-221.265 |
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_9_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.487 | TNS=-221.249 |
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_244_n_4. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_379_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net SYNC/comptY_reg[3]_3[2]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-735] Processed net SYNC/ROMAddress[3]_i_307_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.480 | TNS=-221.235 |
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_24_n_0_repN.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_24_replica
INFO: [Physopt 32-710] Processed net RAMCTRL/SNAKE_RAM/SNAKE/p_11_out[2]. Critical path length was reduced through logic transformation on cell RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_3_comp.
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_24_n_0_repN. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.475 | TNS=-221.098 |
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/output_reg[1]_7[15]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/mem_reg_7_0_3_repN.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_10_replica
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/mem_reg_7_0_3_repN. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.474 | TNS=-221.096 |
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_63_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_63
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_63_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-572] Net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_17_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_17_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_17
INFO: [Physopt 32-710] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_63_n_0. Critical path length was reduced through logic transformation on cell RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_63_comp.
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_17_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.469 | TNS=-221.154 |
INFO: [Physopt 32-663] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_169_n_0.  Re-placed instance RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_169
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_169_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.460 | TNS=-221.136 |
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_24_n_0_repN.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_24_replica
INFO: [Physopt 32-710] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_14_n_0. Critical path length was reduced through logic transformation on cell RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_14_comp.
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_24_n_0_repN. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.458 | TNS=-221.137 |
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_8__0_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-663] Processed net RAMCTRL/SNAKE_RAM/SNAKE/p_11_out[1].  Re-placed instance RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_4
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/SNAKE/p_11_out[1]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.457 | TNS=-220.780 |
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_6_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-663] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_15_n_0.  Re-placed instance RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_15
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_15_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.457 | TNS=-220.780 |
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_32_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_32
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_32_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_81_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_81
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_81_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.449 | TNS=-220.764 |
INFO: [Physopt 32-663] Processed net RAMCTRL/SNAKE_RAM/SNAKE/p_11_out[3].  Re-placed instance RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_2
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/SNAKE/p_11_out[3]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.445 | TNS=-220.568 |
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_166_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net SYNC/comptX_reg[10]_0[1]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/mem_reg_2_0_3[0]. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.444 | TNS=-220.567 |
INFO: [Physopt 32-702] Processed net SYNC/comptX_reg[10]_1[2]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-572] Net SYNC/Xi[5] was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-662] Processed net SYNC/Xi[5].  Did not re-place instance SYNC/cCaseX[1]_i_1
INFO: [Physopt 32-702] Processed net SYNC/Xi[5]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net SYNC/cCaseX[1]_i_2_n_0.  Did not re-place instance SYNC/cCaseX[1]_i_2
INFO: [Physopt 32-710] Processed net SYNC/Xi[5]. Critical path length was reduced through logic transformation on cell SYNC/cCaseX[1]_i_1_comp.
INFO: [Physopt 32-735] Processed net SYNC/cCaseX[1]_i_2_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.432 | TNS=-220.541 |
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_245_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_245
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_245_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_647_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_647
INFO: [Physopt 32-710] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_245_n_0. Critical path length was reduced through logic transformation on cell RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_245_comp.
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_647_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.431 | TNS=-220.540 |
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_33_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_33
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_33_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-663] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_83_n_0.  Re-placed instance RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_83
INFO: [Physopt 32-735] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_83_n_0. Optimization improves timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.430 | TNS=-220.538 |
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/mem_reg_2_0_3[0]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/D[9]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net H125MHz_IBUF. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net H125MHz. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net SNAKE/ROMAddress_reg[9]_0[0]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/output_reg[7]_0[9]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_6_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_22_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_22
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_22_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_14_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_14
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_14_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_51_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_51_comp_1
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_51_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_199_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_199_comp
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_199_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_200_n_7. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_166_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net SYNC/comptX_reg[10]_0[1]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/mem_reg_2_0_3[0]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/D[9]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net H125MHz_IBUF. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net H125MHz. Optimizations did not improve timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.430 | TNS=-220.538 |
Phase 3 Critical Path Optimization | Checksum: 1446c420d

Time (s): cpu = 00:00:46 ; elapsed = 00:00:18 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 160 ; free virtual = 4257

Phase 4 Critical Path Optimization
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.430 | TNS=-220.538 |
INFO: [Physopt 32-702] Processed net SNAKE/ROMAddress_reg[9]_0[0]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/output_reg[7]_0[9]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_1_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_6_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_22_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_22
INFO: [Physopt 32-134] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_22_n_0. Rewiring did not optimize the net.
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_22_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_14_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_14
INFO: [Physopt 32-572] Net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_14_n_0 was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_14_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_51_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_51_comp_1
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_51_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_199_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_199_comp
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_199_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_200_n_7. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_91_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_166_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net SYNC/comptX_reg[10]_0[1]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/mem_reg_2_0_3[0]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/D[9]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net H125MHz_IBUF. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net H125MHz. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net SNAKE/ROMAddress_reg[9]_0[0]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/output_reg[7]_0[9]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_6_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_22_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_22
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_22_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_14_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_14
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_14_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_51_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_51_comp_1
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_51_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-662] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_199_n_0.  Did not re-place instance RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_199_comp
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_199_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_200_n_7. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_166_n_0. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net SYNC/comptX_reg[10]_0[1]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/mem_reg_2_0_3[0]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net RAMCTRL/SNAKE_RAM/D[9]. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net H125MHz_IBUF. Optimizations did not improve timing on the net.
INFO: [Physopt 32-702] Processed net H125MHz. Optimizations did not improve timing on the net.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-3.430 | TNS=-220.538 |
Phase 4 Critical Path Optimization | Checksum: 1446c420d

Time (s): cpu = 00:00:50 ; elapsed = 00:00:19 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 98 ; free virtual = 4146
Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 112 ; free virtual = 4157
INFO: [Physopt 32-603] Post Physical Optimization Timing Summary | WNS=-3.430 | TNS=-220.538 |

Summary of Physical Synthesis Optimizations
============================================


-------------------------------------------------------------------------------------------------------------------------------------------------------------
|  Optimization   |  WNS Gain (ns)  |  TNS Gain (ns)  |  Added Cells  |  Removed Cells  |  Optimized Cells/Nets  |  Dont Touch  |  Iterations  |  Elapsed   |
-------------------------------------------------------------------------------------------------------------------------------------------------------------
|  DSP Register   |          0.000  |          0.000  |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Critical Path  |          0.970  |          3.598  |           11  |              0  |                    81  |           0  |           2  |  00:00:18  |
|  Total          |          0.970  |          3.598  |           11  |              0  |                    81  |           0  |           3  |  00:00:18  |
-------------------------------------------------------------------------------------------------------------------------------------------------------------


Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 113 ; free virtual = 4143
Ending Physical Synthesis Task | Checksum: 21d4da86d

Time (s): cpu = 00:00:50 ; elapsed = 00:00:19 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 116 ; free virtual = 4139
INFO: [Common 17-83] Releasing license: Implementation
548 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
phys_opt_design completed successfully
phys_opt_design: Time (s): cpu = 00:00:52 ; elapsed = 00:00:20 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 120 ; free virtual = 4144
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.41 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 110 ; free virtual = 4083
INFO: [Common 17-1381] The checkpoint '/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.runs/impl_1/VGA_top_physopt.dcp' has been generated.
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
Checksum: PlaceDB: 775974f8 ConstDB: 0 ShapeSum: c117e099 RouteDB: 0

Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: 6ee23b84

Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 658 ; free virtual = 3872
Post Restoration Checksum: NetGraph: 23f5293 NumContArr: 6ca2e8f1 Constraints: 0 Timing: 0

Phase 2 Router Initialization

Phase 2.1 Create Timer
Phase 2.1 Create Timer | Checksum: 6ee23b84

Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 655 ; free virtual = 3872

Phase 2.2 Fix Topology Constraints
Phase 2.2 Fix Topology Constraints | Checksum: 6ee23b84

Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 625 ; free virtual = 3847

Phase 2.3 Pre Route Cleanup
Phase 2.3 Pre Route Cleanup | Checksum: 6ee23b84

Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 625 ; free virtual = 3847
 Number of Nodes with overlaps = 0

Phase 2.4 Update Timing
Phase 2.4 Update Timing | Checksum: d2cf57be

Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 600 ; free virtual = 3848
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-3.439 | TNS=-206.899| WHS=-0.452 | THS=-47.323|

Phase 2 Router Initialization | Checksum: f0a7b30f

Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 596 ; free virtual = 3849

Router Utilization Summary
  Global Vertical Routing Utilization    = 0.0164696 %
  Global Horizontal Routing Utilization  = 0.00643382 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 2437
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 2403
  Number of Partially Routed Nets     = 34
  Number of Node Overlaps             = 24


Phase 3 Initial Routing

Phase 3.1 Global Routing
Phase 3.1 Global Routing | Checksum: f0a7b30f

Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 607 ; free virtual = 3862
Phase 3 Initial Routing | Checksum: d4e5a6fc

Time (s): cpu = 00:00:19 ; elapsed = 00:00:14 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 600 ; free virtual = 3878
INFO: [Route 35-580] Design has 17 pins with tight setup and hold constraints.

The top 5 pins with tight setup and hold constraints:

+--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+
|       Launch Clock       |      Capture Clock       |                                                 Pin                                                      |
+--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+
|              sys_clk_pin |              sys_clk_pin |                                                                                     UPD/writeEnable_reg/D|
|              sys_clk_pin |              sys_clk_pin |                                                                                      UPD/dataOut_reg[8]/D|
|              sys_clk_pin |              sys_clk_pin |                                                                                        UPD/state_reg[2]/D|
|              sys_clk_pin |              sys_clk_pin |                                                                                   UPD/matAddress_reg[4]/D|
|              sys_clk_pin |              sys_clk_pin |                                                                                   UPD/matAddress_reg[3]/D|
+--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+

File with complete list of pins: tight_setup_hold_pins.txt


Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0
 Number of Nodes with overlaps = 1750
 Number of Nodes with overlaps = 857
 Number of Nodes with overlaps = 496
 Number of Nodes with overlaps = 265
 Number of Nodes with overlaps = 159
 Number of Nodes with overlaps = 80
 Number of Nodes with overlaps = 48
 Number of Nodes with overlaps = 15
 Number of Nodes with overlaps = 12
 Number of Nodes with overlaps = 4
 Number of Nodes with overlaps = 1
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-4.439 | TNS=-207.616| WHS=N/A    | THS=N/A    |

Phase 4.1 Global Iteration 0 | Checksum: 1b07b44da

Time (s): cpu = 00:01:48 ; elapsed = 00:00:42 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 454 ; free virtual = 3790

Phase 4.2 Global Iteration 1
 Number of Nodes with overlaps = 233
 Number of Nodes with overlaps = 71
 Number of Nodes with overlaps = 37
 Number of Nodes with overlaps = 20
 Number of Nodes with overlaps = 5
 Number of Nodes with overlaps = 1
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-4.432 | TNS=-206.205| WHS=N/A    | THS=N/A    |

Phase 4.2 Global Iteration 1 | Checksum: 19be42c2e

Time (s): cpu = 00:02:03 ; elapsed = 00:00:53 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 447 ; free virtual = 3807
Phase 4 Rip-up And Reroute | Checksum: 19be42c2e

Time (s): cpu = 00:02:03 ; elapsed = 00:00:53 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 446 ; free virtual = 3807

Phase 5 Delay and Skew Optimization

Phase 5.1 Delay CleanUp

Phase 5.1.1 Update Timing
Phase 5.1.1 Update Timing | Checksum: 1320645b4

Time (s): cpu = 00:02:04 ; elapsed = 00:00:53 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 445 ; free virtual = 3805
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-4.419 | TNS=-204.083| WHS=N/A    | THS=N/A    |

 Number of Nodes with overlaps = 0
Phase 5.1 Delay CleanUp | Checksum: 1b48725e8

Time (s): cpu = 00:02:08 ; elapsed = 00:00:54 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 436 ; free virtual = 3796

Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 1b48725e8

Time (s): cpu = 00:02:08 ; elapsed = 00:00:54 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 435 ; free virtual = 3796
Phase 5 Delay and Skew Optimization | Checksum: 1b48725e8

Time (s): cpu = 00:02:08 ; elapsed = 00:00:54 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 435 ; free virtual = 3796

Phase 6 Post Hold Fix

Phase 6.1 Hold Fix Iter

Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 1909b1d0a

Time (s): cpu = 00:02:08 ; elapsed = 00:00:54 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 433 ; free virtual = 3794
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-4.366 | TNS=-201.449| WHS=0.088  | THS=0.000  |

Phase 6.1 Hold Fix Iter | Checksum: 12511e063

Time (s): cpu = 00:02:08 ; elapsed = 00:00:54 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 433 ; free virtual = 3794
Phase 6 Post Hold Fix | Checksum: 12511e063

Time (s): cpu = 00:02:08 ; elapsed = 00:00:54 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 433 ; free virtual = 3793

Phase 7 Route finalize

Router Utilization Summary
  Global Vertical Routing Utilization    = 3.22241 %
  Global Horizontal Routing Utilization  = 4.24495 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0

Congestion Report
North Dir 1x1 Area, Max Cong = 49.5495%, No Congested Regions.
South Dir 1x1 Area, Max Cong = 67.5676%, No Congested Regions.
East Dir 1x1 Area, Max Cong = 69.1176%, No Congested Regions.
West Dir 1x1 Area, Max Cong = 70.5882%, No Congested Regions.

------------------------------
Reporting congestion hotspots
------------------------------
Direction: North
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: South
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: East
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: West
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0

Phase 7 Route finalize | Checksum: 149019589

Time (s): cpu = 00:02:08 ; elapsed = 00:00:55 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 432 ; free virtual = 3793

Phase 8 Verifying routed nets

 Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 149019589

Time (s): cpu = 00:02:09 ; elapsed = 00:00:55 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 432 ; free virtual = 3793

Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 18541e61b

Time (s): cpu = 00:02:09 ; elapsed = 00:00:55 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 428 ; free virtual = 3789

Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=-4.366 | TNS=-201.449| WHS=0.088  | THS=0.000  |

WARNING: [Route 35-328] Router estimated timing not met.
Resolution: For a complete and accurate timing signoff, report_timing_summary must be run after route_design. Alternatively, route_design can be run with the -timing_summary option to enable a complete timing signoff at the end of route_design.
Phase 10 Post Router Timing | Checksum: 18541e61b

Time (s): cpu = 00:02:09 ; elapsed = 00:00:55 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 428 ; free virtual = 3789
INFO: [Route 35-16] Router Completed Successfully

Time (s): cpu = 00:02:09 ; elapsed = 00:00:55 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 478 ; free virtual = 3839

Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
567 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:02:14 ; elapsed = 00:01:05 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 478 ; free virtual = 3840
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.42 . Memory (MB): peak = 2970.512 ; gain = 0.000 ; free physical = 452 ; free virtual = 3828
INFO: [Common 17-1381] The checkpoint '/home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.runs/impl_1/VGA_top_routed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx
Command: report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Coretcl 2-168] The results of DRC are in file /home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.runs/impl_1/VGA_top_drc_routed.rpt.
report_drc completed successfully
INFO: [runtcl-4] Executing : report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx
Command: report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-133] Running Methodology with 8 threads
INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/leo/projet-electronique/projet-electronique-clean/projet-electronique-clean.runs/impl_1/VGA_top_methodology_drc_routed.rpt.
report_methodology completed successfully
INFO: [runtcl-4] Executing : report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx
Command: report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
579 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
INFO: [runtcl-4] Executing : report_route_status -file VGA_top_route_status.rpt -pb VGA_top_route_status.pb
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file VGA_top_timing_summary_routed.rpt -pb VGA_top_timing_summary_routed.pb -rpx VGA_top_timing_summary_routed.rpx -warn_on_violation 
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
CRITICAL WARNING: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.
INFO: [runtcl-4] Executing : report_incremental_reuse -file VGA_top_incremental_reuse_routed.rpt
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
INFO: [runtcl-4] Executing : report_clock_utilization -file VGA_top_clock_utilization_routed.rpt
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file VGA_top_bus_skew_routed.rpt -pb VGA_top_bus_skew_routed.pb -rpx VGA_top_bus_skew_routed.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
Command: write_bitstream -force VGA_top.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 8 threads
WARNING: [DRC PDRC-153] Gated clock check: Net UPD/resetPomme_reg_1 is a gated clock net sourced by a combinational pin UPD/state_reg[3]_LDC_i_1/O, cell UPD/state_reg[3]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 2 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Writing bitstream ./VGA_top.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-83] Releasing license: Implementation
12 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:18 ; elapsed = 00:00:35 . Memory (MB): peak = 3226.406 ; gain = 197.031 ; free physical = 946 ; free virtual = 4590
INFO: [Common 17-206] Exiting Vivado at Tue Jan 11 11:44:09 2022...
