Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec  6 23:38:27 MST 2018
| Date         : Tue Jan  4 12:21:24 2022
| Host         : irb121-12-w running 64-bit major release  (build 9200)
| Command      : report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx
| Design       : VGA_top
| Device       : xc7z010clg400-1
| Speed File   : -1
| Design State : Fully Routed
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Report Methodology

Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS

1. REPORT SUMMARY
-----------------
            Netlist: netlist
          Floorplan: design_1
      Design limits: <entire design considered>
             Max violations: <unlimited>
             Violations found: 95
+-----------+----------+----------------------------------------------------+------------+
| Rule      | Severity | Description                                        | Violations |
+-----------+----------+----------------------------------------------------+------------+
| LUTAR-1   | Warning  | LUT drives async reset alert                       | 14         |
| SYNTH-6   | Warning  | Timing of a block RAM might be sub-optimal         | 26         |
| TIMING-4  | Warning  | Invalid primary clock redefinition on a clock tree | 1          |
| TIMING-6  | Warning  | No common primary clock between related clocks     | 2          |
| TIMING-7  | Warning  | No common node between related clocks              | 2          |
| TIMING-16 | Warning  | Large setup violation                              | 21         |
| TIMING-18 | Warning  | Missing input or output delay                      | 5          |
| TIMING-20 | Warning  | Non-clocked latch                                  | 23         |
| TIMING-27 | Warning  | Invalid primary clock on hierarchical pin          | 1          |
+-----------+----------+----------------------------------------------------+------------+

2. REPORT DETAILS
-----------------
LUTAR-1#1 Warning
LUT drives async reset alert  
LUT cell SNAKE/startUpdate_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) SNAKE/startUpdate_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
Related violations: <none>

LUTAR-1#2 Warning
LUT drives async reset alert  
LUT cell UPD/dataOut_reg[18]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) UPD/dataOut_reg[18]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
Related violations: <none>

LUTAR-1#3 Warning
LUT drives async reset alert  
LUT cell UPD/dataOut_reg[18]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) UPD/dataOut_reg[18]_C/CLR, UPD/dataOut_reg[18]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
Related violations: <none>

LUTAR-1#4 Warning
LUT drives async reset alert  
LUT cell UPD/dataOut_reg[19]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) UPD/dataOut_reg[19]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
Related violations: <none>

LUTAR-1#5 Warning
LUT drives async reset alert  
LUT cell UPD/dataOut_reg[19]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) UPD/dataOut_reg[19]_C/CLR, UPD/dataOut_reg[19]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
Related violations: <none>

LUTAR-1#6 Warning
LUT drives async reset alert  
LUT cell UPD/dataOut_reg[1]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) UPD/dataOut_reg[1]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
Related violations: <none>

LUTAR-1#7 Warning
LUT drives async reset alert  
LUT cell UPD/dataOut_reg[1]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) UPD/dataOut_reg[1]_C/CLR, UPD/dataOut_reg[1]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
Related violations: <none>

LUTAR-1#8 Warning
LUT drives async reset alert  
LUT cell UPD/dataOut_reg[20]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) UPD/dataOut_reg[20]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
Related violations: <none>

LUTAR-1#9 Warning
LUT drives async reset alert  
LUT cell UPD/dataOut_reg[20]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) UPD/dataOut_reg[20]_C/CLR, UPD/dataOut_reg[20]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
Related violations: <none>

LUTAR-1#10 Warning
LUT drives async reset alert  
LUT cell UPD/dataOut_reg[21]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) UPD/dataOut_reg[21]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
Related violations: <none>

LUTAR-1#11 Warning
LUT drives async reset alert  
LUT cell UPD/dataOut_reg[21]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) UPD/dataOut_reg[21]_C/CLR, UPD/dataOut_reg[21]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
Related violations: <none>

LUTAR-1#12 Warning
LUT drives async reset alert  
LUT cell UPD/dataOut_reg[4]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) UPD/dataOut_reg[0]_P/PRE, UPD/dataOut_reg[3]_P/PRE, UPD/dataOut_reg[4]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
Related violations: <none>

LUTAR-1#13 Warning
LUT drives async reset alert  
LUT cell UPD/dataOut_reg[4]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) UPD/dataOut_reg[0]_C/CLR, UPD/dataOut_reg[3]_C/CLR, UPD/dataOut_reg[4]_C/CLR, UPD/dataOut_reg[4]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
Related violations: <none>

LUTAR-1#14 Warning
LUT drives async reset alert  
LUT cell UPD_CLK_DIV/temp[0]_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) UPD_CLK_DIV/temp_reg[0]/CLR, UPD_CLK_DIV/temp_reg[10]/CLR, UPD_CLK_DIV/temp_reg[11]/CLR, UPD_CLK_DIV/temp_reg[12]/CLR, UPD_CLK_DIV/temp_reg[13]/CLR, UPD_CLK_DIV/temp_reg[14]/CLR, UPD_CLK_DIV/temp_reg[15]/CLR, UPD_CLK_DIV/temp_reg[16]/CLR, UPD_CLK_DIV/temp_reg[17]/CLR, UPD_CLK_DIV/temp_reg[18]/CLR, UPD_CLK_DIV/temp_reg[19]/CLR, UPD_CLK_DIV/temp_reg[1]/CLR, UPD_CLK_DIV/temp_reg[20]/CLR, UPD_CLK_DIV/temp_reg[21]/CLR, UPD_CLK_DIV/temp_reg[22]/CLR (the first 15 of 25 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
Related violations: <none>

SYNTH-6#1 Warning
Timing of a block RAM might be sub-optimal  
The timing for the instance RAMCTRL/MAT_RAM/mem_reg_1, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
Related violations: <none>

SYNTH-6#2 Warning
Timing of a block RAM might be sub-optimal  
The timing for the instance RAMCTRL/MAT_RAM/mem_reg_2, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
Related violations: <none>

SYNTH-6#3 Warning
Timing of a block RAM might be sub-optimal  
The timing for the instance RAMCTRL/MAT_RAM/mem_reg_3, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
Related violations: <none>

SYNTH-6#4 Warning
Timing of a block RAM might be sub-optimal  
The timing for the instance RAMCTRL/MAT_RAM/mem_reg_4, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
Related violations: <none>

SYNTH-6#5 Warning
Timing of a block RAM might be sub-optimal  
The timing for the instance RAMCTRL/MAT_RAM/mem_reg_6, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
Related violations: <none>

SYNTH-6#6 Warning
Timing of a block RAM might be sub-optimal  
The timing for the instance RAMCTRL/MAT_RAM/mem_reg_7, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
Related violations: <none>

SYNTH-6#7 Warning
Timing of a block RAM might be sub-optimal  
The timing for the instance RAMCTRL/MAT_RAM/mem_reg_8, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
Related violations: <none>

SYNTH-6#8 Warning
Timing of a block RAM might be sub-optimal  
The timing for the instance RAMCTRL/MAT_RAM/mem_reg_9, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
Related violations: <none>

SYNTH-6#9 Warning
Timing of a block RAM might be sub-optimal  
The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_1_0, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
Related violations: <none>

SYNTH-6#10 Warning
Timing of a block RAM might be sub-optimal  
The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_1_1, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
Related violations: <none>

SYNTH-6#11 Warning
Timing of a block RAM might be sub-optimal  
The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_2_0, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
Related violations: <none>

SYNTH-6#12 Warning
Timing of a block RAM might be sub-optimal  
The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_2_1, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
Related violations: <none>

SYNTH-6#13 Warning
Timing of a block RAM might be sub-optimal  
The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_3_0, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
Related violations: <none>

SYNTH-6#14 Warning
Timing of a block RAM might be sub-optimal  
The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_3_1, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
Related violations: <none>

SYNTH-6#15 Warning
Timing of a block RAM might be sub-optimal  
The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_4_0, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
Related violations: <none>

SYNTH-6#16 Warning
Timing of a block RAM might be sub-optimal  
The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_4_1, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
Related violations: <none>

SYNTH-6#17 Warning
Timing of a block RAM might be sub-optimal  
The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_5_0, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
Related violations: <none>

SYNTH-6#18 Warning
Timing of a block RAM might be sub-optimal  
The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_5_1, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
Related violations: <none>

SYNTH-6#19 Warning
Timing of a block RAM might be sub-optimal  
The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_6_0, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
Related violations: <none>

SYNTH-6#20 Warning
Timing of a block RAM might be sub-optimal  
The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_6_1, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
Related violations: <none>

SYNTH-6#21 Warning
Timing of a block RAM might be sub-optimal  
The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_7_0, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
Related violations: <none>

SYNTH-6#22 Warning
Timing of a block RAM might be sub-optimal  
The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_7_1, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
Related violations: <none>

SYNTH-6#23 Warning
Timing of a block RAM might be sub-optimal  
The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_8_0, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
Related violations: <none>

SYNTH-6#24 Warning
Timing of a block RAM might be sub-optimal  
The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_8_1, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
Related violations: <none>

SYNTH-6#25 Warning
Timing of a block RAM might be sub-optimal  
The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_9_0, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
Related violations: <none>

SYNTH-6#26 Warning
Timing of a block RAM might be sub-optimal  
The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_9_1, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
Related violations: <none>

TIMING-4#1 Warning
Invalid primary clock redefinition on a clock tree  
Invalid clock redefinition on a clock tree. The primary clock U0/inst/clk_in1 is defined downstream of clock sys_clk_pin and overrides its insertion delay and/or waveform definition
Related violations: <none>

TIMING-6#1 Warning
No common primary clock between related clocks  
The clocks clk_out1_clk_wiz_1 and sys_clk_pin are related (timed together) but they have no common primary clock. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks clk_out1_clk_wiz_1] -to [get_clocks sys_clk_pin]
Related violations: <none>

TIMING-6#2 Warning
No common primary clock between related clocks  
The clocks sys_clk_pin and clk_out1_clk_wiz_1 are related (timed together) but they have no common primary clock. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks sys_clk_pin] -to [get_clocks clk_out1_clk_wiz_1]
Related violations: <none>

TIMING-7#1 Warning
No common node between related clocks  
The clocks clk_out1_clk_wiz_1 and sys_clk_pin are related (timed together) but they have no common node. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks clk_out1_clk_wiz_1] -to [get_clocks sys_clk_pin]
Related violations: <none>

TIMING-7#2 Warning
No common node between related clocks  
The clocks sys_clk_pin and clk_out1_clk_wiz_1 are related (timed together) but they have no common node. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks sys_clk_pin] -to [get_clocks clk_out1_clk_wiz_1]
Related violations: <none>

TIMING-16#1 Warning
Large setup violation  
There is a large setup violation of -2.757 ns between RAMCTRL/SNAKE_RAM/mem_reg_4_1/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/snakeHere_reg/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#2 Warning
Large setup violation  
There is a large setup violation of -3.112 ns between RAMCTRL/SNAKE_RAM/mem_reg_5_1/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[0]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#3 Warning
Large setup violation  
There is a large setup violation of -3.660 ns between RAMCTRL/SNAKE_RAM/mem_reg_7_0/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[1]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#4 Warning
Large setup violation  
There is a large setup violation of -3.702 ns between RAMCTRL/SNAKE_RAM/mem_reg_4_1/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[0]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#5 Warning
Large setup violation  
There is a large setup violation of -3.702 ns between RAMCTRL/SNAKE_RAM/mem_reg_4_1/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[1]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#6 Warning
Large setup violation  
There is a large setup violation of -3.702 ns between RAMCTRL/SNAKE_RAM/mem_reg_4_1/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[2]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#7 Warning
Large setup violation  
There is a large setup violation of -3.702 ns between RAMCTRL/SNAKE_RAM/mem_reg_4_1/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[3]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#8 Warning
Large setup violation  
There is a large setup violation of -3.740 ns between RAMCTRL/SNAKE_RAM/mem_reg_4_1/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[8]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#9 Warning
Large setup violation  
There is a large setup violation of -3.740 ns between RAMCTRL/SNAKE_RAM/mem_reg_4_1/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[9]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#10 Warning
Large setup violation  
There is a large setup violation of -3.881 ns between RAMCTRL/SNAKE_RAM/mem_reg_4_1/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[4]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#11 Warning
Large setup violation  
There is a large setup violation of -3.881 ns between RAMCTRL/SNAKE_RAM/mem_reg_4_1/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[5]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#12 Warning
Large setup violation  
There is a large setup violation of -3.881 ns between RAMCTRL/SNAKE_RAM/mem_reg_4_1/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[6]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#13 Warning
Large setup violation  
There is a large setup violation of -3.881 ns between RAMCTRL/SNAKE_RAM/mem_reg_4_1/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[7]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#14 Warning
Large setup violation  
There is a large setup violation of -4.008 ns between RAMCTRL/SNAKE_RAM/mem_reg_7_0/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[2]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#15 Warning
Large setup violation  
There is a large setup violation of -4.073 ns between RAMCTRL/SNAKE_RAM/mem_reg_7_0/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[3]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#16 Warning
Large setup violation  
There is a large setup violation of -4.846 ns between RAMCTRL/SNAKE_RAM/mem_reg_7_0/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[4]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#17 Warning
Large setup violation  
There is a large setup violation of -4.866 ns between RAMCTRL/SNAKE_RAM/mem_reg_7_0/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[6]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#18 Warning
Large setup violation  
There is a large setup violation of -4.942 ns between RAMCTRL/SNAKE_RAM/mem_reg_7_0/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[7]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#19 Warning
Large setup violation  
There is a large setup violation of -4.950 ns between RAMCTRL/SNAKE_RAM/mem_reg_7_0/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[5]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#20 Warning
Large setup violation  
There is a large setup violation of -5.507 ns between RAMCTRL/SNAKE_RAM/mem_reg_5_0/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[8]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-16#21 Warning
Large setup violation  
There is a large setup violation of -5.611 ns between RAMCTRL/SNAKE_RAM/mem_reg_5_0/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[9]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture
Related violations: <none>

TIMING-18#1 Warning
Missing input or output delay  
An input delay is missing on resetGeneral relative to clock(s) sys_clk_pin
Related violations: <none>

TIMING-18#2 Warning
Missing input or output delay  
An output delay is missing on led[0] relative to clock(s) sys_clk_pin
Related violations: <none>

TIMING-18#3 Warning
Missing input or output delay  
An output delay is missing on led[1] relative to clock(s) sys_clk_pin
Related violations: <none>

TIMING-18#4 Warning
Missing input or output delay  
An output delay is missing on led[2] relative to clock(s) sys_clk_pin
Related violations: <none>

TIMING-18#5 Warning
Missing input or output delay  
An output delay is missing on led[3] relative to clock(s) sys_clk_pin
Related violations: <none>

TIMING-20#1 Warning
Non-clocked latch  
The latch UPD/currentSnake_reg[X][4] cannot be properly analyzed as its control pin UPD/currentSnake_reg[X][4]/G is not reached by a timing clock
Related violations: <none>

TIMING-20#2 Warning
Non-clocked latch  
The latch UPD/currentSnake_reg[X][5] cannot be properly analyzed as its control pin UPD/currentSnake_reg[X][5]/G is not reached by a timing clock
Related violations: <none>

TIMING-20#3 Warning
Non-clocked latch  
The latch UPD/currentSnake_reg[X][6] cannot be properly analyzed as its control pin UPD/currentSnake_reg[X][6]/G is not reached by a timing clock
Related violations: <none>

TIMING-20#4 Warning
Non-clocked latch  
The latch UPD/currentSnake_reg[X][7] cannot be properly analyzed as its control pin UPD/currentSnake_reg[X][7]/G is not reached by a timing clock
Related violations: <none>

TIMING-20#5 Warning
Non-clocked latch  
The latch UPD/currentSnake_reg[dirX][1] cannot be properly analyzed as its control pin UPD/currentSnake_reg[dirX][1]/G is not reached by a timing clock
Related violations: <none>

TIMING-20#6 Warning
Non-clocked latch  
The latch UPD/currentSnake_reg[dirY][0] cannot be properly analyzed as its control pin UPD/currentSnake_reg[dirY][0]/G is not reached by a timing clock
Related violations: <none>

TIMING-20#7 Warning
Non-clocked latch  
The latch UPD/dataOut_reg[18]_LDC cannot be properly analyzed as its control pin UPD/dataOut_reg[18]_LDC/G is not reached by a timing clock
Related violations: <none>

TIMING-20#8 Warning
Non-clocked latch  
The latch UPD/dataOut_reg[19]_LDC cannot be properly analyzed as its control pin UPD/dataOut_reg[19]_LDC/G is not reached by a timing clock
Related violations: <none>

TIMING-20#9 Warning
Non-clocked latch  
The latch UPD/dataOut_reg[1]_LDC cannot be properly analyzed as its control pin UPD/dataOut_reg[1]_LDC/G is not reached by a timing clock
Related violations: <none>

TIMING-20#10 Warning
Non-clocked latch  
The latch UPD/dataOut_reg[20]_LDC cannot be properly analyzed as its control pin UPD/dataOut_reg[20]_LDC/G is not reached by a timing clock
Related violations: <none>

TIMING-20#11 Warning
Non-clocked latch  
The latch UPD/dataOut_reg[21]_LDC cannot be properly analyzed as its control pin UPD/dataOut_reg[21]_LDC/G is not reached by a timing clock
Related violations: <none>

TIMING-20#12 Warning
Non-clocked latch  
The latch UPD/dataOut_reg[4]_LDC cannot be properly analyzed as its control pin UPD/dataOut_reg[4]_LDC/G is not reached by a timing clock
Related violations: <none>

TIMING-20#13 Warning
Non-clocked latch  
The latch UPD/matAddress_reg[0] cannot be properly analyzed as its control pin UPD/matAddress_reg[0]/G is not reached by a timing clock
Related violations: <none>

TIMING-20#14 Warning
Non-clocked latch  
The latch UPD/matAddress_reg[10] cannot be properly analyzed as its control pin UPD/matAddress_reg[10]/G is not reached by a timing clock
Related violations: <none>

TIMING-20#15 Warning
Non-clocked latch  
The latch UPD/matAddress_reg[1] cannot be properly analyzed as its control pin UPD/matAddress_reg[1]/G is not reached by a timing clock
Related violations: <none>

TIMING-20#16 Warning
Non-clocked latch  
The latch UPD/matAddress_reg[2] cannot be properly analyzed as its control pin UPD/matAddress_reg[2]/G is not reached by a timing clock
Related violations: <none>

TIMING-20#17 Warning
Non-clocked latch  
The latch UPD/matAddress_reg[3] cannot be properly analyzed as its control pin UPD/matAddress_reg[3]/G is not reached by a timing clock
Related violations: <none>

TIMING-20#18 Warning
Non-clocked latch  
The latch UPD/matAddress_reg[4] cannot be properly analyzed as its control pin UPD/matAddress_reg[4]/G is not reached by a timing clock
Related violations: <none>

TIMING-20#19 Warning
Non-clocked latch  
The latch UPD/matAddress_reg[5] cannot be properly analyzed as its control pin UPD/matAddress_reg[5]/G is not reached by a timing clock
Related violations: <none>

TIMING-20#20 Warning
Non-clocked latch  
The latch UPD/matAddress_reg[6] cannot be properly analyzed as its control pin UPD/matAddress_reg[6]/G is not reached by a timing clock
Related violations: <none>

TIMING-20#21 Warning
Non-clocked latch  
The latch UPD/matAddress_reg[7] cannot be properly analyzed as its control pin UPD/matAddress_reg[7]/G is not reached by a timing clock
Related violations: <none>

TIMING-20#22 Warning
Non-clocked latch  
The latch UPD/matAddress_reg[8] cannot be properly analyzed as its control pin UPD/matAddress_reg[8]/G is not reached by a timing clock
Related violations: <none>

TIMING-20#23 Warning
Non-clocked latch  
The latch UPD/matAddress_reg[9] cannot be properly analyzed as its control pin UPD/matAddress_reg[9]/G is not reached by a timing clock
Related violations: <none>

TIMING-27#1 Warning
Invalid primary clock on hierarchical pin  
A primary clock U0/inst/clk_in1 is created on an inappropriate internal pin U0/inst/clk_in1. It is not recommended to create a primary clock on a hierarchical pin when its driver pin has a fanout connected to multiple clock pins
Related violations: <none>


