----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 19.10.2017 08:01:54
-- Design Name: 
-- Module Name: VGA_top - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

library ourTypes;
use ourTypes.types.all;

entity VGA_top is
    Port ( H125MHz : in STD_LOGIC;
           resetGeneral : in std_logic;
           led : out std_logic_vector (3 downto 0);
           vga_hs : out STD_LOGIC;
           vga_vs : out STD_LOGIC;
           vga_r : out STD_LOGIC_VECTOR (4 downto 0);
           vga_g : out STD_LOGIC_VECTOR (5 downto 0);
           vga_b : out STD_LOGIC_VECTOR (4 downto 0));
end VGA_top;

architecture Behavioral of VGA_top is

component clk_wiz_0
port
 (-- Clock in ports
  clk_in1           : in     std_logic;
  -- Clock out ports
  clk_out1          : out    std_logic
 );
end component;

ATTRIBUTE SYN_BLACK_BOX : BOOLEAN;
ATTRIBUTE SYN_BLACK_BOX OF clk_wiz_0 : COMPONENT IS TRUE;

ATTRIBUTE BLACK_BOX_PAD_PIN : STRING;
ATTRIBUTE BLACK_BOX_PAD_PIN OF clk_wiz_0 : COMPONENT IS "clk_in1,clk_out1";

component GeneSync is
    Port ( CLK   : in std_logic;
           HSYNC : out std_logic;
           VSYNC : out std_logic;
		   IMG   : out std_logic;
           X     : out std_logic_vector(9 downto 0);
           Y     : out std_logic_vector(8 downto 0));
end component;

component GeneRGB_V1  is
    Port ( 
	       X     : in unsigned(9 downto 0);
           Y     : in unsigned(8 downto 0);
           IMG   : in std_logic;
		   R     : out std_logic_vector(4 downto 0);
           G     : out std_logic_vector(5 downto 0);
           B     : out std_logic_vector(4 downto 0);
           snakeIn : in color);
end component;

component Gene_Snake
generic ( addressSize : integer:=SNAKE_ADDRESS_SIZE);
Port ( X : in unsigned (9 downto 0);
       Y : in unsigned (8 downto 0);
       clk: in std_logic;
       reset: in std_logic;
       
       currentSnake : in pos;
       updateOrder : in std_logic;
       listRef : in unsigned(addressSize-1 downto 0);
       
       colorOut : out color;
       
       currentAddress : out unsigned(addressSize-1 downto 0);
       matAddress : out unsigned(addressSize-1 downto 0);
       
       ROMAddress : out unsigned(SPRITES_ADDRESS_SIZE-1 downto 0);
       ROMData : in std_logic_vector(SPRITES_DATA_SIZE-1 downto 0)
       
       );
end component Gene_Snake;

signal dummyPos : pos; --juste pour avoir la taille du type
component updateSnake
generic ( dataSize : integer := to_stdlogicvector(dummyPos)'length);
Port (
        clk : in std_logic;
        reset : in std_logic;
        
        address : out unsigned(SNAKE_ADDRESS_SIZE-1 downto 0);
        data : out std_logic_vector(dataSize-1 downto 0);
        writeEnable : out std_logic;
        
        matAddress : out unsigned(SNAKE_ADDRESS_SIZE-1 downto 0);
        matData : out unsigned(SNAKE_ADDRESS_SIZE-1 downto 0);
        matWriteEnable : out std_logic
        );
end component updateSnake;

component snakeRam
generic (length : integer;
        addressSize : integer;
        dataSize : integer
);
Port ( address1 : in unsigned(addressSize-1 downto 0);
       data1 : out std_logic_vector(dataSize-1 downto 0);
       writeEnable1 : in STD_LOGIC;
       clk1 : in STD_LOGIC;
           
       address2 : in unsigned(addressSize-1 downto 0);
       data2 : in std_logic_vector(dataSize-1 downto 0);
       writeEnable2 : in STD_LOGIC;
       clk2 : in STD_LOGIC);
end component snakeRam;

component spritesRom
generic( addressSize : integer := SPRITES_ADDRESS_SIZE;
         length : integer := SPRITES_DATA_LENGTH;
         dataSize : integer := SPRITES_DATA_SIZE;
         fileName : string := "/home/leo/projet-electronique/sprites/sprites.mem"
);
Port ( address : in unsigned (addressSize-1 downto 0);
       data : out STD_LOGIC_VECTOR (dataSize-1 downto 0);
       clk : in STD_LOGIC);
end component spritesRom;

component Diviseur
  generic (nbBits : integer:=8);
  Port (  clk_in : in STD_LOGIC;
          reset : in STD_LOGIC;
          max : in unsigned (nbBits-1 downto 0);
          clk_out : out STD_LOGIC);
end component Diviseur;

signal Xi          : std_logic_vector(9 downto 0);
signal Yi          : std_logic_vector(8 downto 0);
signal Xpxl        : unsigned(9 downto 0);
signal Ypxl        : unsigned(8 downto 0);
signal IMGi        : std_logic;  
signal pxl_clk     : std_logic;

signal clk_lente: std_logic;
signal valPosX: unsigned (9 downto 0);
signal valPosY: unsigned (8 downto 0);
signal snakeColor: color;

signal displayRAMAddress : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0);
signal displayRAMData : std_logic_vector(to_stdlogicvector(dummyPos)'length-1 downto 0);

signal updateRAMAddress : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0);
signal updateRAMData : std_logic_vector(to_stdlogicvector(dummyPos)'length-1 downto 0);
signal updateRAMWE : std_logic;

signal matdispRAMAddress : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0);
signal matdispRAMData : std_logic_vector(SNAKE_ADDRESS_SIZE-1 downto 0);

signal matupdRAMAddress : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0);
signal matupdRAMData : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0);
signal matupdRAMWE : std_logic;

signal spritesROMAddress : unsigned(SPRITES_ADDRESS_SIZE-1 downto 0);
signal spritesROMData : std_logic_vector(SPRITES_DATA_SIZE-1 downto 0);

signal clk_latch : std_logic;

begin

Xpxl <= unsigned(Xi);
Ypxl <= unsigned(Yi);

U0 : clk_wiz_0
   port map ( 
   -- Clock in ports
   clk_in1 => H125MHz,
  -- Clock out ports  
   clk_out1 => pxl_clk              
 );
 
U1 : GeneSync 
    port map(
    CLK    => pxl_clk,
    HSYNC  => vga_hs,
    VSYNC  => vga_vs,
    IMG    => IMGi,
	X      => Xi,
    Y      => Yi);
	 
U2 : GeneRGB_V1  
    port map(
	X     => Xpxl,
    Y     => Ypxl,
    IMG   => IMGi,
    R     => vga_r,
    G     => vga_g,
    B     => vga_b,
    snakeIn => snakeColor);
    
U3 : Diviseur
    -- pxl_clock 25MHz, clk_lente ~60Hz, 1 coup sur clk_lente = 25e6/60 = 4.2e5 coups sur pxl_clk. ln(4.2e5)/ln(2)=18.6, donc on prend 19bits
    generic map (nbBits => 19)
    port map (
      clk_in => pxl_clk,
      reset => resetGeneral,
      max => to_unsigned(420000,19),
      clk_out => clk_lente
    );
    
U4 : Gene_Snake
    port map (
      X => Xpxl,
      Y => Ypxl,
      clk => H125Mhz,
      reset => resetGeneral,
      currentSnake => to_pos(displayRamData),
      updateOrder => pxl_clk,
      listRef => unsigned(matdispRAMData),
      colorOut => snakeColor,
      currentAddress => displayRamAddress,
      matAddress => matdispRAMAddress,
      ROMAddress => spritesROMAddress,
      ROMData => spritesROMData
    );

U5 : updateSnake
    port map (
        clk => H125MHz,
        reset => resetGeneral,
        
        address => updateRAMAddress,
        data => updateRAMData,
        writeEnable => updateRAMWE,
        
        matAddress => matupdRAMAddress,
        matData => matupdRAMData,
        matWriteEnable => matupdRAMWE
    );
    
U6 : snakeRAM --La RAM pour le snake
    generic map (
        length => MAX_SNAKE,
        addressSize => SNAKE_ADDRESS_SIZE,
        dataSize => to_stdlogicvector(dummyPos)'length
    )
    port map (
        address1 => displayRAMAddress,
        data1 => displayRAMdata,
        writeEnable1 => '0',
        clk1 => H125MHz,
        
        address2 => updateRAMAddress,
        data2 => updateRAMData,
        writeEnable2 => updateRAMWE,
        clk2 => H125MHz
    );
    
U7 : snakeRAM --La RAM pour la matrice de correspondance
    generic map (
        length => MAX_SNAKE,
        addressSize => SNAKE_ADDRESS_SIZE,
        dataSize => SNAKE_ADDRESS_SIZE
    )
    port map (
        address1 => matdispRAMAddress,
        data1 => matdispRAMdata,
        writeEnable1 => '0',
        clk1 => H125MHz,
        
        address2 => matupdRAMAddress,
        data2 => std_logic_vector(matupdRAMData),
        writeEnable2 => matupdRAMWE,
        clk2 => H125MHz
    );
    
 U8 : spritesROM
    port map(
        address => spritesROMAddress,
        data => spritesROMData,
        clk => H125MHz
    );

led(0) <= resetGeneral;
led(1) <= updateRAMWE;
end Behavioral;
