#-----------------------------------------------------------
# Vivado v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec  6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec  7 01:43:56 MST 2018
# Start of session at: Tue Dec  7 12:41:01 2021
# Process ID: 5952
# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/synth_1
# Command line: vivado.exe -log VGA_top.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source VGA_top.tcl
# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/synth_1/VGA_top.vds
# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/synth_1\vivado.jou
#-----------------------------------------------------------
source VGA_top.tcl -notrace
Command: synth_design -top VGA_top -part xc7z010clg400-1
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010'
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 12208 
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Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 467.680 ; gain = 94.113
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INFO: [Synth 8-638] synthesizing module 'VGA_top' [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/VGA_top.vhd:48]
INFO: [Synth 8-637] synthesizing blackbox instance 'U0' of component 'clk_wiz_0' [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/VGA_top.vhd:148]
INFO: [Synth 8-3491] module 'GeneSync' declared at 'C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/GeneSync.vhd:7' bound to instance 'U1' of component 'GeneSync' [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/VGA_top.vhd:156]
INFO: [Synth 8-638] synthesizing module 'GeneSync' [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/GeneSync.vhd:16]
INFO: [Synth 8-256] done synthesizing module 'GeneSync' (1#1) [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/GeneSync.vhd:16]
INFO: [Synth 8-3491] module 'GeneRGB_V1' declared at 'C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/GeneRGB_V1.vhd:36' bound to instance 'U2' of component 'GeneRGB_V1' [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/VGA_top.vhd:165]
INFO: [Synth 8-638] synthesizing module 'GeneRGB_V1' [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/GeneRGB_V1.vhd:47]
INFO: [Synth 8-256] done synthesizing module 'GeneRGB_V1' (2#1) [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/GeneRGB_V1.vhd:47]
INFO: [Synth 8-3491] module 'Gene_Position' declared at 'C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Position.vhd:34' bound to instance 'U4' of component 'Gene_Position' [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/VGA_top.vhd:183]
INFO: [Synth 8-638] synthesizing module 'Gene_Position' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Position.vhd:45]
INFO: [Synth 8-256] done synthesizing module 'Gene_Position' (3#1) [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Position.vhd:45]
	Parameter nbBits bound to: 18 - type: integer 
INFO: [Synth 8-3491] module 'Diviseur' declared at 'C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Diviseur.vhd:34' bound to instance 'U5' of component 'Diviseur' [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/VGA_top.vhd:194]
INFO: [Synth 8-638] synthesizing module 'Diviseur' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Diviseur.vhd:42]
	Parameter nbBits bound to: 18 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'Diviseur' (4#1) [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Diviseur.vhd:42]
INFO: [Synth 8-3491] module 'Gene_Snake' declared at 'C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:36' bound to instance 'U6' of component 'Gene_Snake' [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/VGA_top.vhd:202]
INFO: [Synth 8-638] synthesizing module 'Gene_Snake' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:49]
WARNING: [Synth 8-614] signal 'snakeHere' is read in the process but is not in the sensitivity list [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:70]
WARNING: [Synth 8-5858] RAM snake_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers
INFO: [Synth 8-256] done synthesizing module 'Gene_Snake' (5#1) [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:49]
INFO: [Synth 8-256] done synthesizing module 'VGA_top' (6#1) [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/VGA_top.vhd:48]
WARNING: [Synth 8-3331] design Gene_Snake has unconnected port up
WARNING: [Synth 8-3331] design Gene_Snake has unconnected port down
WARNING: [Synth 8-3331] design Gene_Snake has unconnected port left
WARNING: [Synth 8-3331] design Gene_Snake has unconnected port right
WARNING: [Synth 8-3331] design Gene_Snake has unconnected port clk_rapide
WARNING: [Synth 8-3331] design Gene_Snake has unconnected port clk_lente
WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port X[9]
WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port X[8]
WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port X[7]
WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port X[6]
WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port X[5]
WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port X[4]
WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port X[3]
WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port X[2]
WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port X[1]
WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port X[0]
WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port Y[8]
WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port Y[7]
WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port Y[6]
WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port Y[5]
WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port Y[4]
WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port Y[3]
WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port Y[2]
WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port Y[1]
WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port Y[0]
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Finished RTL Elaboration : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 780.012 ; gain = 406.445
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Report Check Netlist: 
+------+------------------+-------+---------+-------+------------------+
|      |Item              |Errors |Warnings |Status |Description       |
+------+------------------+-------+---------+-------+------------------+
|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
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Start Handling Custom Attributes
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Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 780.012 ; gain = 406.445
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Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 780.012 ; gain = 406.445
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INFO: [Device 21-403] Loading part xc7z010clg400-1
INFO: [Project 1-570] Preparing netlist for logic optimization

Processing XDC Constraints
Initializing timing engine
Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0/clk_wiz_1_in_context.xdc] for cell 'U0'
Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0/clk_wiz_1_in_context.xdc] for cell 'U0'
Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc]
Finished Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/VGA_top_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/VGA_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/synth_1/dont_touch.xdc]
Finished Parsing XDC File [C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/synth_1/dont_touch.xdc]
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1102.379 ; gain = 0.000
Completed Processing XDC Constraints

Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1102.379 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1102.379 ; gain = 0.000
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1102.379 ; gain = 0.000
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Finished Constraint Validation : Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 1102.379 ; gain = 728.812
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Start Loading Part and Timing Information
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Loading part: xc7z010clg400-1
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Finished Loading Part and Timing Information : Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 1102.379 ; gain = 728.812
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Start Applying 'set_property' XDC Constraints
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Applied set_property IO_BUFFER_TYPE = NONE for H125MHz. (constraint file  c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0/clk_wiz_1_in_context.xdc, line 3).
Applied set_property CLOCK_BUFFER_TYPE = NONE for H125MHz. (constraint file  c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0/clk_wiz_1_in_context.xdc, line 4).
Applied set_property DONT_TOUCH = true for U0. (constraint file  auto generated constraint, line ).
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Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 1102.379 ; gain = 728.812
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INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Position.vhd:58]
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Position.vhd:58]
WARNING: [Synth 8-327] inferring latch for variable 'snake_reg[0][X]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:80]
WARNING: [Synth 8-327] inferring latch for variable 'snake_reg[101][X]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:80]
WARNING: [Synth 8-327] inferring latch for variable 'snake_reg[102][X]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:80]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[0,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[1,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[2,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[3,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[4,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[5,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[6,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[7,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[8,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[9,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[10,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[11,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[12,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[13,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[14,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[15,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[16,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[17,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[18,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[19,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[20,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[21,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[22,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[23,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[24,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[25,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[26,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[27,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[28,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[29,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[30,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[31,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[32,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[33,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[34,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[35,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[36,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[37,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[38,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[39,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[0,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[1,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[2,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[3,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[4,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[5,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[6,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[7,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[8,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[9,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[10,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[11,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[12,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[13,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[14,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[15,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[16,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[17,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[18,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[19,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[20,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[21,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[22,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[23,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[24,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[25,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[26,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[27,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[28,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[29,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[30,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[31,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[32,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[33,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[34,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[35,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[36,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[37,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[38,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[39,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[0,2]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[1,2]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[2,2]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[3,2]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[4,2]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[5,2]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[6,2]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[7,2]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[8,2]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[9,2]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[10,2]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[11,2]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[12,2]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[13,2]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[14,2]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[15,2]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[16,2]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93]
INFO: [Common 17-14] Message 'Synth 8-327' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:44 ; elapsed = 00:00:50 . Memory (MB): peak = 1272.715 ; gain = 899.148
---------------------------------------------------------------------------------

Report RTL Partitions: 
+------+----------------+------------+----------+
|      |RTL Partition   |Replication |Instances |
+------+----------------+------------+----------+
|1     |Gene_Snake__GB0 |           1|     55621|
|2     |Gene_Snake__GB1 |           1|      2622|
|3     |Gene_Snake__GB2 |           1|     11799|
|4     |Gene_Snake__GB3 |           1|     15734|
|5     |VGA_top__GC0    |           1|       947|
+------+----------------+------------+----------+
---------------------------------------------------------------------------------
Start RTL Component Statistics 
---------------------------------------------------------------------------------
Detailed RTL Component Info : 
+---Adders : 
	   2 Input     11 Bit       Adders := 1     
	   2 Input     10 Bit       Adders := 11    
	   2 Input      9 Bit       Adders := 10    
+---Registers : 
	               11 Bit    Registers := 1     
	               10 Bit    Registers := 2     
	                9 Bit    Registers := 1     
	                1 Bit    Registers := 1     
+---Muxes : 
	   3 Input     10 Bit        Muxes := 4     
	   2 Input     10 Bit        Muxes := 3     
	   2 Input      9 Bit        Muxes := 3     
	   2 Input      6 Bit        Muxes := 1     
	1201 Input      2 Bit        Muxes := 4     
	   2 Input      2 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 8     
	1201 Input      1 Bit        Muxes := 3     
---------------------------------------------------------------------------------
Finished RTL Component Statistics 
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Hierarchical Component Statistics 
---------------------------------------------------------------------------------
Hierarchical RTL Component report 
Module Gene_Snake 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input     10 Bit       Adders := 8     
	   2 Input      9 Bit       Adders := 8     
+---Muxes : 
	   3 Input     10 Bit        Muxes := 4     
	1201 Input      2 Bit        Muxes := 4     
	   2 Input      1 Bit        Muxes := 6     
	1201 Input      1 Bit        Muxes := 3     
Module GeneSync 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input     11 Bit       Adders := 1     
	   2 Input     10 Bit       Adders := 2     
	   2 Input      9 Bit       Adders := 1     
+---Registers : 
	               11 Bit    Registers := 1     
	               10 Bit    Registers := 1     
+---Muxes : 
	   2 Input     10 Bit        Muxes := 3     
	   2 Input      9 Bit        Muxes := 3     
Module GeneRGB_V1 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input      6 Bit        Muxes := 1     
Module Gene_Position 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input     10 Bit       Adders := 1     
	   2 Input      9 Bit       Adders := 1     
+---Registers : 
	               10 Bit    Registers := 1     
	                9 Bit    Registers := 1     
+---Muxes : 
	   2 Input      2 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 2     
Module Diviseur 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 1     
---------------------------------------------------------------------------------
Finished RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 80 (col length:40)
BRAMs: 120 (col length: RAMB18 40 RAMB36 20)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
Warning: Parallel synthesis criteria is not met 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[101][Y][0] )
INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][Y][0] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[101][Y][1] )
INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][Y][1] )
INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][X][0] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[101][X][0] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[102][X][0] )
INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][X][1] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[101][X][1] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[102][X][1] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[101][Y][2] )
INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][Y][2] )
INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[101][Y][3] )
INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][Y][3] )
INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[101][Y][4] )
INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][Y][4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[101][Y][5] )
INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][Y][5] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[101][Y][6] )
INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][Y][6] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[101][Y][7] )
INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][Y][7] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[101][Y][8] )
INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][Y][8] )
INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][X][2] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[101][X][2] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[102][X][2] )
INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][X][8] )
INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[101][X][8] )
INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[102][X][8] )
INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][X][7] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[101][X][7] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[102][X][7] )
INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][X][6] )
INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[101][X][6] )
INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[102][X][6] )
INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][X][5] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[101][X][5] )
INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[102][X][5] )
INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][X][4] )
INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[101][X][4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[102][X][4] )
INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][X][3] )
INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[101][X][3] )
INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[102][X][3] )
INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][X][9] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[101][X][9] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[102][X][9] )
INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[101][isDefined] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[39,21][4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[38,21][4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[37,21][4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[36,21][4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[35,21][4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[34,21][4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[33,21][4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[32,21][4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[31,21][4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[30,21][4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[29,21][4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[28,21][4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[27,21][4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[26,21][4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[25,21][4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[24,21][4] )
INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\mat_reg[23,21][4] )
INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\mat_reg[22,21][4] )
INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\mat_reg[21,21][4] )
INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\mat_reg[20,21][4] )
INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\mat_reg[19,21][4] )
INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\mat_reg[18,21][4] )
INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\mat_reg[17,21][4] )
INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\mat_reg[16,21][4] )
INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\mat_reg[15,21][4] )
INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\mat_reg[14,21][4] )
INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\mat_reg[13,21][4] )
INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\mat_reg[12,21][4] )
INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\mat_reg[11,21][4] )
INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\mat_reg[10,21][4] )
INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\mat_reg[9,21][4] )
INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\mat_reg[8,21][4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[7,21][4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[6,21][4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[5,21][4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[4,21][4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[3,21][4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[2,21][4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[1,21][4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[0,21][4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[39,13][4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[38,13][4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[37,13][4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[36,13][4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[35,13][4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[34,13][4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[33,13][4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[32,13][4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[31,13][4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[30,13][4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[29,13][4] )
INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[39,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[38,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[37,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[36,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[35,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[34,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[33,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[32,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[31,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[30,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[29,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[28,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[27,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[26,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[25,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[24,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[23,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[22,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[21,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[20,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[19,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[18,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[17,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[16,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[15,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[14,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[13,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[12,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[11,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[10,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[9,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[8,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[7,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[6,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[5,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[4,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[3,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[2,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[1,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[0,22][0]' (LD) to 'U6i_2/mat_reg[0,22][1]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[39,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[38,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[37,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[36,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[35,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[34,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[33,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[32,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[31,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[30,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[29,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[28,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[27,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[26,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[25,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[24,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[23,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[22,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[21,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[20,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[19,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[18,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[17,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[16,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[15,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[14,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[13,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[12,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[11,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[10,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[9,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[8,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[7,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[6,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[5,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[4,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[3,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[2,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[1,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[0,22][1]' (LD) to 'U6i_2/mat_reg[0,22][2]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[39,22][2]' (LD) to 'U6i_2/mat_reg[0,22][4]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[38,22][2]' (LD) to 'U6i_2/mat_reg[0,22][4]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[37,22][2]' (LD) to 'U6i_2/mat_reg[0,22][4]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[36,22][2]' (LD) to 'U6i_2/mat_reg[0,22][4]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[35,22][2]' (LD) to 'U6i_2/mat_reg[0,22][2]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[34,22][2]' (LD) to 'U6i_2/mat_reg[0,22][2]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[33,22][2]' (LD) to 'U6i_2/mat_reg[0,22][2]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[32,22][2]' (LD) to 'U6i_2/mat_reg[0,22][2]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[31,22][2]' (LD) to 'U6i_2/mat_reg[0,22][4]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[30,22][2]' (LD) to 'U6i_2/mat_reg[0,22][4]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[29,22][2]' (LD) to 'U6i_2/mat_reg[0,22][4]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[28,22][2]' (LD) to 'U6i_2/mat_reg[0,22][4]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[27,22][2]' (LD) to 'U6i_2/mat_reg[0,22][2]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[26,22][2]' (LD) to 'U6i_2/mat_reg[0,22][2]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[25,22][2]' (LD) to 'U6i_2/mat_reg[0,22][2]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[24,22][2]' (LD) to 'U6i_2/mat_reg[0,22][2]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[23,22][2]' (LD) to 'U6i_2/mat_reg[0,22][4]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[22,22][2]' (LD) to 'U6i_2/mat_reg[0,22][4]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[21,22][2]' (LD) to 'U6i_2/mat_reg[0,22][4]'
INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[20,22][2]' (LD) to 'U6i_2/mat_reg[0,22][4]'
INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:22 ; elapsed = 00:01:28 . Memory (MB): peak = 1310.512 ; gain = 936.945
---------------------------------------------------------------------------------

Report RTL Partitions: 
+------+----------------+------------+----------+
|      |RTL Partition   |Replication |Instances |
+------+----------------+------------+----------+
|1     |Gene_Snake__GB0 |           1|       504|
|2     |Gene_Snake__GB2 |           1|        80|
|3     |Gene_Snake__GB3 |           1|        58|
|4     |VGA_top__GC0    |           1|       179|
+------+----------------+------------+----------+
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
INFO: [Synth 8-5578] Moved timing constraint from pin 'U0/clk_out1' to pin 'U0/bbstub_clk_out1/O'
INFO: [Synth 8-5819] Moved 1 constraints on hierarchical pins to their respective driving/loading pins
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:28 ; elapsed = 00:01:34 . Memory (MB): peak = 1310.512 ; gain = 936.945
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:01:28 ; elapsed = 00:01:34 . Memory (MB): peak = 1310.512 ; gain = 936.945
---------------------------------------------------------------------------------

Report RTL Partitions: 
+------+----------------+------------+----------+
|      |RTL Partition   |Replication |Instances |
+------+----------------+------------+----------+
|1     |Gene_Snake__GB0 |           1|       504|
|2     |Gene_Snake__GB2 |           1|        80|
|3     |Gene_Snake__GB3 |           1|        58|
|4     |VGA_top__GC0    |           1|       179|
+------+----------------+------------+----------+
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:01:28 ; elapsed = 00:01:34 . Memory (MB): peak = 1310.512 ; gain = 936.945
---------------------------------------------------------------------------------

Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:01:29 ; elapsed = 00:01:35 . Memory (MB): peak = 1310.512 ; gain = 936.945
---------------------------------------------------------------------------------

Report Check Netlist: 
+------+------------------+-------+---------+-------+------------------+
|      |Item              |Errors |Warnings |Status |Description       |
+------+------------------+-------+---------+-------+------------------+
|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:01:29 ; elapsed = 00:01:35 . Memory (MB): peak = 1310.512 ; gain = 936.945
---------------------------------------------------------------------------------

Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:29 ; elapsed = 00:01:35 . Memory (MB): peak = 1310.512 ; gain = 936.945
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:01:29 ; elapsed = 00:01:35 . Memory (MB): peak = 1310.512 ; gain = 936.945
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:01:29 ; elapsed = 00:01:35 . Memory (MB): peak = 1310.512 ; gain = 936.945
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:01:29 ; elapsed = 00:01:35 . Memory (MB): peak = 1310.512 ; gain = 936.945
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------

Report BlackBoxes: 
+------+--------------+----------+
|      |BlackBox name |Instances |
+------+--------------+----------+
|1     |clk_wiz_0     |         1|
+------+--------------+----------+

Report Cell Usage: 
+------+-----------------+------+
|      |Cell             |Count |
+------+-----------------+------+
|1     |clk_wiz_0_bbox_0 |     1|
|2     |CARRY4           |    34|
|3     |LUT1             |     4|
|4     |LUT2             |    28|
|5     |LUT3             |     7|
|6     |LUT4             |    62|
|7     |LUT5             |    47|
|8     |LUT6             |    65|
|9     |FDRE             |    21|
|10    |OBUF             |    18|
+------+-----------------+------+

Report Instance Areas: 
+------+---------+---------+------+
|      |Instance |Module   |Cells |
+------+---------+---------+------+
|1     |top      |         |   287|
|2     |  U1     |GeneSync |   267|
+------+---------+---------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:01:29 ; elapsed = 00:01:35 . Memory (MB): peak = 1310.512 ; gain = 936.945
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 1207 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:01:03 ; elapsed = 00:01:23 . Memory (MB): peak = 1310.512 ; gain = 614.578
Synthesis Optimization Complete : Time (s): cpu = 00:01:29 ; elapsed = 00:01:35 . Memory (MB): peak = 1310.512 ; gain = 936.945
INFO: [Project 1-571] Translating synthesized netlist
INFO: [Netlist 29-17] Analyzing 34 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1310.512 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

INFO: [Common 17-83] Releasing license: Synthesis
237 Infos, 127 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:01:30 ; elapsed = 00:01:37 . Memory (MB): peak = 1310.512 ; gain = 948.426
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1310.512 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/synth_1/VGA_top.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file VGA_top_utilization_synth.rpt -pb VGA_top_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Tue Dec  7 12:42:42 2021...
