diff --git a/.gitignore b/.gitignore index e69de29..3756940 100644 --- a/.gitignore +++ b/.gitignore @@ -0,0 +1,3 @@ +.gitignore +sources_snake/Gene_Balle.vhd +sources_snake/Gene_Position.vhd diff --git a/sources_snake/.gitkeep b/sources_snake/.gitkeep deleted file mode 100644 index e69de29..0000000 diff --git a/sources_snake/Gene_Snake.vhd b/sources_snake/Gene_Snake.vhd index 6834877..dda5c16 100644 --- a/sources_snake/Gene_Snake.vhd +++ b/sources_snake/Gene_Snake.vhd @@ -37,112 +37,111 @@ use ourTypes.types.all; --use UNISIM.VComponents.all; entity Gene_Snake is +generic( addressSize : integer:=10); Port ( X : in unsigned (9 downto 0); Y : in unsigned (8 downto 0); - clk_rapide: in std_logic; - clk_lente : in std_logic; + currentSnake : in pos; + clk: in std_logic; + updateOrder : in std_logic; reset: in std_logic; - snakePresent : out std_logic); + snakePresent : out std_logic; + currentAddress : out unsigned(addressSize-1 downto 0)); end Gene_Snake; architecture Behavioral of Gene_Snake is -component updateSnake -Port ( inSnake : in pos; - outSnake : out pos; - inIndex : in unsigned(10 downto 0); - outIndex : out unsigned(10 downto 0)); -end component updateSnake; - -- D???claration des signaux -signal mat: coord; -signal snake: listSnake; -signal snakeHere: std_logic; -signal update: std_logic; -signal current_index: unsigned(10 downto 0); -signal updatedIndex: unsigned(10 downto 0); -signal currentSnake: pos; -signal updatedSnake: pos; +signal mat: coord; --mat de correspondance "grille d'affichage (x,y)" vers position dans la RAM +signal snakeHere: std_logic; --1 si on doit afficher le pixel 0 sinon +signal dx : signed(1 downto 0); +signal dy : signed(1 downto 0); +signal running : std_logic; + begin -U0 : updateSnake -port map( - inSnake => currentSnake, - outSnake => updatedSnake, - inIndex => current_index, - outIndex => updatedIndex -); --- Process d'initialisation -process(mat,snake,reset,clk_rapide,current_index,clk_lente) -variable current_dir : direction; -begin - if(reset='0') - then - update <= '0'; - current_index <= to_unsigned(0,11); - for x in 0 to 39 loop - for y in 0 to 29 loop - mat(x,y) <= to_unsigned(snake'length-1,11); - end loop; - end loop; +---- Process d'initialisation +--process(mat,snake,reset,current_index) +--variable current_dir : direction; +--begin +-- if(reset='0') +-- then +-- update <= '0'; +-- current_index <= to_unsigned(0,11); +-- for x in 0 to 39 loop +-- for y in 0 to 29 loop +-- mat(x,y) <= to_unsigned(snake'length-1,11); +-- end loop; +-- end loop; - mat(0,0) <= to_unsigned(0,11); - mat(1,0) <= to_unsigned(1,11); +-- mat(0,0) <= to_unsigned(0,11); +-- mat(1,0) <= to_unsigned(1,11); - snake(0).X <= to_unsigned(8,10); - snake(0).Y <= to_unsigned(8,9); - snake(0).dir <= droite; - snake(0).isDefined <= '1'; +-- snake(0).X <= to_unsigned(8,10); +-- snake(0).Y <= to_unsigned(8,9); +-- snake(0).dir <= droite; +-- snake(0).isDefined <= '1'; - snake(1).X <= to_unsigned(24,10); - snake(1).Y <= to_unsigned(8,9); - snake(1).dir <= droite; - snake(1).isDefined <= '1'; +-- snake(1).X <= to_unsigned(24,10); +-- snake(1).Y <= to_unsigned(8,9); +-- snake(1).dir <= droite; +-- snake(1).isDefined <= '1'; - for i in 2 to snake'length-1 loop - snake(i).X <= to_unsigned(0,10); - snake(i).Y <= to_unsigned(0,9); - snake(i).dir <= gauche; - snake(i).isDefined <= '0'; - end loop; - elsif(clk_rapide'event and clk_rapide = '1') - then - snake(to_integer(current_index)) <= updatedSnake; - current_index <= updatedIndex; - end if; +-- for i in 2 to snake'length-1 loop +-- snake(i).X <= to_unsigned(0,10); +-- snake(i).Y <= to_unsigned(0,9); +-- snake(i).dir <= gauche; +-- snake(i).isDefined <= '0'; +-- end loop; +-- elsif(clk_rapide'event and clk_rapide = '1') +-- then +-- snake(to_integer(current_index)) <= updatedSnake; +-- current_index <= updatedIndex; +-- end if; - if (to_integer(current_index) = snake'length) then - update <= '0'; - current_index <= to_unsigned(0,11); - end if; +-- if (to_integer(current_index) = snake'length) then +-- update <= '0'; +-- current_index <= to_unsigned(0,11); +-- end if; - if(clk_lente'event and clk_lente = '1') - then - update <= '1'; - end if; +-- if(clk_lente'event and clk_lente = '1') +-- then +-- update <= '1'; +-- end if; -end process; +--end process; -- Process de calcul d'affichage -process(X,Y,mat, snake) -variable ref : unsigned(10 downto 0); -variable position : pos; +process(X,Y,clk,mat) begin - snakeHere <= '0'; - for dx in -1 to 1 loop - for dy in -1 to 1 loop - ref := mat(to_integer(X/16)+dx,to_integer(Y/16)+dy); - position := snake(to_integer(ref)); - if(position.isDefined= '1') then - if(X>=position.X-8 and X<=position.X+8 and Y>=position.Y-8 and Y<=position.Y+8) then - snakeHere <= '1'; - end if; - end if; - end loop; - end loop; +if(reset = '0') then + dx <= to_signed(0,2); + dy <= to_signed(0,2); +elsif(clk'event and clk = '1' and running = '1') then + if(currentSnake.isDefined= '1') then + if(X>=currentSnake.X-8 and X<=currentSnake.X+8 and Y>=currentSnake.Y-8 and Y<=currentSnake.Y+8) then + snakeHere <= '1'; + end if; + end if; + + dx <= dx + 1; + if(dx = 2) then + dx <= to_signed(-1,2); + dy <= dy + 1; + end if; +end if; + +if(dy = 2) then + dy <= to_signed(-1,2); + running <= '0'; +end if; + +if(updateOrder'event and updateOrder = '1') then + running <= '1'; +end if; end process; -currentSnake <= snake(to_integer(current_index)); +currentAddress <= mat(to_integer(X/16)+to_integer(dx),to_integer(Y/16)+to_integer(dy)); + snakePresent <= snakeHere; end Behavioral; diff --git a/sources_snake/VGA_top.vhd b/sources_snake/VGA_top.vhd index 3a34557..369c1b8 100644 --- a/sources_snake/VGA_top.vhd +++ b/sources_snake/VGA_top.vhd @@ -31,6 +31,9 @@ use IEEE.NUMERIC_STD.ALL; --library UNISIM; --use UNISIM.VComponents.all; +library ourTypes; +use ourTypes.types.all; + entity VGA_top is Port ( H125MHz : in STD_LOGIC; resetGeneral : in std_logic; @@ -80,14 +83,27 @@ component GeneRGB_V1 is end component; component Gene_Snake +generic ( addressSize : integer:=SNAKE_ADDRESS_SIZE); Port ( X : in unsigned (9 downto 0); Y : in unsigned (8 downto 0); - clk_rapide: in std_logic; - clk_lente : in std_logic; + currentSnake : in pos; + clk: in std_logic; + updateOrder : in std_logic; reset: in std_logic; - snakePresent : out std_logic); + snakePresent : out std_logic; + currentAddress : out unsigned(SNAKE_ADDRESS_SIZE-1 downto 0)); end component Gene_Snake; +component snakeRam +generic (length : integer:=1200; --30x40=1200, taille max du snake + addressSize : integer:=11 --ln(1200)/ln(2)>10 on prend 11 +); +Port ( address : in unsigned(addressSize-1 downto 0); + data : inout pos; + writeEnable : in STD_LOGIC; + clk : in STD_LOGIC); +end component snakeRam; + component Diviseur generic (nbBits : integer:=8); Port ( clk_in : in STD_LOGIC; @@ -108,6 +124,9 @@ signal valPosX: unsigned (9 downto 0); signal valPosY: unsigned (8 downto 0); signal valSnakePresent: std_logic; +signal displayRAMAddress : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0); +signal displayRAMData : pos; + signal clk_latch : std_logic; begin @@ -156,10 +175,20 @@ U4 : Gene_Snake port map ( X => Xpxl, Y => Ypxl, - clk_lente => clk_lente, - clk_rapide => H125Mhz, + currentSnake => displayRamData, + clk => H125Mhz, + updateOrder => pxl_clk, reset => resetGeneral, - snakePresent => valSnakePresent + snakePresent => valSnakePresent, + currentAddress => displayRamAddress + ); + +U5 : snakeRAM + port map ( + address => displayRAMAddress, + data => displayRAMdata, + writeEnable => '0', + clk => H125Mhz ); process(clk_lente,clk_latch) diff --git a/sources_snake/types.vhd b/sources_snake/types.vhd index b9a0bbf..a5527eb 100644 --- a/sources_snake/types.vhd +++ b/sources_snake/types.vhd @@ -3,7 +3,9 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; package types is - type coord is array(0 to 39, 0 to 29) of unsigned(10 downto 0); + constant MAX_SNAKE : integer := 1200; + constant SNAKE_ADDRESS_SIZE : integer :=11; + type coord is array(0 to 39, 0 to 29) of unsigned(SNAKE_ADDRESS_SIZE-1 downto 0); type direction is (haut, bas, gauche, droite); type pos is record X: unsigned(9 downto 0); @@ -11,5 +13,4 @@ package types is dir: direction; isDefined: std_logic; end record; - type listSnake is array(0 to 1200) of pos; end package;