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8====

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leo 2022-01-11 04:22:30 +01:00
parent 52e9909e0f
commit 49c08c4f69
2 changed files with 46 additions and 6 deletions
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16
sources_snake/VGA_top.vhd
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@ -279,6 +279,7 @@ signal pommeMatData : std_logic_vector(SNAKE_ADDRESS_SIZE-1 downto 0);
signal tailIndex : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0); signal tailIndex : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0);
signal lost : std_logic; signal lost : std_logic;
signal clkCnt : unsigned(24 downto 0);
--signal clk_latch : std_logic; --signal clk_latch : std_logic;
begin begin
@ -326,12 +327,13 @@ RGB : GeneRGB_V1
); );
UPD_CLK_DIV : Diviseur UPD_CLK_DIV : Diviseur
-- pxl_clock 25MHz, clk_lente ~60Hz, 1 coup sur clk_lente = 25e6/60 = 4.2e5 coups sur pxl_clk. ln(4.2e5)/ln(2)=18.6, donc on prend 19bits -- pxl_clock 25MHz, clk_lente ~60Hz, 1 coup sur clk_lente = 25e6/60 = 4.2e5 coups sur pxl_clk. ln(4.2e5)/ln(2)=18.6, donc on prend 19bits. nv on part sur 25
generic map (nbBits => 25) generic map (nbBits => 25)
port map ( port map (
clk_in => pxl_clk, clk_in => pxl_clk,
reset => resetGeneral, reset => resetGeneral,
max => to_unsigned(420000,25), max => clkCnt,
--max => to_unsigned(420000,25),
--max => to_unsigned(25000000,25), --max => to_unsigned(25000000,25),
--max => to_unsigned(1000,25), --max => to_unsigned(1000,25),
--max => (others => '0'), --max => (others => '0'),
@ -480,6 +482,16 @@ begin
end if; end if;
end process; end process;
process(lost)
begin
if(lost = '1') then
clkCnt <= to_unsigned(0,25);
else
clkCnt <= to_unsigned(100000,25);
end if;
end process;
--clkCnt <= to_unsigned(420000,25);
led(0) <= resetGeneral; led(0) <= resetGeneral;
led(1) <= updateRAMWE; led(1) <= updateRAMWE;
led(2) <= clk_lente; led(2) <= clk_lente;

32
sources_snake/updateSnake.vhd
View File

@ -72,6 +72,7 @@ signal index : unsigned(SNAKE_ADDRESS_SIZE downto 0) := to_unsigned(0,SNAKE_ADDR
signal isUpdating: std_logic := '0'; signal isUpdating: std_logic := '0';
signal updateIndex : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0) := (others => '0'); signal updateIndex : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0) := (others => '0');
signal state : unsigned(4 downto 0) := (others => '0'); signal state : unsigned(4 downto 0) := (others => '0');
signal checkLost : std_logic := '0';
signal nbOfEls : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0) := to_unsigned(12,SNAKE_ADDRESS_SIZE); signal nbOfEls : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0) := to_unsigned(12,SNAKE_ADDRESS_SIZE);
begin begin
process(updateIndex, clk_rapide, clk_lente,reset,index) --process de reset process(updateIndex, clk_rapide, clk_lente,reset,index) --process de reset
@ -97,6 +98,7 @@ begin
writeEnable <= '1'; writeEnable <= '1';
matWriteEnable <= '1'; matWriteEnable <= '1';
update := '0'; update := '0';
lost <= '0';
else else
index <= index + 1; index <= index + 1;
if(indext = MAX_SNAKE-1) then if(indext = MAX_SNAKE-1) then
@ -111,13 +113,26 @@ begin
if(state = 0) then --UPDATE if(state = 0) then --UPDATE
writeEnable <= '0'; writeEnable <= '0';
matWriteEnable <= '0';
address <= updateIndext; address <= updateIndext;
elsif(state = 2) then elsif(state = 2) then
cSnake := to_pos(dataIn); cSnake := to_pos(dataIn);
lSnake := to_pos(dataIn); lSnake := to_pos(dataIn);
if(cSnake.isDefined = '1') then if(cSnake.isDefined = '1') then
if(cSnake.X = 0 and cSnake.dirX = -1) then
cSnake.X := to_unsigned(639,10);
elsif(cSnake.X = 639 and cSnake.dirX = 1) then
cSnake.X := to_unsigned(0,10);
else
cSnake.X := to_unsigned(to_integer(cSnake.X) + to_integer(cSnake.dirX),10); cSnake.X := to_unsigned(to_integer(cSnake.X) + to_integer(cSnake.dirX),10);
end if;
if(cSnake.Y = 0 and cSnake.dirY = -1) then
cSnake.Y := to_unsigned(479,9);
elsif(cSnake.Y = 479 and cSnake.dirY = 1) then
cSnake.Y := to_unsigned(0,9);
else
cSnake.Y := to_unsigned(to_integer(cSnake.Y) + to_integer(cSnake.dirY),9); cSnake.Y := to_unsigned(to_integer(cSnake.Y) + to_integer(cSnake.dirY),9);
end if;
if(cSnake.X(2 downto 0) = 0 and cSnake.X(3) = '1' and cSnake.Y(2 downto 0) = 0 and cSnake.Y(3) = '1') then --si on est au centre d'une case if(cSnake.X(2 downto 0) = 0 and cSnake.X(3) = '1' and cSnake.Y(2 downto 0) = 0 and cSnake.Y(3) = '1') then --si on est au centre d'une case
if(updateIndext = 0) then if(updateIndext = 0) then
if(button_up = '1') then if(button_up = '1') then
@ -143,11 +158,15 @@ begin
dataOut <= to_stdlogicvector(cSnake); dataOut <= to_stdlogicvector(cSnake);
writeEnable <= '1'; writeEnable <= '1';
end if; end if;
matAddress <= to_unsigned(to_integer(cSnake.Y(cSnake.Y'high downto 4)) * 40 + to_integer(cSnake.X(cSnake.X'high downto 4)),SNAKE_ADDRESS_SIZE);
else else
state <= PROG_END; --jump end state <= PROG_END; --jump end
end if; end if;
elsif(state = 4) then -- MAJ MATRICE elsif(state = 4) then -- MAJ MATRICE
address <= unsigned(matDataIn);
writeEnable <= '0'; writeEnable <= '0';
if(cSnake.X(cSnake.X'high downto 4) /= lSnake.X(lSnake.X'high downto 4) or cSnake.Y(cSnake.Y'high downto 4) /= lSnake.Y(lSnake.Y'high downto 4)) then --si on as changé de case if(cSnake.X(cSnake.X'high downto 4) /= lSnake.X(lSnake.X'high downto 4) or cSnake.Y(cSnake.Y'high downto 4) /= lSnake.Y(lSnake.Y'high downto 4)) then --si on as changé de case
matWriteEnable <= '1'; matWriteEnable <= '1';
@ -164,11 +183,16 @@ begin
elsif(state = 6) then elsif(state = 6) then
matWriteEnable <= '0'; matWriteEnable <= '0';
matAddress <= to_unsigned(to_integer(lSnake.Y(lSnake.Y'high downto 4)) * 40 + to_integer(lSnake.X(lSnake.X'high downto 4)),SNAKE_ADDRESS_SIZE); matAddress <= to_unsigned(to_integer(lSnake.Y(lSnake.Y'high downto 4)) * 40 + to_integer(lSnake.X(lSnake.X'high downto 4)),SNAKE_ADDRESS_SIZE);
pSnake := to_pos(dataIn);
if(pSnake.isDefined = '1' and updateIndext = 0) then
lost <= '1';
end if;
--matDataOut <= std_logic_vector(updateIndex); --matDataOut <= std_logic_vector(updateIndex);
elsif(state = 8) then elsif(state = 8) then
if(matDataIn = std_logic_vector(to_unsigned(to_integer(lSnake.Y(lSnake.Y'high downto 4)) * 40 + to_integer(lSnake.X(lSnake.X'high downto 4)),SNAKE_ADDRESS_SIZE))) then if(matDataIn = std_logic_vector(updateIndext)) then
matWriteEnable <= '1'; matWriteEnable <= '1';
matDataOut <= std_logic_vector(to_unsigned(MAX_SNAKE-1,SNAKE_ADDRESS_SIZE)); matDataOut <= std_logic_vector(to_unsigned(MAX_SNAKE-10,SNAKE_ADDRESS_SIZE));
end if; end if;
if(addEl = '1') then if(addEl = '1') then
state <= to_unsigned(12,5); state <= to_unsigned(12,5);
@ -178,6 +202,7 @@ begin
end if; end if;
elsif(state = 10) then -- PROPAGATION DE LA DIRECTION elsif(state = 10) then -- PROPAGATION DE LA DIRECTION
matWriteEnable <= '0';
pSnake := to_pos(dataIn); pSnake := to_pos(dataIn);
cSnake.dirX := pSnake.dirX; cSnake.dirX := pSnake.dirX;
cSnake.dirY := pSnake.dirY; cSnake.dirY := pSnake.dirY;
@ -204,6 +229,9 @@ begin
addEl := '0'; addEl := '0';
state <= PROG_END; state <= PROG_END;
--elsif(state = 16) then
-- matWriteEnable <= '0';
elsif(state = PROG_END) then --END elsif(state = PROG_END) then --END
matWriteEnable <= '0'; matWriteEnable <= '0';
writeEnable <= '0'; writeEnable <= '0';