From 52e9909e0f2eaeac9823ec75d867001bdf272527 Mon Sep 17 00:00:00 2001 From: leo Date: Tue, 11 Jan 2022 01:02:01 +0100 Subject: [PATCH] pomme effect --- sources_snake/Diviseur.vhd | 3 +- sources_snake/GeneRGB_V1.vhd | 2 +- sources_snake/VGA_top.vhd | 30 +++++++++++++----- sources_snake/ZYBO_Master.xdc | 6 ++-- sources_snake/pomme.vhd | 8 +++-- sources_snake/updateSnake.vhd | 58 +++++++++++++++++++++++++++++------ 6 files changed, 82 insertions(+), 25 deletions(-) diff --git a/sources_snake/Diviseur.vhd b/sources_snake/Diviseur.vhd index 51deab7..cd8b2b9 100644 --- a/sources_snake/Diviseur.vhd +++ b/sources_snake/Diviseur.vhd @@ -36,7 +36,8 @@ entity Diviseur is Port ( clk_in : in STD_LOGIC; reset : in STD_LOGIC; max : in unsigned (nbBits-1 downto 0); - clk_out : out STD_LOGIC); + clk_out : out STD_LOGIC + ); end Diviseur; architecture Behavioral of Diviseur is diff --git a/sources_snake/GeneRGB_V1.vhd b/sources_snake/GeneRGB_V1.vhd index 1ef2605..25ee00a 100644 --- a/sources_snake/GeneRGB_V1.vhd +++ b/sources_snake/GeneRGB_V1.vhd @@ -50,7 +50,7 @@ architecture Behavioral of GeneRGB_V1 is begin -process(X,Y,IMG,snakeIn) +process(X,Y,IMG,snakeIn,pommeIn) variable snakeCol,pommeCol : color; begin if (IMG='0') then diff --git a/sources_snake/VGA_top.vhd b/sources_snake/VGA_top.vhd index 8d715d6..efbe20f 100644 --- a/sources_snake/VGA_top.vhd +++ b/sources_snake/VGA_top.vhd @@ -37,7 +37,6 @@ use ourTypes.types.all; entity VGA_top is Port ( H125MHz : in STD_LOGIC; resetGeneral : in std_logic; - resetPomme : in std_logic; led : out std_logic_vector (3 downto 0); vga_hs : out STD_LOGIC; vga_vs : out STD_LOGIC; @@ -139,8 +138,13 @@ Port ( button_right : in STD_LOGIC; pommeCE : out std_logic; - pommeX : unsigned(5 downto 0); - pommeY : unsigned(4 downto 0) + pommeX : in unsigned(5 downto 0); + pommeY : in unsigned(4 downto 0); + resetPomme : out std_logic; + + tailIndex : out unsigned(SNAKE_ADDRESS_SIZE-1 downto 0); + + lost : out std_logic ); end component updateSnake; @@ -265,11 +269,16 @@ signal pommeCE : std_logic; signal pommeX : unsigned(5 downto 0); signal pommeY : unsigned(4 downto 0); signal pommeColor : color; +signal pommeReset : std_logic; signal pommeAddress : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0); signal pommeData : std_logic_vector(to_stdlogicvector(dummyPos)'length-1 downto 0); signal pommeMatAddress : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0); signal pommeMatData : std_logic_vector(SNAKE_ADDRESS_SIZE-1 downto 0); + +signal tailIndex : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0); + +signal lost : std_logic; --signal clk_latch : std_logic; begin @@ -325,6 +334,7 @@ UPD_CLK_DIV : Diviseur max => to_unsigned(420000,25), --max => to_unsigned(25000000,25), --max => to_unsigned(1000,25), + --max => (others => '0'), clk_out => clk_lente ); @@ -338,7 +348,7 @@ SNAKE : Gene_Snake listRefs => listRefs, updateOrder => pxl_clk, dataReady => dataReady, - tailIndex => to_unsigned(12,SNAKE_ADDRESS_SIZE), + tailIndex => tailIndex, cCaseX => cCaseX, cCaseY => cCaseY, dataRequest => dataRequest, @@ -395,14 +405,19 @@ UPD : updateSnake pommeCE => pommeCE, pommeX => pommeX, - pommeY => pommeY + pommeY => pommeY, + resetPomme => pommeReset, + + tailIndex => tailIndex, + + lost => lost ); APPLE : pomme port map ( clk => H125MHz, pxl_clk => pxl_clk, - reset => resetPomme, + reset => pommeReset, CE => pommeCE, X => Xpxl, Y => Ypxl, @@ -444,7 +459,7 @@ APPLE : pomme clk => H125MHz ); -process(pommeCE,updateRAMAddress,pommeMatAddress,RAMDataIn,matUpdRAMAddress,matRAMDataIn) +process(pommeCE,updateRAMAddress,pommeAddress,pommeMatAddress,RAMDataIn,matUpdRAMAddress,matRAMDataIn) begin if(pommeCE = '0') then RAMAddress <= updateRAMAddress; @@ -468,4 +483,5 @@ end process; led(0) <= resetGeneral; led(1) <= updateRAMWE; led(2) <= clk_lente; +led(3) <= lost; end Behavioral; diff --git a/sources_snake/ZYBO_Master.xdc b/sources_snake/ZYBO_Master.xdc index 6937453..19dc6bf 100644 --- a/sources_snake/ZYBO_Master.xdc +++ b/sources_snake/ZYBO_Master.xdc @@ -14,9 +14,9 @@ create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports H125 set_property PACKAGE_PIN G15 [get_ports resetGeneral] set_property IOSTANDARD LVCMOS33 [get_ports resetGeneral] - #IO_L24P_T3_34 - set_property PACKAGE_PIN P15 [get_ports resetPomme] - set_property IOSTANDARD LVCMOS33 [get_ports resetPomme] +# #IO_L24P_T3_34 +# set_property PACKAGE_PIN P15 [get_ports resetPomme] +# set_property IOSTANDARD LVCMOS33 [get_ports resetPomme] # #IO_L4N_T0_34 # set_property PACKAGE_PIN W13 [get_ports {sw[2]}] diff --git a/sources_snake/pomme.vhd b/sources_snake/pomme.vhd index f9180c4..59af388 100644 --- a/sources_snake/pomme.vhd +++ b/sources_snake/pomme.vhd @@ -69,7 +69,8 @@ constant FINISHED : unsigned(3 downto 0) := to_unsigned(15,4); signal state : unsigned(3 downto 0) := (others => '0'); signal pommeHere : std_logic; begin -process(clk,reset,CE) +process(clk,reset,CE,state) +variable randInd : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0) := (others => '0'); begin if(reset = '0') then state <= to_unsigned(0,4); @@ -86,8 +87,9 @@ begin state <= FINISHED; end if; if(state = 0) then - Xpos <= (((Xpos + 733) rem 640) and "1111110000") or "0000001000"; - Ypos <= (((Ypos + 587) rem 480) and "111110000") or "000001000"; + randInd := (randInd + 937) rem MAX_SNAKE; + Xpos <= (randInd(5 downto 0) rem 40) & "1000"; + Ypos <= resize(randInd rem 30,5) & "1000"; elsif(state = 1) then matAddress <= to_unsigned(to_integer(Ypos(Ypos'HIGH downto 4)) * 40 + to_integer(Xpos(Xpos'HIGH downto 4)),SNAKE_ADDRESS_SIZE); elsif(state = 3) then diff --git a/sources_snake/updateSnake.vhd b/sources_snake/updateSnake.vhd index fd41902..a57c99f 100644 --- a/sources_snake/updateSnake.vhd +++ b/sources_snake/updateSnake.vhd @@ -57,8 +57,13 @@ entity updateSnake is button_right : in STD_LOGIC; pommeCE : out std_logic := '0'; - pommeX : unsigned(5 downto 0); - pommeY : unsigned(4 downto 0) + pommeX : in unsigned(5 downto 0); + pommeY : in unsigned(4 downto 0); + resetPomme : out std_logic := '1'; + + tailIndex : out unsigned(SNAKE_ADDRESS_SIZE-1 downto 0); + + lost : out std_logic := '0' ); end updateSnake; @@ -66,17 +71,19 @@ architecture Behavioral of updateSnake is signal index : unsigned(SNAKE_ADDRESS_SIZE downto 0) := to_unsigned(0,SNAKE_ADDRESS_SIZE+1); signal isUpdating: std_logic := '0'; signal updateIndex : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0) := (others => '0'); -signal state : unsigned(3 downto 0) := (others => '0'); +signal state : unsigned(4 downto 0) := (others => '0'); +signal nbOfEls : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0) := to_unsigned(12,SNAKE_ADDRESS_SIZE); begin process(updateIndex, clk_rapide, clk_lente,reset,index) --process de reset variable cSnake : pos; --current snake, celui qu'on met à jour variable lSnake : pos; --last snake, sauvegarde de l'état précédent -variable pSnake : pos; --previous snake, snake precedent dans la chaine +variable pSnake : pos; --previous snake, snake precedent dans la chaine (on s'en sert aussi de stockage temp pour ajouter un el) variable currentSnake : pos; variable update : std_logic := '0'; variable indext : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0) := to_unsigned(0,SNAKE_ADDRESS_SIZE); variable updateIndext : unsigned(SNAKE_ADDRESS_SIZE-1 downto 0) := (others => '0'); -constant PROG_END : unsigned(3 downto 0) := to_unsigned(15,4); +variable addEl : std_logic := '0'; +constant PROG_END : unsigned(4 downto 0) := to_unsigned(31,5); begin if rising_edge(clk_lente) then @@ -130,7 +137,7 @@ begin writeEnable <= '1'; else address <= updateIndext-1; - state <= to_unsigned(9,4); + state <= to_unsigned(9,5); end if; else dataOut <= to_stdlogicvector(cSnake); @@ -146,6 +153,11 @@ begin matWriteEnable <= '1'; matAddress <= to_unsigned(to_integer(cSnake.Y(cSnake.Y'high downto 4)) * 40 + to_integer(cSnake.X(cSnake.X'high downto 4)),SNAKE_ADDRESS_SIZE); matDataOut <= std_logic_vector(updateIndext); + + if(cSnake.X(cSnake.X'high downto 4) = pommeX and cSnake.Y(cSnake.Y'high downto 4) = pommeY) then + resetPomme <= '0'; + addEl := '1'; + end if; else state <= PROG_END; --jump end end if; @@ -158,7 +170,12 @@ begin matWriteEnable <= '1'; matDataOut <= std_logic_vector(to_unsigned(MAX_SNAKE-1,SNAKE_ADDRESS_SIZE)); end if; - state <= PROG_END; --jump end + if(addEl = '1') then + state <= to_unsigned(12,5); + resetPomme <= '1'; + else + state <= PROG_END; --jump end + end if; elsif(state = 10) then -- PROPAGATION DE LA DIRECTION pSnake := to_pos(dataIn); @@ -167,18 +184,37 @@ begin dataOut <= to_stdlogicvector(cSnake); writeEnable <= '1'; address <= updateIndext; - state <= to_unsigned(3,4); --on peut ptet directement jump à la fin? + state <= to_unsigned(3,5); --on peut ptet directement jump à la fin? + + elsif(state = 12) then + address <= nbOfEls; + matWriteEnable <= '0'; + nbOfEls <= nbOfEls + 1; + elsif(state = 14) then + pSnake := to_pos(dataIn); + pSnake.X := to_unsigned(to_integer(pSnake.X) - 16 * to_integer(pSnake.dirX),10); + pSnake.Y := to_unsigned(to_integer(pSnake.Y) - 16 * to_integer(pSnake.dirY),9); + dataOut <= to_stdlogicvector(pSnake); + address <= nbOfEls; + matDataOut <= std_logic_vector(nbOfEls); + matAddress <= to_unsigned(to_integer(pSnake.Y(pSnake.Y'high downto 4)) * 40 + to_integer(pSnake.X(pSnake.X'high downto 4)),SNAKE_ADDRESS_SIZE); + elsif(state = 15) then + writeEnable <= '1'; + matWriteEnable <= '1'; + addEl := '0'; + state <= PROG_END; elsif(state = PROG_END) then --END matWriteEnable <= '0'; writeEnable <= '0'; updateIndex <= updateIndex + 1; - state <= to_unsigned(0,4); + state <= to_unsigned(0,5); end if; end if; if update = '0' then if(indext = 0) then + nbOfEls <= to_unsigned(12,SNAKE_ADDRESS_SIZE); currentSnake.X := to_unsigned(8+to_integer(indext)*16,10); currentSnake.Y := to_unsigned(8,9); currentSnake.dirX := to_signed(0,2); @@ -214,7 +250,9 @@ begin if(updateIndex = MAX_SNAKE) then isUpdating <= '0'; updateIndex <= to_unsigned(0,SNAKE_ADDRESS_SIZE); - state <= to_unsigned(0,4); + state <= to_unsigned(0,5); end if; end process; + +tailIndex <= nbOfEls; end Behavioral;