reecriture-VGA_top

brouillons/VGA_top.vhd

@@ -0,0 +1,145 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 16.11.2021 12:02:26
+-- Design Name:
+-- Module Name: Gene_Position - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool Versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+-- Ce qui manque certainement:
+--   - le composant clk_wiz0
+--   - le composant Gene_RGB
+--   - des signaux (en particulier X et Y)
+entity VGA_top is
+    Port ( button_up : in STD_LOGIC;
+           button_down : in STD_LOGIC;
+           button_left : in STD_LOGIC;
+           button_right : in STD_LOGIC;
+           H125Mhz: in STD_LOGIC;
+           resetGeneral: in STD_LOGIC;
+           );
+end VGA_top;
+
+architecture Behavioral of VGA_top is
+
+-- Déclaration des composants
+component Gene_Position
+  Port (  up : in STD_LOGIC;
+          down : in STD_LOGIC;
+          left : in STD_LOGIC;
+          right : in STD_LOGIC;
+          clk: in STD_LOGIC;
+          reset: in STD_LOGIC;
+          PosX : out unsigned (9 downto 0);
+          PosY : out unsigned (8 downto 0));
+end component Gene_Position;
+
+component Diviseur
+  generic (nbBits : integer:=8);
+  Port (  clk_in : in STD_LOGIC;
+          reset : in STD_LOGIC;
+          max : in unsigned (nbBits-1 downto 0);
+          clk_out : out STD_LOGIC);
+end component Diviseur;
+
+component Gene_Balle
+  Port (  X : in unsigned (9 downto 0);
+          Y : in unsigned (8 downto 0);
+          PosX : in unsigned (9 downto 0);
+          PosY : in unsigned (8 downto 0);
+          ballePresente : out std_logic);
+end component Gene_Balle;
+
+component Gene_Snake
+Port ( X : in unsigned (9 downto 0);
+       Y : in unsigned (8 downto 0);
+       up : in std_logic;
+       down : in std_logic;
+       left : in std_logic;
+       right : in std_logic;
+       clk_rapide: in std_logic;
+       clk_lente : in std_logic;
+       reset: in std_logic;
+       snakePresent : out std_logic);
+end component Gene_Snake;
+
+-- Déclaration des signaux
+signal clk_lente: std_logic;
+signal valPosX: unsigned (9 downto 0);
+signal valPosY: unsigned (8 downto 0);
+signal valBallePresente: std_logic;
+
+begin
+ U1 : Gene_Position
+    port map (
+      up => button_up,
+      down => button_down,
+      left => button_left,
+      right => button_right,
+      clk => clk_lente,
+      reset => resetGeneral,
+      PosX => valPosX,
+      PosY => valPosY
+    );
+
+ U2 : Diviseur
+    -- je n'ai plus le souvenir du bon nombre de bits ici
+    generic map (nbBits => 11)
+    port map (
+      clk_in => H125Mhz,
+      reset => resetGeneral,
+      -- ne pense pas que ce soit bon ici
+      -- on avait surement branché autre chose à "max"
+      max => unsigned (nbBits - 1 downto 0),
+      clk_out => clk_lente
+    );
+
+--  U3 : Gene_Balle
+--     port map (
+--       X => ,
+--       Y => ,
+--       PosX => ,
+--       PosY => ,
+--       ballePresente => valBallePresente
+--     );
+
+ U4 : Gene_Snake
+    port map (
+      X => ,
+      Y => ,
+      up => button_up,
+      down => button_down,
+      left => button_left,
+      right => button_right,
+      clk_lente => clk_lente,
+      clk_rapide => H125Mhz,
+      reset => resetGeneral,
+      snakePresent => valBallePresente
+    );
+
+end Behavioral;

projet-vga.srcs/sources_1/new/Diviseur.vhd

@@ -1,21 +1,21 @@
 ----------------------------------------------------------------------------------
--- Company: 
+-- Company:
--- Engineer: 
+-- Engineer:
--- 
+--
 -- Create Date: 23.11.2021 11:56:55
--- Design Name: 
+-- Design Name:
 -- Module Name: Diviseur - Behavioral
--- Project Name: 
+-- Project Name:
--- Target Devices: 
+-- Target Devices:
--- Tool Versions: 
+-- Tool Versions:
--- Description: 
+-- Description:
--- 
+--
--- Dependencies: 
+-- Dependencies:
--- 
+--
 -- Revision:
 -- Revision 0.01 - File Created
 -- Additional Comments:
--- 
+--
 ----------------------------------------------------------------------------------
 
 
@@ -52,7 +52,7 @@ begin
         if temp=max then
         clk_out <= '1';
         temp <= (others => '0');
-        else 
+        else
         clk_out <= '0';
         end if;
     end if;