From 9ac654c6c1a5f17787c77617911c1d8b3304680f Mon Sep 17 00:00:00 2001
From: Leo Lemaire <leo.lemaire@etu.univ-nantes.fr>
Date: Wed, 15 Dec 2021 18:35:38 +0000
Subject: [PATCH] Upload New File

---
 sources_snake/Diviseur.vhd | 62 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 62 insertions(+)
 create mode 100644 sources_snake/Diviseur.vhd

diff --git a/sources_snake/Diviseur.vhd b/sources_snake/Diviseur.vhd
new file mode 100644
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+++ b/sources_snake/Diviseur.vhd
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+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 23.11.2021 11:56:55
+-- Design Name: 
+-- Module Name: Diviseur - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity Diviseur is
+    generic (nbBits : integer:=8);
+    Port ( clk_in : in STD_LOGIC;
+           reset : in STD_LOGIC;
+           max : in unsigned (nbBits-1 downto 0);
+           clk_out : out STD_LOGIC);
+end Diviseur;
+
+architecture Behavioral of Diviseur is
+signal temp : unsigned (nbBits-1 downto 0);
+
+begin
+process(clk_in,reset)
+begin
+    if reset='0' then
+    temp<=(others=>'0');
+    elsif (clk_in'event and clk_in='1') then
+        temp <= temp+1;
+        if temp=max then
+            clk_out <= '1';
+            temp <= (others => '0');
+        else 
+            clk_out <= '0';
+        end if;
+    end if;
+end process;
+
+
+end Behavioral;