diff --git a/projet-vga.cache/ip/2018.3/adeea2ece8e77c4b/stats.txt b/projet-vga.cache/ip/2018.3/adeea2ece8e77c4b/stats.txt index dca137a..1631ecc 100644 --- a/projet-vga.cache/ip/2018.3/adeea2ece8e77c4b/stats.txt +++ b/projet-vga.cache/ip/2018.3/adeea2ece8e77c4b/stats.txt @@ -1,2 +1,2 @@ -NumberHits:1 -Timestamp: Tue Nov 16 09:42:22 UTC 2021 +NumberHits:2 +Timestamp: Tue Jan 04 09:12:04 UTC 2022 diff --git a/projet-vga.cache/wt/gui_handlers.wdf b/projet-vga.cache/wt/gui_handlers.wdf index b99f66b..2c61d72 100644 --- a/projet-vga.cache/wt/gui_handlers.wdf +++ b/projet-vga.cache/wt/gui_handlers.wdf @@ -2,70 +2,87 @@ version:1 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6162737472616374636f6d62696e656470616e656c5f6164645f656c656d656e74:39:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6162737472616374636f6d62696e656470616e656c5f72656d6f76655f73656c65637465645f656c656d656e7473:32:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:616273747261637466696c65766965775f636c6f7365:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:3435:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:616273747261637466696c65766965775f72656c6f6164:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f6f725f6372656174655f636f6e73747261696e745f66696c6573:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:3539:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f636c6f7365:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6e6f:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:333937:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f796573:32:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6e73747261696e747363686f6f73657270616e656c5f6164645f66696c6573:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f7265747265657461626c6570616e656c5f636f72655f747265655f7461626c65:3138:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6e6f:33:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:343734:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f796573:34:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6f6b:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6e6669726d736176657465787465646974736469616c6f675f6e6f:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6e73747261696e747363686f6f73657270616e656c5f6164645f66696c6573:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f7265747265657461626c6570616e656c5f636f72655f747265655f7461626c65:3234:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6372656174656e65776469616772616d6469616c6f675f64657369676e5f6e616d65:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:63726561746573726366696c656469616c6f675f66696c655f6e616d65:35:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:646566696e656d6f64756c65736469616c6f675f646566696e655f6d6f64756c65735f616e645f737065636966795f696f5f706f727473:3935:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6670676163686f6f7365725f667067615f7461626c65:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:313537:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:666c6f776e6176696761746f727472656570616e656c5f666c6f775f6e6176696761746f725f74726565:323037:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6372656174655f6e65775f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:323039:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:666c6f776e6176696761746f727472656570616e656c5f666c6f775f6e6176696761746f725f74726565:323631:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6372656174655f6e65775f70726f6a656374:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6f70656e5f70726f6a656374:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:68636f6465656469746f725f626c616e6b5f6f7065726174696f6e73:3137:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:68636f6465656469746f725f636c6f7365:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:68636f6465656469746f725f636c6f7365:33:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:68636f6465656469746f725f636f6d6d616e64735f746f5f666f6c645f74657874:32:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:68636f6465656469746f725f646966665f77697468:38:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:68636f6465656469746f725f7365617263685f746578745f636f6d626f5f626f78:3135:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:68636f6465656469746f725f7365617263685f746578745f636f6d626f5f626f78:3230:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:68696e70757468616e646c65725f696e64656e745f73656c656374696f6e:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:68696e70757468616e646c65725f746f67676c655f6c696e655f636f6d6d656e7473:3337:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:68696e70757468616e646c65725f746f67676c655f6c696e655f636f6d6d656e7473:3430:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:68696e70757468616e646c65725f756e696e64656e745f73656c656374696f6e:32:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:68706f7075707469746c655f636c6f7365:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6c6f676d6f6e69746f725f6d6f6e69746f72:33:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d73677472656570616e656c5f6d616e6167655f7375707072657373696f6e:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d73677472656570616e656c5f6d6573736167655f766965775f74726565:3739:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d7367766965775f636c6561725f6d657373616765735f726573756c74696e675f66726f6d5f757365725f6578656375746564:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d73677472656570616e656c5f6d6573736167655f766965775f74726565:313337:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d7367766965775f636c6561725f6d657373616765735f726573756c74696e675f66726f6d5f757365725f6578656375746564:34:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d7367766965775f637269746963616c5f7761726e696e6773:32:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d7367766965775f6572726f725f6d65737361676573:34:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d7367766965775f696e666f726d6174696f6e5f6d65737361676573:33:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d7367766965775f7761726e696e675f6d65737361676573:39:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6e756d6a6f627363686f6f7365725f6e756d6265725f6f665f6a6f6273:32:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6175746f5f636f6e6e6563745f746172676574:3136:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6175746f5f7570646174655f68696572:3131:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f676f746f5f696d706c656d656e7465645f64657369676e:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d7367766965775f7761726e696e675f6d65737361676573:3131:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6e65746c69737474726565766965775f6e65746c6973745f74726565:34:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6e756d6a6f627363686f6f7365725f6e756d6265725f6f665f6a6f6273:33:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6175746f5f636f6e6e6563745f746172676574:3138:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6175746f5f7570646174655f68696572:3135:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f676f746f5f696d706c656d656e7465645f64657369676e:32:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f676f746f5f6e65746c6973745f64657369676e:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6c6f675f77696e646f77:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6d6573736167655f77696e646f77:32:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6f70656e5f68617264776172655f6d616e61676572:32:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f7265637573746f6d697a655f636f7265:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f72756e5f62697467656e:3432:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f72756e5f62697467656e:3435:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f72756e5f696d706c656d656e746174696f6e:38:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f636f6465:35:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f7372635f64697361626c65:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f636f6465:37:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f646576696365:33:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f69705f636174616c6f67:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f70726f6a6563745f73756d6d617279:3231:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f736368656d61746963:39:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6772616d64656275677461625f726566726573685f646576696365:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6772616d667067616469616c6f675f70726f6772616d:3436:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f67726573736469616c6f675f6261636b67726f756e64:34:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f69705f636174616c6f67:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f70726f6a6563745f73756d6d617279:3236:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f736368656d61746963:3130:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6772616d64656275677461625f70726f6772616d5f646576696365:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6772616d64656275677461625f726566726573685f646576696365:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6772616d667067616469616c6f675f70726f6772616d:3531:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f67726573736469616c6f675f6261636b67726f756e64:35:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f67726573736469616c6f675f63616e63656c:35:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563746e616d6563686f6f7365725f70726f6a6563745f6e616d65:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563747461625f72656c6f6164:36:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:726469636f6d6d616e64735f64656c657465:34:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563747461625f72656c6f6164:39:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:726469636f6d6d616e64735f636f7079:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:726469636f6d6d616e64735f64656c657465:38:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:72656d6f7665736f75726365736469616c6f675f616c736f5f64656c657465:32:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:72756e6761646765745f73686f775f7761726e696e675f616e645f6572726f725f6d657373616765735f696e5f6d65737361676573:32:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7361766570726f6a6563747574696c735f646f6e745f73617665:38:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7361766570726f6a6563747574696c735f73617665:35:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7361766570726f6a6563747574696c735f73617665:36:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:736368656d61746963766965775f70726576696f7573:3130:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d706c656f757470757470726f647563746469616c6f675f67656e65726174655f6f75747075745f70726f64756374735f696d6d6564696174656c79:33:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f68646c5f616e645f6e65746c6973745f66696c65735f746f5f796f75725f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d706c656f757470757470726f647563746469616c6f675f67656e65726174655f6f75747075745f70726f64756374735f696d6d6564696174656c79:34:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:737065636966796c6962726172796469616c6f675f6c6962726172795f6e616d65:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f6469726563746f72696573:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f68646c5f616e645f6e65746c6973745f66696c65735f746f5f796f75725f70726f6a656374:33:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f6f725f6372656174655f736f757263655f66696c65:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6372656174655f66696c65:36:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7372636d656e755f69705f646f63756d656e746174696f6e:35:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7372636d656e755f69705f686965726172636879:38:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726366696c6570726f7070616e656c735f74797065:34:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726366696c6574797065636f6d626f626f785f736f757263655f66696c655f74797065:34:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7372636d656e755f69705f646f63756d656e746174696f6e:36:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7372636d656e755f69705f686965726172636879:3130:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7372636d656e755f7365745f6c696272617279:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7374616c6572756e6469616c6f675f6e6f:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636167657474696e6773746172746564766965775f726563656e745f70726f6a65637473:34:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636173746174656d6f6e69746f725f63616e63656c:35:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7461736b62616e6e65725f636c6f7365:3136:00:00 -eof:1716158420 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636173746174656d6f6e69746f725f63616e63656c:37:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7461736b62616e6e65725f636c6f7365:3139:00:00 +eof:2086603918 diff --git a/projet-vga.cache/wt/java_command_handlers.wdf b/projet-vga.cache/wt/java_command_handlers.wdf index 489f953..4d84210 100644 --- a/projet-vga.cache/wt/java_command_handlers.wdf +++ b/projet-vga.cache/wt/java_command_handlers.wdf @@ -1,24 +1,28 @@ version:1 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:36:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6175746f636f6e6e656374746172676574:3136:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636f726576696577:33:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:637573746f6d697a65636f7265:34:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697464656c657465:34:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:656469747061737465:32:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:3131:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6175746f636f6e6e656374746172676574:3138:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636f726576696577:34:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:637265617465626c6f636b64657369676e:33:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:637573746f6d697a65636f7265:35:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697464656c657465:39:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:656469747061737465:33:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:65646974756e646f:31:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6c61756e636870726f6772616d66706761:3436:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:31:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e68617264776172656d616e61676572:3638:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e726563656e74746172676574:3231:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:70726f6772616d646576696365:3436:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:666c6970746f766965777461736b72746c616e616c79736973:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6c61756e636870726f6772616d66706761:3531:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:32:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e68617264776172656d616e61676572:3734:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e726563656e74746172676574:3234:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:70726f6772616d646576696365:3530:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7265637573746f6d697a65636f7265:33:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e62697467656e:3435:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e696d706c656d656e746174696f6e:3539:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e62697467656e:3534:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e696d706c656d656e746174696f6e:3638:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e736368656d61746963:37:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e73796e746865736973:3932:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e73796e746865736973:313134:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7361766566696c6570726f787968616e646c6572:33:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73686f7776696577:3235:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:736574736f75726365656e61626c6564:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73686f7776696577:3335:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b696d706c656d656e746174696f6e:38:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b72746c616e616c79736973:33:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b72746c616e616c79736973:37:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b73796e746865736973:32:00:00 -eof:2668022594 +eof:2810968177 diff --git a/projet-vga.cache/wt/project.wpc b/projet-vga.cache/wt/project.wpc index f728c24..9734ac0 100644 --- a/projet-vga.cache/wt/project.wpc +++ b/projet-vga.cache/wt/project.wpc @@ -1,4 +1,4 @@ version:1 -57656254616c6b5472616e736d697373696f6e417474656d70746564:43 -6d6f64655f636f756e7465727c4755494d6f6465:5 +57656254616c6b5472616e736d697373696f6e417474656d70746564:49 +6d6f64655f636f756e7465727c4755494d6f6465:6 eof: diff --git a/projet-vga.cache/wt/synthesis.wdf b/projet-vga.cache/wt/synthesis.wdf index 09e996f..08fb104 100644 --- a/projet-vga.cache/wt/synthesis.wdf +++ b/projet-vga.cache/wt/synthesis.wdf @@ -33,7 +33,7 @@ version:1 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 -73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30313a333673:00:00 -73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313331302e3531324d42:00:00 -73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3934382e3432364d42:00:00 -eof:1833541424 +73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a343673:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:3937362e3134354d42:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3631332e3539304d42:00:00 +eof:1302994828 diff --git a/projet-vga.cache/wt/webtalk_pa.xml b/projet-vga.cache/wt/webtalk_pa.xml index c52bf9c..38f7f7e 100644 --- a/projet-vga.cache/wt/webtalk_pa.xml +++ b/projet-vga.cache/wt/webtalk_pa.xml @@ -3,10 +3,10 @@ - +
- +
@@ -17,104 +17,120 @@ This means code written to parse this file will need to be revisited each subseq - - - - - - + + + + + + + - - - - - + + + + + + + - - + + - + - + + - + - + + + - - - - - + + + + + + + + - - - + + + + - + - + - + - - + + - - - - - + + + + + + + - + - + + - - - - - - + + + + + + + - - + + + + - + - - + + + + - - + + + + + - - - - - - - + +
diff --git a/projet-vga.runs/impl_1/.init_design.begin.rst b/projet-vga.runs/impl_1/.init_design.begin.rst index ffef227..e3f30fe 100644 --- a/projet-vga.runs/impl_1/.init_design.begin.rst +++ b/projet-vga.runs/impl_1/.init_design.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/projet-vga.runs/impl_1/.opt_design.begin.rst b/projet-vga.runs/impl_1/.opt_design.begin.rst index ffef227..e3f30fe 100644 --- a/projet-vga.runs/impl_1/.opt_design.begin.rst +++ b/projet-vga.runs/impl_1/.opt_design.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/projet-vga.runs/impl_1/.place_design.begin.rst b/projet-vga.runs/impl_1/.place_design.begin.rst index ffef227..e3f30fe 100644 --- a/projet-vga.runs/impl_1/.place_design.begin.rst +++ b/projet-vga.runs/impl_1/.place_design.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/projet-vga.runs/impl_1/.place_design.error.rst b/projet-vga.runs/impl_1/.place_design.error.rst deleted file mode 100644 index e69de29..0000000 diff --git a/projet-vga.runs/impl_1/.route_design.begin.rst b/projet-vga.runs/impl_1/.route_design.begin.rst index ffef227..e3f30fe 100644 --- a/projet-vga.runs/impl_1/.route_design.begin.rst +++ b/projet-vga.runs/impl_1/.route_design.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/projet-vga.runs/impl_1/.vivado.begin.rst b/projet-vga.runs/impl_1/.vivado.begin.rst index ea9ae64..c4c21b1 100644 --- a/projet-vga.runs/impl_1/.vivado.begin.rst +++ b/projet-vga.runs/impl_1/.vivado.begin.rst @@ -1,10 +1,5 @@ - - - - - - + diff --git a/projet-vga.runs/impl_1/.vivado.error.rst b/projet-vga.runs/impl_1/.vivado.error.rst deleted file mode 100644 index e69de29..0000000 diff --git a/projet-vga.runs/impl_1/.write_bitstream.begin.rst b/projet-vga.runs/impl_1/.write_bitstream.begin.rst index 9014d1f..e3f30fe 100644 --- a/projet-vga.runs/impl_1/.write_bitstream.begin.rst +++ b/projet-vga.runs/impl_1/.write_bitstream.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/projet-vga.runs/impl_1/VGA_top.bit b/projet-vga.runs/impl_1/VGA_top.bit index bffedf8..6aeb2d5 100644 Binary files a/projet-vga.runs/impl_1/VGA_top.bit and b/projet-vga.runs/impl_1/VGA_top.bit differ diff --git a/projet-vga.runs/impl_1/VGA_top.tcl b/projet-vga.runs/impl_1/VGA_top.tcl index 986ce55..d2b197d 100644 --- a/projet-vga.runs/impl_1/VGA_top.tcl +++ b/projet-vga.runs/impl_1/VGA_top.tcl @@ -60,18 +60,104 @@ proc step_failed { step } { close $ch } -set_msg_config -id {Common 17-41} -limit 10000000 set_msg_config -id {Synth 8-256} -limit 10000 set_msg_config -id {Synth 8-638} -limit 10000 +start_step init_design +set ACTIVE_STEP init_design +set rc [catch { + create_msg_db init_design.pb + set_param xicom.use_bs_reader 1 + create_project -in_memory -part xc7z010clg400-1 + set_property design_mode GateLvl [current_fileset] + set_param project.singleFileAddWarning.threshold 0 + set_property webtalk.parent_dir C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.cache/wt [current_project] + set_property parent.project_path C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.xpr [current_project] + set_property ip_output_repo C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.cache/ip [current_project] + set_property ip_cache_permissions {read write} [current_project] + set_property XPM_LIBRARIES XPM_CDC [current_project] + add_files -quiet C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/synth_1/VGA_top.dcp + read_ip -quiet c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0.xci + read_xdc C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/ZYBO_Master.xdc + link_design -top VGA_top -part xc7z010clg400-1 + close_msg_db -file init_design.pb +} RESULT] +if {$rc} { + step_failed init_design + return -code error $RESULT +} else { + end_step init_design + unset ACTIVE_STEP +} + +start_step opt_design +set ACTIVE_STEP opt_design +set rc [catch { + create_msg_db opt_design.pb + opt_design + write_checkpoint -force VGA_top_opt.dcp + create_report "impl_1_opt_report_drc_0" "report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx" + close_msg_db -file opt_design.pb +} RESULT] +if {$rc} { + step_failed opt_design + return -code error $RESULT +} else { + end_step opt_design + unset ACTIVE_STEP +} + +start_step place_design +set ACTIVE_STEP place_design +set rc [catch { + create_msg_db place_design.pb + if { [llength [get_debug_cores -quiet] ] > 0 } { + implement_debug_core + } + place_design + write_checkpoint -force VGA_top_placed.dcp + create_report "impl_1_place_report_io_0" "report_io -file VGA_top_io_placed.rpt" + create_report "impl_1_place_report_utilization_0" "report_utilization -file VGA_top_utilization_placed.rpt -pb VGA_top_utilization_placed.pb" + create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file VGA_top_control_sets_placed.rpt" + close_msg_db -file place_design.pb +} RESULT] +if {$rc} { + step_failed place_design + return -code error $RESULT +} else { + end_step place_design + unset ACTIVE_STEP +} + +start_step route_design +set ACTIVE_STEP route_design +set rc [catch { + create_msg_db route_design.pb + route_design + write_checkpoint -force VGA_top_routed.dcp + create_report "impl_1_route_report_drc_0" "report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx" + create_report "impl_1_route_report_methodology_0" "report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx" + create_report "impl_1_route_report_power_0" "report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx" + create_report "impl_1_route_report_route_status_0" "report_route_status -file VGA_top_route_status.rpt -pb VGA_top_route_status.pb" + create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file VGA_top_timing_summary_routed.rpt -pb VGA_top_timing_summary_routed.pb -rpx VGA_top_timing_summary_routed.rpx -warn_on_violation " + create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file VGA_top_incremental_reuse_routed.rpt" + create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file VGA_top_clock_utilization_routed.rpt" + create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file VGA_top_bus_skew_routed.rpt -pb VGA_top_bus_skew_routed.pb -rpx VGA_top_bus_skew_routed.rpx" + close_msg_db -file route_design.pb +} RESULT] +if {$rc} { + write_checkpoint -force VGA_top_routed_error.dcp + step_failed route_design + return -code error $RESULT +} else { + end_step route_design + unset ACTIVE_STEP +} + start_step write_bitstream set ACTIVE_STEP write_bitstream set rc [catch { create_msg_db write_bitstream.pb - set_param synth.incrementalSynthesisCache C:/Users/E209098F/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-12508-irb121-02-w/incrSyn - set_param xicom.use_bs_reader 1 - open_checkpoint VGA_top_routed.dcp - set_property webtalk.parent_dir C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.cache/wt [current_project] set_property XPM_LIBRARIES XPM_CDC [current_project] catch { write_mem_info -force VGA_top.mmi } write_bitstream -force VGA_top.bit diff --git a/projet-vga.runs/impl_1/VGA_top.vdi b/projet-vga.runs/impl_1/VGA_top.vdi index 404086c..83174f0 100644 --- a/projet-vga.runs/impl_1/VGA_top.vdi +++ b/projet-vga.runs/impl_1/VGA_top.vdi @@ -2,40 +2,43 @@ # Vivado v2018.3 (64-bit) # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Tue Dec 7 12:42:58 2021 -# Process ID: 4856 -# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1 +# Start of session at: Tue Jan 4 12:18:37 2022 +# Process ID: 13232 +# Current directory: C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/impl_1 # Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace -# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi -# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou +# Log file: C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/impl_1/VGA_top.vdi +# Journal file: C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/impl_1\vivado.jou #----------------------------------------------------------- source VGA_top.tcl -notrace Command: link_design -top VGA_top -part xc7z010clg400-1 Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 -INFO: [Project 1-454] Reading design checkpoint 'c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.dcp' for cell 'U0' -INFO: [Netlist 29-17] Analyzing 35 Unisim elements for replacement +INFO: [Project 1-454] Reading design checkpoint 'c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0.dcp' for cell 'U0' +INFO: [Netlist 29-17] Analyzing 314 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2018.3 INFO: [Device 21-403] Loading part xc7z010clg400-1 INFO: [Project 1-570] Preparing netlist for logic optimization -Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst' -Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst' -Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst' -INFO: [Timing 38-35] Done setting XDC timing constraints. [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57] -INFO: [Timing 38-2] Deriving generated clocks [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57] -get_clocks: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1248.586 ; gain = 558.375 -Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst' -Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc] -Finished Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc] +WARNING: [Opt 31-35] Removing redundant IBUF, U0/inst/clkin1_ibufg, from the path connected to top-level port: H125MHz +Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design. +WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'U0/clk_in1' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. +Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0_board.xdc] for cell 'U0/inst' +Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0_board.xdc] for cell 'U0/inst' +Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0.xdc] for cell 'U0/inst' +INFO: [Timing 38-35] Done setting XDC timing constraints. [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0.xdc:57] +INFO: [Timing 38-2] Deriving generated clocks [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0.xdc:57] +get_clocks: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1251.785 ; gain = 552.953 +Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0.xdc] for cell 'U0/inst' +Parsing XDC File [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/ZYBO_Master.xdc] +Finished Parsing XDC File [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/ZYBO_Master.xdc] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1248.586 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1251.785 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. -10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +10 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. link_design completed successfully -link_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:16 . Memory (MB): peak = 1248.586 ; gain = 885.598 +link_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:25 . Memory (MB): peak = 1251.785 ; gain = 888.395 Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' @@ -46,57 +49,58 @@ INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.499 . Memory (MB): peak = 1248.586 ; gain = 0.000 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.501 . Memory (MB): peak = 1251.785 ; gain = 0.000 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [Timing 38-2] Deriving generated clocks -Ending Cache Timing Information Task | Checksum: 20ae1d4cd +Ending Cache Timing Information Task | Checksum: 19f3e8d5f -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1265.152 ; gain = 16.566 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.092 . Memory (MB): peak = 1265.977 ; gain = 14.191 Starting Logic Optimization Task Phase 1 Retarget INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). -Phase 1 Retarget | Checksum: ddde5939 +Phase 1 Retarget | Checksum: c8a6b5ae -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 1351.098 ; gain = 0.000 -INFO: [Opt 31-389] Phase Retarget created 4 cells and removed 4 cells +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.096 . Memory (MB): peak = 1346.285 ; gain = 0.000 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 2 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Phase 2 Constant propagation | Checksum: ddde5939 +Phase 2 Constant propagation | Checksum: 1409f9166 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1351.098 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.123 . Memory (MB): peak = 1346.285 ; gain = 0.000 INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells Phase 3 Sweep -Phase 3 Sweep | Checksum: fec5e707 +Phase 3 Sweep | Checksum: 1b7440179 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 1351.098 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.178 . Memory (MB): peak = 1346.285 ; gain = 0.000 INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells +INFO: [Opt 31-1021] In phase Sweep, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 4 BUFG optimization INFO: [Opt 31-194] Inserted BUFG U0/inst/clk_out1_clk_wiz_1_BUFG_inst to drive 0 load(s) on clock net U0/inst/clk_out1_clk_wiz_1_BUFG -INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets -Phase 4 BUFG optimization | Checksum: 137e6b9d1 +INFO: [Opt 31-194] Inserted BUFG H125MHz_IBUF_BUFG_inst to drive 182 load(s) on clock net H125MHz_IBUF_BUFG +INFO: [Opt 31-193] Inserted 2 BUFG(s) on clock nets +Phase 4 BUFG optimization | Checksum: cecab300 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1351.098 ; gain = 0.000 -INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.259 . Memory (MB): peak = 1346.285 ; gain = 0.000 +INFO: [Opt 31-662] Phase BUFG optimization created 1 cells of which 1 are BUFGs and removed 0 cells. Phase 5 Shift Register Optimization -Phase 5 Shift Register Optimization | Checksum: 12c29fba6 +Phase 5 Shift Register Optimization | Checksum: 193828ea0 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.054 . Memory (MB): peak = 1351.098 ; gain = 0.000 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.412 . Memory (MB): peak = 1346.285 ; gain = 0.000 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 6 Post Processing Netlist -Phase 6 Post Processing Netlist | Checksum: 10c49128f +Phase 6 Post Processing Netlist | Checksum: 16ceef5f4 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.055 . Memory (MB): peak = 1351.098 ; gain = 0.000 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.421 . Memory (MB): peak = 1346.285 ; gain = 0.000 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells Opt_design Change Summary ========================= @@ -105,10 +109,10 @@ Opt_design Change Summary ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- -| Retarget | 4 | 4 | 1 | +| Retarget | 0 | 0 | 1 | | Constant propagation | 0 | 0 | 0 | -| Sweep | 0 | 0 | 0 | -| BUFG optimization | 0 | 0 | 0 | +| Sweep | 0 | 0 | 1 | +| BUFG optimization | 1 | 0 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 0 | 0 | ------------------------------------------------------------------------------------------------------------------------- @@ -117,44 +121,70 @@ Opt_design Change Summary Starting Connectivity Check Task -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1351.098 ; gain = 0.000 -Ending Logic Optimization Task | Checksum: e54fefee +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1346.285 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 20356351c -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.057 . Memory (MB): peak = 1351.098 ; gain = 0.000 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.429 . Memory (MB): peak = 1346.285 ; gain = 0.000 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. -Ending Power Optimization Task | Checksum: e54fefee +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-4.133 | TNS=-46.099 | +Running Vector-less Activity Propagation... -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1351.098 ; gain = 0.000 +Finished Running Vector-less Activity Propagation +INFO: [Pwropt 34-9] Applying IDT optimizations ... +INFO: [Pwropt 34-10] Applying ODC optimizations ... + + +Starting PowerOpt Patch Enables Task +INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 27 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. +INFO: [Pwropt 34-201] Structural ODC has moved 16 WE to EN ports +Number of BRAM Ports augmented: 0 newly gated: 25 Total Ports: 54 +Number of Flops added for Enable Generation: 2 + +Ending PowerOpt Patch Enables Task | Checksum: 215f1437d + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.085 . Memory (MB): peak = 1500.016 ; gain = 0.000 +Ending Power Optimization Task | Checksum: 215f1437d + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1500.016 ; gain = 153.730 Starting Final Cleanup Task -Ending Final Cleanup Task | Checksum: e54fefee -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000 +Starting Logic Optimization Task +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Opt 31-194] Inserted BUFG U0/inst/clk_out1_clk_wiz_1_BUFG_inst to drive 0 load(s) on clock net U0/inst/clk_out1_clk_wiz_1_BUFG +INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets +Ending Logic Optimization Task | Checksum: 2182f781c + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.228 . Memory (MB): peak = 1500.016 ; gain = 0.000 +Ending Final Cleanup Task | Checksum: 2182f781c + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.967 . Memory (MB): peak = 1500.016 ; gain = 0.000 Starting Netlist Obfuscation Task -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000 -Ending Netlist Obfuscation Task | Checksum: e54fefee +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1500.016 ; gain = 0.000 +Ending Netlist Obfuscation Task | Checksum: 2182f781c -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1500.016 ; gain = 0.000 INFO: [Common 17-83] Releasing license: Implementation -30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +40 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1500.016 ; gain = 0.000 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1351.098 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_opt.dcp' has been generated. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.035 . Memory (MB): peak = 1500.016 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1500.016 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/impl_1/VGA_top_opt.dcp' has been generated. INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx Command: report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_opted.rpt. +INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/impl_1/VGA_top_drc_opted.rpt. report_drc completed successfully Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' @@ -173,48 +203,56 @@ INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000 -Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 4ed236ad +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1500.016 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 131936915 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1351.098 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1500.016 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1500.016 ; gain = 0.000 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1a1c16c9c +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: d8624408 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.262 . Memory (MB): peak = 1351.098 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.459 . Memory (MB): peak = 1500.016 ; gain = 0.000 Phase 1.3 Build Placer Netlist Model -Phase 1.3 Build Placer Netlist Model | Checksum: 2939760d0 +Phase 1.3 Build Placer Netlist Model | Checksum: 1315496dd -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.351 . Memory (MB): peak = 1351.098 ; gain = 0.000 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.837 . Memory (MB): peak = 1500.016 ; gain = 0.000 Phase 1.4 Constrain Clocks/Macros -Phase 1.4 Constrain Clocks/Macros | Checksum: 2939760d0 +Phase 1.4 Constrain Clocks/Macros | Checksum: 1315496dd -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.353 . Memory (MB): peak = 1351.098 ; gain = 0.000 -Phase 1 Placer Initialization | Checksum: 2939760d0 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.840 . Memory (MB): peak = 1500.016 ; gain = 0.000 +Phase 1 Placer Initialization | Checksum: 1315496dd -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.353 . Memory (MB): peak = 1351.098 ; gain = 0.000 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.843 . Memory (MB): peak = 1500.016 ; gain = 0.000 Phase 2 Global Placement Phase 2.1 Floorplanning -Phase 2.1 Floorplanning | Checksum: 28231f14d +Phase 2.1 Floorplanning | Checksum: 1a8bfe1e0 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.397 . Memory (MB): peak = 1351.098 ; gain = 0.000 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.991 . Memory (MB): peak = 1500.016 ; gain = 0.000 Phase 2.2 Physical Synthesis In Placer INFO: [Physopt 32-65] No nets found for high-fanout optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell -INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed. -INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed. -INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed. +INFO: [Physopt 32-117] Net SNAKE/listRefs[8][0] could not be optimized because driver SNAKE/mem_reg_3_i_4 could not be replicated +INFO: [Physopt 32-117] Net SNAKE/listRefs[6][2] could not be optimized because driver SNAKE/mem_reg_1_i_4 could not be replicated +INFO: [Physopt 32-68] No nets found for critical-cell optimization. +INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. +INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-949] No candidate nets found for HD net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1351.098 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1500.016 ; gain = 0.000 Summary of Physical Synthesis Optimizations ============================================ @@ -224,60 +262,71 @@ Summary of Physical Synthesis Optimizations | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ---------------------------------------------------------------------------------------------------------------------------------------- | Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | +| Critical Cell | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| BRAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | HD Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| Total | 0 | 0 | 0 | 0 | 2 | 00:00:00 | +| Total | 0 | 0 | 0 | 0 | 6 | 00:00:00 | ---------------------------------------------------------------------------------------------------------------------------------------- -Phase 2.2 Physical Synthesis In Placer | Checksum: 22348ffd6 +Phase 2.2 Physical Synthesis In Placer | Checksum: aaf1c87e -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000 -Phase 2 Global Placement | Checksum: 2038a7242 +Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1500.016 ; gain = 0.000 +Phase 2 Global Placement | Checksum: 17a0bd3eb -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000 +Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1500.016 ; gain = 0.000 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros -Phase 3.1 Commit Multi Column Macros | Checksum: 2038a7242 +Phase 3.1 Commit Multi Column Macros | Checksum: 17a0bd3eb -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000 +Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1500.016 ; gain = 0.000 Phase 3.2 Commit Most Macros & LUTRAMs -Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 2c58c3354 +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 18c86a722 -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000 +Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1500.016 ; gain = 0.000 Phase 3.3 Area Swap Optimization -Phase 3.3 Area Swap Optimization | Checksum: 279aeb7b4 +Phase 3.3 Area Swap Optimization | Checksum: 19f5ea993 -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000 +Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1500.016 ; gain = 0.000 Phase 3.4 Pipeline Register Optimization -Phase 3.4 Pipeline Register Optimization | Checksum: 279aeb7b4 +Phase 3.4 Pipeline Register Optimization | Checksum: 1bfb8a901 -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000 +Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1500.016 ; gain = 0.000 -Phase 3.5 Small Shape Detail Placement -Phase 3.5 Small Shape Detail Placement | Checksum: 1e0aaeea1 +Phase 3.5 Fast Optimization +Phase 3.5 Fast Optimization | Checksum: 108c906c7 -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 1500.016 ; gain = 0.000 -Phase 3.6 Re-assign LUT pins -Phase 3.6 Re-assign LUT pins | Checksum: 2d338840d +Phase 3.6 Small Shape Detail Placement +Phase 3.6 Small Shape Detail Placement | Checksum: 1f5ba145a -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000 +Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 1500.016 ; gain = 0.000 -Phase 3.7 Pipeline Register Optimization -Phase 3.7 Pipeline Register Optimization | Checksum: 2d338840d +Phase 3.7 Re-assign LUT pins +Phase 3.7 Re-assign LUT pins | Checksum: 1ca5326f1 -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000 -Phase 3 Detail Placement | Checksum: 2d338840d +Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 1500.016 ; gain = 0.000 -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000 +Phase 3.8 Pipeline Register Optimization +Phase 3.8 Pipeline Register Optimization | Checksum: 1aa2d2687 + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 1500.016 ; gain = 0.000 + +Phase 3.9 Fast Optimization +Phase 3.9 Fast Optimization | Checksum: a4f5789a + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 1500.016 ; gain = 0.000 +Phase 3 Detail Placement | Checksum: a4f5789a + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 1500.016 ; gain = 0.000 Phase 4 Post Placement Optimization and Clean-Up @@ -285,59 +334,60 @@ Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization -Post Placement Optimization Initialization | Checksum: 15c68dcd4 +Post Placement Optimization Initialization | Checksum: 100368e26 Phase 4.1.1.1 BUFG Insertion INFO: [Place 46-46] BUFG insertion identified 0 candidate nets, 0 success, 0 bufg driver replicated, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason -Phase 4.1.1.1 BUFG Insertion | Checksum: 15c68dcd4 +Phase 4.1.1.1 BUFG Insertion | Checksum: 100368e26 -Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1351.098 ; gain = 0.000 -INFO: [Place 30-746] Post Placement Timing Summary WNS=35.245. For the most accurate timing information please run report_timing. -Phase 4.1.1 Post Placement Optimization | Checksum: 142e419cd +Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 1500.016 ; gain = 0.000 +INFO: [Place 30-746] Post Placement Timing Summary WNS=-3.374. For the most accurate timing information please run report_timing. +Phase 4.1.1 Post Placement Optimization | Checksum: be8bba9e -Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1351.098 ; gain = 0.000 -Phase 4.1 Post Commit Optimization | Checksum: 142e419cd +Time (s): cpu = 00:00:18 ; elapsed = 00:00:16 . Memory (MB): peak = 1500.016 ; gain = 0.000 +Phase 4.1 Post Commit Optimization | Checksum: be8bba9e -Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1351.098 ; gain = 0.000 +Time (s): cpu = 00:00:18 ; elapsed = 00:00:17 . Memory (MB): peak = 1500.016 ; gain = 0.000 Phase 4.2 Post Placement Cleanup -Phase 4.2 Post Placement Cleanup | Checksum: 142e419cd +Phase 4.2 Post Placement Cleanup | Checksum: be8bba9e -Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1351.098 ; gain = 0.000 +Time (s): cpu = 00:00:18 ; elapsed = 00:00:17 . Memory (MB): peak = 1500.016 ; gain = 0.000 Phase 4.3 Placer Reporting -Phase 4.3 Placer Reporting | Checksum: 142e419cd +Phase 4.3 Placer Reporting | Checksum: be8bba9e -Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1351.098 ; gain = 0.000 +Time (s): cpu = 00:00:18 ; elapsed = 00:00:17 . Memory (MB): peak = 1500.016 ; gain = 0.000 Phase 4.4 Final Placement Cleanup -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000 -Phase 4.4 Final Placement Cleanup | Checksum: 20695260e +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1500.016 ; gain = 0.000 +Phase 4.4 Final Placement Cleanup | Checksum: 540ff3bc -Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1351.098 ; gain = 0.000 -Phase 4 Post Placement Optimization and Clean-Up | Checksum: 20695260e +Time (s): cpu = 00:00:18 ; elapsed = 00:00:17 . Memory (MB): peak = 1500.016 ; gain = 0.000 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 540ff3bc -Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1351.098 ; gain = 0.000 -Ending Placer Task | Checksum: 1f2b3c1b8 +Time (s): cpu = 00:00:18 ; elapsed = 00:00:17 . Memory (MB): peak = 1500.016 ; gain = 0.000 +Ending Placer Task | Checksum: 531de2ac -Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1351.098 ; gain = 0.000 +Time (s): cpu = 00:00:18 ; elapsed = 00:00:17 . Memory (MB): peak = 1500.016 ; gain = 0.000 INFO: [Common 17-83] Releasing license: Implementation -57 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +75 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000 +place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:17 . Memory (MB): peak = 1500.016 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1500.016 ; gain = 0.000 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1500.016 ; gain = 0.000 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.050 . Memory (MB): peak = 1351.098 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_placed.dcp' has been generated. +Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.200 . Memory (MB): peak = 1500.016 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/impl_1/VGA_top_placed.dcp' has been generated. INFO: [runtcl-4] Executing : report_io -file VGA_top_io_placed.rpt -report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1351.098 ; gain = 0.000 +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.040 . Memory (MB): peak = 1500.016 ; gain = 0.000 INFO: [runtcl-4] Executing : report_utilization -file VGA_top_utilization_placed.rpt -pb VGA_top_utilization_placed.pb INFO: [runtcl-4] Executing : report_control_sets -verbose -file VGA_top_control_sets_placed.rpt -report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1351.098 ; gain = 0.000 +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1500.016 ; gain = 0.000 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' @@ -349,98 +399,150 @@ INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more in Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs -Checksum: PlaceDB: f9e7c0c6 ConstDB: 0 ShapeSum: f8cc00f2 RouteDB: 0 +Checksum: PlaceDB: 3ad47cdf ConstDB: 0 ShapeSum: 184965cd RouteDB: 0 Phase 1 Build RT Design -Phase 1 Build RT Design | Checksum: 9a64d846 +Phase 1 Build RT Design | Checksum: 13e412dc8 -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1417.348 ; gain = 66.250 -Post Restoration Checksum: NetGraph: 7c5b36de NumContArr: 1e09a168 Constraints: 0 Timing: 0 +Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1500.016 ; gain = 0.000 +Post Restoration Checksum: NetGraph: 58741a68 NumContArr: e5cd1360 Constraints: 0 Timing: 0 Phase 2 Router Initialization Phase 2.1 Create Timer -Phase 2.1 Create Timer | Checksum: 9a64d846 +Phase 2.1 Create Timer | Checksum: 13e412dc8 -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1449.676 ; gain = 98.578 +Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1500.016 ; gain = 0.000 Phase 2.2 Fix Topology Constraints -Phase 2.2 Fix Topology Constraints | Checksum: 9a64d846 +Phase 2.2 Fix Topology Constraints | Checksum: 13e412dc8 -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1455.699 ; gain = 104.602 +Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1500.016 ; gain = 0.000 Phase 2.3 Pre Route Cleanup -Phase 2.3 Pre Route Cleanup | Checksum: 9a64d846 +Phase 2.3 Pre Route Cleanup | Checksum: 13e412dc8 -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1455.699 ; gain = 104.602 +Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1500.016 ; gain = 0.000 Number of Nodes with overlaps = 0 Phase 2.4 Update Timing -Phase 2.4 Update Timing | Checksum: 82bae049 +Phase 2.4 Update Timing | Checksum: 1195a0f5b -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1460.445 ; gain = 109.348 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.391 | TNS=0.000 | WHS=-0.239 | THS=-2.915 | +Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1500.016 ; gain = 0.000 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=-3.513 | TNS=-50.092| WHS=-1.636 | THS=-51.724| -Phase 2 Router Initialization | Checksum: cf693307 +Phase 2 Router Initialization | Checksum: 12ae7c807 -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1460.445 ; gain = 109.348 +Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1500.016 ; gain = 0.000 Phase 3 Initial Routing -Phase 3 Initial Routing | Checksum: 16fee48da +Phase 3 Initial Routing | Checksum: 1b62d99da -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348 +Time (s): cpu = 00:00:24 ; elapsed = 00:00:17 . Memory (MB): peak = 1546.250 ; gain = 46.234 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 - Number of Nodes with overlaps = 36 + Number of Nodes with overlaps = 954 + Number of Nodes with overlaps = 235 + Number of Nodes with overlaps = 66 + Number of Nodes with overlaps = 42 + Number of Nodes with overlaps = 19 + Number of Nodes with overlaps = 16 + Number of Nodes with overlaps = 15 + Number of Nodes with overlaps = 7 + Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=33.088 | TNS=0.000 | WHS=N/A | THS=N/A | +INFO: [Route 35-416] Intermediate Timing Summary | WNS=-5.639 | TNS=-90.744| WHS=N/A | THS=N/A | -Phase 4.1 Global Iteration 0 | Checksum: 1c93f85f6 +Phase 4.1 Global Iteration 0 | Checksum: 1a754acba -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348 -Phase 4 Rip-up And Reroute | Checksum: 1c93f85f6 +Time (s): cpu = 00:01:24 ; elapsed = 00:01:06 . Memory (MB): peak = 1596.598 ; gain = 96.582 -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348 +Phase 4.2 Global Iteration 1 + Number of Nodes with overlaps = 146 + Number of Nodes with overlaps = 24 + Number of Nodes with overlaps = 9 + Number of Nodes with overlaps = 8 + Number of Nodes with overlaps = 8 + Number of Nodes with overlaps = 5 + Number of Nodes with overlaps = 7 + Number of Nodes with overlaps = 5 + Number of Nodes with overlaps = 5 + Number of Nodes with overlaps = 2 + Number of Nodes with overlaps = 2 + Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 7 + Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 6 + Number of Nodes with overlaps = 0 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=-5.630 | TNS=-88.178| WHS=N/A | THS=N/A | + +Phase 4.2 Global Iteration 1 | Checksum: 13f25b21c + +Time (s): cpu = 00:02:20 ; elapsed = 00:01:46 . Memory (MB): peak = 1630.195 ; gain = 130.180 +Phase 4 Rip-up And Reroute | Checksum: 13f25b21c + +Time (s): cpu = 00:02:20 ; elapsed = 00:01:46 . Memory (MB): peak = 1630.195 ; gain = 130.180 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp -Phase 5.1 Delay CleanUp | Checksum: 1c93f85f6 -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348 +Phase 5.1.1 Update Timing +Phase 5.1.1 Update Timing | Checksum: 21c9bd585 + +Time (s): cpu = 00:02:20 ; elapsed = 00:01:46 . Memory (MB): peak = 1630.195 ; gain = 130.180 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=-5.617 | TNS=-86.848| WHS=N/A | THS=N/A | + + Number of Nodes with overlaps = 0 +Phase 5.1 Delay CleanUp | Checksum: e7e5e811 + +Time (s): cpu = 00:02:20 ; elapsed = 00:01:46 . Memory (MB): peak = 1630.195 ; gain = 130.180 Phase 5.2 Clock Skew Optimization -Phase 5.2 Clock Skew Optimization | Checksum: 1c93f85f6 +Phase 5.2 Clock Skew Optimization | Checksum: e7e5e811 -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348 -Phase 5 Delay and Skew Optimization | Checksum: 1c93f85f6 +Time (s): cpu = 00:02:20 ; elapsed = 00:01:46 . Memory (MB): peak = 1630.195 ; gain = 130.180 +Phase 5 Delay and Skew Optimization | Checksum: e7e5e811 -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348 +Time (s): cpu = 00:02:20 ; elapsed = 00:01:46 . Memory (MB): peak = 1630.195 ; gain = 130.180 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing -Phase 6.1.1 Update Timing | Checksum: 144941f51 +Phase 6.1.1 Update Timing | Checksum: ef9abc12 -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=33.241 | TNS=0.000 | WHS=0.083 | THS=0.000 | +Time (s): cpu = 00:02:21 ; elapsed = 00:01:47 . Memory (MB): peak = 1630.195 ; gain = 130.180 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=-5.617 | TNS=-86.439| WHS=-0.443 | THS=-0.849 | -Phase 6.1 Hold Fix Iter | Checksum: 144941f51 +Phase 6.1 Hold Fix Iter | Checksum: 151f6c881 -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348 -Phase 6 Post Hold Fix | Checksum: 144941f51 +Time (s): cpu = 00:02:22 ; elapsed = 00:01:48 . Memory (MB): peak = 1630.195 ; gain = 130.180 +WARNING: [Route 35-468] The router encountered 388 pins that are both setup-critical and hold-critical and tried to fix hold violations at the expense of setup slack. Such pins are: + RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_302/I0 + SYNC/ROMAddress_reg[3]_i_146/DI[3] + SYNC/ROMAddress_reg[9]_i_237/DI[3] + SYNC/ROMAddress[9]_i_588/I0 + SYNC/ROMAddress[9]_i_595/I0 + RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_589/I1 + RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_624/I1 + SYNC/ROMAddress_reg[9]_i_237/DI[2] + SYNC/ROMAddress_reg[9]_i_266/DI[2] + SYNC/ROMAddress[3]_i_103/I5 + .. and 378 more pins. -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348 +Phase 6 Post Hold Fix | Checksum: 197295544 + +Time (s): cpu = 00:02:22 ; elapsed = 00:01:48 . Memory (MB): peak = 1630.195 ; gain = 130.180 Phase 7 Route finalize Router Utilization Summary - Global Vertical Routing Utilization = 0.0881194 % - Global Horizontal Routing Utilization = 0.100414 % + Global Vertical Routing Utilization = 2.83094 % + Global Horizontal Routing Utilization = 3.41935 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. @@ -449,58 +551,90 @@ Router Utilization Summary Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 -Phase 7 Route finalize | Checksum: 19cea99c1 +Congestion Report +North Dir 1x1 Area, Max Cong = 54.0541%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 79.2793%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 60.2941%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 75%, No Congested Regions. -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348 +------------------------------ +Reporting congestion hotspots +------------------------------ +Direction: North +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: South +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: East +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: West +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 + +Phase 7 Route finalize | Checksum: 1f1dffd6a + +Time (s): cpu = 00:02:22 ; elapsed = 00:01:48 . Memory (MB): peak = 1630.195 ; gain = 130.180 Phase 8 Verifying routed nets Verification completed successfully -Phase 8 Verifying routed nets | Checksum: 19cea99c1 +Phase 8 Verifying routed nets | Checksum: 1f1dffd6a -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1461.477 ; gain = 110.379 +Time (s): cpu = 00:02:22 ; elapsed = 00:01:48 . Memory (MB): peak = 1630.195 ; gain = 130.180 Phase 9 Depositing Routes -Phase 9 Depositing Routes | Checksum: 17f26a4e0 +Phase 9 Depositing Routes | Checksum: 238ddaa41 -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1461.477 ; gain = 110.379 +Time (s): cpu = 00:02:23 ; elapsed = 00:01:49 . Memory (MB): peak = 1630.195 ; gain = 130.180 Phase 10 Post Router Timing -INFO: [Route 35-57] Estimated Timing Summary | WNS=33.241 | TNS=0.000 | WHS=0.083 | THS=0.000 | -INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. -Phase 10 Post Router Timing | Checksum: 17f26a4e0 +Phase 10.1 Update Timing +Phase 10.1 Update Timing | Checksum: 1f42f7dac -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1461.477 ; gain = 110.379 +Time (s): cpu = 00:02:23 ; elapsed = 00:01:49 . Memory (MB): peak = 1630.195 ; gain = 130.180 +INFO: [Route 35-57] Estimated Timing Summary | WNS=-5.617 | TNS=-86.439| WHS=-0.027 | THS=-0.027 | + +WARNING: [Route 35-328] Router estimated timing not met. +Resolution: For a complete and accurate timing signoff, report_timing_summary must be run after route_design. Alternatively, route_design can be run with the -timing_summary option to enable a complete timing signoff at the end of route_design. +Phase 10 Post Router Timing | Checksum: 1f42f7dac + +Time (s): cpu = 00:02:23 ; elapsed = 00:01:49 . Memory (MB): peak = 1630.195 ; gain = 130.180 INFO: [Route 35-16] Router Completed Successfully -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1461.477 ; gain = 110.379 +Time (s): cpu = 00:02:23 ; elapsed = 00:01:49 . Memory (MB): peak = 1630.195 ; gain = 130.180 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation -74 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +93 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully -route_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:22 . Memory (MB): peak = 1461.477 ; gain = 110.379 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1461.477 ; gain = 0.000 +route_design: Time (s): cpu = 00:02:25 ; elapsed = 00:01:52 . Memory (MB): peak = 1630.195 ; gain = 130.180 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1630.195 ; gain = 0.000 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1630.195 ; gain = 0.000 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.054 . Memory (MB): peak = 1461.910 ; gain = 0.434 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1461.910 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_routed.dcp' has been generated. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.257 . Memory (MB): peak = 1630.195 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/impl_1/VGA_top_routed.dcp' has been generated. INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx Command: report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_routed.rpt. +INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/impl_1/VGA_top_drc_routed.rpt. report_drc completed successfully INFO: [runtcl-4] Executing : report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx Command: report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [DRC 23-133] Running Methodology with 2 threads -INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_methodology_drc_routed.rpt. +INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/impl_1/VGA_top_methodology_drc_routed.rpt. report_methodology completed successfully INFO: [runtcl-4] Executing : report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx Command: report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx @@ -508,67 +642,33 @@ INFO: [Timing 38-35] Done setting XDC timing constraints. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation -86 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +105 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. report_power completed successfully INFO: [runtcl-4] Executing : report_route_status -file VGA_top_route_status.rpt -pb VGA_top_route_status.pb INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file VGA_top_timing_summary_routed.rpt -pb VGA_top_timing_summary_routed.pb -rpx VGA_top_timing_summary_routed.rpx -warn_on_violation INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +CRITICAL WARNING: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations. INFO: [runtcl-4] Executing : report_incremental_reuse -file VGA_top_incremental_reuse_routed.rpt INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. INFO: [runtcl-4] Executing : report_clock_utilization -file VGA_top_clock_utilization_routed.rpt INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file VGA_top_bus_skew_routed.rpt -pb VGA_top_bus_skew_routed.pb -rpx VGA_top_bus_skew_routed.rpx INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs -INFO: [Common 17-206] Exiting Vivado at Tue Dec 7 12:43:48 2021... -#----------------------------------------------------------- -# Vivado v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Tue Dec 7 12:44:06 2021 -# Process ID: 5252 -# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1 -# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace -# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi -# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou -#----------------------------------------------------------- -source VGA_top.tcl -notrace -Command: open_checkpoint VGA_top_routed.dcp - -Starting open_checkpoint Task - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 250.652 ; gain = 0.000 -INFO: [Netlist 29-17] Analyzing 35 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-479] Netlist was created with Vivado 2018.3 -INFO: [Device 21-403] Loading part xc7z010clg400-1 -INFO: [Project 1-570] Preparing netlist for logic optimization -INFO: [Timing 38-478] Restoring timing data from binary archive. -INFO: [Timing 38-479] Binary timing data restore complete. -INFO: [Project 1-856] Restoring constraints from binary archive. -INFO: [Project 1-853] Binary constraint restore complete. -Reading XDEF placement. -Reading placer database... -Reading XDEF routing. -Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.095 . Memory (MB): peak = 1208.145 ; gain = 0.000 -Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB | -Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.095 . Memory (MB): peak = 1208.145 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1208.145 ; gain = 0.000 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -INFO: [Project 1-604] Checkpoint was created with Vivado v2018.3 (64-bit) build 2405991 -open_checkpoint: Time (s): cpu = 00:00:12 ; elapsed = 00:00:17 . Memory (MB): peak = 1208.145 ; gain = 957.492 Command: write_bitstream -force VGA_top.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' Running DRC as a precondition to command write_bitstream -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1704] No user IP repositories specified -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2018.3/data/ip'. +INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [DRC 23-27] Running DRC with 2 threads +WARNING: [DRC PDRC-153] Gated clock check: Net UPD/dataOut_reg[18]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin UPD/dataOut_reg[18]_LDC_i_1/O, cell UPD/dataOut_reg[18]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net UPD/dataOut_reg[19]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin UPD/dataOut_reg[19]_LDC_i_1/O, cell UPD/dataOut_reg[19]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net UPD/dataOut_reg[1]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin UPD/dataOut_reg[1]_LDC_i_1/O, cell UPD/dataOut_reg[1]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net UPD/dataOut_reg[20]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin UPD/dataOut_reg[20]_LDC_i_1/O, cell UPD/dataOut_reg[20]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net UPD/dataOut_reg[21]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin UPD/dataOut_reg[21]_LDC_i_1/O, cell UPD/dataOut_reg[21]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net UPD/dataOut_reg[4]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin UPD/dataOut_reg[4]_LDC_i_1/O, cell UPD/dataOut_reg[4]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. -INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings +INFO: [Vivado 12-3199] DRC finished with 0 Errors, 7 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Designutils 20-2272] Running write_bitstream with 2 threads. Loading data files... @@ -579,9 +679,9 @@ Creating bitmap... Creating bitstream... Writing bitstream ./VGA_top.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. -INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. +INFO: [Project 1-118] WebTalk data collection is enabled (User setting is ON. Install Setting is ON.). INFO: [Common 17-83] Releasing license: Implementation -22 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +124 Infos, 11 Warnings, 1 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully -write_bitstream: Time (s): cpu = 00:00:10 ; elapsed = 00:00:28 . Memory (MB): peak = 1679.344 ; gain = 471.199 -INFO: [Common 17-206] Exiting Vivado at Tue Dec 7 12:44:53 2021... +write_bitstream: Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1942.887 ; gain = 312.691 +INFO: [Common 17-206] Exiting Vivado at Tue Jan 4 12:21:36 2022... diff --git a/projet-vga.runs/impl_1/VGA_top_11872.backup.vdi b/projet-vga.runs/impl_1/VGA_top_11872.backup.vdi deleted file mode 100644 index df23f99..0000000 --- a/projet-vga.runs/impl_1/VGA_top_11872.backup.vdi +++ /dev/null @@ -1,534 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Tue Nov 23 09:55:17 2021 -# Process ID: 11872 -# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1 -# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace -# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi -# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou -#----------------------------------------------------------- -source VGA_top.tcl -notrace -Command: link_design -top VGA_top -part xc7z010clg400-1 -Design is defaulting to srcset: sources_1 -Design is defaulting to constrset: constrs_1 -INFO: [Project 1-454] Reading design checkpoint 'c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.dcp' for cell 'U0' -INFO: [Netlist 29-17] Analyzing 7 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-479] Netlist was created with Vivado 2018.3 -INFO: [Device 21-403] Loading part xc7z010clg400-1 -INFO: [Project 1-570] Preparing netlist for logic optimization -Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst' -Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst' -Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst' -INFO: [Timing 38-35] Done setting XDC timing constraints. [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57] -INFO: [Timing 38-2] Deriving generated clocks [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57] -get_clocks: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1242.094 ; gain = 551.320 -Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst' -Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc] -Finished Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc] -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1242.094 ; gain = 0.000 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -link_design completed successfully -link_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:24 . Memory (MB): peak = 1242.094 ; gain = 879.125 -Command: opt_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' -Running DRC as a precondition to command opt_design - -Starting DRC Task -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Project 1-461] DRC finished with 0 Errors -INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.510 . Memory (MB): peak = 1242.094 ; gain = 0.000 - -Starting Cache Timing Information Task -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [Timing 38-2] Deriving generated clocks -Ending Cache Timing Information Task | Checksum: 167d6f2bc - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1258.906 ; gain = 16.812 - -Starting Logic Optimization Task - -Phase 1 Retarget -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -INFO: [Opt 31-49] Retargeted 0 cell(s). -Phase 1 Retarget | Checksum: 167d6f2bc - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1342.871 ; gain = 0.000 -INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells -INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. - -Phase 2 Constant propagation -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Phase 2 Constant propagation | Checksum: 167d6f2bc - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1342.871 ; gain = 0.000 -INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells - -Phase 3 Sweep -Phase 3 Sweep | Checksum: bfc412b4 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 1342.871 ; gain = 0.000 -INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells - -Phase 4 BUFG optimization -INFO: [Opt 31-194] Inserted BUFG U0/inst/clk_out1_clk_wiz_1_BUFG_inst to drive 0 load(s) on clock net U0/inst/clk_out1_clk_wiz_1_BUFG -INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets -Phase 4 BUFG optimization | Checksum: 1480b8b7b - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1342.871 ; gain = 0.000 -INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. - -Phase 5 Shift Register Optimization -Phase 5 Shift Register Optimization | Checksum: 20e74a998 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.031 . Memory (MB): peak = 1342.871 ; gain = 0.000 -INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells - -Phase 6 Post Processing Netlist -Phase 6 Post Processing Netlist | Checksum: 1b12e64f9 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1342.871 ; gain = 0.000 -INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells -Opt_design Change Summary -========================= - - -------------------------------------------------------------------------------------------------------------------------- -| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | -------------------------------------------------------------------------------------------------------------------------- -| Retarget | 0 | 0 | 1 | -| Constant propagation | 0 | 0 | 0 | -| Sweep | 0 | 0 | 0 | -| BUFG optimization | 0 | 0 | 0 | -| Shift Register Optimization | 0 | 0 | 0 | -| Post Processing Netlist | 0 | 0 | 0 | -------------------------------------------------------------------------------------------------------------------------- - - - -Starting Connectivity Check Task - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.871 ; gain = 0.000 -Ending Logic Optimization Task | Checksum: 14d3cc591 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1342.871 ; gain = 0.000 - -Starting Power Optimization Task -INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. -Ending Power Optimization Task | Checksum: 14d3cc591 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1342.871 ; gain = 0.000 - -Starting Final Cleanup Task -Ending Final Cleanup Task | Checksum: 14d3cc591 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.871 ; gain = 0.000 - -Starting Netlist Obfuscation Task -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.871 ; gain = 0.000 -Ending Netlist Obfuscation Task | Checksum: 14d3cc591 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.871 ; gain = 0.000 -INFO: [Common 17-83] Releasing license: Implementation -30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -opt_design completed successfully -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.871 ; gain = 0.000 -INFO: [Timing 38-480] Writing timing data to binary archive. -Writing placer database... -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1342.871 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.871 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_opt.dcp' has been generated. -INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx -Command: report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx -INFO: [IP_Flow 19-1839] IP Catalog is up to date. -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_opted.rpt. -report_drc completed successfully -Command: place_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. -Running DRC as a precondition to command place_design -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. - -Starting Placer Task -INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs - -Phase 1 Placer Initialization - -Phase 1.1 Placer Initialization Netlist Sorting -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.871 ; gain = 0.000 -Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 12c34edfb - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1342.871 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.871 ; gain = 0.000 - -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device -INFO: [Timing 38-35] Done setting XDC timing constraints. -WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. - - bouton_down_IBUF_inst (IBUF.O) is locked to IOB_X0Y1 - bouton_down_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 -Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 172dde9eb - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.276 . Memory (MB): peak = 1342.871 ; gain = 0.000 - -Phase 1.3 Build Placer Netlist Model -Phase 1.3 Build Placer Netlist Model | Checksum: 1fe9c5a85 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.329 . Memory (MB): peak = 1342.871 ; gain = 0.000 - -Phase 1.4 Constrain Clocks/Macros -Phase 1.4 Constrain Clocks/Macros | Checksum: 1fe9c5a85 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.330 . Memory (MB): peak = 1342.871 ; gain = 0.000 -Phase 1 Placer Initialization | Checksum: 1fe9c5a85 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.330 . Memory (MB): peak = 1342.871 ; gain = 0.000 - -Phase 2 Global Placement - -Phase 2.1 Floorplanning -Phase 2.1 Floorplanning | Checksum: 24fbfc31b - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.362 . Memory (MB): peak = 1342.871 ; gain = 0.000 - -Phase 2.2 Physical Synthesis In Placer -INFO: [Physopt 32-65] No nets found for high-fanout optimization. -INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. -INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell -INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed. -INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed. -INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed. -INFO: [Physopt 32-949] No candidate nets found for HD net replication -INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.871 ; gain = 0.000 - -Summary of Physical Synthesis Optimizations -============================================ - - ----------------------------------------------------------------------------------------------------------------------------------------- -| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------- -| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| HD Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| Total | 0 | 0 | 0 | 0 | 2 | 00:00:00 | ----------------------------------------------------------------------------------------------------------------------------------------- - - -Phase 2.2 Physical Synthesis In Placer | Checksum: 19571fbec - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.767 . Memory (MB): peak = 1342.871 ; gain = 0.000 -Phase 2 Global Placement | Checksum: 19f068e3b - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.778 . Memory (MB): peak = 1342.871 ; gain = 0.000 - -Phase 3 Detail Placement - -Phase 3.1 Commit Multi Column Macros -Phase 3.1 Commit Multi Column Macros | Checksum: 19f068e3b - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.779 . Memory (MB): peak = 1342.871 ; gain = 0.000 - -Phase 3.2 Commit Most Macros & LUTRAMs -Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 15793daff - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.810 . Memory (MB): peak = 1342.871 ; gain = 0.000 - -Phase 3.3 Area Swap Optimization -Phase 3.3 Area Swap Optimization | Checksum: 140188978 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.812 . Memory (MB): peak = 1342.871 ; gain = 0.000 - -Phase 3.4 Pipeline Register Optimization -Phase 3.4 Pipeline Register Optimization | Checksum: 1b233c362 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.813 . Memory (MB): peak = 1342.871 ; gain = 0.000 - -Phase 3.5 Small Shape Detail Placement -Phase 3.5 Small Shape Detail Placement | Checksum: 13118e91f - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.865 . Memory (MB): peak = 1342.871 ; gain = 0.000 - -Phase 3.6 Re-assign LUT pins -Phase 3.6 Re-assign LUT pins | Checksum: 8f675022 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.871 . Memory (MB): peak = 1342.871 ; gain = 0.000 - -Phase 3.7 Pipeline Register Optimization -Phase 3.7 Pipeline Register Optimization | Checksum: 1208a0a3c - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.872 . Memory (MB): peak = 1342.871 ; gain = 0.000 -Phase 3 Detail Placement | Checksum: 1208a0a3c - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.873 . Memory (MB): peak = 1342.871 ; gain = 0.000 - -Phase 4 Post Placement Optimization and Clean-Up - -Phase 4.1 Post Commit Optimization -INFO: [Timing 38-35] Done setting XDC timing constraints. - -Phase 4.1.1 Post Placement Optimization -Post Placement Optimization Initialization | Checksum: 150311e2f - -Phase 4.1.1.1 BUFG Insertion -INFO: [Place 46-46] BUFG insertion identified 0 candidate nets, 0 success, 0 bufg driver replicated, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason -Phase 4.1.1.1 BUFG Insertion | Checksum: 150311e2f - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.917 . Memory (MB): peak = 1342.871 ; gain = 0.000 -INFO: [Place 30-746] Post Placement Timing Summary WNS=35.783. For the most accurate timing information please run report_timing. -Phase 4.1.1 Post Placement Optimization | Checksum: 1b17843c4 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.918 . Memory (MB): peak = 1342.871 ; gain = 0.000 -Phase 4.1 Post Commit Optimization | Checksum: 1b17843c4 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.918 . Memory (MB): peak = 1342.871 ; gain = 0.000 - -Phase 4.2 Post Placement Cleanup -Phase 4.2 Post Placement Cleanup | Checksum: 1b17843c4 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.920 . Memory (MB): peak = 1342.871 ; gain = 0.000 - -Phase 4.3 Placer Reporting -Phase 4.3 Placer Reporting | Checksum: 1b17843c4 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.921 . Memory (MB): peak = 1342.871 ; gain = 0.000 - -Phase 4.4 Final Placement Cleanup -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.871 ; gain = 0.000 -Phase 4.4 Final Placement Cleanup | Checksum: 18c66ff7a - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.923 . Memory (MB): peak = 1342.871 ; gain = 0.000 -Phase 4 Post Placement Optimization and Clean-Up | Checksum: 18c66ff7a - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.923 . Memory (MB): peak = 1342.871 ; gain = 0.000 -Ending Placer Task | Checksum: d428089a - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.924 . Memory (MB): peak = 1342.871 ; gain = 0.000 -INFO: [Common 17-83] Releasing license: Implementation -57 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. -place_design completed successfully -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.871 ; gain = 0.000 -INFO: [Timing 38-480] Writing timing data to binary archive. -Writing placer database... -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.041 . Memory (MB): peak = 1342.871 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.871 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_placed.dcp' has been generated. -INFO: [runtcl-4] Executing : report_io -file VGA_top_io_placed.rpt -report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 1342.871 ; gain = 0.000 -INFO: [runtcl-4] Executing : report_utilization -file VGA_top_utilization_placed.rpt -pb VGA_top_utilization_placed.pb -INFO: [runtcl-4] Executing : report_control_sets -verbose -file VGA_top_control_sets_placed.rpt -report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1342.871 ; gain = 0.000 -Command: route_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' -Running DRC as a precondition to command route_design -INFO: [DRC 23-27] Running DRC with 2 threads -WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. -Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. - This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. - - bouton_down_IBUF_inst (IBUF.O) is locked to IOB_X0Y1 - bouton_down_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. - - -Starting Routing Task -INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs -Checksum: PlaceDB: efe4607 ConstDB: 0 ShapeSum: c529c293 RouteDB: 0 - -Phase 1 Build RT Design -Phase 1 Build RT Design | Checksum: ce868b76 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1412.223 ; gain = 69.352 -Post Restoration Checksum: NetGraph: a7807a20 NumContArr: 27061156 Constraints: 0 Timing: 0 - -Phase 2 Router Initialization - -Phase 2.1 Create Timer -Phase 2.1 Create Timer | Checksum: ce868b76 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1442.484 ; gain = 99.613 - -Phase 2.2 Fix Topology Constraints -Phase 2.2 Fix Topology Constraints | Checksum: ce868b76 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1448.547 ; gain = 105.676 - -Phase 2.3 Pre Route Cleanup -Phase 2.3 Pre Route Cleanup | Checksum: ce868b76 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1448.547 ; gain = 105.676 - Number of Nodes with overlaps = 0 - -Phase 2.4 Update Timing -Phase 2.4 Update Timing | Checksum: dcb7e2f8 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1453.652 ; gain = 110.781 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.908 | TNS=0.000 | WHS=-0.278 | THS=-4.597 | - -Phase 2 Router Initialization | Checksum: 173ad2ca3 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1453.652 ; gain = 110.781 - -Phase 3 Initial Routing -Phase 3 Initial Routing | Checksum: 1c424a5c2 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1453.652 ; gain = 110.781 - -Phase 4 Rip-up And Reroute - -Phase 4.1 Global Iteration 0 - Number of Nodes with overlaps = 9 - Number of Nodes with overlaps = 0 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=34.457 | TNS=0.000 | WHS=N/A | THS=N/A | - -Phase 4.1 Global Iteration 0 | Checksum: 123c29b62 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1453.652 ; gain = 110.781 -Phase 4 Rip-up And Reroute | Checksum: 123c29b62 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1453.652 ; gain = 110.781 - -Phase 5 Delay and Skew Optimization - -Phase 5.1 Delay CleanUp -Phase 5.1 Delay CleanUp | Checksum: 123c29b62 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1453.652 ; gain = 110.781 - -Phase 5.2 Clock Skew Optimization -Phase 5.2 Clock Skew Optimization | Checksum: 123c29b62 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1453.652 ; gain = 110.781 -Phase 5 Delay and Skew Optimization | Checksum: 123c29b62 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1453.652 ; gain = 110.781 - -Phase 6 Post Hold Fix - -Phase 6.1 Hold Fix Iter - -Phase 6.1.1 Update Timing -Phase 6.1.1 Update Timing | Checksum: fe7535e4 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1453.652 ; gain = 110.781 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=34.610 | TNS=0.000 | WHS=0.075 | THS=0.000 | - -Phase 6.1 Hold Fix Iter | Checksum: fe7535e4 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1453.652 ; gain = 110.781 -Phase 6 Post Hold Fix | Checksum: fe7535e4 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1453.652 ; gain = 110.781 - -Phase 7 Route finalize - -Router Utilization Summary - Global Vertical Routing Utilization = 0.0425113 % - Global Horizontal Routing Utilization = 0.0321691 % - Routable Net Status* - *Does not include unroutable nets such as driverless and loadless. - Run report_route_status for detailed report. - Number of Failed Nets = 0 - Number of Unrouted Nets = 0 - Number of Partially Routed Nets = 0 - Number of Node Overlaps = 0 - -Phase 7 Route finalize | Checksum: fe7535e4 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1453.652 ; gain = 110.781 - -Phase 8 Verifying routed nets - - Verification completed successfully -Phase 8 Verifying routed nets | Checksum: fe7535e4 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1454.480 ; gain = 111.609 - -Phase 9 Depositing Routes -Phase 9 Depositing Routes | Checksum: ac130b84 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1454.480 ; gain = 111.609 - -Phase 10 Post Router Timing -INFO: [Route 35-57] Estimated Timing Summary | WNS=34.610 | TNS=0.000 | WHS=0.075 | THS=0.000 | - -INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. -Phase 10 Post Router Timing | Checksum: ac130b84 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1454.480 ; gain = 111.609 -INFO: [Route 35-16] Router Completed Successfully - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1454.480 ; gain = 111.609 - -Routing Is Done. -INFO: [Common 17-83] Releasing license: Implementation -74 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. -route_design completed successfully -route_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1454.480 ; gain = 111.609 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1454.480 ; gain = 0.000 -INFO: [Timing 38-480] Writing timing data to binary archive. -Writing placer database... -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.043 . Memory (MB): peak = 1454.938 ; gain = 0.457 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1454.938 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_routed.dcp' has been generated. -INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx -Command: report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx -INFO: [IP_Flow 19-1839] IP Catalog is up to date. -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_routed.rpt. -report_drc completed successfully -INFO: [runtcl-4] Executing : report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx -Command: report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [DRC 23-133] Running Methodology with 2 threads -INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_methodology_drc_routed.rpt. -report_methodology completed successfully -INFO: [runtcl-4] Executing : report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx -Command: report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx -INFO: [Timing 38-35] Done setting XDC timing constraints. -Running Vector-less Activity Propagation... - -Finished Running Vector-less Activity Propagation -86 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. -report_power completed successfully -INFO: [runtcl-4] Executing : report_route_status -file VGA_top_route_status.rpt -pb VGA_top_route_status.pb -INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file VGA_top_timing_summary_routed.rpt -pb VGA_top_timing_summary_routed.pb -rpx VGA_top_timing_summary_routed.rpx -warn_on_violation -INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. -INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs -INFO: [runtcl-4] Executing : report_incremental_reuse -file VGA_top_incremental_reuse_routed.rpt -INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. -INFO: [runtcl-4] Executing : report_clock_utilization -file VGA_top_clock_utilization_routed.rpt -INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file VGA_top_bus_skew_routed.rpt -pb VGA_top_bus_skew_routed.pb -rpx VGA_top_bus_skew_routed.rpx -INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. -INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs -INFO: [Common 17-206] Exiting Vivado at Tue Nov 23 09:56:04 2021... diff --git a/projet-vga.runs/impl_1/VGA_top_12280.backup.vdi b/projet-vga.runs/impl_1/VGA_top_12280.backup.vdi deleted file mode 100644 index 46da341..0000000 --- a/projet-vga.runs/impl_1/VGA_top_12280.backup.vdi +++ /dev/null @@ -1,523 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Tue Nov 30 12:02:04 2021 -# Process ID: 12280 -# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1 -# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace -# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi -# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou -#----------------------------------------------------------- -source VGA_top.tcl -notrace -Command: link_design -top VGA_top -part xc7z010clg400-1 -Design is defaulting to srcset: sources_1 -Design is defaulting to constrset: constrs_1 -INFO: [Project 1-454] Reading design checkpoint 'c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.dcp' for cell 'U0' -INFO: [Netlist 29-17] Analyzing 3 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-479] Netlist was created with Vivado 2018.3 -INFO: [Device 21-403] Loading part xc7z010clg400-1 -INFO: [Project 1-570] Preparing netlist for logic optimization -Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst' -Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst' -Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst' -INFO: [Timing 38-35] Done setting XDC timing constraints. [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57] -INFO: [Timing 38-2] Deriving generated clocks [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57] -get_clocks: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1224.238 ; gain = 533.496 -Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst' -Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc] -Finished Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc] -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1224.238 ; gain = 0.000 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -link_design completed successfully -link_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:16 . Memory (MB): peak = 1224.238 ; gain = 861.020 -Command: opt_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' -Running DRC as a precondition to command opt_design - -Starting DRC Task -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Project 1-461] DRC finished with 0 Errors -INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.499 . Memory (MB): peak = 1224.238 ; gain = 0.000 - -Starting Cache Timing Information Task -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [Timing 38-2] Deriving generated clocks -Ending Cache Timing Information Task | Checksum: d1b7283d - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1241.336 ; gain = 17.098 - -Starting Logic Optimization Task - -Phase 1 Retarget -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -INFO: [Opt 31-49] Retargeted 0 cell(s). -Phase 1 Retarget | Checksum: d1b7283d - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1327.883 ; gain = 0.000 -INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells -INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. - -Phase 2 Constant propagation -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Phase 2 Constant propagation | Checksum: d1b7283d - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1327.883 ; gain = 0.000 -INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells - -Phase 3 Sweep -Phase 3 Sweep | Checksum: 4c4916a3 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1327.883 ; gain = 0.000 -INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells - -Phase 4 BUFG optimization -INFO: [Opt 31-194] Inserted BUFG U0/inst/clk_out1_clk_wiz_1_BUFG_inst to drive 0 load(s) on clock net U0/inst/clk_out1_clk_wiz_1_BUFG -INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets -Phase 4 BUFG optimization | Checksum: ea635365 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1327.883 ; gain = 0.000 -INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. - -Phase 5 Shift Register Optimization -Phase 5 Shift Register Optimization | Checksum: 189961a21 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 1327.883 ; gain = 0.000 -INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells - -Phase 6 Post Processing Netlist -Phase 6 Post Processing Netlist | Checksum: fdaedd04 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1327.883 ; gain = 0.000 -INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells -Opt_design Change Summary -========================= - - -------------------------------------------------------------------------------------------------------------------------- -| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | -------------------------------------------------------------------------------------------------------------------------- -| Retarget | 0 | 0 | 1 | -| Constant propagation | 0 | 0 | 0 | -| Sweep | 0 | 0 | 0 | -| BUFG optimization | 0 | 0 | 0 | -| Shift Register Optimization | 0 | 0 | 0 | -| Post Processing Netlist | 0 | 0 | 0 | -------------------------------------------------------------------------------------------------------------------------- - - - -Starting Connectivity Check Task - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1327.883 ; gain = 0.000 -Ending Logic Optimization Task | Checksum: 1a5a98288 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 1327.883 ; gain = 0.000 - -Starting Power Optimization Task -INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. -Ending Power Optimization Task | Checksum: 1a5a98288 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1327.883 ; gain = 0.000 - -Starting Final Cleanup Task -Ending Final Cleanup Task | Checksum: 1a5a98288 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1327.883 ; gain = 0.000 - -Starting Netlist Obfuscation Task -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1327.883 ; gain = 0.000 -Ending Netlist Obfuscation Task | Checksum: 1a5a98288 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1327.883 ; gain = 0.000 -INFO: [Common 17-83] Releasing license: Implementation -30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -opt_design completed successfully -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1327.883 ; gain = 0.000 -INFO: [Timing 38-480] Writing timing data to binary archive. -Writing placer database... -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1327.883 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1327.883 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_opt.dcp' has been generated. -INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx -Command: report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx -INFO: [IP_Flow 19-1839] IP Catalog is up to date. -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_opted.rpt. -report_drc completed successfully -Command: place_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. -Running DRC as a precondition to command place_design -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. - -Starting Placer Task -INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs - -Phase 1 Placer Initialization - -Phase 1.1 Placer Initialization Netlist Sorting -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1327.883 ; gain = 0.000 -Phase 1.1 Placer Initialization Netlist Sorting | Checksum: f74f5d31 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1327.883 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1327.883 ; gain = 0.000 - -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device -INFO: [Timing 38-35] Done setting XDC timing constraints. -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: dff97cf7 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.238 . Memory (MB): peak = 1327.883 ; gain = 0.000 - -Phase 1.3 Build Placer Netlist Model -Phase 1.3 Build Placer Netlist Model | Checksum: 1427c2c70 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.291 . Memory (MB): peak = 1327.883 ; gain = 0.000 - -Phase 1.4 Constrain Clocks/Macros -Phase 1.4 Constrain Clocks/Macros | Checksum: 1427c2c70 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.292 . Memory (MB): peak = 1327.883 ; gain = 0.000 -Phase 1 Placer Initialization | Checksum: 1427c2c70 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.293 . Memory (MB): peak = 1327.883 ; gain = 0.000 - -Phase 2 Global Placement - -Phase 2.1 Floorplanning -Phase 2.1 Floorplanning | Checksum: fef86770 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.335 . Memory (MB): peak = 1327.883 ; gain = 0.000 - -Phase 2.2 Physical Synthesis In Placer -INFO: [Physopt 32-65] No nets found for high-fanout optimization. -INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. -INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell -INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed. -INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed. -INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed. -INFO: [Physopt 32-949] No candidate nets found for HD net replication -INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1327.883 ; gain = 0.000 - -Summary of Physical Synthesis Optimizations -============================================ - - ----------------------------------------------------------------------------------------------------------------------------------------- -| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------- -| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| HD Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| Total | 0 | 0 | 0 | 0 | 2 | 00:00:00 | ----------------------------------------------------------------------------------------------------------------------------------------- - - -Phase 2.2 Physical Synthesis In Placer | Checksum: 1ace7cfcc - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.633 . Memory (MB): peak = 1327.883 ; gain = 0.000 -Phase 2 Global Placement | Checksum: 141a32296 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.643 . Memory (MB): peak = 1327.883 ; gain = 0.000 - -Phase 3 Detail Placement - -Phase 3.1 Commit Multi Column Macros -Phase 3.1 Commit Multi Column Macros | Checksum: 141a32296 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.644 . Memory (MB): peak = 1327.883 ; gain = 0.000 - -Phase 3.2 Commit Most Macros & LUTRAMs -Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 78fa4a02 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.691 . Memory (MB): peak = 1327.883 ; gain = 0.000 - -Phase 3.3 Area Swap Optimization -Phase 3.3 Area Swap Optimization | Checksum: d7dfc3b7 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.694 . Memory (MB): peak = 1327.883 ; gain = 0.000 - -Phase 3.4 Pipeline Register Optimization -Phase 3.4 Pipeline Register Optimization | Checksum: d7dfc3b7 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.695 . Memory (MB): peak = 1327.883 ; gain = 0.000 - -Phase 3.5 Small Shape Detail Placement -Phase 3.5 Small Shape Detail Placement | Checksum: 12debda8c - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.741 . Memory (MB): peak = 1327.883 ; gain = 0.000 - -Phase 3.6 Re-assign LUT pins -Phase 3.6 Re-assign LUT pins | Checksum: 14ae64a6f - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.744 . Memory (MB): peak = 1327.883 ; gain = 0.000 - -Phase 3.7 Pipeline Register Optimization -Phase 3.7 Pipeline Register Optimization | Checksum: 14ae64a6f - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.744 . Memory (MB): peak = 1327.883 ; gain = 0.000 -Phase 3 Detail Placement | Checksum: 14ae64a6f - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.745 . Memory (MB): peak = 1327.883 ; gain = 0.000 - -Phase 4 Post Placement Optimization and Clean-Up - -Phase 4.1 Post Commit Optimization -INFO: [Timing 38-35] Done setting XDC timing constraints. - -Phase 4.1.1 Post Placement Optimization -Post Placement Optimization Initialization | Checksum: 1cebea503 - -Phase 4.1.1.1 BUFG Insertion -INFO: [Place 46-46] BUFG insertion identified 0 candidate nets, 0 success, 0 bufg driver replicated, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason -Phase 4.1.1.1 BUFG Insertion | Checksum: 1cebea503 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.774 . Memory (MB): peak = 1327.883 ; gain = 0.000 -INFO: [Place 30-746] Post Placement Timing Summary WNS=36.129. For the most accurate timing information please run report_timing. -Phase 4.1.1 Post Placement Optimization | Checksum: 20987d072 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.775 . Memory (MB): peak = 1327.883 ; gain = 0.000 -Phase 4.1 Post Commit Optimization | Checksum: 20987d072 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.775 . Memory (MB): peak = 1327.883 ; gain = 0.000 - -Phase 4.2 Post Placement Cleanup -Phase 4.2 Post Placement Cleanup | Checksum: 20987d072 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.776 . Memory (MB): peak = 1327.883 ; gain = 0.000 - -Phase 4.3 Placer Reporting -Phase 4.3 Placer Reporting | Checksum: 20987d072 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.777 . Memory (MB): peak = 1327.883 ; gain = 0.000 - -Phase 4.4 Final Placement Cleanup -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1327.883 ; gain = 0.000 -Phase 4.4 Final Placement Cleanup | Checksum: 27c4f344f - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.779 . Memory (MB): peak = 1327.883 ; gain = 0.000 -Phase 4 Post Placement Optimization and Clean-Up | Checksum: 27c4f344f - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.779 . Memory (MB): peak = 1327.883 ; gain = 0.000 -Ending Placer Task | Checksum: 1ab889c44 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.780 . Memory (MB): peak = 1327.883 ; gain = 0.000 -INFO: [Common 17-83] Releasing license: Implementation -57 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -place_design completed successfully -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1327.883 ; gain = 0.000 -INFO: [Timing 38-480] Writing timing data to binary archive. -Writing placer database... -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 1327.883 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1327.883 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_placed.dcp' has been generated. -INFO: [runtcl-4] Executing : report_io -file VGA_top_io_placed.rpt -report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.040 . Memory (MB): peak = 1327.883 ; gain = 0.000 -INFO: [runtcl-4] Executing : report_utilization -file VGA_top_utilization_placed.rpt -pb VGA_top_utilization_placed.pb -INFO: [runtcl-4] Executing : report_control_sets -verbose -file VGA_top_control_sets_placed.rpt -report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1327.883 ; gain = 0.000 -Command: route_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' -Running DRC as a precondition to command route_design -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. - - -Starting Routing Task -INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs -Checksum: PlaceDB: e36d3f86 ConstDB: 0 ShapeSum: c81b5cbe RouteDB: 0 - -Phase 1 Build RT Design -Phase 1 Build RT Design | Checksum: 408a135c - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1399.160 ; gain = 71.277 -Post Restoration Checksum: NetGraph: 2bba0e1e NumContArr: 14d0053e Constraints: 0 Timing: 0 - -Phase 2 Router Initialization - -Phase 2.1 Create Timer -Phase 2.1 Create Timer | Checksum: 408a135c - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1423.402 ; gain = 95.520 - -Phase 2.2 Fix Topology Constraints -Phase 2.2 Fix Topology Constraints | Checksum: 408a135c - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1429.410 ; gain = 101.527 - -Phase 2.3 Pre Route Cleanup -Phase 2.3 Pre Route Cleanup | Checksum: 408a135c - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1429.410 ; gain = 101.527 - Number of Nodes with overlaps = 0 - -Phase 2.4 Update Timing -Phase 2.4 Update Timing | Checksum: 193e9052a - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1432.094 ; gain = 104.211 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=36.042 | TNS=0.000 | WHS=-0.250 | THS=-3.548 | - -Phase 2 Router Initialization | Checksum: 196977bdb - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1432.094 ; gain = 104.211 - -Phase 3 Initial Routing -Phase 3 Initial Routing | Checksum: 14455b7e9 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1432.094 ; gain = 104.211 - -Phase 4 Rip-up And Reroute - -Phase 4.1 Global Iteration 0 - Number of Nodes with overlaps = 4 - Number of Nodes with overlaps = 0 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.940 | TNS=0.000 | WHS=N/A | THS=N/A | - -Phase 4.1 Global Iteration 0 | Checksum: e844e306 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1432.094 ; gain = 104.211 -Phase 4 Rip-up And Reroute | Checksum: e844e306 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1432.094 ; gain = 104.211 - -Phase 5 Delay and Skew Optimization - -Phase 5.1 Delay CleanUp -Phase 5.1 Delay CleanUp | Checksum: e844e306 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1432.094 ; gain = 104.211 - -Phase 5.2 Clock Skew Optimization -Phase 5.2 Clock Skew Optimization | Checksum: e844e306 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1432.094 ; gain = 104.211 -Phase 5 Delay and Skew Optimization | Checksum: e844e306 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1432.094 ; gain = 104.211 - -Phase 6 Post Hold Fix - -Phase 6.1 Hold Fix Iter - -Phase 6.1.1 Update Timing -Phase 6.1.1 Update Timing | Checksum: 9a801cee - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1432.094 ; gain = 104.211 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=36.093 | TNS=0.000 | WHS=0.063 | THS=0.000 | - -Phase 6.1 Hold Fix Iter | Checksum: 9a801cee - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1432.094 ; gain = 104.211 -Phase 6 Post Hold Fix | Checksum: 9a801cee - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1432.094 ; gain = 104.211 - -Phase 7 Route finalize - -Router Utilization Summary - Global Vertical Routing Utilization = 0.0209741 % - Global Horizontal Routing Utilization = 0.00827206 % - Routable Net Status* - *Does not include unroutable nets such as driverless and loadless. - Run report_route_status for detailed report. - Number of Failed Nets = 0 - Number of Unrouted Nets = 0 - Number of Partially Routed Nets = 0 - Number of Node Overlaps = 0 - -Phase 7 Route finalize | Checksum: 12bf57e3c - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1432.094 ; gain = 104.211 - -Phase 8 Verifying routed nets - - Verification completed successfully -Phase 8 Verifying routed nets | Checksum: 12bf57e3c - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1433.680 ; gain = 105.797 - -Phase 9 Depositing Routes -Phase 9 Depositing Routes | Checksum: f9632067 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1433.680 ; gain = 105.797 - -Phase 10 Post Router Timing -INFO: [Route 35-57] Estimated Timing Summary | WNS=36.093 | TNS=0.000 | WHS=0.063 | THS=0.000 | - -INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. -Phase 10 Post Router Timing | Checksum: f9632067 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1433.680 ; gain = 105.797 -INFO: [Route 35-16] Router Completed Successfully - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1433.680 ; gain = 105.797 - -Routing Is Done. -INFO: [Common 17-83] Releasing license: Implementation -74 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -route_design completed successfully -route_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:23 . Memory (MB): peak = 1433.680 ; gain = 105.797 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1433.680 ; gain = 0.000 -INFO: [Timing 38-480] Writing timing data to binary archive. -Writing placer database... -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1433.680 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1433.793 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_routed.dcp' has been generated. -INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx -Command: report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx -INFO: [IP_Flow 19-1839] IP Catalog is up to date. -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_routed.rpt. -report_drc completed successfully -INFO: [runtcl-4] Executing : report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx -Command: report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [DRC 23-133] Running Methodology with 2 threads -INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_methodology_drc_routed.rpt. -report_methodology completed successfully -INFO: [runtcl-4] Executing : report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx -Command: report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx -INFO: [Timing 38-35] Done setting XDC timing constraints. -Running Vector-less Activity Propagation... - -Finished Running Vector-less Activity Propagation -86 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -report_power completed successfully -INFO: [runtcl-4] Executing : report_route_status -file VGA_top_route_status.rpt -pb VGA_top_route_status.pb -INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file VGA_top_timing_summary_routed.rpt -pb VGA_top_timing_summary_routed.pb -rpx VGA_top_timing_summary_routed.rpx -warn_on_violation -INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. -INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs -INFO: [runtcl-4] Executing : report_incremental_reuse -file VGA_top_incremental_reuse_routed.rpt -INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. -INFO: [runtcl-4] Executing : report_clock_utilization -file VGA_top_clock_utilization_routed.rpt -INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file VGA_top_bus_skew_routed.rpt -pb VGA_top_bus_skew_routed.pb -rpx VGA_top_bus_skew_routed.rpx -INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. -INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs -INFO: [Common 17-206] Exiting Vivado at Tue Nov 30 12:02:53 2021... diff --git a/projet-vga.runs/impl_1/VGA_top_12864.backup.vdi b/projet-vga.runs/impl_1/VGA_top_12864.backup.vdi deleted file mode 100644 index 8ddff62..0000000 --- a/projet-vga.runs/impl_1/VGA_top_12864.backup.vdi +++ /dev/null @@ -1,523 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Tue Dec 7 12:19:39 2021 -# Process ID: 12864 -# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1 -# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace -# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi -# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou -#----------------------------------------------------------- -source VGA_top.tcl -notrace -Command: link_design -top VGA_top -part xc7z010clg400-1 -Design is defaulting to srcset: sources_1 -Design is defaulting to constrset: constrs_1 -INFO: [Project 1-454] Reading design checkpoint 'c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.dcp' for cell 'U0' -INFO: [Netlist 29-17] Analyzing 3 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-479] Netlist was created with Vivado 2018.3 -INFO: [Device 21-403] Loading part xc7z010clg400-1 -INFO: [Project 1-570] Preparing netlist for logic optimization -Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst' -Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst' -Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst' -INFO: [Timing 38-35] Done setting XDC timing constraints. [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57] -INFO: [Timing 38-2] Deriving generated clocks [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57] -get_clocks: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1224.508 ; gain = 533.289 -Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst' -Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc] -Finished Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc] -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1224.508 ; gain = 0.000 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -link_design completed successfully -link_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:16 . Memory (MB): peak = 1224.508 ; gain = 861.285 -Command: opt_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' -Running DRC as a precondition to command opt_design - -Starting DRC Task -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Project 1-461] DRC finished with 0 Errors -INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.506 . Memory (MB): peak = 1224.508 ; gain = 0.000 - -Starting Cache Timing Information Task -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [Timing 38-2] Deriving generated clocks -Ending Cache Timing Information Task | Checksum: 1089519a1 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1241.430 ; gain = 16.922 - -Starting Logic Optimization Task - -Phase 1 Retarget -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -INFO: [Opt 31-49] Retargeted 0 cell(s). -Phase 1 Retarget | Checksum: 1089519a1 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1322.203 ; gain = 0.000 -INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells -INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. - -Phase 2 Constant propagation -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Phase 2 Constant propagation | Checksum: 1089519a1 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1322.203 ; gain = 0.000 -INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells - -Phase 3 Sweep -Phase 3 Sweep | Checksum: 50d21832 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1322.203 ; gain = 0.000 -INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells - -Phase 4 BUFG optimization -INFO: [Opt 31-194] Inserted BUFG U0/inst/clk_out1_clk_wiz_1_BUFG_inst to drive 0 load(s) on clock net U0/inst/clk_out1_clk_wiz_1_BUFG -INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets -Phase 4 BUFG optimization | Checksum: 95a74d60 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1322.203 ; gain = 0.000 -INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. - -Phase 5 Shift Register Optimization -Phase 5 Shift Register Optimization | Checksum: 19dd21140 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 1322.203 ; gain = 0.000 -INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells - -Phase 6 Post Processing Netlist -Phase 6 Post Processing Netlist | Checksum: 1575eedad - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 1322.203 ; gain = 0.000 -INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells -Opt_design Change Summary -========================= - - -------------------------------------------------------------------------------------------------------------------------- -| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | -------------------------------------------------------------------------------------------------------------------------- -| Retarget | 0 | 0 | 1 | -| Constant propagation | 0 | 0 | 0 | -| Sweep | 0 | 0 | 0 | -| BUFG optimization | 0 | 0 | 0 | -| Shift Register Optimization | 0 | 0 | 0 | -| Post Processing Netlist | 0 | 0 | 0 | -------------------------------------------------------------------------------------------------------------------------- - - - -Starting Connectivity Check Task - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1322.203 ; gain = 0.000 -Ending Logic Optimization Task | Checksum: 1955eb16f - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 1322.203 ; gain = 0.000 - -Starting Power Optimization Task -INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. -Ending Power Optimization Task | Checksum: 1955eb16f - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1322.203 ; gain = 0.000 - -Starting Final Cleanup Task -Ending Final Cleanup Task | Checksum: 1955eb16f - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1322.203 ; gain = 0.000 - -Starting Netlist Obfuscation Task -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1322.203 ; gain = 0.000 -Ending Netlist Obfuscation Task | Checksum: 1955eb16f - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1322.203 ; gain = 0.000 -INFO: [Common 17-83] Releasing license: Implementation -30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -opt_design completed successfully -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1322.203 ; gain = 0.000 -INFO: [Timing 38-480] Writing timing data to binary archive. -Writing placer database... -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1322.203 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1322.203 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_opt.dcp' has been generated. -INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx -Command: report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx -INFO: [IP_Flow 19-1839] IP Catalog is up to date. -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_opted.rpt. -report_drc completed successfully -Command: place_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. -Running DRC as a precondition to command place_design -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. - -Starting Placer Task -INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs - -Phase 1 Placer Initialization - -Phase 1.1 Placer Initialization Netlist Sorting -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1322.203 ; gain = 0.000 -Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a1a0325f - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1322.203 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1322.203 ; gain = 0.000 - -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device -INFO: [Timing 38-35] Done setting XDC timing constraints. -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: eef95bbb - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.244 . Memory (MB): peak = 1322.203 ; gain = 0.000 - -Phase 1.3 Build Placer Netlist Model -Phase 1.3 Build Placer Netlist Model | Checksum: 1d3a049f7 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.298 . Memory (MB): peak = 1322.203 ; gain = 0.000 - -Phase 1.4 Constrain Clocks/Macros -Phase 1.4 Constrain Clocks/Macros | Checksum: 1d3a049f7 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.299 . Memory (MB): peak = 1322.203 ; gain = 0.000 -Phase 1 Placer Initialization | Checksum: 1d3a049f7 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.299 . Memory (MB): peak = 1322.203 ; gain = 0.000 - -Phase 2 Global Placement - -Phase 2.1 Floorplanning -Phase 2.1 Floorplanning | Checksum: 1722d3694 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.337 . Memory (MB): peak = 1322.203 ; gain = 0.000 - -Phase 2.2 Physical Synthesis In Placer -INFO: [Physopt 32-65] No nets found for high-fanout optimization. -INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. -INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell -INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed. -INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed. -INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed. -INFO: [Physopt 32-949] No candidate nets found for HD net replication -INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1322.203 ; gain = 0.000 - -Summary of Physical Synthesis Optimizations -============================================ - - ----------------------------------------------------------------------------------------------------------------------------------------- -| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------- -| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| HD Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| Total | 0 | 0 | 0 | 0 | 2 | 00:00:00 | ----------------------------------------------------------------------------------------------------------------------------------------- - - -Phase 2.2 Physical Synthesis In Placer | Checksum: 10663e9fd - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.812 . Memory (MB): peak = 1322.203 ; gain = 0.000 -Phase 2 Global Placement | Checksum: 1aa3f7fa5 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.822 . Memory (MB): peak = 1322.203 ; gain = 0.000 - -Phase 3 Detail Placement - -Phase 3.1 Commit Multi Column Macros -Phase 3.1 Commit Multi Column Macros | Checksum: 1aa3f7fa5 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.823 . Memory (MB): peak = 1322.203 ; gain = 0.000 - -Phase 3.2 Commit Most Macros & LUTRAMs -Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1fa94e875 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.890 . Memory (MB): peak = 1322.203 ; gain = 0.000 - -Phase 3.3 Area Swap Optimization -Phase 3.3 Area Swap Optimization | Checksum: 1bc3b5afc - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.892 . Memory (MB): peak = 1322.203 ; gain = 0.000 - -Phase 3.4 Pipeline Register Optimization -Phase 3.4 Pipeline Register Optimization | Checksum: 1bc3b5afc - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.893 . Memory (MB): peak = 1322.203 ; gain = 0.000 - -Phase 3.5 Small Shape Detail Placement -Phase 3.5 Small Shape Detail Placement | Checksum: 133e8332f - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.941 . Memory (MB): peak = 1322.203 ; gain = 0.000 - -Phase 3.6 Re-assign LUT pins -Phase 3.6 Re-assign LUT pins | Checksum: d843b10d - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.945 . Memory (MB): peak = 1322.203 ; gain = 0.000 - -Phase 3.7 Pipeline Register Optimization -Phase 3.7 Pipeline Register Optimization | Checksum: d843b10d - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.945 . Memory (MB): peak = 1322.203 ; gain = 0.000 -Phase 3 Detail Placement | Checksum: d843b10d - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.946 . Memory (MB): peak = 1322.203 ; gain = 0.000 - -Phase 4 Post Placement Optimization and Clean-Up - -Phase 4.1 Post Commit Optimization -INFO: [Timing 38-35] Done setting XDC timing constraints. - -Phase 4.1.1 Post Placement Optimization -Post Placement Optimization Initialization | Checksum: 19cf8a569 - -Phase 4.1.1.1 BUFG Insertion -INFO: [Place 46-46] BUFG insertion identified 0 candidate nets, 0 success, 0 bufg driver replicated, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason -Phase 4.1.1.1 BUFG Insertion | Checksum: 19cf8a569 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.978 . Memory (MB): peak = 1322.203 ; gain = 0.000 -INFO: [Place 30-746] Post Placement Timing Summary WNS=35.155. For the most accurate timing information please run report_timing. -Phase 4.1.1 Post Placement Optimization | Checksum: 1e5cba416 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.979 . Memory (MB): peak = 1322.203 ; gain = 0.000 -Phase 4.1 Post Commit Optimization | Checksum: 1e5cba416 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.979 . Memory (MB): peak = 1322.203 ; gain = 0.000 - -Phase 4.2 Post Placement Cleanup -Phase 4.2 Post Placement Cleanup | Checksum: 1e5cba416 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.980 . Memory (MB): peak = 1322.203 ; gain = 0.000 - -Phase 4.3 Placer Reporting -Phase 4.3 Placer Reporting | Checksum: 1e5cba416 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.981 . Memory (MB): peak = 1322.203 ; gain = 0.000 - -Phase 4.4 Final Placement Cleanup -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1322.203 ; gain = 0.000 -Phase 4.4 Final Placement Cleanup | Checksum: 1f250909b - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.983 . Memory (MB): peak = 1322.203 ; gain = 0.000 -Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1f250909b - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.983 . Memory (MB): peak = 1322.203 ; gain = 0.000 -Ending Placer Task | Checksum: 10d62737c - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.985 . Memory (MB): peak = 1322.203 ; gain = 0.000 -INFO: [Common 17-83] Releasing license: Implementation -57 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -place_design completed successfully -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1322.203 ; gain = 0.000 -INFO: [Timing 38-480] Writing timing data to binary archive. -Writing placer database... -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 1322.203 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1322.203 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_placed.dcp' has been generated. -INFO: [runtcl-4] Executing : report_io -file VGA_top_io_placed.rpt -report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1322.203 ; gain = 0.000 -INFO: [runtcl-4] Executing : report_utilization -file VGA_top_utilization_placed.rpt -pb VGA_top_utilization_placed.pb -INFO: [runtcl-4] Executing : report_control_sets -verbose -file VGA_top_control_sets_placed.rpt -report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1322.203 ; gain = 0.000 -Command: route_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' -Running DRC as a precondition to command route_design -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. - - -Starting Routing Task -INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs -Checksum: PlaceDB: a04ecaff ConstDB: 0 ShapeSum: 6d13a87d RouteDB: 0 - -Phase 1 Build RT Design -Phase 1 Build RT Design | Checksum: dd396fb6 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1402.008 ; gain = 79.566 -Post Restoration Checksum: NetGraph: 7c3cbf24 NumContArr: 60fcb092 Constraints: 0 Timing: 0 - -Phase 2 Router Initialization - -Phase 2.1 Create Timer -Phase 2.1 Create Timer | Checksum: dd396fb6 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1426.234 ; gain = 103.793 - -Phase 2.2 Fix Topology Constraints -Phase 2.2 Fix Topology Constraints | Checksum: dd396fb6 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1432.270 ; gain = 109.828 - -Phase 2.3 Pre Route Cleanup -Phase 2.3 Pre Route Cleanup | Checksum: dd396fb6 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1432.270 ; gain = 109.828 - Number of Nodes with overlaps = 0 - -Phase 2.4 Update Timing -Phase 2.4 Update Timing | Checksum: 112cc3ffa - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1435.043 ; gain = 112.602 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.100 | TNS=0.000 | WHS=-0.267 | THS=-3.705 | - -Phase 2 Router Initialization | Checksum: 170dc172d - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1435.043 ; gain = 112.602 - -Phase 3 Initial Routing -Phase 3 Initial Routing | Checksum: 22395080e - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1435.043 ; gain = 112.602 - -Phase 4 Rip-up And Reroute - -Phase 4.1 Global Iteration 0 - Number of Nodes with overlaps = 2 - Number of Nodes with overlaps = 0 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=34.628 | TNS=0.000 | WHS=N/A | THS=N/A | - -Phase 4.1 Global Iteration 0 | Checksum: 84c8e4d7 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1435.043 ; gain = 112.602 -Phase 4 Rip-up And Reroute | Checksum: 84c8e4d7 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1435.043 ; gain = 112.602 - -Phase 5 Delay and Skew Optimization - -Phase 5.1 Delay CleanUp -Phase 5.1 Delay CleanUp | Checksum: 84c8e4d7 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1435.043 ; gain = 112.602 - -Phase 5.2 Clock Skew Optimization -Phase 5.2 Clock Skew Optimization | Checksum: 84c8e4d7 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1435.043 ; gain = 112.602 -Phase 5 Delay and Skew Optimization | Checksum: 84c8e4d7 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1435.043 ; gain = 112.602 - -Phase 6 Post Hold Fix - -Phase 6.1 Hold Fix Iter - -Phase 6.1.1 Update Timing -Phase 6.1.1 Update Timing | Checksum: 7ed72ff4 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1435.043 ; gain = 112.602 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=34.781 | TNS=0.000 | WHS=0.050 | THS=0.000 | - -Phase 6.1 Hold Fix Iter | Checksum: 7ed72ff4 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1435.043 ; gain = 112.602 -Phase 6 Post Hold Fix | Checksum: 7ed72ff4 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1435.043 ; gain = 112.602 - -Phase 7 Route finalize - -Router Utilization Summary - Global Vertical Routing Utilization = 0.0236486 % - Global Horizontal Routing Utilization = 0.0124081 % - Routable Net Status* - *Does not include unroutable nets such as driverless and loadless. - Run report_route_status for detailed report. - Number of Failed Nets = 0 - Number of Unrouted Nets = 0 - Number of Partially Routed Nets = 0 - Number of Node Overlaps = 0 - -Phase 7 Route finalize | Checksum: a2cd4f9e - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1435.043 ; gain = 112.602 - -Phase 8 Verifying routed nets - - Verification completed successfully -Phase 8 Verifying routed nets | Checksum: a2cd4f9e - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1436.496 ; gain = 114.055 - -Phase 9 Depositing Routes -Phase 9 Depositing Routes | Checksum: 7931b51c - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1436.496 ; gain = 114.055 - -Phase 10 Post Router Timing -INFO: [Route 35-57] Estimated Timing Summary | WNS=34.781 | TNS=0.000 | WHS=0.050 | THS=0.000 | - -INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. -Phase 10 Post Router Timing | Checksum: 7931b51c - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1436.496 ; gain = 114.055 -INFO: [Route 35-16] Router Completed Successfully - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1436.496 ; gain = 114.055 - -Routing Is Done. -INFO: [Common 17-83] Releasing license: Implementation -74 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -route_design completed successfully -route_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:23 . Memory (MB): peak = 1436.496 ; gain = 114.293 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1436.496 ; gain = 0.000 -INFO: [Timing 38-480] Writing timing data to binary archive. -Writing placer database... -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1436.496 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1436.496 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_routed.dcp' has been generated. -INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx -Command: report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx -INFO: [IP_Flow 19-1839] IP Catalog is up to date. -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_routed.rpt. -report_drc completed successfully -INFO: [runtcl-4] Executing : report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx -Command: report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [DRC 23-133] Running Methodology with 2 threads -INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_methodology_drc_routed.rpt. -report_methodology completed successfully -INFO: [runtcl-4] Executing : report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx -Command: report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx -INFO: [Timing 38-35] Done setting XDC timing constraints. -Running Vector-less Activity Propagation... - -Finished Running Vector-less Activity Propagation -86 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -report_power completed successfully -INFO: [runtcl-4] Executing : report_route_status -file VGA_top_route_status.rpt -pb VGA_top_route_status.pb -INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file VGA_top_timing_summary_routed.rpt -pb VGA_top_timing_summary_routed.pb -rpx VGA_top_timing_summary_routed.rpx -warn_on_violation -INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. -INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs -INFO: [runtcl-4] Executing : report_incremental_reuse -file VGA_top_incremental_reuse_routed.rpt -INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. -INFO: [runtcl-4] Executing : report_clock_utilization -file VGA_top_clock_utilization_routed.rpt -INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file VGA_top_bus_skew_routed.rpt -pb VGA_top_bus_skew_routed.pb -rpx VGA_top_bus_skew_routed.rpx -INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. -INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs -INFO: [Common 17-206] Exiting Vivado at Tue Dec 7 12:20:28 2021... diff --git a/projet-vga.runs/impl_1/VGA_top_12968.backup.vdi b/projet-vga.runs/impl_1/VGA_top_12968.backup.vdi deleted file mode 100644 index e4950c9..0000000 --- a/projet-vga.runs/impl_1/VGA_top_12968.backup.vdi +++ /dev/null @@ -1,523 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Tue Nov 30 12:20:41 2021 -# Process ID: 12968 -# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1 -# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace -# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi -# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou -#----------------------------------------------------------- -source VGA_top.tcl -notrace -Command: link_design -top VGA_top -part xc7z010clg400-1 -Design is defaulting to srcset: sources_1 -Design is defaulting to constrset: constrs_1 -INFO: [Project 1-454] Reading design checkpoint 'c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.dcp' for cell 'U0' -INFO: [Netlist 29-17] Analyzing 3 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-479] Netlist was created with Vivado 2018.3 -INFO: [Device 21-403] Loading part xc7z010clg400-1 -INFO: [Project 1-570] Preparing netlist for logic optimization -Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst' -Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst' -Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst' -INFO: [Timing 38-35] Done setting XDC timing constraints. [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57] -INFO: [Timing 38-2] Deriving generated clocks [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57] -get_clocks: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1226.977 ; gain = 533.066 -Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst' -Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc] -Finished Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc] -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1226.977 ; gain = 0.000 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -link_design completed successfully -link_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:16 . Memory (MB): peak = 1226.977 ; gain = 862.352 -Command: opt_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' -Running DRC as a precondition to command opt_design - -Starting DRC Task -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Project 1-461] DRC finished with 0 Errors -INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.501 . Memory (MB): peak = 1226.977 ; gain = 0.000 - -Starting Cache Timing Information Task -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [Timing 38-2] Deriving generated clocks -Ending Cache Timing Information Task | Checksum: dc2ced6f - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1243.789 ; gain = 16.812 - -Starting Logic Optimization Task - -Phase 1 Retarget -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -INFO: [Opt 31-49] Retargeted 0 cell(s). -Phase 1 Retarget | Checksum: dc2ced6f - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1325.523 ; gain = 0.000 -INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells -INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. - -Phase 2 Constant propagation -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Phase 2 Constant propagation | Checksum: dc2ced6f - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1325.523 ; gain = 0.000 -INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells - -Phase 3 Sweep -Phase 3 Sweep | Checksum: 19e1c8f17 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1325.523 ; gain = 0.000 -INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells - -Phase 4 BUFG optimization -INFO: [Opt 31-194] Inserted BUFG U0/inst/clk_out1_clk_wiz_1_BUFG_inst to drive 0 load(s) on clock net U0/inst/clk_out1_clk_wiz_1_BUFG -INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets -Phase 4 BUFG optimization | Checksum: c943f809 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1325.523 ; gain = 0.000 -INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. - -Phase 5 Shift Register Optimization -Phase 5 Shift Register Optimization | Checksum: ba2b01e3 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1325.523 ; gain = 0.000 -INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells - -Phase 6 Post Processing Netlist -Phase 6 Post Processing Netlist | Checksum: b57bee7a - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 1325.523 ; gain = 0.000 -INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells -Opt_design Change Summary -========================= - - -------------------------------------------------------------------------------------------------------------------------- -| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | -------------------------------------------------------------------------------------------------------------------------- -| Retarget | 0 | 0 | 1 | -| Constant propagation | 0 | 0 | 0 | -| Sweep | 0 | 0 | 0 | -| BUFG optimization | 0 | 0 | 0 | -| Shift Register Optimization | 0 | 0 | 0 | -| Post Processing Netlist | 0 | 0 | 0 | -------------------------------------------------------------------------------------------------------------------------- - - - -Starting Connectivity Check Task - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1325.523 ; gain = 0.000 -Ending Logic Optimization Task | Checksum: 13b7a3fb2 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.026 . Memory (MB): peak = 1325.523 ; gain = 0.000 - -Starting Power Optimization Task -INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. -Ending Power Optimization Task | Checksum: 13b7a3fb2 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1325.523 ; gain = 0.000 - -Starting Final Cleanup Task -Ending Final Cleanup Task | Checksum: 13b7a3fb2 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1325.523 ; gain = 0.000 - -Starting Netlist Obfuscation Task -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1325.523 ; gain = 0.000 -Ending Netlist Obfuscation Task | Checksum: 13b7a3fb2 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1325.523 ; gain = 0.000 -INFO: [Common 17-83] Releasing license: Implementation -30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -opt_design completed successfully -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1325.523 ; gain = 0.000 -INFO: [Timing 38-480] Writing timing data to binary archive. -Writing placer database... -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.033 . Memory (MB): peak = 1325.523 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1325.523 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_opt.dcp' has been generated. -INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx -Command: report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx -INFO: [IP_Flow 19-1839] IP Catalog is up to date. -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_opted.rpt. -report_drc completed successfully -Command: place_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. -Running DRC as a precondition to command place_design -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. - -Starting Placer Task -INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs - -Phase 1 Placer Initialization - -Phase 1.1 Placer Initialization Netlist Sorting -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1325.523 ; gain = 0.000 -Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 67b44082 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1325.523 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1325.523 ; gain = 0.000 - -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device -INFO: [Timing 38-35] Done setting XDC timing constraints. -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 14d1cdeaf - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.242 . Memory (MB): peak = 1325.523 ; gain = 0.000 - -Phase 1.3 Build Placer Netlist Model -Phase 1.3 Build Placer Netlist Model | Checksum: 1bfc53c93 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.304 . Memory (MB): peak = 1325.523 ; gain = 0.000 - -Phase 1.4 Constrain Clocks/Macros -Phase 1.4 Constrain Clocks/Macros | Checksum: 1bfc53c93 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.306 . Memory (MB): peak = 1325.523 ; gain = 0.000 -Phase 1 Placer Initialization | Checksum: 1bfc53c93 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.306 . Memory (MB): peak = 1325.523 ; gain = 0.000 - -Phase 2 Global Placement - -Phase 2.1 Floorplanning -Phase 2.1 Floorplanning | Checksum: 152ddf35d - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.344 . Memory (MB): peak = 1325.523 ; gain = 0.000 - -Phase 2.2 Physical Synthesis In Placer -INFO: [Physopt 32-65] No nets found for high-fanout optimization. -INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. -INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell -INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed. -INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed. -INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed. -INFO: [Physopt 32-949] No candidate nets found for HD net replication -INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1325.523 ; gain = 0.000 - -Summary of Physical Synthesis Optimizations -============================================ - - ----------------------------------------------------------------------------------------------------------------------------------------- -| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------- -| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| HD Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| Total | 0 | 0 | 0 | 0 | 2 | 00:00:00 | ----------------------------------------------------------------------------------------------------------------------------------------- - - -Phase 2.2 Physical Synthesis In Placer | Checksum: 166883134 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.872 . Memory (MB): peak = 1325.523 ; gain = 0.000 -Phase 2 Global Placement | Checksum: 1ea5262ce - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.881 . Memory (MB): peak = 1325.523 ; gain = 0.000 - -Phase 3 Detail Placement - -Phase 3.1 Commit Multi Column Macros -Phase 3.1 Commit Multi Column Macros | Checksum: 1ea5262ce - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.882 . Memory (MB): peak = 1325.523 ; gain = 0.000 - -Phase 3.2 Commit Most Macros & LUTRAMs -Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1350cd04a - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.922 . Memory (MB): peak = 1325.523 ; gain = 0.000 - -Phase 3.3 Area Swap Optimization -Phase 3.3 Area Swap Optimization | Checksum: 1c8d9a95a - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.924 . Memory (MB): peak = 1325.523 ; gain = 0.000 - -Phase 3.4 Pipeline Register Optimization -Phase 3.4 Pipeline Register Optimization | Checksum: 1c8d9a95a - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.925 . Memory (MB): peak = 1325.523 ; gain = 0.000 - -Phase 3.5 Small Shape Detail Placement -Phase 3.5 Small Shape Detail Placement | Checksum: 236b118c7 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.980 . Memory (MB): peak = 1325.523 ; gain = 0.000 - -Phase 3.6 Re-assign LUT pins -Phase 3.6 Re-assign LUT pins | Checksum: 182b978ad - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.983 . Memory (MB): peak = 1325.523 ; gain = 0.000 - -Phase 3.7 Pipeline Register Optimization -Phase 3.7 Pipeline Register Optimization | Checksum: 182b978ad - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.983 . Memory (MB): peak = 1325.523 ; gain = 0.000 -Phase 3 Detail Placement | Checksum: 182b978ad - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.984 . Memory (MB): peak = 1325.523 ; gain = 0.000 - -Phase 4 Post Placement Optimization and Clean-Up - -Phase 4.1 Post Commit Optimization -INFO: [Timing 38-35] Done setting XDC timing constraints. - -Phase 4.1.1 Post Placement Optimization -Post Placement Optimization Initialization | Checksum: c19cad15 - -Phase 4.1.1.1 BUFG Insertion -INFO: [Place 46-46] BUFG insertion identified 0 candidate nets, 0 success, 0 bufg driver replicated, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason -Phase 4.1.1.1 BUFG Insertion | Checksum: c19cad15 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1325.523 ; gain = 0.000 -INFO: [Place 30-746] Post Placement Timing Summary WNS=36.030. For the most accurate timing information please run report_timing. -Phase 4.1.1 Post Placement Optimization | Checksum: a4d8353e - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1325.523 ; gain = 0.000 -Phase 4.1 Post Commit Optimization | Checksum: a4d8353e - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1325.523 ; gain = 0.000 - -Phase 4.2 Post Placement Cleanup -Phase 4.2 Post Placement Cleanup | Checksum: a4d8353e - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1325.523 ; gain = 0.000 - -Phase 4.3 Placer Reporting -Phase 4.3 Placer Reporting | Checksum: a4d8353e - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1325.523 ; gain = 0.000 - -Phase 4.4 Final Placement Cleanup -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1325.523 ; gain = 0.000 -Phase 4.4 Final Placement Cleanup | Checksum: 80d205c8 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1325.523 ; gain = 0.000 -Phase 4 Post Placement Optimization and Clean-Up | Checksum: 80d205c8 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1325.523 ; gain = 0.000 -Ending Placer Task | Checksum: 362c66e8 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1325.523 ; gain = 0.000 -INFO: [Common 17-83] Releasing license: Implementation -57 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -place_design completed successfully -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1325.523 ; gain = 0.000 -INFO: [Timing 38-480] Writing timing data to binary archive. -Writing placer database... -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 1325.523 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1325.523 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_placed.dcp' has been generated. -INFO: [runtcl-4] Executing : report_io -file VGA_top_io_placed.rpt -report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1325.781 ; gain = 0.000 -INFO: [runtcl-4] Executing : report_utilization -file VGA_top_utilization_placed.rpt -pb VGA_top_utilization_placed.pb -INFO: [runtcl-4] Executing : report_control_sets -verbose -file VGA_top_control_sets_placed.rpt -report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1325.781 ; gain = 0.000 -Command: route_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' -Running DRC as a precondition to command route_design -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. - - -Starting Routing Task -INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs -Checksum: PlaceDB: 1579e8f6 ConstDB: 0 ShapeSum: 20b27df2 RouteDB: 0 - -Phase 1 Build RT Design -Phase 1 Build RT Design | Checksum: b6d8bcc7 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1400.633 ; gain = 74.445 -Post Restoration Checksum: NetGraph: acd0c6a6 NumContArr: a07f621 Constraints: 0 Timing: 0 - -Phase 2 Router Initialization - -Phase 2.1 Create Timer -Phase 2.1 Create Timer | Checksum: b6d8bcc7 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1424.875 ; gain = 98.688 - -Phase 2.2 Fix Topology Constraints -Phase 2.2 Fix Topology Constraints | Checksum: b6d8bcc7 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1430.887 ; gain = 104.699 - -Phase 2.3 Pre Route Cleanup -Phase 2.3 Pre Route Cleanup | Checksum: b6d8bcc7 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1430.887 ; gain = 104.699 - Number of Nodes with overlaps = 0 - -Phase 2.4 Update Timing -Phase 2.4 Update Timing | Checksum: 1c88f2ffd - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1433.641 ; gain = 107.453 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.958 | TNS=0.000 | WHS=-0.276 | THS=-3.718 | - -Phase 2 Router Initialization | Checksum: 10a6ee9df - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1433.641 ; gain = 107.453 - -Phase 3 Initial Routing -Phase 3 Initial Routing | Checksum: 17776be02 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1433.641 ; gain = 107.453 - -Phase 4 Rip-up And Reroute - -Phase 4.1 Global Iteration 0 - Number of Nodes with overlaps = 4 - Number of Nodes with overlaps = 0 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=36.113 | TNS=0.000 | WHS=N/A | THS=N/A | - -Phase 4.1 Global Iteration 0 | Checksum: 19eac515a - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.641 ; gain = 107.453 -Phase 4 Rip-up And Reroute | Checksum: 19eac515a - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.641 ; gain = 107.453 - -Phase 5 Delay and Skew Optimization - -Phase 5.1 Delay CleanUp -Phase 5.1 Delay CleanUp | Checksum: 19eac515a - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.641 ; gain = 107.453 - -Phase 5.2 Clock Skew Optimization -Phase 5.2 Clock Skew Optimization | Checksum: 19eac515a - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.641 ; gain = 107.453 -Phase 5 Delay and Skew Optimization | Checksum: 19eac515a - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.641 ; gain = 107.453 - -Phase 6 Post Hold Fix - -Phase 6.1 Hold Fix Iter - -Phase 6.1.1 Update Timing -Phase 6.1.1 Update Timing | Checksum: 219991e28 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.641 ; gain = 107.453 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=36.266 | TNS=0.000 | WHS=0.076 | THS=0.000 | - -Phase 6.1 Hold Fix Iter | Checksum: 219991e28 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.641 ; gain = 107.453 -Phase 6 Post Hold Fix | Checksum: 219991e28 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.641 ; gain = 107.453 - -Phase 7 Route finalize - -Router Utilization Summary - Global Vertical Routing Utilization = 0.00900901 % - Global Horizontal Routing Utilization = 0.00344669 % - Routable Net Status* - *Does not include unroutable nets such as driverless and loadless. - Run report_route_status for detailed report. - Number of Failed Nets = 0 - Number of Unrouted Nets = 0 - Number of Partially Routed Nets = 0 - Number of Node Overlaps = 0 - -Phase 7 Route finalize | Checksum: 1f6edf796 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.641 ; gain = 107.453 - -Phase 8 Verifying routed nets - - Verification completed successfully -Phase 8 Verifying routed nets | Checksum: 1f6edf796 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1435.129 ; gain = 108.941 - -Phase 9 Depositing Routes -Phase 9 Depositing Routes | Checksum: 1ba53fff2 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1435.129 ; gain = 108.941 - -Phase 10 Post Router Timing -INFO: [Route 35-57] Estimated Timing Summary | WNS=36.266 | TNS=0.000 | WHS=0.076 | THS=0.000 | - -INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. -Phase 10 Post Router Timing | Checksum: 1ba53fff2 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1435.129 ; gain = 108.941 -INFO: [Route 35-16] Router Completed Successfully - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1435.129 ; gain = 108.941 - -Routing Is Done. -INFO: [Common 17-83] Releasing license: Implementation -74 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -route_design completed successfully -route_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:22 . Memory (MB): peak = 1435.129 ; gain = 109.348 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1435.129 ; gain = 0.000 -INFO: [Timing 38-480] Writing timing data to binary archive. -Writing placer database... -Writing XDEF routing. -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1435.129 ; gain = 0.000 -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.059 . Memory (MB): peak = 1435.129 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_routed.dcp' has been generated. -INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx -Command: report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx -INFO: [IP_Flow 19-1839] IP Catalog is up to date. -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_routed.rpt. -report_drc completed successfully -INFO: [runtcl-4] Executing : report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx -Command: report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [DRC 23-133] Running Methodology with 2 threads -INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_methodology_drc_routed.rpt. -report_methodology completed successfully -INFO: [runtcl-4] Executing : report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx -Command: report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx -INFO: [Timing 38-35] Done setting XDC timing constraints. -Running Vector-less Activity Propagation... - -Finished Running Vector-less Activity Propagation -86 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -report_power completed successfully -INFO: [runtcl-4] Executing : report_route_status -file VGA_top_route_status.rpt -pb VGA_top_route_status.pb -INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file VGA_top_timing_summary_routed.rpt -pb VGA_top_timing_summary_routed.pb -rpx VGA_top_timing_summary_routed.rpx -warn_on_violation -INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. -INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs -INFO: [runtcl-4] Executing : report_incremental_reuse -file VGA_top_incremental_reuse_routed.rpt -INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. -INFO: [runtcl-4] Executing : report_clock_utilization -file VGA_top_clock_utilization_routed.rpt -INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file VGA_top_bus_skew_routed.rpt -pb VGA_top_bus_skew_routed.pb -rpx VGA_top_bus_skew_routed.rpx -INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. -INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs -INFO: [Common 17-206] Exiting Vivado at Tue Nov 30 12:21:30 2021... diff --git a/projet-vga.runs/impl_1/VGA_top_13936.backup.vdi b/projet-vga.runs/impl_1/VGA_top_13936.backup.vdi deleted file mode 100644 index 8d4c3d8..0000000 --- a/projet-vga.runs/impl_1/VGA_top_13936.backup.vdi +++ /dev/null @@ -1,530 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Tue Nov 30 12:26:23 2021 -# Process ID: 13936 -# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1 -# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace -# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi -# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou -#----------------------------------------------------------- -source VGA_top.tcl -notrace -Command: link_design -top VGA_top -part xc7z010clg400-1 -Design is defaulting to srcset: sources_1 -Design is defaulting to constrset: constrs_1 -INFO: [Project 1-454] Reading design checkpoint 'c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.dcp' for cell 'U0' -INFO: [Netlist 29-17] Analyzing 3 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-479] Netlist was created with Vivado 2018.3 -INFO: [Device 21-403] Loading part xc7z010clg400-1 -INFO: [Project 1-570] Preparing netlist for logic optimization -Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst' -Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst' -Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst' -INFO: [Timing 38-35] Done setting XDC timing constraints. [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57] -INFO: [Timing 38-2] Deriving generated clocks [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57] -get_clocks: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1223.945 ; gain = 534.242 -Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst' -Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc] -Finished Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc] -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1223.945 ; gain = 0.000 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -link_design completed successfully -link_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:16 . Memory (MB): peak = 1223.945 ; gain = 861.488 -Command: opt_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' -Running DRC as a precondition to command opt_design - -Starting DRC Task -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Project 1-461] DRC finished with 0 Errors -INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.505 . Memory (MB): peak = 1223.945 ; gain = 0.000 - -Starting Cache Timing Information Task -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [Timing 38-2] Deriving generated clocks -Ending Cache Timing Information Task | Checksum: 123818214 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1240.480 ; gain = 16.535 - -Starting Logic Optimization Task - -Phase 1 Retarget -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -INFO: [Opt 31-49] Retargeted 0 cell(s). -Phase 1 Retarget | Checksum: 123818214 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1321.344 ; gain = 0.000 -INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells -INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. - -Phase 2 Constant propagation -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Phase 2 Constant propagation | Checksum: 123818214 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1321.344 ; gain = 0.000 -INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells - -Phase 3 Sweep -Phase 3 Sweep | Checksum: 126eab858 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1321.344 ; gain = 0.000 -INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells - -Phase 4 BUFG optimization -INFO: [Opt 31-194] Inserted BUFG U0/inst/clk_out1_clk_wiz_1_BUFG_inst to drive 0 load(s) on clock net U0/inst/clk_out1_clk_wiz_1_BUFG -INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets -Phase 4 BUFG optimization | Checksum: 12a935bc2 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1321.344 ; gain = 0.000 -INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. - -Phase 5 Shift Register Optimization -Phase 5 Shift Register Optimization | Checksum: 187d22a05 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.025 . Memory (MB): peak = 1321.344 ; gain = 0.000 -INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells - -Phase 6 Post Processing Netlist -Phase 6 Post Processing Netlist | Checksum: 1eadce572 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.026 . Memory (MB): peak = 1321.344 ; gain = 0.000 -INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells -Opt_design Change Summary -========================= - - -------------------------------------------------------------------------------------------------------------------------- -| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | -------------------------------------------------------------------------------------------------------------------------- -| Retarget | 0 | 0 | 1 | -| Constant propagation | 0 | 0 | 0 | -| Sweep | 0 | 0 | 0 | -| BUFG optimization | 0 | 0 | 0 | -| Shift Register Optimization | 0 | 0 | 0 | -| Post Processing Netlist | 0 | 0 | 0 | -------------------------------------------------------------------------------------------------------------------------- - - - -Starting Connectivity Check Task - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1321.344 ; gain = 0.000 -Ending Logic Optimization Task | Checksum: 1626ce552 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.027 . Memory (MB): peak = 1321.344 ; gain = 0.000 - -Starting Power Optimization Task -INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. -Ending Power Optimization Task | Checksum: 1626ce552 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1321.344 ; gain = 0.000 - -Starting Final Cleanup Task -Ending Final Cleanup Task | Checksum: 1626ce552 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1321.344 ; gain = 0.000 - -Starting Netlist Obfuscation Task -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1321.344 ; gain = 0.000 -Ending Netlist Obfuscation Task | Checksum: 1626ce552 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1321.344 ; gain = 0.000 -INFO: [Common 17-83] Releasing license: Implementation -30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -opt_design completed successfully -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1321.344 ; gain = 0.000 -INFO: [Timing 38-480] Writing timing data to binary archive. -Writing placer database... -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1321.344 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1321.344 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_opt.dcp' has been generated. -INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx -Command: report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx -INFO: [IP_Flow 19-1839] IP Catalog is up to date. -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_opted.rpt. -report_drc completed successfully -Command: place_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. -Running DRC as a precondition to command place_design -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. - -Starting Placer Task -INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs - -Phase 1 Placer Initialization - -Phase 1.1 Placer Initialization Netlist Sorting -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1321.344 ; gain = 0.000 -Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 11a18955b - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1321.344 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1321.344 ; gain = 0.000 - -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device -INFO: [Timing 38-35] Done setting XDC timing constraints. -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: b93ed54f - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.242 . Memory (MB): peak = 1321.344 ; gain = 0.000 - -Phase 1.3 Build Placer Netlist Model -Phase 1.3 Build Placer Netlist Model | Checksum: 188d76266 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.297 . Memory (MB): peak = 1321.344 ; gain = 0.000 - -Phase 1.4 Constrain Clocks/Macros -Phase 1.4 Constrain Clocks/Macros | Checksum: 188d76266 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.298 . Memory (MB): peak = 1321.344 ; gain = 0.000 -Phase 1 Placer Initialization | Checksum: 188d76266 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.299 . Memory (MB): peak = 1321.344 ; gain = 0.000 - -Phase 2 Global Placement - -Phase 2.1 Floorplanning -Phase 2.1 Floorplanning | Checksum: 18a35186d - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.334 . Memory (MB): peak = 1321.344 ; gain = 0.000 - -Phase 2.2 Physical Synthesis In Placer -INFO: [Physopt 32-65] No nets found for high-fanout optimization. -INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. -INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell -INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed. -INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed. -INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed. -INFO: [Physopt 32-949] No candidate nets found for HD net replication -INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1321.344 ; gain = 0.000 - -Summary of Physical Synthesis Optimizations -============================================ - - ----------------------------------------------------------------------------------------------------------------------------------------- -| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------- -| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| HD Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| Total | 0 | 0 | 0 | 0 | 2 | 00:00:00 | ----------------------------------------------------------------------------------------------------------------------------------------- - - -Phase 2.2 Physical Synthesis In Placer | Checksum: 137f00f39 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.789 . Memory (MB): peak = 1321.344 ; gain = 0.000 -Phase 2 Global Placement | Checksum: 1432572bb - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.799 . Memory (MB): peak = 1321.344 ; gain = 0.000 - -Phase 3 Detail Placement - -Phase 3.1 Commit Multi Column Macros -Phase 3.1 Commit Multi Column Macros | Checksum: 1432572bb - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.800 . Memory (MB): peak = 1321.344 ; gain = 0.000 - -Phase 3.2 Commit Most Macros & LUTRAMs -Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 111ffa250 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.850 . Memory (MB): peak = 1321.344 ; gain = 0.000 - -Phase 3.3 Area Swap Optimization -Phase 3.3 Area Swap Optimization | Checksum: 14c2f5404 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.853 . Memory (MB): peak = 1321.344 ; gain = 0.000 - -Phase 3.4 Pipeline Register Optimization -Phase 3.4 Pipeline Register Optimization | Checksum: 14c2f5404 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.853 . Memory (MB): peak = 1321.344 ; gain = 0.000 - -Phase 3.5 Small Shape Detail Placement -Phase 3.5 Small Shape Detail Placement | Checksum: 8649c46f - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.901 . Memory (MB): peak = 1321.344 ; gain = 0.000 - -Phase 3.6 Re-assign LUT pins -Phase 3.6 Re-assign LUT pins | Checksum: 1481f6ae7 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.904 . Memory (MB): peak = 1321.344 ; gain = 0.000 - -Phase 3.7 Pipeline Register Optimization -Phase 3.7 Pipeline Register Optimization | Checksum: 1481f6ae7 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.905 . Memory (MB): peak = 1321.344 ; gain = 0.000 -Phase 3 Detail Placement | Checksum: 1481f6ae7 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.905 . Memory (MB): peak = 1321.344 ; gain = 0.000 - -Phase 4 Post Placement Optimization and Clean-Up - -Phase 4.1 Post Commit Optimization -INFO: [Timing 38-35] Done setting XDC timing constraints. - -Phase 4.1.1 Post Placement Optimization -Post Placement Optimization Initialization | Checksum: 1e8de705c - -Phase 4.1.1.1 BUFG Insertion -INFO: [Place 46-46] BUFG insertion identified 0 candidate nets, 0 success, 0 bufg driver replicated, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason -Phase 4.1.1.1 BUFG Insertion | Checksum: 1e8de705c - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.938 . Memory (MB): peak = 1321.344 ; gain = 0.000 -INFO: [Place 30-746] Post Placement Timing Summary WNS=35.347. For the most accurate timing information please run report_timing. -Phase 4.1.1 Post Placement Optimization | Checksum: 20dc81c88 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.938 . Memory (MB): peak = 1321.344 ; gain = 0.000 -Phase 4.1 Post Commit Optimization | Checksum: 20dc81c88 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.939 . Memory (MB): peak = 1321.344 ; gain = 0.000 - -Phase 4.2 Post Placement Cleanup -Phase 4.2 Post Placement Cleanup | Checksum: 20dc81c88 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.940 . Memory (MB): peak = 1321.344 ; gain = 0.000 - -Phase 4.3 Placer Reporting -Phase 4.3 Placer Reporting | Checksum: 20dc81c88 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.941 . Memory (MB): peak = 1321.344 ; gain = 0.000 - -Phase 4.4 Final Placement Cleanup -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1321.344 ; gain = 0.000 -Phase 4.4 Final Placement Cleanup | Checksum: 1e1df3375 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.943 . Memory (MB): peak = 1321.344 ; gain = 0.000 -Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1e1df3375 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.943 . Memory (MB): peak = 1321.344 ; gain = 0.000 -Ending Placer Task | Checksum: 13b3db9c6 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.945 . Memory (MB): peak = 1321.344 ; gain = 0.000 -INFO: [Common 17-83] Releasing license: Implementation -57 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -place_design completed successfully -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1321.344 ; gain = 0.000 -INFO: [Timing 38-480] Writing timing data to binary archive. -Writing placer database... -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 1321.344 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1321.344 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_placed.dcp' has been generated. -INFO: [runtcl-4] Executing : report_io -file VGA_top_io_placed.rpt -report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1323.125 ; gain = 0.000 -INFO: [runtcl-4] Executing : report_utilization -file VGA_top_utilization_placed.rpt -pb VGA_top_utilization_placed.pb -INFO: [runtcl-4] Executing : report_control_sets -verbose -file VGA_top_control_sets_placed.rpt -report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1323.125 ; gain = 0.000 -Command: route_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' -Running DRC as a precondition to command route_design -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. - - -Starting Routing Task -INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs -Checksum: PlaceDB: c37a5850 ConstDB: 0 ShapeSum: 77c36176 RouteDB: 0 - -Phase 1 Build RT Design -Phase 1 Build RT Design | Checksum: bd1c2272 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1396.336 ; gain = 73.211 -Post Restoration Checksum: NetGraph: bbeff794 NumContArr: 12c2ade Constraints: 0 Timing: 0 - -Phase 2 Router Initialization - -Phase 2.1 Create Timer -Phase 2.1 Create Timer | Checksum: bd1c2272 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1420.555 ; gain = 97.430 - -Phase 2.2 Fix Topology Constraints -Phase 2.2 Fix Topology Constraints | Checksum: bd1c2272 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1426.578 ; gain = 103.453 - -Phase 2.3 Pre Route Cleanup -Phase 2.3 Pre Route Cleanup | Checksum: bd1c2272 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1426.578 ; gain = 103.453 - Number of Nodes with overlaps = 0 - -Phase 2.4 Update Timing -Phase 2.4 Update Timing | Checksum: 19cf4eeba - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1429.270 ; gain = 106.145 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.290 | TNS=0.000 | WHS=-0.256 | THS=-3.320 | - -Phase 2 Router Initialization | Checksum: 1eb51a031 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1429.270 ; gain = 106.145 - -Phase 3 Initial Routing -Phase 3 Initial Routing | Checksum: 12fb8703e - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1429.473 ; gain = 106.348 - -Phase 4 Rip-up And Reroute - -Phase 4.1 Global Iteration 0 - Number of Nodes with overlaps = 4 - Number of Nodes with overlaps = 0 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.101 | TNS=0.000 | WHS=N/A | THS=N/A | - -Phase 4.1 Global Iteration 0 | Checksum: eab409dc - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1429.477 ; gain = 106.352 -Phase 4 Rip-up And Reroute | Checksum: eab409dc - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1429.477 ; gain = 106.352 - -Phase 5 Delay and Skew Optimization - -Phase 5.1 Delay CleanUp - -Phase 5.1.1 Update Timing -Phase 5.1.1 Update Timing | Checksum: eab409dc - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1429.477 ; gain = 106.352 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.254 | TNS=0.000 | WHS=N/A | THS=N/A | - -Phase 5.1 Delay CleanUp | Checksum: eab409dc - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1429.477 ; gain = 106.352 - -Phase 5.2 Clock Skew Optimization -Phase 5.2 Clock Skew Optimization | Checksum: eab409dc - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1429.477 ; gain = 106.352 -Phase 5 Delay and Skew Optimization | Checksum: eab409dc - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1429.477 ; gain = 106.352 - -Phase 6 Post Hold Fix - -Phase 6.1 Hold Fix Iter - -Phase 6.1.1 Update Timing -Phase 6.1.1 Update Timing | Checksum: 133414f2c - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1429.477 ; gain = 106.352 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.254 | TNS=0.000 | WHS=0.074 | THS=0.000 | - -Phase 6.1 Hold Fix Iter | Checksum: fbd5f750 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1429.477 ; gain = 106.352 -Phase 6 Post Hold Fix | Checksum: fbd5f750 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1429.477 ; gain = 106.352 - -Phase 7 Route finalize - -Router Utilization Summary - Global Vertical Routing Utilization = 0.0239302 % - Global Horizontal Routing Utilization = 0.00919118 % - Routable Net Status* - *Does not include unroutable nets such as driverless and loadless. - Run report_route_status for detailed report. - Number of Failed Nets = 0 - Number of Unrouted Nets = 0 - Number of Partially Routed Nets = 0 - Number of Node Overlaps = 0 - -Phase 7 Route finalize | Checksum: 1a2bd3c5a - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1429.477 ; gain = 106.352 - -Phase 8 Verifying routed nets - - Verification completed successfully -Phase 8 Verifying routed nets | Checksum: 1a2bd3c5a - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1431.516 ; gain = 108.391 - -Phase 9 Depositing Routes -Phase 9 Depositing Routes | Checksum: 239975ea0 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1431.516 ; gain = 108.391 - -Phase 10 Post Router Timing -INFO: [Route 35-57] Estimated Timing Summary | WNS=35.254 | TNS=0.000 | WHS=0.074 | THS=0.000 | - -INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. -Phase 10 Post Router Timing | Checksum: 239975ea0 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1431.516 ; gain = 108.391 -INFO: [Route 35-16] Router Completed Successfully - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1431.516 ; gain = 108.391 - -Routing Is Done. -INFO: [Common 17-83] Releasing license: Implementation -75 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -route_design completed successfully -route_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:23 . Memory (MB): peak = 1431.516 ; gain = 108.391 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1431.516 ; gain = 0.000 -INFO: [Timing 38-480] Writing timing data to binary archive. -Writing placer database... -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1432.102 ; gain = 0.586 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1432.102 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_routed.dcp' has been generated. -INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx -Command: report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx -INFO: [IP_Flow 19-1839] IP Catalog is up to date. -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_routed.rpt. -report_drc completed successfully -INFO: [runtcl-4] Executing : report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx -Command: report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [DRC 23-133] Running Methodology with 2 threads -INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_methodology_drc_routed.rpt. -report_methodology completed successfully -INFO: [runtcl-4] Executing : report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx -Command: report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx -INFO: [Timing 38-35] Done setting XDC timing constraints. -Running Vector-less Activity Propagation... - -Finished Running Vector-less Activity Propagation -87 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -report_power completed successfully -INFO: [runtcl-4] Executing : report_route_status -file VGA_top_route_status.rpt -pb VGA_top_route_status.pb -INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file VGA_top_timing_summary_routed.rpt -pb VGA_top_timing_summary_routed.pb -rpx VGA_top_timing_summary_routed.rpx -warn_on_violation -INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. -INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs -INFO: [runtcl-4] Executing : report_incremental_reuse -file VGA_top_incremental_reuse_routed.rpt -INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. -INFO: [runtcl-4] Executing : report_clock_utilization -file VGA_top_clock_utilization_routed.rpt -INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file VGA_top_bus_skew_routed.rpt -pb VGA_top_bus_skew_routed.pb -rpx VGA_top_bus_skew_routed.rpx -INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. -INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs -INFO: [Common 17-206] Exiting Vivado at Tue Nov 30 12:27:12 2021... diff --git a/projet-vga.runs/impl_1/VGA_top_14844.backup.vdi b/projet-vga.runs/impl_1/VGA_top_14844.backup.vdi deleted file mode 100644 index 42d96d7..0000000 --- a/projet-vga.runs/impl_1/VGA_top_14844.backup.vdi +++ /dev/null @@ -1,545 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Tue Nov 23 10:29:07 2021 -# Process ID: 14844 -# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1 -# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace -# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi -# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou -#----------------------------------------------------------- -source VGA_top.tcl -notrace -Command: link_design -top VGA_top -part xc7z010clg400-1 -Design is defaulting to srcset: sources_1 -Design is defaulting to constrset: constrs_1 -INFO: [Project 1-454] Reading design checkpoint 'c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.dcp' for cell 'U0' -INFO: [Netlist 29-17] Analyzing 11 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-479] Netlist was created with Vivado 2018.3 -INFO: [Device 21-403] Loading part xc7z010clg400-1 -INFO: [Project 1-570] Preparing netlist for logic optimization -Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst' -Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst' -Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst' -INFO: [Timing 38-35] Done setting XDC timing constraints. [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57] -INFO: [Timing 38-2] Deriving generated clocks [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57] -get_clocks: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1244.230 ; gain = 551.977 -Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst' -Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc] -Finished Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc] -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1244.230 ; gain = 0.000 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -link_design completed successfully -link_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:24 . Memory (MB): peak = 1244.230 ; gain = 880.109 -Command: opt_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' -Running DRC as a precondition to command opt_design - -Starting DRC Task -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Project 1-461] DRC finished with 0 Errors -INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.506 . Memory (MB): peak = 1244.230 ; gain = 0.000 - -Starting Cache Timing Information Task -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [Timing 38-2] Deriving generated clocks -Ending Cache Timing Information Task | Checksum: b8ea7a4e - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1262.832 ; gain = 18.602 - -Starting Logic Optimization Task - -Phase 1 Retarget -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -INFO: [Opt 31-49] Retargeted 0 cell(s). -Phase 1 Retarget | Checksum: b8ea7a4e - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1344.859 ; gain = 0.000 -INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells -INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. - -Phase 2 Constant propagation -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Phase 2 Constant propagation | Checksum: b8ea7a4e - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1344.859 ; gain = 0.000 -INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells - -Phase 3 Sweep -Phase 3 Sweep | Checksum: 69d8ab95 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1344.859 ; gain = 0.000 -INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells - -Phase 4 BUFG optimization -INFO: [Opt 31-194] Inserted BUFG U0/inst/clk_out1_clk_wiz_1_BUFG_inst to drive 0 load(s) on clock net U0/inst/clk_out1_clk_wiz_1_BUFG -INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets -Phase 4 BUFG optimization | Checksum: 13bee9dc1 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 1344.859 ; gain = 0.000 -INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. - -Phase 5 Shift Register Optimization -Phase 5 Shift Register Optimization | Checksum: 1a59d5459 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.037 . Memory (MB): peak = 1344.859 ; gain = 0.000 -INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells - -Phase 6 Post Processing Netlist -Phase 6 Post Processing Netlist | Checksum: 14a40c514 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 1344.859 ; gain = 0.000 -INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells -Opt_design Change Summary -========================= - - -------------------------------------------------------------------------------------------------------------------------- -| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | -------------------------------------------------------------------------------------------------------------------------- -| Retarget | 0 | 0 | 1 | -| Constant propagation | 0 | 0 | 0 | -| Sweep | 0 | 0 | 0 | -| BUFG optimization | 0 | 0 | 0 | -| Shift Register Optimization | 0 | 0 | 0 | -| Post Processing Netlist | 0 | 0 | 0 | -------------------------------------------------------------------------------------------------------------------------- - - - -Starting Connectivity Check Task - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1344.859 ; gain = 0.000 -Ending Logic Optimization Task | Checksum: 14dbbd0bc - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.040 . Memory (MB): peak = 1344.859 ; gain = 0.000 - -Starting Power Optimization Task -INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. -Ending Power Optimization Task | Checksum: 14dbbd0bc - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1344.859 ; gain = 0.000 - -Starting Final Cleanup Task -Ending Final Cleanup Task | Checksum: 14dbbd0bc - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1344.859 ; gain = 0.000 - -Starting Netlist Obfuscation Task -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1344.859 ; gain = 0.000 -Ending Netlist Obfuscation Task | Checksum: 14dbbd0bc - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1344.859 ; gain = 0.000 -INFO: [Common 17-83] Releasing license: Implementation -30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -opt_design completed successfully -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1344.859 ; gain = 0.000 -INFO: [Timing 38-480] Writing timing data to binary archive. -Writing placer database... -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1344.859 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1344.859 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_opt.dcp' has been generated. -INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx -Command: report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx -INFO: [IP_Flow 19-1839] IP Catalog is up to date. -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_opted.rpt. -report_drc completed successfully -Command: place_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. -Running DRC as a precondition to command place_design -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. - -Starting Placer Task -INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs - -Phase 1 Placer Initialization - -Phase 1.1 Placer Initialization Netlist Sorting -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1344.859 ; gain = 0.000 -Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fa6d7a79 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1344.859 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1344.859 ; gain = 0.000 - -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device -INFO: [Timing 38-35] Done setting XDC timing constraints. -WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. - - bouton_down_IBUF_inst (IBUF.O) is locked to IOB_X0Y1 - bouton_down_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y1 -Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. -WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. - - bouton_right_IBUF_inst (IBUF.O) is locked to IOB_X0Y36 - bouton_right_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 -Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 12622357c - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.285 . Memory (MB): peak = 1344.859 ; gain = 0.000 - -Phase 1.3 Build Placer Netlist Model -Phase 1.3 Build Placer Netlist Model | Checksum: 1b3b55d5e - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.343 . Memory (MB): peak = 1344.859 ; gain = 0.000 - -Phase 1.4 Constrain Clocks/Macros -Phase 1.4 Constrain Clocks/Macros | Checksum: 1b3b55d5e - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.345 . Memory (MB): peak = 1344.859 ; gain = 0.000 -Phase 1 Placer Initialization | Checksum: 1b3b55d5e - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.345 . Memory (MB): peak = 1344.859 ; gain = 0.000 - -Phase 2 Global Placement - -Phase 2.1 Floorplanning -Phase 2.1 Floorplanning | Checksum: 1f34e0130 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.376 . Memory (MB): peak = 1344.859 ; gain = 0.000 - -Phase 2.2 Physical Synthesis In Placer -INFO: [Physopt 32-65] No nets found for high-fanout optimization. -INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. -INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell -INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed. -INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed. -INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed. -INFO: [Physopt 32-949] No candidate nets found for HD net replication -INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1344.859 ; gain = 0.000 - -Summary of Physical Synthesis Optimizations -============================================ - - ----------------------------------------------------------------------------------------------------------------------------------------- -| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------- -| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| HD Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| Total | 0 | 0 | 0 | 0 | 2 | 00:00:00 | ----------------------------------------------------------------------------------------------------------------------------------------- - - -Phase 2.2 Physical Synthesis In Placer | Checksum: 1f822ab4a - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.886 . Memory (MB): peak = 1344.859 ; gain = 0.000 -Phase 2 Global Placement | Checksum: 17fde1b87 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.897 . Memory (MB): peak = 1344.859 ; gain = 0.000 - -Phase 3 Detail Placement - -Phase 3.1 Commit Multi Column Macros -Phase 3.1 Commit Multi Column Macros | Checksum: 17fde1b87 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.898 . Memory (MB): peak = 1344.859 ; gain = 0.000 - -Phase 3.2 Commit Most Macros & LUTRAMs -Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 258919723 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.931 . Memory (MB): peak = 1344.859 ; gain = 0.000 - -Phase 3.3 Area Swap Optimization -Phase 3.3 Area Swap Optimization | Checksum: 1af65d909 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.933 . Memory (MB): peak = 1344.859 ; gain = 0.000 - -Phase 3.4 Pipeline Register Optimization -Phase 3.4 Pipeline Register Optimization | Checksum: 245deb5d9 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.934 . Memory (MB): peak = 1344.859 ; gain = 0.000 - -Phase 3.5 Small Shape Detail Placement -Phase 3.5 Small Shape Detail Placement | Checksum: 1dab8f54b - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.998 . Memory (MB): peak = 1344.859 ; gain = 0.000 - -Phase 3.6 Re-assign LUT pins -Phase 3.6 Re-assign LUT pins | Checksum: 1e1eee966 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1344.859 ; gain = 0.000 - -Phase 3.7 Pipeline Register Optimization -Phase 3.7 Pipeline Register Optimization | Checksum: f76e0896 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1344.859 ; gain = 0.000 -Phase 3 Detail Placement | Checksum: f76e0896 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1344.859 ; gain = 0.000 - -Phase 4 Post Placement Optimization and Clean-Up - -Phase 4.1 Post Commit Optimization -INFO: [Timing 38-35] Done setting XDC timing constraints. - -Phase 4.1.1 Post Placement Optimization -Post Placement Optimization Initialization | Checksum: 13e7bd2c2 - -Phase 4.1.1.1 BUFG Insertion -INFO: [Place 46-46] BUFG insertion identified 0 candidate nets, 0 success, 0 bufg driver replicated, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason -Phase 4.1.1.1 BUFG Insertion | Checksum: 13e7bd2c2 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1344.859 ; gain = 0.000 -INFO: [Place 30-746] Post Placement Timing Summary WNS=35.645. For the most accurate timing information please run report_timing. -Phase 4.1.1 Post Placement Optimization | Checksum: 15c183492 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1344.859 ; gain = 0.000 -Phase 4.1 Post Commit Optimization | Checksum: 15c183492 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1344.859 ; gain = 0.000 - -Phase 4.2 Post Placement Cleanup -Phase 4.2 Post Placement Cleanup | Checksum: 15c183492 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1344.859 ; gain = 0.000 - -Phase 4.3 Placer Reporting -Phase 4.3 Placer Reporting | Checksum: 15c183492 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1344.859 ; gain = 0.000 - -Phase 4.4 Final Placement Cleanup -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1344.859 ; gain = 0.000 -Phase 4.4 Final Placement Cleanup | Checksum: 17d5ce04d - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1344.859 ; gain = 0.000 -Phase 4 Post Placement Optimization and Clean-Up | Checksum: 17d5ce04d - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1344.859 ; gain = 0.000 -Ending Placer Task | Checksum: d443f812 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1344.859 ; gain = 0.000 -INFO: [Common 17-83] Releasing license: Implementation -57 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. -place_design completed successfully -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1344.859 ; gain = 0.000 -INFO: [Timing 38-480] Writing timing data to binary archive. -Writing placer database... -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.047 . Memory (MB): peak = 1344.859 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1344.859 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_placed.dcp' has been generated. -INFO: [runtcl-4] Executing : report_io -file VGA_top_io_placed.rpt -report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 1344.859 ; gain = 0.000 -INFO: [runtcl-4] Executing : report_utilization -file VGA_top_utilization_placed.rpt -pb VGA_top_utilization_placed.pb -INFO: [runtcl-4] Executing : report_control_sets -verbose -file VGA_top_control_sets_placed.rpt -report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1344.859 ; gain = 0.000 -Command: route_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' -Running DRC as a precondition to command route_design -INFO: [DRC 23-27] Running DRC with 2 threads -WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. -Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. - This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. - - bouton_down_IBUF_inst (IBUF.O) is locked to IOB_X0Y1 - bouton_down_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y1 -WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. -Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. - This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. - - bouton_right_IBUF_inst (IBUF.O) is locked to IOB_X0Y36 - bouton_right_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 2 Warnings -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. - - -Starting Routing Task -INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs -Checksum: PlaceDB: 52480e80 ConstDB: 0 ShapeSum: 81fbe992 RouteDB: 0 - -Phase 1 Build RT Design -Phase 1 Build RT Design | Checksum: fee31c87 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1413.766 ; gain = 68.906 -Post Restoration Checksum: NetGraph: e323ff66 NumContArr: 1bbf1d21 Constraints: 0 Timing: 0 - -Phase 2 Router Initialization - -Phase 2.1 Create Timer -Phase 2.1 Create Timer | Checksum: fee31c87 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1444.059 ; gain = 99.199 - -Phase 2.2 Fix Topology Constraints -Phase 2.2 Fix Topology Constraints | Checksum: fee31c87 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1450.090 ; gain = 105.230 - -Phase 2.3 Pre Route Cleanup -Phase 2.3 Pre Route Cleanup | Checksum: fee31c87 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1450.090 ; gain = 105.230 - Number of Nodes with overlaps = 0 - -Phase 2.4 Update Timing -Phase 2.4 Update Timing | Checksum: 1441c14dd - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1454.070 ; gain = 109.211 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.769 | TNS=0.000 | WHS=-0.258 | THS=-3.023 | - -Phase 2 Router Initialization | Checksum: 173a347ed - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1454.070 ; gain = 109.211 - -Phase 3 Initial Routing -Phase 3 Initial Routing | Checksum: 205eb8b74 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1454.996 ; gain = 110.137 - -Phase 4 Rip-up And Reroute - -Phase 4.1 Global Iteration 0 - Number of Nodes with overlaps = 17 - Number of Nodes with overlaps = 0 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.132 | TNS=0.000 | WHS=N/A | THS=N/A | - -Phase 4.1 Global Iteration 0 | Checksum: 2843d0f71 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1454.996 ; gain = 110.137 -Phase 4 Rip-up And Reroute | Checksum: 2843d0f71 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1454.996 ; gain = 110.137 - -Phase 5 Delay and Skew Optimization - -Phase 5.1 Delay CleanUp -Phase 5.1 Delay CleanUp | Checksum: 2843d0f71 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1454.996 ; gain = 110.137 - -Phase 5.2 Clock Skew Optimization -Phase 5.2 Clock Skew Optimization | Checksum: 2843d0f71 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1454.996 ; gain = 110.137 -Phase 5 Delay and Skew Optimization | Checksum: 2843d0f71 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1454.996 ; gain = 110.137 - -Phase 6 Post Hold Fix - -Phase 6.1 Hold Fix Iter - -Phase 6.1.1 Update Timing -Phase 6.1.1 Update Timing | Checksum: 1adede088 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1454.996 ; gain = 110.137 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.132 | TNS=0.000 | WHS=0.069 | THS=0.000 | - -Phase 6.1 Hold Fix Iter | Checksum: 1adede088 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1454.996 ; gain = 110.137 -Phase 6 Post Hold Fix | Checksum: 1adede088 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1454.996 ; gain = 110.137 - -Phase 7 Route finalize - -Router Utilization Summary - Global Vertical Routing Utilization = 0.0615146 % - Global Horizontal Routing Utilization = 0.0558364 % - Routable Net Status* - *Does not include unroutable nets such as driverless and loadless. - Run report_route_status for detailed report. - Number of Failed Nets = 0 - Number of Unrouted Nets = 0 - Number of Partially Routed Nets = 0 - Number of Node Overlaps = 0 - -Phase 7 Route finalize | Checksum: 2005f65b4 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1454.996 ; gain = 110.137 - -Phase 8 Verifying routed nets - - Verification completed successfully -Phase 8 Verifying routed nets | Checksum: 2005f65b4 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1456.047 ; gain = 111.188 - -Phase 9 Depositing Routes -Phase 9 Depositing Routes | Checksum: 18ba5fe80 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1456.047 ; gain = 111.188 - -Phase 10 Post Router Timing -INFO: [Route 35-57] Estimated Timing Summary | WNS=35.132 | TNS=0.000 | WHS=0.069 | THS=0.000 | - -INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. -Phase 10 Post Router Timing | Checksum: 18ba5fe80 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1456.047 ; gain = 111.188 -INFO: [Route 35-16] Router Completed Successfully - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1456.047 ; gain = 111.188 - -Routing Is Done. -INFO: [Common 17-83] Releasing license: Implementation -74 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. -route_design completed successfully -route_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1456.047 ; gain = 111.188 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1456.047 ; gain = 0.000 -INFO: [Timing 38-480] Writing timing data to binary archive. -Writing placer database... -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.046 . Memory (MB): peak = 1456.453 ; gain = 0.406 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1456.453 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_routed.dcp' has been generated. -INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx -Command: report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx -INFO: [IP_Flow 19-1839] IP Catalog is up to date. -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_routed.rpt. -report_drc completed successfully -INFO: [runtcl-4] Executing : report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx -Command: report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [DRC 23-133] Running Methodology with 2 threads -INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_methodology_drc_routed.rpt. -report_methodology completed successfully -INFO: [runtcl-4] Executing : report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx -Command: report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx -INFO: [Timing 38-35] Done setting XDC timing constraints. -Running Vector-less Activity Propagation... - -Finished Running Vector-less Activity Propagation -86 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. -report_power completed successfully -INFO: [runtcl-4] Executing : report_route_status -file VGA_top_route_status.rpt -pb VGA_top_route_status.pb -INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file VGA_top_timing_summary_routed.rpt -pb VGA_top_timing_summary_routed.pb -rpx VGA_top_timing_summary_routed.rpx -warn_on_violation -INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. -INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs -INFO: [runtcl-4] Executing : report_incremental_reuse -file VGA_top_incremental_reuse_routed.rpt -INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. -INFO: [runtcl-4] Executing : report_clock_utilization -file VGA_top_clock_utilization_routed.rpt -INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file VGA_top_bus_skew_routed.rpt -pb VGA_top_bus_skew_routed.pb -rpx VGA_top_bus_skew_routed.rpx -INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. -INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs -INFO: [Common 17-206] Exiting Vivado at Tue Nov 23 10:29:55 2021... diff --git a/projet-vga.runs/impl_1/VGA_top_15112.backup.vdi b/projet-vga.runs/impl_1/VGA_top_15112.backup.vdi deleted file mode 100644 index 2240c88..0000000 --- a/projet-vga.runs/impl_1/VGA_top_15112.backup.vdi +++ /dev/null @@ -1,523 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Tue Nov 30 12:16:55 2021 -# Process ID: 15112 -# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1 -# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace -# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi -# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou -#----------------------------------------------------------- -source VGA_top.tcl -notrace -Command: link_design -top VGA_top -part xc7z010clg400-1 -Design is defaulting to srcset: sources_1 -Design is defaulting to constrset: constrs_1 -INFO: [Project 1-454] Reading design checkpoint 'c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.dcp' for cell 'U0' -INFO: [Netlist 29-17] Analyzing 3 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-479] Netlist was created with Vivado 2018.3 -INFO: [Device 21-403] Loading part xc7z010clg400-1 -INFO: [Project 1-570] Preparing netlist for logic optimization -Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst' -Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst' -Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst' -INFO: [Timing 38-35] Done setting XDC timing constraints. [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57] -INFO: [Timing 38-2] Deriving generated clocks [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57] -get_clocks: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1224.488 ; gain = 533.477 -Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst' -Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc] -Finished Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc] -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1224.488 ; gain = 0.000 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -link_design completed successfully -link_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:16 . Memory (MB): peak = 1224.488 ; gain = 861.793 -Command: opt_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' -Running DRC as a precondition to command opt_design - -Starting DRC Task -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Project 1-461] DRC finished with 0 Errors -INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.505 . Memory (MB): peak = 1224.488 ; gain = 0.000 - -Starting Cache Timing Information Task -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [Timing 38-2] Deriving generated clocks -Ending Cache Timing Information Task | Checksum: dc2ced6f - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1241.574 ; gain = 17.086 - -Starting Logic Optimization Task - -Phase 1 Retarget -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -INFO: [Opt 31-49] Retargeted 0 cell(s). -Phase 1 Retarget | Checksum: dc2ced6f - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1325.754 ; gain = 0.000 -INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells -INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. - -Phase 2 Constant propagation -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Phase 2 Constant propagation | Checksum: dc2ced6f - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1325.754 ; gain = 0.000 -INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells - -Phase 3 Sweep -Phase 3 Sweep | Checksum: 19e1c8f17 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1325.754 ; gain = 0.000 -INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells - -Phase 4 BUFG optimization -INFO: [Opt 31-194] Inserted BUFG U0/inst/clk_out1_clk_wiz_1_BUFG_inst to drive 0 load(s) on clock net U0/inst/clk_out1_clk_wiz_1_BUFG -INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets -Phase 4 BUFG optimization | Checksum: c943f809 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1325.754 ; gain = 0.000 -INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. - -Phase 5 Shift Register Optimization -Phase 5 Shift Register Optimization | Checksum: ba2b01e3 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 1325.754 ; gain = 0.000 -INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells - -Phase 6 Post Processing Netlist -Phase 6 Post Processing Netlist | Checksum: b57bee7a - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1325.754 ; gain = 0.000 -INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells -Opt_design Change Summary -========================= - - -------------------------------------------------------------------------------------------------------------------------- -| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | -------------------------------------------------------------------------------------------------------------------------- -| Retarget | 0 | 0 | 1 | -| Constant propagation | 0 | 0 | 0 | -| Sweep | 0 | 0 | 0 | -| BUFG optimization | 0 | 0 | 0 | -| Shift Register Optimization | 0 | 0 | 0 | -| Post Processing Netlist | 0 | 0 | 0 | -------------------------------------------------------------------------------------------------------------------------- - - - -Starting Connectivity Check Task - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1325.754 ; gain = 0.000 -Ending Logic Optimization Task | Checksum: 13b7a3fb2 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 1325.754 ; gain = 0.000 - -Starting Power Optimization Task -INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. -Ending Power Optimization Task | Checksum: 13b7a3fb2 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1325.754 ; gain = 0.000 - -Starting Final Cleanup Task -Ending Final Cleanup Task | Checksum: 13b7a3fb2 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1325.754 ; gain = 0.000 - -Starting Netlist Obfuscation Task -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1325.754 ; gain = 0.000 -Ending Netlist Obfuscation Task | Checksum: 13b7a3fb2 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1325.754 ; gain = 0.000 -INFO: [Common 17-83] Releasing license: Implementation -30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -opt_design completed successfully -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1325.754 ; gain = 0.000 -INFO: [Timing 38-480] Writing timing data to binary archive. -Writing placer database... -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.036 . Memory (MB): peak = 1325.754 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1325.754 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_opt.dcp' has been generated. -INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx -Command: report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx -INFO: [IP_Flow 19-1839] IP Catalog is up to date. -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_opted.rpt. -report_drc completed successfully -Command: place_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. -Running DRC as a precondition to command place_design -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. - -Starting Placer Task -INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs - -Phase 1 Placer Initialization - -Phase 1.1 Placer Initialization Netlist Sorting -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1325.754 ; gain = 0.000 -Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 67b44082 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1325.754 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1325.754 ; gain = 0.000 - -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device -INFO: [Timing 38-35] Done setting XDC timing constraints. -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 14d1cdeaf - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.242 . Memory (MB): peak = 1325.754 ; gain = 0.000 - -Phase 1.3 Build Placer Netlist Model -Phase 1.3 Build Placer Netlist Model | Checksum: 1bfc53c93 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.307 . Memory (MB): peak = 1325.754 ; gain = 0.000 - -Phase 1.4 Constrain Clocks/Macros -Phase 1.4 Constrain Clocks/Macros | Checksum: 1bfc53c93 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.308 . Memory (MB): peak = 1325.754 ; gain = 0.000 -Phase 1 Placer Initialization | Checksum: 1bfc53c93 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.309 . Memory (MB): peak = 1325.754 ; gain = 0.000 - -Phase 2 Global Placement - -Phase 2.1 Floorplanning -Phase 2.1 Floorplanning | Checksum: 152ddf35d - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.349 . Memory (MB): peak = 1325.754 ; gain = 0.000 - -Phase 2.2 Physical Synthesis In Placer -INFO: [Physopt 32-65] No nets found for high-fanout optimization. -INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. -INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell -INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed. -INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed. -INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed. -INFO: [Physopt 32-949] No candidate nets found for HD net replication -INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1325.754 ; gain = 0.000 - -Summary of Physical Synthesis Optimizations -============================================ - - ----------------------------------------------------------------------------------------------------------------------------------------- -| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------- -| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| HD Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| Total | 0 | 0 | 0 | 0 | 2 | 00:00:00 | ----------------------------------------------------------------------------------------------------------------------------------------- - - -Phase 2.2 Physical Synthesis In Placer | Checksum: 166883134 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.854 . Memory (MB): peak = 1325.754 ; gain = 0.000 -Phase 2 Global Placement | Checksum: 1ea5262ce - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.863 . Memory (MB): peak = 1325.754 ; gain = 0.000 - -Phase 3 Detail Placement - -Phase 3.1 Commit Multi Column Macros -Phase 3.1 Commit Multi Column Macros | Checksum: 1ea5262ce - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.864 . Memory (MB): peak = 1325.754 ; gain = 0.000 - -Phase 3.2 Commit Most Macros & LUTRAMs -Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1350cd04a - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.906 . Memory (MB): peak = 1325.754 ; gain = 0.000 - -Phase 3.3 Area Swap Optimization -Phase 3.3 Area Swap Optimization | Checksum: 1c8d9a95a - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.908 . Memory (MB): peak = 1325.754 ; gain = 0.000 - -Phase 3.4 Pipeline Register Optimization -Phase 3.4 Pipeline Register Optimization | Checksum: 1c8d9a95a - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.908 . Memory (MB): peak = 1325.754 ; gain = 0.000 - -Phase 3.5 Small Shape Detail Placement -Phase 3.5 Small Shape Detail Placement | Checksum: 236b118c7 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.965 . Memory (MB): peak = 1325.754 ; gain = 0.000 - -Phase 3.6 Re-assign LUT pins -Phase 3.6 Re-assign LUT pins | Checksum: 182b978ad - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.968 . Memory (MB): peak = 1325.754 ; gain = 0.000 - -Phase 3.7 Pipeline Register Optimization -Phase 3.7 Pipeline Register Optimization | Checksum: 182b978ad - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.968 . Memory (MB): peak = 1325.754 ; gain = 0.000 -Phase 3 Detail Placement | Checksum: 182b978ad - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.969 . Memory (MB): peak = 1325.754 ; gain = 0.000 - -Phase 4 Post Placement Optimization and Clean-Up - -Phase 4.1 Post Commit Optimization -INFO: [Timing 38-35] Done setting XDC timing constraints. - -Phase 4.1.1 Post Placement Optimization -Post Placement Optimization Initialization | Checksum: c19cad15 - -Phase 4.1.1.1 BUFG Insertion -INFO: [Place 46-46] BUFG insertion identified 0 candidate nets, 0 success, 0 bufg driver replicated, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason -Phase 4.1.1.1 BUFG Insertion | Checksum: c19cad15 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.996 . Memory (MB): peak = 1325.754 ; gain = 0.000 -INFO: [Place 30-746] Post Placement Timing Summary WNS=36.030. For the most accurate timing information please run report_timing. -Phase 4.1.1 Post Placement Optimization | Checksum: a4d8353e - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.997 . Memory (MB): peak = 1325.754 ; gain = 0.000 -Phase 4.1 Post Commit Optimization | Checksum: a4d8353e - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.997 . Memory (MB): peak = 1325.754 ; gain = 0.000 - -Phase 4.2 Post Placement Cleanup -Phase 4.2 Post Placement Cleanup | Checksum: a4d8353e - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.999 . Memory (MB): peak = 1325.754 ; gain = 0.000 - -Phase 4.3 Placer Reporting -Phase 4.3 Placer Reporting | Checksum: a4d8353e - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.999 . Memory (MB): peak = 1325.754 ; gain = 0.000 - -Phase 4.4 Final Placement Cleanup -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1325.754 ; gain = 0.000 -Phase 4.4 Final Placement Cleanup | Checksum: 80d205c8 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1325.754 ; gain = 0.000 -Phase 4 Post Placement Optimization and Clean-Up | Checksum: 80d205c8 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1325.754 ; gain = 0.000 -Ending Placer Task | Checksum: 362c66e8 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1325.754 ; gain = 0.000 -INFO: [Common 17-83] Releasing license: Implementation -57 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -place_design completed successfully -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1325.754 ; gain = 0.000 -INFO: [Timing 38-480] Writing timing data to binary archive. -Writing placer database... -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1325.754 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1325.754 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_placed.dcp' has been generated. -INFO: [runtcl-4] Executing : report_io -file VGA_top_io_placed.rpt -report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 1325.754 ; gain = 0.000 -INFO: [runtcl-4] Executing : report_utilization -file VGA_top_utilization_placed.rpt -pb VGA_top_utilization_placed.pb -INFO: [runtcl-4] Executing : report_control_sets -verbose -file VGA_top_control_sets_placed.rpt -report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1325.754 ; gain = 0.000 -Command: route_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' -Running DRC as a precondition to command route_design -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. - - -Starting Routing Task -INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs -Checksum: PlaceDB: 1579e8f6 ConstDB: 0 ShapeSum: 20b27df2 RouteDB: 0 - -Phase 1 Build RT Design -Phase 1 Build RT Design | Checksum: b6d8bcc7 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1398.246 ; gain = 72.492 -Post Restoration Checksum: NetGraph: acd0c6a6 NumContArr: a07f621 Constraints: 0 Timing: 0 - -Phase 2 Router Initialization - -Phase 2.1 Create Timer -Phase 2.1 Create Timer | Checksum: b6d8bcc7 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1422.508 ; gain = 96.754 - -Phase 2.2 Fix Topology Constraints -Phase 2.2 Fix Topology Constraints | Checksum: b6d8bcc7 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1428.512 ; gain = 102.758 - -Phase 2.3 Pre Route Cleanup -Phase 2.3 Pre Route Cleanup | Checksum: b6d8bcc7 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1428.512 ; gain = 102.758 - Number of Nodes with overlaps = 0 - -Phase 2.4 Update Timing -Phase 2.4 Update Timing | Checksum: 1c88f2ffd - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1431.293 ; gain = 105.539 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.958 | TNS=0.000 | WHS=-0.276 | THS=-3.718 | - -Phase 2 Router Initialization | Checksum: 10a6ee9df - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1431.293 ; gain = 105.539 - -Phase 3 Initial Routing -Phase 3 Initial Routing | Checksum: 17776be02 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1431.293 ; gain = 105.539 - -Phase 4 Rip-up And Reroute - -Phase 4.1 Global Iteration 0 - Number of Nodes with overlaps = 4 - Number of Nodes with overlaps = 0 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=36.113 | TNS=0.000 | WHS=N/A | THS=N/A | - -Phase 4.1 Global Iteration 0 | Checksum: 19eac515a - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1431.293 ; gain = 105.539 -Phase 4 Rip-up And Reroute | Checksum: 19eac515a - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1431.293 ; gain = 105.539 - -Phase 5 Delay and Skew Optimization - -Phase 5.1 Delay CleanUp -Phase 5.1 Delay CleanUp | Checksum: 19eac515a - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1431.293 ; gain = 105.539 - -Phase 5.2 Clock Skew Optimization -Phase 5.2 Clock Skew Optimization | Checksum: 19eac515a - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1431.293 ; gain = 105.539 -Phase 5 Delay and Skew Optimization | Checksum: 19eac515a - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1431.293 ; gain = 105.539 - -Phase 6 Post Hold Fix - -Phase 6.1 Hold Fix Iter - -Phase 6.1.1 Update Timing -Phase 6.1.1 Update Timing | Checksum: 219991e28 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1431.293 ; gain = 105.539 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=36.266 | TNS=0.000 | WHS=0.076 | THS=0.000 | - -Phase 6.1 Hold Fix Iter | Checksum: 219991e28 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1431.293 ; gain = 105.539 -Phase 6 Post Hold Fix | Checksum: 219991e28 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1431.293 ; gain = 105.539 - -Phase 7 Route finalize - -Router Utilization Summary - Global Vertical Routing Utilization = 0.00900901 % - Global Horizontal Routing Utilization = 0.00344669 % - Routable Net Status* - *Does not include unroutable nets such as driverless and loadless. - Run report_route_status for detailed report. - Number of Failed Nets = 0 - Number of Unrouted Nets = 0 - Number of Partially Routed Nets = 0 - Number of Node Overlaps = 0 - -Phase 7 Route finalize | Checksum: 1f6edf796 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1431.293 ; gain = 105.539 - -Phase 8 Verifying routed nets - - Verification completed successfully -Phase 8 Verifying routed nets | Checksum: 1f6edf796 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.059 ; gain = 107.305 - -Phase 9 Depositing Routes -Phase 9 Depositing Routes | Checksum: 1ba53fff2 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.059 ; gain = 107.305 - -Phase 10 Post Router Timing -INFO: [Route 35-57] Estimated Timing Summary | WNS=36.266 | TNS=0.000 | WHS=0.076 | THS=0.000 | - -INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. -Phase 10 Post Router Timing | Checksum: 1ba53fff2 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.059 ; gain = 107.305 -INFO: [Route 35-16] Router Completed Successfully - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.059 ; gain = 107.305 - -Routing Is Done. -INFO: [Common 17-83] Releasing license: Implementation -74 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -route_design completed successfully -route_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:22 . Memory (MB): peak = 1433.059 ; gain = 107.305 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1433.059 ; gain = 0.000 -INFO: [Timing 38-480] Writing timing data to binary archive. -Writing placer database... -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 1433.059 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1433.148 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_routed.dcp' has been generated. -INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx -Command: report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx -INFO: [IP_Flow 19-1839] IP Catalog is up to date. -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_routed.rpt. -report_drc completed successfully -INFO: [runtcl-4] Executing : report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx -Command: report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [DRC 23-133] Running Methodology with 2 threads -INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_methodology_drc_routed.rpt. -report_methodology completed successfully -INFO: [runtcl-4] Executing : report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx -Command: report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx -INFO: [Timing 38-35] Done setting XDC timing constraints. -Running Vector-less Activity Propagation... - -Finished Running Vector-less Activity Propagation -86 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -report_power completed successfully -INFO: [runtcl-4] Executing : report_route_status -file VGA_top_route_status.rpt -pb VGA_top_route_status.pb -INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file VGA_top_timing_summary_routed.rpt -pb VGA_top_timing_summary_routed.pb -rpx VGA_top_timing_summary_routed.rpx -warn_on_violation -INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. -INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs -INFO: [runtcl-4] Executing : report_incremental_reuse -file VGA_top_incremental_reuse_routed.rpt -INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. -INFO: [runtcl-4] Executing : report_clock_utilization -file VGA_top_clock_utilization_routed.rpt -INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file VGA_top_bus_skew_routed.rpt -pb VGA_top_bus_skew_routed.pb -rpx VGA_top_bus_skew_routed.rpx -INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. -INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs -INFO: [Common 17-206] Exiting Vivado at Tue Nov 30 12:17:44 2021... diff --git a/projet-vga.runs/impl_1/VGA_top_1568.backup.vdi b/projet-vga.runs/impl_1/VGA_top_1568.backup.vdi deleted file mode 100644 index 7635e86..0000000 --- a/projet-vga.runs/impl_1/VGA_top_1568.backup.vdi +++ /dev/null @@ -1,523 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Tue Nov 30 12:43:37 2021 -# Process ID: 1568 -# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1 -# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace -# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi -# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou -#----------------------------------------------------------- -source VGA_top.tcl -notrace -Command: link_design -top VGA_top -part xc7z010clg400-1 -Design is defaulting to srcset: sources_1 -Design is defaulting to constrset: constrs_1 -INFO: [Project 1-454] Reading design checkpoint 'c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.dcp' for cell 'U0' -INFO: [Netlist 29-17] Analyzing 3 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-479] Netlist was created with Vivado 2018.3 -INFO: [Device 21-403] Loading part xc7z010clg400-1 -INFO: [Project 1-570] Preparing netlist for logic optimization -Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst' -Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst' -Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst' -INFO: [Timing 38-35] Done setting XDC timing constraints. [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57] -INFO: [Timing 38-2] Deriving generated clocks [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57] -get_clocks: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1225.328 ; gain = 533.879 -Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst' -Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc] -Finished Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc] -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1225.328 ; gain = 0.000 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -link_design completed successfully -link_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:16 . Memory (MB): peak = 1225.328 ; gain = 861.820 -Command: opt_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' -Running DRC as a precondition to command opt_design - -Starting DRC Task -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Project 1-461] DRC finished with 0 Errors -INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.509 . Memory (MB): peak = 1225.328 ; gain = 0.000 - -Starting Cache Timing Information Task -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [Timing 38-2] Deriving generated clocks -Ending Cache Timing Information Task | Checksum: 1cd387b97 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1242.352 ; gain = 17.023 - -Starting Logic Optimization Task - -Phase 1 Retarget -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -INFO: [Opt 31-49] Retargeted 0 cell(s). -Phase 1 Retarget | Checksum: 1cd387b97 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1322.477 ; gain = 0.000 -INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells -INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. - -Phase 2 Constant propagation -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Phase 2 Constant propagation | Checksum: 1cd387b97 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1322.477 ; gain = 0.000 -INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells - -Phase 3 Sweep -Phase 3 Sweep | Checksum: 11a1ea9c4 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1322.477 ; gain = 0.000 -INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells - -Phase 4 BUFG optimization -INFO: [Opt 31-194] Inserted BUFG U0/inst/clk_out1_clk_wiz_1_BUFG_inst to drive 0 load(s) on clock net U0/inst/clk_out1_clk_wiz_1_BUFG -INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets -Phase 4 BUFG optimization | Checksum: 1b004ba0c - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1322.477 ; gain = 0.000 -INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. - -Phase 5 Shift Register Optimization -Phase 5 Shift Register Optimization | Checksum: 154e32ba9 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 1322.477 ; gain = 0.000 -INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells - -Phase 6 Post Processing Netlist -Phase 6 Post Processing Netlist | Checksum: 14b38df59 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 1322.477 ; gain = 0.000 -INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells -Opt_design Change Summary -========================= - - -------------------------------------------------------------------------------------------------------------------------- -| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | -------------------------------------------------------------------------------------------------------------------------- -| Retarget | 0 | 0 | 1 | -| Constant propagation | 0 | 0 | 0 | -| Sweep | 0 | 0 | 0 | -| BUFG optimization | 0 | 0 | 0 | -| Shift Register Optimization | 0 | 0 | 0 | -| Post Processing Netlist | 0 | 0 | 0 | -------------------------------------------------------------------------------------------------------------------------- - - - -Starting Connectivity Check Task - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1322.477 ; gain = 0.000 -Ending Logic Optimization Task | Checksum: 1327b0867 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 1322.477 ; gain = 0.000 - -Starting Power Optimization Task -INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. -Ending Power Optimization Task | Checksum: 1327b0867 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1322.477 ; gain = 0.000 - -Starting Final Cleanup Task -Ending Final Cleanup Task | Checksum: 1327b0867 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1322.477 ; gain = 0.000 - -Starting Netlist Obfuscation Task -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1322.477 ; gain = 0.000 -Ending Netlist Obfuscation Task | Checksum: 1327b0867 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1322.477 ; gain = 0.000 -INFO: [Common 17-83] Releasing license: Implementation -30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -opt_design completed successfully -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1322.477 ; gain = 0.000 -INFO: [Timing 38-480] Writing timing data to binary archive. -Writing placer database... -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1322.477 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1322.477 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_opt.dcp' has been generated. -INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx -Command: report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx -INFO: [IP_Flow 19-1839] IP Catalog is up to date. -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_opted.rpt. -report_drc completed successfully -Command: place_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. -Running DRC as a precondition to command place_design -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. - -Starting Placer Task -INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs - -Phase 1 Placer Initialization - -Phase 1.1 Placer Initialization Netlist Sorting -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1322.477 ; gain = 0.000 -Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 11a18955b - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1322.477 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1322.477 ; gain = 0.000 - -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device -INFO: [Timing 38-35] Done setting XDC timing constraints. -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 14857c37a - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.244 . Memory (MB): peak = 1322.477 ; gain = 0.000 - -Phase 1.3 Build Placer Netlist Model -Phase 1.3 Build Placer Netlist Model | Checksum: 1be26ef67 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.306 . Memory (MB): peak = 1323.027 ; gain = 0.551 - -Phase 1.4 Constrain Clocks/Macros -Phase 1.4 Constrain Clocks/Macros | Checksum: 1be26ef67 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.307 . Memory (MB): peak = 1323.027 ; gain = 0.551 -Phase 1 Placer Initialization | Checksum: 1be26ef67 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.308 . Memory (MB): peak = 1323.027 ; gain = 0.551 - -Phase 2 Global Placement - -Phase 2.1 Floorplanning -Phase 2.1 Floorplanning | Checksum: 225160abb - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.356 . Memory (MB): peak = 1323.027 ; gain = 0.551 - -Phase 2.2 Physical Synthesis In Placer -INFO: [Physopt 32-65] No nets found for high-fanout optimization. -INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. -INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell -INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed. -INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed. -INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed. -INFO: [Physopt 32-949] No candidate nets found for HD net replication -INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1323.027 ; gain = 0.000 - -Summary of Physical Synthesis Optimizations -============================================ - - ----------------------------------------------------------------------------------------------------------------------------------------- -| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------- -| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| HD Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| Total | 0 | 0 | 0 | 0 | 2 | 00:00:00 | ----------------------------------------------------------------------------------------------------------------------------------------- - - -Phase 2.2 Physical Synthesis In Placer | Checksum: 1ba25206f - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.875 . Memory (MB): peak = 1323.027 ; gain = 0.551 -Phase 2 Global Placement | Checksum: 23614170f - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.885 . Memory (MB): peak = 1323.027 ; gain = 0.551 - -Phase 3 Detail Placement - -Phase 3.1 Commit Multi Column Macros -Phase 3.1 Commit Multi Column Macros | Checksum: 23614170f - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.886 . Memory (MB): peak = 1323.027 ; gain = 0.551 - -Phase 3.2 Commit Most Macros & LUTRAMs -Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 192f50611 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.941 . Memory (MB): peak = 1323.027 ; gain = 0.551 - -Phase 3.3 Area Swap Optimization -Phase 3.3 Area Swap Optimization | Checksum: 163924b15 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.942 . Memory (MB): peak = 1323.027 ; gain = 0.551 - -Phase 3.4 Pipeline Register Optimization -Phase 3.4 Pipeline Register Optimization | Checksum: 163924b15 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.943 . Memory (MB): peak = 1323.027 ; gain = 0.551 - -Phase 3.5 Small Shape Detail Placement -Phase 3.5 Small Shape Detail Placement | Checksum: 19c86ae3a - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.990 . Memory (MB): peak = 1323.027 ; gain = 0.551 - -Phase 3.6 Re-assign LUT pins -Phase 3.6 Re-assign LUT pins | Checksum: 175abb83f - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.994 . Memory (MB): peak = 1323.027 ; gain = 0.551 - -Phase 3.7 Pipeline Register Optimization -Phase 3.7 Pipeline Register Optimization | Checksum: 175abb83f - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.994 . Memory (MB): peak = 1323.027 ; gain = 0.551 -Phase 3 Detail Placement | Checksum: 175abb83f - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.995 . Memory (MB): peak = 1323.027 ; gain = 0.551 - -Phase 4 Post Placement Optimization and Clean-Up - -Phase 4.1 Post Commit Optimization -INFO: [Timing 38-35] Done setting XDC timing constraints. - -Phase 4.1.1 Post Placement Optimization -Post Placement Optimization Initialization | Checksum: 284ea0e0d - -Phase 4.1.1.1 BUFG Insertion -INFO: [Place 46-46] BUFG insertion identified 0 candidate nets, 0 success, 0 bufg driver replicated, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason -Phase 4.1.1.1 BUFG Insertion | Checksum: 284ea0e0d - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1323.027 ; gain = 0.551 -INFO: [Place 30-746] Post Placement Timing Summary WNS=35.407. For the most accurate timing information please run report_timing. -Phase 4.1.1 Post Placement Optimization | Checksum: 26a7dbbcb - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1323.027 ; gain = 0.551 -Phase 4.1 Post Commit Optimization | Checksum: 26a7dbbcb - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1323.027 ; gain = 0.551 - -Phase 4.2 Post Placement Cleanup -Phase 4.2 Post Placement Cleanup | Checksum: 26a7dbbcb - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1323.027 ; gain = 0.551 - -Phase 4.3 Placer Reporting -Phase 4.3 Placer Reporting | Checksum: 26a7dbbcb - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1323.027 ; gain = 0.551 - -Phase 4.4 Final Placement Cleanup -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1323.027 ; gain = 0.000 -Phase 4.4 Final Placement Cleanup | Checksum: 1e396e624 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1323.027 ; gain = 0.551 -Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1e396e624 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1323.027 ; gain = 0.551 -Ending Placer Task | Checksum: 10ebd1779 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1323.027 ; gain = 0.551 -INFO: [Common 17-83] Releasing license: Implementation -57 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -place_design completed successfully -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1323.027 ; gain = 0.000 -INFO: [Timing 38-480] Writing timing data to binary archive. -Writing placer database... -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1323.746 ; gain = 0.719 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1323.746 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_placed.dcp' has been generated. -INFO: [runtcl-4] Executing : report_io -file VGA_top_io_placed.rpt -report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1323.762 ; gain = 0.000 -INFO: [runtcl-4] Executing : report_utilization -file VGA_top_utilization_placed.rpt -pb VGA_top_utilization_placed.pb -INFO: [runtcl-4] Executing : report_control_sets -verbose -file VGA_top_control_sets_placed.rpt -report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1323.762 ; gain = 0.000 -Command: route_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' -Running DRC as a precondition to command route_design -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. - - -Starting Routing Task -INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs -Checksum: PlaceDB: b0b141f5 ConstDB: 0 ShapeSum: 5e0bd584 RouteDB: 0 - -Phase 1 Build RT Design -Phase 1 Build RT Design | Checksum: 15f37acc5 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1400.961 ; gain = 77.199 -Post Restoration Checksum: NetGraph: 6fc77d0c NumContArr: ef702fb9 Constraints: 0 Timing: 0 - -Phase 2 Router Initialization - -Phase 2.1 Create Timer -Phase 2.1 Create Timer | Checksum: 15f37acc5 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1425.180 ; gain = 101.418 - -Phase 2.2 Fix Topology Constraints -Phase 2.2 Fix Topology Constraints | Checksum: 15f37acc5 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1431.219 ; gain = 107.457 - -Phase 2.3 Pre Route Cleanup -Phase 2.3 Pre Route Cleanup | Checksum: 15f37acc5 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1431.219 ; gain = 107.457 - Number of Nodes with overlaps = 0 - -Phase 2.4 Update Timing -Phase 2.4 Update Timing | Checksum: ca14e25f - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1433.867 ; gain = 110.105 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.355 | TNS=0.000 | WHS=-0.272 | THS=-3.945 | - -Phase 2 Router Initialization | Checksum: ac53c1db - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1433.867 ; gain = 110.105 - -Phase 3 Initial Routing -Phase 3 Initial Routing | Checksum: 19f2e1359 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1433.867 ; gain = 110.105 - -Phase 4 Rip-up And Reroute - -Phase 4.1 Global Iteration 0 - Number of Nodes with overlaps = 1 - Number of Nodes with overlaps = 0 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=34.993 | TNS=0.000 | WHS=N/A | THS=N/A | - -Phase 4.1 Global Iteration 0 | Checksum: a28f5e66 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.867 ; gain = 110.105 -Phase 4 Rip-up And Reroute | Checksum: a28f5e66 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.867 ; gain = 110.105 - -Phase 5 Delay and Skew Optimization - -Phase 5.1 Delay CleanUp -Phase 5.1 Delay CleanUp | Checksum: a28f5e66 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.867 ; gain = 110.105 - -Phase 5.2 Clock Skew Optimization -Phase 5.2 Clock Skew Optimization | Checksum: a28f5e66 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.867 ; gain = 110.105 -Phase 5 Delay and Skew Optimization | Checksum: a28f5e66 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.867 ; gain = 110.105 - -Phase 6 Post Hold Fix - -Phase 6.1 Hold Fix Iter - -Phase 6.1.1 Update Timing -Phase 6.1.1 Update Timing | Checksum: 121d82faf - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.867 ; gain = 110.105 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.146 | TNS=0.000 | WHS=0.055 | THS=0.000 | - -Phase 6.1 Hold Fix Iter | Checksum: 121d82faf - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.867 ; gain = 110.105 -Phase 6 Post Hold Fix | Checksum: 121d82faf - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.867 ; gain = 110.105 - -Phase 7 Route finalize - -Router Utilization Summary - Global Vertical Routing Utilization = 0.0235079 % - Global Horizontal Routing Utilization = 0.0110294 % - Routable Net Status* - *Does not include unroutable nets such as driverless and loadless. - Run report_route_status for detailed report. - Number of Failed Nets = 0 - Number of Unrouted Nets = 0 - Number of Partially Routed Nets = 0 - Number of Node Overlaps = 0 - -Phase 7 Route finalize | Checksum: 174fa15d5 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.867 ; gain = 110.105 - -Phase 8 Verifying routed nets - - Verification completed successfully -Phase 8 Verifying routed nets | Checksum: 174fa15d5 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1435.516 ; gain = 111.754 - -Phase 9 Depositing Routes -Phase 9 Depositing Routes | Checksum: 175dfb98b - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1435.516 ; gain = 111.754 - -Phase 10 Post Router Timing -INFO: [Route 35-57] Estimated Timing Summary | WNS=35.146 | TNS=0.000 | WHS=0.055 | THS=0.000 | - -INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. -Phase 10 Post Router Timing | Checksum: 175dfb98b - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1435.516 ; gain = 111.754 -INFO: [Route 35-16] Router Completed Successfully - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1435.516 ; gain = 111.754 - -Routing Is Done. -INFO: [Common 17-83] Releasing license: Implementation -74 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -route_design completed successfully -route_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:22 . Memory (MB): peak = 1435.516 ; gain = 111.754 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1435.516 ; gain = 0.000 -INFO: [Timing 38-480] Writing timing data to binary archive. -Writing placer database... -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.040 . Memory (MB): peak = 1435.516 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1435.516 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_routed.dcp' has been generated. -INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx -Command: report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx -INFO: [IP_Flow 19-1839] IP Catalog is up to date. -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_routed.rpt. -report_drc completed successfully -INFO: [runtcl-4] Executing : report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx -Command: report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [DRC 23-133] Running Methodology with 2 threads -INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_methodology_drc_routed.rpt. -report_methodology completed successfully -INFO: [runtcl-4] Executing : report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx -Command: report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx -INFO: [Timing 38-35] Done setting XDC timing constraints. -Running Vector-less Activity Propagation... - -Finished Running Vector-less Activity Propagation -86 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -report_power completed successfully -INFO: [runtcl-4] Executing : report_route_status -file VGA_top_route_status.rpt -pb VGA_top_route_status.pb -INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file VGA_top_timing_summary_routed.rpt -pb VGA_top_timing_summary_routed.pb -rpx VGA_top_timing_summary_routed.rpx -warn_on_violation -INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. -INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs -INFO: [runtcl-4] Executing : report_incremental_reuse -file VGA_top_incremental_reuse_routed.rpt -INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. -INFO: [runtcl-4] Executing : report_clock_utilization -file VGA_top_clock_utilization_routed.rpt -INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file VGA_top_bus_skew_routed.rpt -pb VGA_top_bus_skew_routed.pb -rpx VGA_top_bus_skew_routed.rpx -INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. -INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs -INFO: [Common 17-206] Exiting Vivado at Tue Nov 30 12:44:26 2021... diff --git a/projet-vga.runs/impl_1/VGA_top_4688.backup.vdi b/projet-vga.runs/impl_1/VGA_top_4688.backup.vdi deleted file mode 100644 index 5ebeec0..0000000 --- a/projet-vga.runs/impl_1/VGA_top_4688.backup.vdi +++ /dev/null @@ -1,545 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Tue Nov 23 10:08:25 2021 -# Process ID: 4688 -# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1 -# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace -# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi -# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou -#----------------------------------------------------------- -source VGA_top.tcl -notrace -Command: link_design -top VGA_top -part xc7z010clg400-1 -Design is defaulting to srcset: sources_1 -Design is defaulting to constrset: constrs_1 -INFO: [Project 1-454] Reading design checkpoint 'c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.dcp' for cell 'U0' -INFO: [Netlist 29-17] Analyzing 11 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-479] Netlist was created with Vivado 2018.3 -INFO: [Device 21-403] Loading part xc7z010clg400-1 -INFO: [Project 1-570] Preparing netlist for logic optimization -Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst' -Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst' -Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst' -INFO: [Timing 38-35] Done setting XDC timing constraints. [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57] -INFO: [Timing 38-2] Deriving generated clocks [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57] -get_clocks: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1242.828 ; gain = 551.719 -Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst' -Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc] -Finished Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc] -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1242.828 ; gain = 0.000 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -link_design completed successfully -link_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:24 . Memory (MB): peak = 1242.828 ; gain = 879.852 -Command: opt_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' -Running DRC as a precondition to command opt_design - -Starting DRC Task -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Project 1-461] DRC finished with 0 Errors -INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.501 . Memory (MB): peak = 1242.828 ; gain = 0.000 - -Starting Cache Timing Information Task -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [Timing 38-2] Deriving generated clocks -Ending Cache Timing Information Task | Checksum: b8ea7a4e - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 1260.746 ; gain = 17.918 - -Starting Logic Optimization Task - -Phase 1 Retarget -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -INFO: [Opt 31-49] Retargeted 0 cell(s). -Phase 1 Retarget | Checksum: b8ea7a4e - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1347.707 ; gain = 0.000 -INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells -INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. - -Phase 2 Constant propagation -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Phase 2 Constant propagation | Checksum: b8ea7a4e - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 1347.707 ; gain = 0.000 -INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells - -Phase 3 Sweep -Phase 3 Sweep | Checksum: 69d8ab95 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1347.707 ; gain = 0.000 -INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells - -Phase 4 BUFG optimization -INFO: [Opt 31-194] Inserted BUFG U0/inst/clk_out1_clk_wiz_1_BUFG_inst to drive 0 load(s) on clock net U0/inst/clk_out1_clk_wiz_1_BUFG -INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets -Phase 4 BUFG optimization | Checksum: 13bee9dc1 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1347.707 ; gain = 0.000 -INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. - -Phase 5 Shift Register Optimization -Phase 5 Shift Register Optimization | Checksum: 1a59d5459 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 1347.707 ; gain = 0.000 -INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells - -Phase 6 Post Processing Netlist -Phase 6 Post Processing Netlist | Checksum: 14a40c514 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1347.707 ; gain = 0.000 -INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells -Opt_design Change Summary -========================= - - -------------------------------------------------------------------------------------------------------------------------- -| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | -------------------------------------------------------------------------------------------------------------------------- -| Retarget | 0 | 0 | 1 | -| Constant propagation | 0 | 0 | 0 | -| Sweep | 0 | 0 | 0 | -| BUFG optimization | 0 | 0 | 0 | -| Shift Register Optimization | 0 | 0 | 0 | -| Post Processing Netlist | 0 | 0 | 0 | -------------------------------------------------------------------------------------------------------------------------- - - - -Starting Connectivity Check Task - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1347.707 ; gain = 0.000 -Ending Logic Optimization Task | Checksum: 14dbbd0bc - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.041 . Memory (MB): peak = 1347.707 ; gain = 0.000 - -Starting Power Optimization Task -INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. -Ending Power Optimization Task | Checksum: 14dbbd0bc - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1347.707 ; gain = 0.000 - -Starting Final Cleanup Task -Ending Final Cleanup Task | Checksum: 14dbbd0bc - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1347.707 ; gain = 0.000 - -Starting Netlist Obfuscation Task -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1347.707 ; gain = 0.000 -Ending Netlist Obfuscation Task | Checksum: 14dbbd0bc - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1347.707 ; gain = 0.000 -INFO: [Common 17-83] Releasing license: Implementation -30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -opt_design completed successfully -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1347.707 ; gain = 0.000 -INFO: [Timing 38-480] Writing timing data to binary archive. -Writing placer database... -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1347.707 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1347.707 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_opt.dcp' has been generated. -INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx -Command: report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx -INFO: [IP_Flow 19-1839] IP Catalog is up to date. -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_opted.rpt. -report_drc completed successfully -Command: place_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. -Running DRC as a precondition to command place_design -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. - -Starting Placer Task -INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs - -Phase 1 Placer Initialization - -Phase 1.1 Placer Initialization Netlist Sorting -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1347.707 ; gain = 0.000 -Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fa6d7a79 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1347.707 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1347.707 ; gain = 0.000 - -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device -INFO: [Timing 38-35] Done setting XDC timing constraints. -WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. - - bouton_down_IBUF_inst (IBUF.O) is locked to IOB_X0Y1 - bouton_down_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y1 -Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. -WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. - - bouton_right_IBUF_inst (IBUF.O) is locked to IOB_X0Y36 - bouton_right_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 -Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 12622357c - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.294 . Memory (MB): peak = 1347.707 ; gain = 0.000 - -Phase 1.3 Build Placer Netlist Model -Phase 1.3 Build Placer Netlist Model | Checksum: 1b3b55d5e - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.354 . Memory (MB): peak = 1347.707 ; gain = 0.000 - -Phase 1.4 Constrain Clocks/Macros -Phase 1.4 Constrain Clocks/Macros | Checksum: 1b3b55d5e - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.356 . Memory (MB): peak = 1347.707 ; gain = 0.000 -Phase 1 Placer Initialization | Checksum: 1b3b55d5e - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.356 . Memory (MB): peak = 1347.707 ; gain = 0.000 - -Phase 2 Global Placement - -Phase 2.1 Floorplanning -Phase 2.1 Floorplanning | Checksum: 1f34e0130 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.387 . Memory (MB): peak = 1347.707 ; gain = 0.000 - -Phase 2.2 Physical Synthesis In Placer -INFO: [Physopt 32-65] No nets found for high-fanout optimization. -INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. -INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell -INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed. -INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed. -INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed. -INFO: [Physopt 32-949] No candidate nets found for HD net replication -INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1347.707 ; gain = 0.000 - -Summary of Physical Synthesis Optimizations -============================================ - - ----------------------------------------------------------------------------------------------------------------------------------------- -| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------- -| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| HD Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| Total | 0 | 0 | 0 | 0 | 2 | 00:00:00 | ----------------------------------------------------------------------------------------------------------------------------------------- - - -Phase 2.2 Physical Synthesis In Placer | Checksum: 1f822ab4a - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.899 . Memory (MB): peak = 1347.707 ; gain = 0.000 -Phase 2 Global Placement | Checksum: 17fde1b87 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.910 . Memory (MB): peak = 1347.707 ; gain = 0.000 - -Phase 3 Detail Placement - -Phase 3.1 Commit Multi Column Macros -Phase 3.1 Commit Multi Column Macros | Checksum: 17fde1b87 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.911 . Memory (MB): peak = 1347.707 ; gain = 0.000 - -Phase 3.2 Commit Most Macros & LUTRAMs -Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 258919723 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.945 . Memory (MB): peak = 1347.707 ; gain = 0.000 - -Phase 3.3 Area Swap Optimization -Phase 3.3 Area Swap Optimization | Checksum: 1af65d909 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.947 . Memory (MB): peak = 1347.707 ; gain = 0.000 - -Phase 3.4 Pipeline Register Optimization -Phase 3.4 Pipeline Register Optimization | Checksum: 245deb5d9 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.948 . Memory (MB): peak = 1347.707 ; gain = 0.000 - -Phase 3.5 Small Shape Detail Placement -Phase 3.5 Small Shape Detail Placement | Checksum: 1dab8f54b - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1347.707 ; gain = 0.000 - -Phase 3.6 Re-assign LUT pins -Phase 3.6 Re-assign LUT pins | Checksum: 1e1eee966 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1347.707 ; gain = 0.000 - -Phase 3.7 Pipeline Register Optimization -Phase 3.7 Pipeline Register Optimization | Checksum: f76e0896 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1347.707 ; gain = 0.000 -Phase 3 Detail Placement | Checksum: f76e0896 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1347.707 ; gain = 0.000 - -Phase 4 Post Placement Optimization and Clean-Up - -Phase 4.1 Post Commit Optimization -INFO: [Timing 38-35] Done setting XDC timing constraints. - -Phase 4.1.1 Post Placement Optimization -Post Placement Optimization Initialization | Checksum: 13e7bd2c2 - -Phase 4.1.1.1 BUFG Insertion -INFO: [Place 46-46] BUFG insertion identified 0 candidate nets, 0 success, 0 bufg driver replicated, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason -Phase 4.1.1.1 BUFG Insertion | Checksum: 13e7bd2c2 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1347.707 ; gain = 0.000 -INFO: [Place 30-746] Post Placement Timing Summary WNS=35.645. For the most accurate timing information please run report_timing. -Phase 4.1.1 Post Placement Optimization | Checksum: 15c183492 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1347.707 ; gain = 0.000 -Phase 4.1 Post Commit Optimization | Checksum: 15c183492 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1347.707 ; gain = 0.000 - -Phase 4.2 Post Placement Cleanup -Phase 4.2 Post Placement Cleanup | Checksum: 15c183492 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1347.707 ; gain = 0.000 - -Phase 4.3 Placer Reporting -Phase 4.3 Placer Reporting | Checksum: 15c183492 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1347.707 ; gain = 0.000 - -Phase 4.4 Final Placement Cleanup -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1347.707 ; gain = 0.000 -Phase 4.4 Final Placement Cleanup | Checksum: 17d5ce04d - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1347.707 ; gain = 0.000 -Phase 4 Post Placement Optimization and Clean-Up | Checksum: 17d5ce04d - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1347.707 ; gain = 0.000 -Ending Placer Task | Checksum: d443f812 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1347.707 ; gain = 0.000 -INFO: [Common 17-83] Releasing license: Implementation -57 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. -place_design completed successfully -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1347.707 ; gain = 0.000 -INFO: [Timing 38-480] Writing timing data to binary archive. -Writing placer database... -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.043 . Memory (MB): peak = 1347.707 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1347.707 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_placed.dcp' has been generated. -INFO: [runtcl-4] Executing : report_io -file VGA_top_io_placed.rpt -report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 1347.707 ; gain = 0.000 -INFO: [runtcl-4] Executing : report_utilization -file VGA_top_utilization_placed.rpt -pb VGA_top_utilization_placed.pb -INFO: [runtcl-4] Executing : report_control_sets -verbose -file VGA_top_control_sets_placed.rpt -report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1347.707 ; gain = 0.000 -Command: route_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' -Running DRC as a precondition to command route_design -INFO: [DRC 23-27] Running DRC with 2 threads -WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. -Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. - This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. - - bouton_down_IBUF_inst (IBUF.O) is locked to IOB_X0Y1 - bouton_down_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y1 -WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. -Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. - This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. - - bouton_right_IBUF_inst (IBUF.O) is locked to IOB_X0Y36 - bouton_right_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 2 Warnings -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. - - -Starting Routing Task -INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs -Checksum: PlaceDB: 52480e80 ConstDB: 0 ShapeSum: 81fbe992 RouteDB: 0 - -Phase 1 Build RT Design -Phase 1 Build RT Design | Checksum: fee31c87 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1413.883 ; gain = 66.176 -Post Restoration Checksum: NetGraph: e323ff66 NumContArr: 1bbf1d21 Constraints: 0 Timing: 0 - -Phase 2 Router Initialization - -Phase 2.1 Create Timer -Phase 2.1 Create Timer | Checksum: fee31c87 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1444.188 ; gain = 96.480 - -Phase 2.2 Fix Topology Constraints -Phase 2.2 Fix Topology Constraints | Checksum: fee31c87 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1450.230 ; gain = 102.523 - -Phase 2.3 Pre Route Cleanup -Phase 2.3 Pre Route Cleanup | Checksum: fee31c87 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1450.230 ; gain = 102.523 - Number of Nodes with overlaps = 0 - -Phase 2.4 Update Timing -Phase 2.4 Update Timing | Checksum: 1441c14dd - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1454.770 ; gain = 107.062 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.769 | TNS=0.000 | WHS=-0.258 | THS=-3.023 | - -Phase 2 Router Initialization | Checksum: 173a347ed - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1454.770 ; gain = 107.062 - -Phase 3 Initial Routing -Phase 3 Initial Routing | Checksum: 205eb8b74 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1455.496 ; gain = 107.789 - -Phase 4 Rip-up And Reroute - -Phase 4.1 Global Iteration 0 - Number of Nodes with overlaps = 17 - Number of Nodes with overlaps = 0 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.132 | TNS=0.000 | WHS=N/A | THS=N/A | - -Phase 4.1 Global Iteration 0 | Checksum: 2843d0f71 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1455.496 ; gain = 107.789 -Phase 4 Rip-up And Reroute | Checksum: 2843d0f71 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1455.496 ; gain = 107.789 - -Phase 5 Delay and Skew Optimization - -Phase 5.1 Delay CleanUp -Phase 5.1 Delay CleanUp | Checksum: 2843d0f71 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1455.496 ; gain = 107.789 - -Phase 5.2 Clock Skew Optimization -Phase 5.2 Clock Skew Optimization | Checksum: 2843d0f71 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1455.496 ; gain = 107.789 -Phase 5 Delay and Skew Optimization | Checksum: 2843d0f71 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1455.496 ; gain = 107.789 - -Phase 6 Post Hold Fix - -Phase 6.1 Hold Fix Iter - -Phase 6.1.1 Update Timing -Phase 6.1.1 Update Timing | Checksum: 1adede088 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1455.496 ; gain = 107.789 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.132 | TNS=0.000 | WHS=0.069 | THS=0.000 | - -Phase 6.1 Hold Fix Iter | Checksum: 1adede088 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1455.496 ; gain = 107.789 -Phase 6 Post Hold Fix | Checksum: 1adede088 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1455.496 ; gain = 107.789 - -Phase 7 Route finalize - -Router Utilization Summary - Global Vertical Routing Utilization = 0.0615146 % - Global Horizontal Routing Utilization = 0.0558364 % - Routable Net Status* - *Does not include unroutable nets such as driverless and loadless. - Run report_route_status for detailed report. - Number of Failed Nets = 0 - Number of Unrouted Nets = 0 - Number of Partially Routed Nets = 0 - Number of Node Overlaps = 0 - -Phase 7 Route finalize | Checksum: 2005f65b4 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1455.496 ; gain = 107.789 - -Phase 8 Verifying routed nets - - Verification completed successfully -Phase 8 Verifying routed nets | Checksum: 2005f65b4 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1456.543 ; gain = 108.836 - -Phase 9 Depositing Routes -Phase 9 Depositing Routes | Checksum: 18ba5fe80 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1456.543 ; gain = 108.836 - -Phase 10 Post Router Timing -INFO: [Route 35-57] Estimated Timing Summary | WNS=35.132 | TNS=0.000 | WHS=0.069 | THS=0.000 | - -INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. -Phase 10 Post Router Timing | Checksum: 18ba5fe80 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1456.543 ; gain = 108.836 -INFO: [Route 35-16] Router Completed Successfully - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1456.543 ; gain = 108.836 - -Routing Is Done. -INFO: [Common 17-83] Releasing license: Implementation -74 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. -route_design completed successfully -route_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1456.543 ; gain = 108.836 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1456.543 ; gain = 0.000 -INFO: [Timing 38-480] Writing timing data to binary archive. -Writing placer database... -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.047 . Memory (MB): peak = 1456.957 ; gain = 0.414 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1456.957 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_routed.dcp' has been generated. -INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx -Command: report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx -INFO: [IP_Flow 19-1839] IP Catalog is up to date. -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_routed.rpt. -report_drc completed successfully -INFO: [runtcl-4] Executing : report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx -Command: report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [DRC 23-133] Running Methodology with 2 threads -INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_methodology_drc_routed.rpt. -report_methodology completed successfully -INFO: [runtcl-4] Executing : report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx -Command: report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx -INFO: [Timing 38-35] Done setting XDC timing constraints. -Running Vector-less Activity Propagation... - -Finished Running Vector-less Activity Propagation -86 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. -report_power completed successfully -INFO: [runtcl-4] Executing : report_route_status -file VGA_top_route_status.rpt -pb VGA_top_route_status.pb -INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file VGA_top_timing_summary_routed.rpt -pb VGA_top_timing_summary_routed.pb -rpx VGA_top_timing_summary_routed.rpx -warn_on_violation -INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. -INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs -INFO: [runtcl-4] Executing : report_incremental_reuse -file VGA_top_incremental_reuse_routed.rpt -INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. -INFO: [runtcl-4] Executing : report_clock_utilization -file VGA_top_clock_utilization_routed.rpt -INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file VGA_top_bus_skew_routed.rpt -pb VGA_top_bus_skew_routed.pb -rpx VGA_top_bus_skew_routed.rpx -INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. -INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs -INFO: [Common 17-206] Exiting Vivado at Tue Nov 23 10:09:12 2021... diff --git a/projet-vga.runs/impl_1/VGA_top_4708.backup.vdi b/projet-vga.runs/impl_1/VGA_top_4708.backup.vdi deleted file mode 100644 index 2764adc..0000000 --- a/projet-vga.runs/impl_1/VGA_top_4708.backup.vdi +++ /dev/null @@ -1,523 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Tue Dec 7 12:30:30 2021 -# Process ID: 4708 -# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1 -# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace -# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi -# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou -#----------------------------------------------------------- -source VGA_top.tcl -notrace -Command: link_design -top VGA_top -part xc7z010clg400-1 -Design is defaulting to srcset: sources_1 -Design is defaulting to constrset: constrs_1 -INFO: [Project 1-454] Reading design checkpoint 'c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.dcp' for cell 'U0' -INFO: [Netlist 29-17] Analyzing 11 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-479] Netlist was created with Vivado 2018.3 -INFO: [Device 21-403] Loading part xc7z010clg400-1 -INFO: [Project 1-570] Preparing netlist for logic optimization -Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst' -Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst' -Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst' -INFO: [Timing 38-35] Done setting XDC timing constraints. [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57] -INFO: [Timing 38-2] Deriving generated clocks [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57] -get_clocks: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1242.105 ; gain = 551.648 -Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst' -Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc] -Finished Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc] -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1242.105 ; gain = 0.000 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -link_design completed successfully -link_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:16 . Memory (MB): peak = 1242.105 ; gain = 878.844 -Command: opt_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' -Running DRC as a precondition to command opt_design - -Starting DRC Task -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Project 1-461] DRC finished with 0 Errors -INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.511 . Memory (MB): peak = 1242.105 ; gain = 0.000 - -Starting Cache Timing Information Task -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [Timing 38-2] Deriving generated clocks -Ending Cache Timing Information Task | Checksum: d2ac4cf6 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1259.926 ; gain = 17.820 - -Starting Logic Optimization Task - -Phase 1 Retarget -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -INFO: [Opt 31-49] Retargeted 0 cell(s). -Phase 1 Retarget | Checksum: 1f756781a - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1343.621 ; gain = 0.000 -INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 1 cells -INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. - -Phase 2 Constant propagation -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Phase 2 Constant propagation | Checksum: 1f756781a - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1343.621 ; gain = 0.000 -INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells - -Phase 3 Sweep -Phase 3 Sweep | Checksum: 20f92b0fa - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 1343.621 ; gain = 0.000 -INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells - -Phase 4 BUFG optimization -INFO: [Opt 31-194] Inserted BUFG U0/inst/clk_out1_clk_wiz_1_BUFG_inst to drive 0 load(s) on clock net U0/inst/clk_out1_clk_wiz_1_BUFG -INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets -Phase 4 BUFG optimization | Checksum: 19f2c89a4 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1343.621 ; gain = 0.000 -INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. - -Phase 5 Shift Register Optimization -Phase 5 Shift Register Optimization | Checksum: 948878b4 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.036 . Memory (MB): peak = 1343.621 ; gain = 0.000 -INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells - -Phase 6 Post Processing Netlist -Phase 6 Post Processing Netlist | Checksum: 10d0c29d4 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.037 . Memory (MB): peak = 1343.621 ; gain = 0.000 -INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells -Opt_design Change Summary -========================= - - -------------------------------------------------------------------------------------------------------------------------- -| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | -------------------------------------------------------------------------------------------------------------------------- -| Retarget | 0 | 1 | 1 | -| Constant propagation | 0 | 0 | 0 | -| Sweep | 0 | 0 | 0 | -| BUFG optimization | 0 | 0 | 0 | -| Shift Register Optimization | 0 | 0 | 0 | -| Post Processing Netlist | 0 | 0 | 0 | -------------------------------------------------------------------------------------------------------------------------- - - - -Starting Connectivity Check Task - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1343.621 ; gain = 0.000 -Ending Logic Optimization Task | Checksum: 1063f0394 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1343.621 ; gain = 0.000 - -Starting Power Optimization Task -INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. -Ending Power Optimization Task | Checksum: 1063f0394 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1343.621 ; gain = 0.000 - -Starting Final Cleanup Task -Ending Final Cleanup Task | Checksum: 1063f0394 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1343.621 ; gain = 0.000 - -Starting Netlist Obfuscation Task -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1343.621 ; gain = 0.000 -Ending Netlist Obfuscation Task | Checksum: 1063f0394 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1343.621 ; gain = 0.000 -INFO: [Common 17-83] Releasing license: Implementation -30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -opt_design completed successfully -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1343.621 ; gain = 0.000 -INFO: [Timing 38-480] Writing timing data to binary archive. -Writing placer database... -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1343.621 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1343.621 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_opt.dcp' has been generated. -INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx -Command: report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx -INFO: [IP_Flow 19-1839] IP Catalog is up to date. -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_opted.rpt. -report_drc completed successfully -Command: place_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. -Running DRC as a precondition to command place_design -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. - -Starting Placer Task -INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs - -Phase 1 Placer Initialization - -Phase 1.1 Placer Initialization Netlist Sorting -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1343.621 ; gain = 0.000 -Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 73a34972 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1343.621 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1343.621 ; gain = 0.000 - -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device -INFO: [Timing 38-35] Done setting XDC timing constraints. -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1183e7dd3 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.259 . Memory (MB): peak = 1343.621 ; gain = 0.000 - -Phase 1.3 Build Placer Netlist Model -Phase 1.3 Build Placer Netlist Model | Checksum: 1d9a96167 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.330 . Memory (MB): peak = 1343.621 ; gain = 0.000 - -Phase 1.4 Constrain Clocks/Macros -Phase 1.4 Constrain Clocks/Macros | Checksum: 1d9a96167 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.331 . Memory (MB): peak = 1343.621 ; gain = 0.000 -Phase 1 Placer Initialization | Checksum: 1d9a96167 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.331 . Memory (MB): peak = 1343.621 ; gain = 0.000 - -Phase 2 Global Placement - -Phase 2.1 Floorplanning -Phase 2.1 Floorplanning | Checksum: 207239471 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.384 . Memory (MB): peak = 1343.621 ; gain = 0.000 - -Phase 2.2 Physical Synthesis In Placer -INFO: [Physopt 32-65] No nets found for high-fanout optimization. -INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. -INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell -INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed. -INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed. -INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed. -INFO: [Physopt 32-949] No candidate nets found for HD net replication -INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1343.621 ; gain = 0.000 - -Summary of Physical Synthesis Optimizations -============================================ - - ----------------------------------------------------------------------------------------------------------------------------------------- -| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------- -| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| HD Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| Total | 0 | 0 | 0 | 0 | 2 | 00:00:00 | ----------------------------------------------------------------------------------------------------------------------------------------- - - -Phase 2.2 Physical Synthesis In Placer | Checksum: 1ec0f74d9 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1343.621 ; gain = 0.000 -Phase 2 Global Placement | Checksum: 1db1d9ae8 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1343.621 ; gain = 0.000 - -Phase 3 Detail Placement - -Phase 3.1 Commit Multi Column Macros -Phase 3.1 Commit Multi Column Macros | Checksum: 1db1d9ae8 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1343.621 ; gain = 0.000 - -Phase 3.2 Commit Most Macros & LUTRAMs -Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1b8be6344 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1343.621 ; gain = 0.000 - -Phase 3.3 Area Swap Optimization -Phase 3.3 Area Swap Optimization | Checksum: 24618d2d2 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1343.621 ; gain = 0.000 - -Phase 3.4 Pipeline Register Optimization -Phase 3.4 Pipeline Register Optimization | Checksum: 24618d2d2 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1343.621 ; gain = 0.000 - -Phase 3.5 Small Shape Detail Placement -Phase 3.5 Small Shape Detail Placement | Checksum: f3458c6a - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1343.621 ; gain = 0.000 - -Phase 3.6 Re-assign LUT pins -Phase 3.6 Re-assign LUT pins | Checksum: 1248ba3b4 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1343.621 ; gain = 0.000 - -Phase 3.7 Pipeline Register Optimization -Phase 3.7 Pipeline Register Optimization | Checksum: 1248ba3b4 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1343.621 ; gain = 0.000 -Phase 3 Detail Placement | Checksum: 1248ba3b4 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1343.621 ; gain = 0.000 - -Phase 4 Post Placement Optimization and Clean-Up - -Phase 4.1 Post Commit Optimization -INFO: [Timing 38-35] Done setting XDC timing constraints. - -Phase 4.1.1 Post Placement Optimization -Post Placement Optimization Initialization | Checksum: 1635a43ad - -Phase 4.1.1.1 BUFG Insertion -INFO: [Place 46-46] BUFG insertion identified 0 candidate nets, 0 success, 0 bufg driver replicated, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason -Phase 4.1.1.1 BUFG Insertion | Checksum: 1635a43ad - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1343.621 ; gain = 0.000 -INFO: [Place 30-746] Post Placement Timing Summary WNS=36.020. For the most accurate timing information please run report_timing. -Phase 4.1.1 Post Placement Optimization | Checksum: 23bd24a0c - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1343.621 ; gain = 0.000 -Phase 4.1 Post Commit Optimization | Checksum: 23bd24a0c - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1343.621 ; gain = 0.000 - -Phase 4.2 Post Placement Cleanup -Phase 4.2 Post Placement Cleanup | Checksum: 23bd24a0c - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1343.621 ; gain = 0.000 - -Phase 4.3 Placer Reporting -Phase 4.3 Placer Reporting | Checksum: 23bd24a0c - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1343.621 ; gain = 0.000 - -Phase 4.4 Final Placement Cleanup -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1343.621 ; gain = 0.000 -Phase 4.4 Final Placement Cleanup | Checksum: 219552bc9 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1343.621 ; gain = 0.000 -Phase 4 Post Placement Optimization and Clean-Up | Checksum: 219552bc9 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1343.621 ; gain = 0.000 -Ending Placer Task | Checksum: 125980005 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1343.621 ; gain = 0.000 -INFO: [Common 17-83] Releasing license: Implementation -57 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -place_design completed successfully -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1343.621 ; gain = 0.000 -INFO: [Timing 38-480] Writing timing data to binary archive. -Writing placer database... -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.044 . Memory (MB): peak = 1343.621 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1343.621 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_placed.dcp' has been generated. -INFO: [runtcl-4] Executing : report_io -file VGA_top_io_placed.rpt -report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1343.621 ; gain = 0.000 -INFO: [runtcl-4] Executing : report_utilization -file VGA_top_utilization_placed.rpt -pb VGA_top_utilization_placed.pb -INFO: [runtcl-4] Executing : report_control_sets -verbose -file VGA_top_control_sets_placed.rpt -report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1343.621 ; gain = 0.000 -Command: route_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' -Running DRC as a precondition to command route_design -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. - - -Starting Routing Task -INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs -Checksum: PlaceDB: af6487ab ConstDB: 0 ShapeSum: 7633785a RouteDB: 0 - -Phase 1 Build RT Design -Phase 1 Build RT Design | Checksum: c740a96f - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1409.477 ; gain = 65.855 -Post Restoration Checksum: NetGraph: 9566862e NumContArr: 31da2341 Constraints: 0 Timing: 0 - -Phase 2 Router Initialization - -Phase 2.1 Create Timer -Phase 2.1 Create Timer | Checksum: c740a96f - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1439.797 ; gain = 96.176 - -Phase 2.2 Fix Topology Constraints -Phase 2.2 Fix Topology Constraints | Checksum: c740a96f - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1445.828 ; gain = 102.207 - -Phase 2.3 Pre Route Cleanup -Phase 2.3 Pre Route Cleanup | Checksum: c740a96f - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1445.828 ; gain = 102.207 - Number of Nodes with overlaps = 0 - -Phase 2.4 Update Timing -Phase 2.4 Update Timing | Checksum: e75bf5ee - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1448.480 ; gain = 104.859 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.988 | TNS=0.000 | WHS=-0.304 | THS=-3.628 | - -Phase 2 Router Initialization | Checksum: 43607781 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1448.480 ; gain = 104.859 - -Phase 3 Initial Routing -Phase 3 Initial Routing | Checksum: 12c466190 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1448.480 ; gain = 104.859 - -Phase 4 Rip-up And Reroute - -Phase 4.1 Global Iteration 0 - Number of Nodes with overlaps = 10 - Number of Nodes with overlaps = 0 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.445 | TNS=0.000 | WHS=N/A | THS=N/A | - -Phase 4.1 Global Iteration 0 | Checksum: 210804e73 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1448.480 ; gain = 104.859 -Phase 4 Rip-up And Reroute | Checksum: 210804e73 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1448.480 ; gain = 104.859 - -Phase 5 Delay and Skew Optimization - -Phase 5.1 Delay CleanUp -Phase 5.1 Delay CleanUp | Checksum: 210804e73 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1448.480 ; gain = 104.859 - -Phase 5.2 Clock Skew Optimization -Phase 5.2 Clock Skew Optimization | Checksum: 210804e73 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1448.480 ; gain = 104.859 -Phase 5 Delay and Skew Optimization | Checksum: 210804e73 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1448.480 ; gain = 104.859 - -Phase 6 Post Hold Fix - -Phase 6.1 Hold Fix Iter - -Phase 6.1.1 Update Timing -Phase 6.1.1 Update Timing | Checksum: 14a89ec0d - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1448.480 ; gain = 104.859 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.560 | TNS=0.000 | WHS=0.076 | THS=0.000 | - -Phase 6.1 Hold Fix Iter | Checksum: 14a89ec0d - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1448.480 ; gain = 104.859 -Phase 6 Post Hold Fix | Checksum: 14a89ec0d - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1448.480 ; gain = 104.859 - -Phase 7 Route finalize - -Router Utilization Summary - Global Vertical Routing Utilization = 0.0451858 % - Global Horizontal Routing Utilization = 0.0363051 % - Routable Net Status* - *Does not include unroutable nets such as driverless and loadless. - Run report_route_status for detailed report. - Number of Failed Nets = 0 - Number of Unrouted Nets = 0 - Number of Partially Routed Nets = 0 - Number of Node Overlaps = 0 - -Phase 7 Route finalize | Checksum: 2224be1cd - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1448.480 ; gain = 104.859 - -Phase 8 Verifying routed nets - - Verification completed successfully -Phase 8 Verifying routed nets | Checksum: 2224be1cd - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1450.207 ; gain = 106.586 - -Phase 9 Depositing Routes -Phase 9 Depositing Routes | Checksum: 180a9d30f - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1450.207 ; gain = 106.586 - -Phase 10 Post Router Timing -INFO: [Route 35-57] Estimated Timing Summary | WNS=35.560 | TNS=0.000 | WHS=0.076 | THS=0.000 | - -INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. -Phase 10 Post Router Timing | Checksum: 180a9d30f - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1450.207 ; gain = 106.586 -INFO: [Route 35-16] Router Completed Successfully - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1450.207 ; gain = 106.586 - -Routing Is Done. -INFO: [Common 17-83] Releasing license: Implementation -74 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -route_design completed successfully -route_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:22 . Memory (MB): peak = 1450.207 ; gain = 106.586 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1450.207 ; gain = 0.000 -INFO: [Timing 38-480] Writing timing data to binary archive. -Writing placer database... -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.045 . Memory (MB): peak = 1450.629 ; gain = 0.422 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1450.629 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_routed.dcp' has been generated. -INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx -Command: report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx -INFO: [IP_Flow 19-1839] IP Catalog is up to date. -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_routed.rpt. -report_drc completed successfully -INFO: [runtcl-4] Executing : report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx -Command: report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [DRC 23-133] Running Methodology with 2 threads -INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_methodology_drc_routed.rpt. -report_methodology completed successfully -INFO: [runtcl-4] Executing : report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx -Command: report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx -INFO: [Timing 38-35] Done setting XDC timing constraints. -Running Vector-less Activity Propagation... - -Finished Running Vector-less Activity Propagation -86 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -report_power completed successfully -INFO: [runtcl-4] Executing : report_route_status -file VGA_top_route_status.rpt -pb VGA_top_route_status.pb -INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file VGA_top_timing_summary_routed.rpt -pb VGA_top_timing_summary_routed.pb -rpx VGA_top_timing_summary_routed.rpx -warn_on_violation -INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. -INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs -INFO: [runtcl-4] Executing : report_incremental_reuse -file VGA_top_incremental_reuse_routed.rpt -INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. -INFO: [runtcl-4] Executing : report_clock_utilization -file VGA_top_clock_utilization_routed.rpt -INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file VGA_top_bus_skew_routed.rpt -pb VGA_top_bus_skew_routed.pb -rpx VGA_top_bus_skew_routed.rpx -INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. -INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs -INFO: [Common 17-206] Exiting Vivado at Tue Dec 7 12:31:19 2021... diff --git a/projet-vga.runs/impl_1/VGA_top_4856.backup.vdi b/projet-vga.runs/impl_1/VGA_top_4856.backup.vdi deleted file mode 100644 index 8b0f10c..0000000 --- a/projet-vga.runs/impl_1/VGA_top_4856.backup.vdi +++ /dev/null @@ -1,523 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Tue Dec 7 12:42:58 2021 -# Process ID: 4856 -# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1 -# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace -# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi -# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou -#----------------------------------------------------------- -source VGA_top.tcl -notrace -Command: link_design -top VGA_top -part xc7z010clg400-1 -Design is defaulting to srcset: sources_1 -Design is defaulting to constrset: constrs_1 -INFO: [Project 1-454] Reading design checkpoint 'c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.dcp' for cell 'U0' -INFO: [Netlist 29-17] Analyzing 35 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-479] Netlist was created with Vivado 2018.3 -INFO: [Device 21-403] Loading part xc7z010clg400-1 -INFO: [Project 1-570] Preparing netlist for logic optimization -Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst' -Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst' -Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst' -INFO: [Timing 38-35] Done setting XDC timing constraints. [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57] -INFO: [Timing 38-2] Deriving generated clocks [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57] -get_clocks: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1248.586 ; gain = 558.375 -Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst' -Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc] -Finished Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc] -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1248.586 ; gain = 0.000 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -link_design completed successfully -link_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:16 . Memory (MB): peak = 1248.586 ; gain = 885.598 -Command: opt_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' -Running DRC as a precondition to command opt_design - -Starting DRC Task -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Project 1-461] DRC finished with 0 Errors -INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.499 . Memory (MB): peak = 1248.586 ; gain = 0.000 - -Starting Cache Timing Information Task -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [Timing 38-2] Deriving generated clocks -Ending Cache Timing Information Task | Checksum: 20ae1d4cd - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1265.152 ; gain = 16.566 - -Starting Logic Optimization Task - -Phase 1 Retarget -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -INFO: [Opt 31-49] Retargeted 0 cell(s). -Phase 1 Retarget | Checksum: ddde5939 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 1351.098 ; gain = 0.000 -INFO: [Opt 31-389] Phase Retarget created 4 cells and removed 4 cells -INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. - -Phase 2 Constant propagation -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Phase 2 Constant propagation | Checksum: ddde5939 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1351.098 ; gain = 0.000 -INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells - -Phase 3 Sweep -Phase 3 Sweep | Checksum: fec5e707 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 1351.098 ; gain = 0.000 -INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells - -Phase 4 BUFG optimization -INFO: [Opt 31-194] Inserted BUFG U0/inst/clk_out1_clk_wiz_1_BUFG_inst to drive 0 load(s) on clock net U0/inst/clk_out1_clk_wiz_1_BUFG -INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets -Phase 4 BUFG optimization | Checksum: 137e6b9d1 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1351.098 ; gain = 0.000 -INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. - -Phase 5 Shift Register Optimization -Phase 5 Shift Register Optimization | Checksum: 12c29fba6 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.054 . Memory (MB): peak = 1351.098 ; gain = 0.000 -INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells - -Phase 6 Post Processing Netlist -Phase 6 Post Processing Netlist | Checksum: 10c49128f - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.055 . Memory (MB): peak = 1351.098 ; gain = 0.000 -INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells -Opt_design Change Summary -========================= - - -------------------------------------------------------------------------------------------------------------------------- -| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | -------------------------------------------------------------------------------------------------------------------------- -| Retarget | 4 | 4 | 1 | -| Constant propagation | 0 | 0 | 0 | -| Sweep | 0 | 0 | 0 | -| BUFG optimization | 0 | 0 | 0 | -| Shift Register Optimization | 0 | 0 | 0 | -| Post Processing Netlist | 0 | 0 | 0 | -------------------------------------------------------------------------------------------------------------------------- - - - -Starting Connectivity Check Task - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1351.098 ; gain = 0.000 -Ending Logic Optimization Task | Checksum: e54fefee - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.057 . Memory (MB): peak = 1351.098 ; gain = 0.000 - -Starting Power Optimization Task -INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. -Ending Power Optimization Task | Checksum: e54fefee - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1351.098 ; gain = 0.000 - -Starting Final Cleanup Task -Ending Final Cleanup Task | Checksum: e54fefee - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000 - -Starting Netlist Obfuscation Task -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000 -Ending Netlist Obfuscation Task | Checksum: e54fefee - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000 -INFO: [Common 17-83] Releasing license: Implementation -30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -opt_design completed successfully -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000 -INFO: [Timing 38-480] Writing timing data to binary archive. -Writing placer database... -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1351.098 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_opt.dcp' has been generated. -INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx -Command: report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx -INFO: [IP_Flow 19-1839] IP Catalog is up to date. -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_opted.rpt. -report_drc completed successfully -Command: place_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. -Running DRC as a precondition to command place_design -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. - -Starting Placer Task -INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs - -Phase 1 Placer Initialization - -Phase 1.1 Placer Initialization Netlist Sorting -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000 -Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 4ed236ad - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1351.098 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000 - -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device -INFO: [Timing 38-35] Done setting XDC timing constraints. -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1a1c16c9c - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.262 . Memory (MB): peak = 1351.098 ; gain = 0.000 - -Phase 1.3 Build Placer Netlist Model -Phase 1.3 Build Placer Netlist Model | Checksum: 2939760d0 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.351 . Memory (MB): peak = 1351.098 ; gain = 0.000 - -Phase 1.4 Constrain Clocks/Macros -Phase 1.4 Constrain Clocks/Macros | Checksum: 2939760d0 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.353 . Memory (MB): peak = 1351.098 ; gain = 0.000 -Phase 1 Placer Initialization | Checksum: 2939760d0 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.353 . Memory (MB): peak = 1351.098 ; gain = 0.000 - -Phase 2 Global Placement - -Phase 2.1 Floorplanning -Phase 2.1 Floorplanning | Checksum: 28231f14d - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.397 . Memory (MB): peak = 1351.098 ; gain = 0.000 - -Phase 2.2 Physical Synthesis In Placer -INFO: [Physopt 32-65] No nets found for high-fanout optimization. -INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. -INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell -INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed. -INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed. -INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed. -INFO: [Physopt 32-949] No candidate nets found for HD net replication -INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1351.098 ; gain = 0.000 - -Summary of Physical Synthesis Optimizations -============================================ - - ----------------------------------------------------------------------------------------------------------------------------------------- -| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------- -| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| HD Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| Total | 0 | 0 | 0 | 0 | 2 | 00:00:00 | ----------------------------------------------------------------------------------------------------------------------------------------- - - -Phase 2.2 Physical Synthesis In Placer | Checksum: 22348ffd6 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000 -Phase 2 Global Placement | Checksum: 2038a7242 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000 - -Phase 3 Detail Placement - -Phase 3.1 Commit Multi Column Macros -Phase 3.1 Commit Multi Column Macros | Checksum: 2038a7242 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000 - -Phase 3.2 Commit Most Macros & LUTRAMs -Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 2c58c3354 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000 - -Phase 3.3 Area Swap Optimization -Phase 3.3 Area Swap Optimization | Checksum: 279aeb7b4 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000 - -Phase 3.4 Pipeline Register Optimization -Phase 3.4 Pipeline Register Optimization | Checksum: 279aeb7b4 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000 - -Phase 3.5 Small Shape Detail Placement -Phase 3.5 Small Shape Detail Placement | Checksum: 1e0aaeea1 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000 - -Phase 3.6 Re-assign LUT pins -Phase 3.6 Re-assign LUT pins | Checksum: 2d338840d - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000 - -Phase 3.7 Pipeline Register Optimization -Phase 3.7 Pipeline Register Optimization | Checksum: 2d338840d - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000 -Phase 3 Detail Placement | Checksum: 2d338840d - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000 - -Phase 4 Post Placement Optimization and Clean-Up - -Phase 4.1 Post Commit Optimization -INFO: [Timing 38-35] Done setting XDC timing constraints. - -Phase 4.1.1 Post Placement Optimization -Post Placement Optimization Initialization | Checksum: 15c68dcd4 - -Phase 4.1.1.1 BUFG Insertion -INFO: [Place 46-46] BUFG insertion identified 0 candidate nets, 0 success, 0 bufg driver replicated, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason -Phase 4.1.1.1 BUFG Insertion | Checksum: 15c68dcd4 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1351.098 ; gain = 0.000 -INFO: [Place 30-746] Post Placement Timing Summary WNS=35.245. For the most accurate timing information please run report_timing. -Phase 4.1.1 Post Placement Optimization | Checksum: 142e419cd - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1351.098 ; gain = 0.000 -Phase 4.1 Post Commit Optimization | Checksum: 142e419cd - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1351.098 ; gain = 0.000 - -Phase 4.2 Post Placement Cleanup -Phase 4.2 Post Placement Cleanup | Checksum: 142e419cd - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1351.098 ; gain = 0.000 - -Phase 4.3 Placer Reporting -Phase 4.3 Placer Reporting | Checksum: 142e419cd - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1351.098 ; gain = 0.000 - -Phase 4.4 Final Placement Cleanup -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000 -Phase 4.4 Final Placement Cleanup | Checksum: 20695260e - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1351.098 ; gain = 0.000 -Phase 4 Post Placement Optimization and Clean-Up | Checksum: 20695260e - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1351.098 ; gain = 0.000 -Ending Placer Task | Checksum: 1f2b3c1b8 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1351.098 ; gain = 0.000 -INFO: [Common 17-83] Releasing license: Implementation -57 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -place_design completed successfully -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000 -INFO: [Timing 38-480] Writing timing data to binary archive. -Writing placer database... -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.050 . Memory (MB): peak = 1351.098 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_placed.dcp' has been generated. -INFO: [runtcl-4] Executing : report_io -file VGA_top_io_placed.rpt -report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1351.098 ; gain = 0.000 -INFO: [runtcl-4] Executing : report_utilization -file VGA_top_utilization_placed.rpt -pb VGA_top_utilization_placed.pb -INFO: [runtcl-4] Executing : report_control_sets -verbose -file VGA_top_control_sets_placed.rpt -report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1351.098 ; gain = 0.000 -Command: route_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' -Running DRC as a precondition to command route_design -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. - - -Starting Routing Task -INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs -Checksum: PlaceDB: f9e7c0c6 ConstDB: 0 ShapeSum: f8cc00f2 RouteDB: 0 - -Phase 1 Build RT Design -Phase 1 Build RT Design | Checksum: 9a64d846 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1417.348 ; gain = 66.250 -Post Restoration Checksum: NetGraph: 7c5b36de NumContArr: 1e09a168 Constraints: 0 Timing: 0 - -Phase 2 Router Initialization - -Phase 2.1 Create Timer -Phase 2.1 Create Timer | Checksum: 9a64d846 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1449.676 ; gain = 98.578 - -Phase 2.2 Fix Topology Constraints -Phase 2.2 Fix Topology Constraints | Checksum: 9a64d846 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1455.699 ; gain = 104.602 - -Phase 2.3 Pre Route Cleanup -Phase 2.3 Pre Route Cleanup | Checksum: 9a64d846 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1455.699 ; gain = 104.602 - Number of Nodes with overlaps = 0 - -Phase 2.4 Update Timing -Phase 2.4 Update Timing | Checksum: 82bae049 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1460.445 ; gain = 109.348 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.391 | TNS=0.000 | WHS=-0.239 | THS=-2.915 | - -Phase 2 Router Initialization | Checksum: cf693307 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1460.445 ; gain = 109.348 - -Phase 3 Initial Routing -Phase 3 Initial Routing | Checksum: 16fee48da - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348 - -Phase 4 Rip-up And Reroute - -Phase 4.1 Global Iteration 0 - Number of Nodes with overlaps = 36 - Number of Nodes with overlaps = 0 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=33.088 | TNS=0.000 | WHS=N/A | THS=N/A | - -Phase 4.1 Global Iteration 0 | Checksum: 1c93f85f6 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348 -Phase 4 Rip-up And Reroute | Checksum: 1c93f85f6 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348 - -Phase 5 Delay and Skew Optimization - -Phase 5.1 Delay CleanUp -Phase 5.1 Delay CleanUp | Checksum: 1c93f85f6 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348 - -Phase 5.2 Clock Skew Optimization -Phase 5.2 Clock Skew Optimization | Checksum: 1c93f85f6 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348 -Phase 5 Delay and Skew Optimization | Checksum: 1c93f85f6 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348 - -Phase 6 Post Hold Fix - -Phase 6.1 Hold Fix Iter - -Phase 6.1.1 Update Timing -Phase 6.1.1 Update Timing | Checksum: 144941f51 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=33.241 | TNS=0.000 | WHS=0.083 | THS=0.000 | - -Phase 6.1 Hold Fix Iter | Checksum: 144941f51 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348 -Phase 6 Post Hold Fix | Checksum: 144941f51 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348 - -Phase 7 Route finalize - -Router Utilization Summary - Global Vertical Routing Utilization = 0.0881194 % - Global Horizontal Routing Utilization = 0.100414 % - Routable Net Status* - *Does not include unroutable nets such as driverless and loadless. - Run report_route_status for detailed report. - Number of Failed Nets = 0 - Number of Unrouted Nets = 0 - Number of Partially Routed Nets = 0 - Number of Node Overlaps = 0 - -Phase 7 Route finalize | Checksum: 19cea99c1 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348 - -Phase 8 Verifying routed nets - - Verification completed successfully -Phase 8 Verifying routed nets | Checksum: 19cea99c1 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1461.477 ; gain = 110.379 - -Phase 9 Depositing Routes -Phase 9 Depositing Routes | Checksum: 17f26a4e0 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1461.477 ; gain = 110.379 - -Phase 10 Post Router Timing -INFO: [Route 35-57] Estimated Timing Summary | WNS=33.241 | TNS=0.000 | WHS=0.083 | THS=0.000 | - -INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. -Phase 10 Post Router Timing | Checksum: 17f26a4e0 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1461.477 ; gain = 110.379 -INFO: [Route 35-16] Router Completed Successfully - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1461.477 ; gain = 110.379 - -Routing Is Done. -INFO: [Common 17-83] Releasing license: Implementation -74 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -route_design completed successfully -route_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:22 . Memory (MB): peak = 1461.477 ; gain = 110.379 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1461.477 ; gain = 0.000 -INFO: [Timing 38-480] Writing timing data to binary archive. -Writing placer database... -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.054 . Memory (MB): peak = 1461.910 ; gain = 0.434 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1461.910 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_routed.dcp' has been generated. -INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx -Command: report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx -INFO: [IP_Flow 19-1839] IP Catalog is up to date. -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_routed.rpt. -report_drc completed successfully -INFO: [runtcl-4] Executing : report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx -Command: report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [DRC 23-133] Running Methodology with 2 threads -INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_methodology_drc_routed.rpt. -report_methodology completed successfully -INFO: [runtcl-4] Executing : report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx -Command: report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx -INFO: [Timing 38-35] Done setting XDC timing constraints. -Running Vector-less Activity Propagation... - -Finished Running Vector-less Activity Propagation -86 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -report_power completed successfully -INFO: [runtcl-4] Executing : report_route_status -file VGA_top_route_status.rpt -pb VGA_top_route_status.pb -INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file VGA_top_timing_summary_routed.rpt -pb VGA_top_timing_summary_routed.pb -rpx VGA_top_timing_summary_routed.rpx -warn_on_violation -INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. -INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs -INFO: [runtcl-4] Executing : report_incremental_reuse -file VGA_top_incremental_reuse_routed.rpt -INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. -INFO: [runtcl-4] Executing : report_clock_utilization -file VGA_top_clock_utilization_routed.rpt -INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file VGA_top_bus_skew_routed.rpt -pb VGA_top_bus_skew_routed.pb -rpx VGA_top_bus_skew_routed.rpx -INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. -INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs -INFO: [Common 17-206] Exiting Vivado at Tue Dec 7 12:43:48 2021... diff --git a/projet-vga.runs/impl_1/VGA_top_6484.backup.vdi b/projet-vga.runs/impl_1/VGA_top_6484.backup.vdi deleted file mode 100644 index 2c0db9a..0000000 --- a/projet-vga.runs/impl_1/VGA_top_6484.backup.vdi +++ /dev/null @@ -1,523 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Tue Dec 7 12:35:58 2021 -# Process ID: 6484 -# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1 -# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace -# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi -# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou -#----------------------------------------------------------- -source VGA_top.tcl -notrace -Command: link_design -top VGA_top -part xc7z010clg400-1 -Design is defaulting to srcset: sources_1 -Design is defaulting to constrset: constrs_1 -INFO: [Project 1-454] Reading design checkpoint 'c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.dcp' for cell 'U0' -INFO: [Netlist 29-17] Analyzing 11 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-479] Netlist was created with Vivado 2018.3 -INFO: [Device 21-403] Loading part xc7z010clg400-1 -INFO: [Project 1-570] Preparing netlist for logic optimization -Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst' -Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst' -Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst' -INFO: [Timing 38-35] Done setting XDC timing constraints. [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57] -INFO: [Timing 38-2] Deriving generated clocks [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57] -get_clocks: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1242.344 ; gain = 551.617 -Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst' -Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc] -Finished Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc] -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1242.344 ; gain = 0.000 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -link_design completed successfully -link_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:16 . Memory (MB): peak = 1242.344 ; gain = 879.055 -Command: opt_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' -Running DRC as a precondition to command opt_design - -Starting DRC Task -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Project 1-461] DRC finished with 0 Errors -INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.520 . Memory (MB): peak = 1242.344 ; gain = 0.000 - -Starting Cache Timing Information Task -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [Timing 38-2] Deriving generated clocks -Ending Cache Timing Information Task | Checksum: 110b259ca - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1259.379 ; gain = 17.035 - -Starting Logic Optimization Task - -Phase 1 Retarget -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -INFO: [Opt 31-49] Retargeted 0 cell(s). -Phase 1 Retarget | Checksum: 84bc87f3 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1342.969 ; gain = 0.000 -INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 1 cells -INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. - -Phase 2 Constant propagation -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Phase 2 Constant propagation | Checksum: 84bc87f3 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1342.969 ; gain = 0.000 -INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells - -Phase 3 Sweep -Phase 3 Sweep | Checksum: b8cdff51 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 1342.969 ; gain = 0.000 -INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells - -Phase 4 BUFG optimization -INFO: [Opt 31-194] Inserted BUFG U0/inst/clk_out1_clk_wiz_1_BUFG_inst to drive 0 load(s) on clock net U0/inst/clk_out1_clk_wiz_1_BUFG -INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets -Phase 4 BUFG optimization | Checksum: 37ad6b15 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1342.969 ; gain = 0.000 -INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. - -Phase 5 Shift Register Optimization -Phase 5 Shift Register Optimization | Checksum: e3a97acd - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.036 . Memory (MB): peak = 1342.969 ; gain = 0.000 -INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells - -Phase 6 Post Processing Netlist -Phase 6 Post Processing Netlist | Checksum: b120801e - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.037 . Memory (MB): peak = 1342.969 ; gain = 0.000 -INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells -Opt_design Change Summary -========================= - - -------------------------------------------------------------------------------------------------------------------------- -| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | -------------------------------------------------------------------------------------------------------------------------- -| Retarget | 0 | 1 | 1 | -| Constant propagation | 0 | 0 | 0 | -| Sweep | 0 | 0 | 0 | -| BUFG optimization | 0 | 0 | 0 | -| Shift Register Optimization | 0 | 0 | 0 | -| Post Processing Netlist | 0 | 0 | 0 | -------------------------------------------------------------------------------------------------------------------------- - - - -Starting Connectivity Check Task - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1342.969 ; gain = 0.000 -Ending Logic Optimization Task | Checksum: 8a9a4abc - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1342.969 ; gain = 0.000 - -Starting Power Optimization Task -INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. -Ending Power Optimization Task | Checksum: 8a9a4abc - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1342.969 ; gain = 0.000 - -Starting Final Cleanup Task -Ending Final Cleanup Task | Checksum: 8a9a4abc - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.969 ; gain = 0.000 - -Starting Netlist Obfuscation Task -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.969 ; gain = 0.000 -Ending Netlist Obfuscation Task | Checksum: 8a9a4abc - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.969 ; gain = 0.000 -INFO: [Common 17-83] Releasing license: Implementation -30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -opt_design completed successfully -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.969 ; gain = 0.000 -INFO: [Timing 38-480] Writing timing data to binary archive. -Writing placer database... -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1342.969 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.969 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_opt.dcp' has been generated. -INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx -Command: report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx -INFO: [IP_Flow 19-1839] IP Catalog is up to date. -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_opted.rpt. -report_drc completed successfully -Command: place_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. -Running DRC as a precondition to command place_design -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. - -Starting Placer Task -INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs - -Phase 1 Placer Initialization - -Phase 1.1 Placer Initialization Netlist Sorting -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.969 ; gain = 0.000 -Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 5ce38b0a - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1342.969 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.969 ; gain = 0.000 - -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device -INFO: [Timing 38-35] Done setting XDC timing constraints. -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1a81b9fdd - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.245 . Memory (MB): peak = 1342.969 ; gain = 0.000 - -Phase 1.3 Build Placer Netlist Model -Phase 1.3 Build Placer Netlist Model | Checksum: 2311220d7 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.315 . Memory (MB): peak = 1342.969 ; gain = 0.000 - -Phase 1.4 Constrain Clocks/Macros -Phase 1.4 Constrain Clocks/Macros | Checksum: 2311220d7 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.316 . Memory (MB): peak = 1342.969 ; gain = 0.000 -Phase 1 Placer Initialization | Checksum: 2311220d7 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.317 . Memory (MB): peak = 1342.969 ; gain = 0.000 - -Phase 2 Global Placement - -Phase 2.1 Floorplanning -Phase 2.1 Floorplanning | Checksum: 28f582a8d - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.357 . Memory (MB): peak = 1342.969 ; gain = 0.000 - -Phase 2.2 Physical Synthesis In Placer -INFO: [Physopt 32-65] No nets found for high-fanout optimization. -INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. -INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell -INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed. -INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed. -INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed. -INFO: [Physopt 32-949] No candidate nets found for HD net replication -INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.969 ; gain = 0.000 - -Summary of Physical Synthesis Optimizations -============================================ - - ----------------------------------------------------------------------------------------------------------------------------------------- -| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------- -| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| HD Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| Total | 0 | 0 | 0 | 0 | 2 | 00:00:00 | ----------------------------------------------------------------------------------------------------------------------------------------- - - -Phase 2.2 Physical Synthesis In Placer | Checksum: 23519395c - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.969 ; gain = 0.000 -Phase 2 Global Placement | Checksum: 2086fb3d6 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.969 ; gain = 0.000 - -Phase 3 Detail Placement - -Phase 3.1 Commit Multi Column Macros -Phase 3.1 Commit Multi Column Macros | Checksum: 2086fb3d6 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.969 ; gain = 0.000 - -Phase 3.2 Commit Most Macros & LUTRAMs -Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 295740530 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.969 ; gain = 0.000 - -Phase 3.3 Area Swap Optimization -Phase 3.3 Area Swap Optimization | Checksum: 2b6e3c48d - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.969 ; gain = 0.000 - -Phase 3.4 Pipeline Register Optimization -Phase 3.4 Pipeline Register Optimization | Checksum: 2b6b80a4e - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.969 ; gain = 0.000 - -Phase 3.5 Small Shape Detail Placement -Phase 3.5 Small Shape Detail Placement | Checksum: 15bcefb3a - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.969 ; gain = 0.000 - -Phase 3.6 Re-assign LUT pins -Phase 3.6 Re-assign LUT pins | Checksum: 1fcac79aa - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.969 ; gain = 0.000 - -Phase 3.7 Pipeline Register Optimization -Phase 3.7 Pipeline Register Optimization | Checksum: 1fc203fe9 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.969 ; gain = 0.000 -Phase 3 Detail Placement | Checksum: 1fc203fe9 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.969 ; gain = 0.000 - -Phase 4 Post Placement Optimization and Clean-Up - -Phase 4.1 Post Commit Optimization -INFO: [Timing 38-35] Done setting XDC timing constraints. - -Phase 4.1.1 Post Placement Optimization -Post Placement Optimization Initialization | Checksum: 227c33555 - -Phase 4.1.1.1 BUFG Insertion -INFO: [Place 46-46] BUFG insertion identified 0 candidate nets, 0 success, 0 bufg driver replicated, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason -Phase 4.1.1.1 BUFG Insertion | Checksum: 227c33555 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.969 ; gain = 0.000 -INFO: [Place 30-746] Post Placement Timing Summary WNS=35.931. For the most accurate timing information please run report_timing. -Phase 4.1.1 Post Placement Optimization | Checksum: 21491ebb1 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.969 ; gain = 0.000 -Phase 4.1 Post Commit Optimization | Checksum: 21491ebb1 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.969 ; gain = 0.000 - -Phase 4.2 Post Placement Cleanup -Phase 4.2 Post Placement Cleanup | Checksum: 21491ebb1 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.969 ; gain = 0.000 - -Phase 4.3 Placer Reporting -Phase 4.3 Placer Reporting | Checksum: 21491ebb1 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.969 ; gain = 0.000 - -Phase 4.4 Final Placement Cleanup -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.969 ; gain = 0.000 -Phase 4.4 Final Placement Cleanup | Checksum: 1be90c9f9 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.969 ; gain = 0.000 -Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1be90c9f9 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.969 ; gain = 0.000 -Ending Placer Task | Checksum: e54542d9 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.969 ; gain = 0.000 -INFO: [Common 17-83] Releasing license: Implementation -57 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -place_design completed successfully -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.969 ; gain = 0.000 -INFO: [Timing 38-480] Writing timing data to binary archive. -Writing placer database... -Writing XDEF routing. -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.969 ; gain = 0.000 -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.052 . Memory (MB): peak = 1342.969 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_placed.dcp' has been generated. -INFO: [runtcl-4] Executing : report_io -file VGA_top_io_placed.rpt -report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1342.969 ; gain = 0.000 -INFO: [runtcl-4] Executing : report_utilization -file VGA_top_utilization_placed.rpt -pb VGA_top_utilization_placed.pb -INFO: [runtcl-4] Executing : report_control_sets -verbose -file VGA_top_control_sets_placed.rpt -report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1342.969 ; gain = 0.000 -Command: route_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' -Running DRC as a precondition to command route_design -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. - - -Starting Routing Task -INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs -Checksum: PlaceDB: c930627b ConstDB: 0 ShapeSum: 1c14e05e RouteDB: 0 - -Phase 1 Build RT Design -Phase 1 Build RT Design | Checksum: 174c0357c - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 1409.715 ; gain = 66.746 -Post Restoration Checksum: NetGraph: ce3f1938 NumContArr: a6811c44 Constraints: 0 Timing: 0 - -Phase 2 Router Initialization - -Phase 2.1 Create Timer -Phase 2.1 Create Timer | Checksum: 174c0357c - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 1440.016 ; gain = 97.047 - -Phase 2.2 Fix Topology Constraints -Phase 2.2 Fix Topology Constraints | Checksum: 174c0357c - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 1446.012 ; gain = 103.043 - -Phase 2.3 Pre Route Cleanup -Phase 2.3 Pre Route Cleanup | Checksum: 174c0357c - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 1446.012 ; gain = 103.043 - Number of Nodes with overlaps = 0 - -Phase 2.4 Update Timing -Phase 2.4 Update Timing | Checksum: 18806e6e0 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 1448.656 ; gain = 105.688 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=36.010 | TNS=0.000 | WHS=-0.256 | THS=-3.626 | - -Phase 2 Router Initialization | Checksum: 1ffe8b068 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 1448.656 ; gain = 105.688 - -Phase 3 Initial Routing -Phase 3 Initial Routing | Checksum: 203c94bde - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1449.172 ; gain = 106.203 - -Phase 4 Rip-up And Reroute - -Phase 4.1 Global Iteration 0 - Number of Nodes with overlaps = 14 - Number of Nodes with overlaps = 0 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.090 | TNS=0.000 | WHS=N/A | THS=N/A | - -Phase 4.1 Global Iteration 0 | Checksum: 1a9606839 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1449.172 ; gain = 106.203 -Phase 4 Rip-up And Reroute | Checksum: 1a9606839 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1449.172 ; gain = 106.203 - -Phase 5 Delay and Skew Optimization - -Phase 5.1 Delay CleanUp -Phase 5.1 Delay CleanUp | Checksum: 1a9606839 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1449.172 ; gain = 106.203 - -Phase 5.2 Clock Skew Optimization -Phase 5.2 Clock Skew Optimization | Checksum: 1a9606839 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1449.172 ; gain = 106.203 -Phase 5 Delay and Skew Optimization | Checksum: 1a9606839 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1449.172 ; gain = 106.203 - -Phase 6 Post Hold Fix - -Phase 6.1 Hold Fix Iter - -Phase 6.1.1 Update Timing -Phase 6.1.1 Update Timing | Checksum: 1e2322df1 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1449.172 ; gain = 106.203 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.205 | TNS=0.000 | WHS=0.073 | THS=0.000 | - -Phase 6.1 Hold Fix Iter | Checksum: 1e2322df1 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1449.172 ; gain = 106.203 -Phase 6 Post Hold Fix | Checksum: 1e2322df1 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1449.172 ; gain = 106.203 - -Phase 7 Route finalize - -Router Utilization Summary - Global Vertical Routing Utilization = 0.0460304 % - Global Horizontal Routing Utilization = 0.0457261 % - Routable Net Status* - *Does not include unroutable nets such as driverless and loadless. - Run report_route_status for detailed report. - Number of Failed Nets = 0 - Number of Unrouted Nets = 0 - Number of Partially Routed Nets = 0 - Number of Node Overlaps = 0 - -Phase 7 Route finalize | Checksum: 181eae35c - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1449.172 ; gain = 106.203 - -Phase 8 Verifying routed nets - - Verification completed successfully -Phase 8 Verifying routed nets | Checksum: 181eae35c - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1451.223 ; gain = 108.254 - -Phase 9 Depositing Routes -Phase 9 Depositing Routes | Checksum: 12f7c034c - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1451.223 ; gain = 108.254 - -Phase 10 Post Router Timing -INFO: [Route 35-57] Estimated Timing Summary | WNS=35.205 | TNS=0.000 | WHS=0.073 | THS=0.000 | - -INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. -Phase 10 Post Router Timing | Checksum: 12f7c034c - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1451.223 ; gain = 108.254 -INFO: [Route 35-16] Router Completed Successfully - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1451.223 ; gain = 108.254 - -Routing Is Done. -INFO: [Common 17-83] Releasing license: Implementation -74 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -route_design completed successfully -route_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:22 . Memory (MB): peak = 1451.223 ; gain = 108.254 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1451.223 ; gain = 0.000 -INFO: [Timing 38-480] Writing timing data to binary archive. -Writing placer database... -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.047 . Memory (MB): peak = 1451.637 ; gain = 0.414 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1451.637 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_routed.dcp' has been generated. -INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx -Command: report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx -INFO: [IP_Flow 19-1839] IP Catalog is up to date. -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_routed.rpt. -report_drc completed successfully -INFO: [runtcl-4] Executing : report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx -Command: report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [DRC 23-133] Running Methodology with 2 threads -INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_methodology_drc_routed.rpt. -report_methodology completed successfully -INFO: [runtcl-4] Executing : report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx -Command: report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx -INFO: [Timing 38-35] Done setting XDC timing constraints. -Running Vector-less Activity Propagation... - -Finished Running Vector-less Activity Propagation -86 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -report_power completed successfully -INFO: [runtcl-4] Executing : report_route_status -file VGA_top_route_status.rpt -pb VGA_top_route_status.pb -INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file VGA_top_timing_summary_routed.rpt -pb VGA_top_timing_summary_routed.pb -rpx VGA_top_timing_summary_routed.rpx -warn_on_violation -INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. -INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs -INFO: [runtcl-4] Executing : report_incremental_reuse -file VGA_top_incremental_reuse_routed.rpt -INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. -INFO: [runtcl-4] Executing : report_clock_utilization -file VGA_top_clock_utilization_routed.rpt -INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file VGA_top_bus_skew_routed.rpt -pb VGA_top_bus_skew_routed.pb -rpx VGA_top_bus_skew_routed.rpx -INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. -INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs -INFO: [Common 17-206] Exiting Vivado at Tue Dec 7 12:36:47 2021... diff --git a/projet-vga.runs/impl_1/VGA_top_8972.backup.vdi b/projet-vga.runs/impl_1/VGA_top_8972.backup.vdi deleted file mode 100644 index 6b2b2e8..0000000 --- a/projet-vga.runs/impl_1/VGA_top_8972.backup.vdi +++ /dev/null @@ -1,529 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Tue Nov 23 10:20:49 2021 -# Process ID: 8972 -# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1 -# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace -# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi -# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou -#----------------------------------------------------------- -source VGA_top.tcl -notrace -Command: link_design -top VGA_top -part xc7z010clg400-1 -Design is defaulting to srcset: sources_1 -Design is defaulting to constrset: constrs_1 -INFO: [Project 1-454] Reading design checkpoint 'c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.dcp' for cell 'U0' -INFO: [Netlist 29-17] Analyzing 3 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-479] Netlist was created with Vivado 2018.3 -INFO: [Device 21-403] Loading part xc7z010clg400-1 -INFO: [Project 1-570] Preparing netlist for logic optimization -Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst' -Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst' -Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst' -INFO: [Timing 38-35] Done setting XDC timing constraints. [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57] -INFO: [Timing 38-2] Deriving generated clocks [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57] -get_clocks: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1224.426 ; gain = 534.145 -Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst' -Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc] -WARNING: [Vivado 12-507] No nets matched 'bouton_down_IBUF'. [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc:12] -CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc:12] -Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. -WARNING: [Vivado 12-507] No nets matched 'bouton_right_IBUF'. [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc:13] -CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc:13] -Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. -Finished Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc] -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1224.426 ; gain = 0.000 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -10 Infos, 2 Warnings, 2 Critical Warnings and 0 Errors encountered. -link_design completed successfully -link_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:24 . Memory (MB): peak = 1224.426 ; gain = 861.312 -Command: opt_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' -Running DRC as a precondition to command opt_design - -Starting DRC Task -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Project 1-461] DRC finished with 0 Errors -INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.489 . Memory (MB): peak = 1224.426 ; gain = 0.000 - -Starting Cache Timing Information Task -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [Timing 38-2] Deriving generated clocks -Ending Cache Timing Information Task | Checksum: 5a9f0cbf - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1240.770 ; gain = 16.344 - -Starting Logic Optimization Task - -Phase 1 Retarget -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -INFO: [Opt 31-49] Retargeted 0 cell(s). -Phase 1 Retarget | Checksum: 5a9f0cbf - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1325.379 ; gain = 0.000 -INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells -INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. - -Phase 2 Constant propagation -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Phase 2 Constant propagation | Checksum: 5a9f0cbf - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1325.379 ; gain = 0.000 -INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells - -Phase 3 Sweep -Phase 3 Sweep | Checksum: 117de2bd6 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1325.379 ; gain = 0.000 -INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells - -Phase 4 BUFG optimization -INFO: [Opt 31-194] Inserted BUFG U0/inst/clk_out1_clk_wiz_1_BUFG_inst to drive 0 load(s) on clock net U0/inst/clk_out1_clk_wiz_1_BUFG -INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets -Phase 4 BUFG optimization | Checksum: 7fbfd86e - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1325.379 ; gain = 0.000 -INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. - -Phase 5 Shift Register Optimization -Phase 5 Shift Register Optimization | Checksum: 17b01d26a - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1325.379 ; gain = 0.000 -INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells - -Phase 6 Post Processing Netlist -Phase 6 Post Processing Netlist | Checksum: b289bdf0 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 1325.379 ; gain = 0.000 -INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells -Opt_design Change Summary -========================= - - -------------------------------------------------------------------------------------------------------------------------- -| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | -------------------------------------------------------------------------------------------------------------------------- -| Retarget | 0 | 0 | 1 | -| Constant propagation | 0 | 0 | 0 | -| Sweep | 0 | 0 | 0 | -| BUFG optimization | 0 | 0 | 0 | -| Shift Register Optimization | 0 | 0 | 0 | -| Post Processing Netlist | 0 | 0 | 0 | -------------------------------------------------------------------------------------------------------------------------- - - - -Starting Connectivity Check Task - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1325.379 ; gain = 0.000 -Ending Logic Optimization Task | Checksum: a7dcf37c - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.026 . Memory (MB): peak = 1325.379 ; gain = 0.000 - -Starting Power Optimization Task -INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. -Ending Power Optimization Task | Checksum: a7dcf37c - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1325.379 ; gain = 0.000 - -Starting Final Cleanup Task -Ending Final Cleanup Task | Checksum: a7dcf37c - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1325.379 ; gain = 0.000 - -Starting Netlist Obfuscation Task -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1325.379 ; gain = 0.000 -Ending Netlist Obfuscation Task | Checksum: a7dcf37c - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1325.379 ; gain = 0.000 -INFO: [Common 17-83] Releasing license: Implementation -30 Infos, 2 Warnings, 2 Critical Warnings and 0 Errors encountered. -opt_design completed successfully -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1325.379 ; gain = 0.000 -INFO: [Timing 38-480] Writing timing data to binary archive. -Writing placer database... -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1325.379 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1325.379 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_opt.dcp' has been generated. -INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx -Command: report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx -INFO: [IP_Flow 19-1839] IP Catalog is up to date. -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_opted.rpt. -report_drc completed successfully -Command: place_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. -Running DRC as a precondition to command place_design -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. - -Starting Placer Task -INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs - -Phase 1 Placer Initialization - -Phase 1.1 Placer Initialization Netlist Sorting -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1325.379 ; gain = 0.000 -Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a1a0325f - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1325.379 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1325.379 ; gain = 0.000 - -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device -INFO: [Timing 38-35] Done setting XDC timing constraints. -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 11cf26ecf - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.233 . Memory (MB): peak = 1325.379 ; gain = 0.000 - -Phase 1.3 Build Placer Netlist Model -Phase 1.3 Build Placer Netlist Model | Checksum: 18315a003 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.277 . Memory (MB): peak = 1325.379 ; gain = 0.000 - -Phase 1.4 Constrain Clocks/Macros -Phase 1.4 Constrain Clocks/Macros | Checksum: 18315a003 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.278 . Memory (MB): peak = 1325.379 ; gain = 0.000 -Phase 1 Placer Initialization | Checksum: 18315a003 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.279 . Memory (MB): peak = 1325.379 ; gain = 0.000 - -Phase 2 Global Placement - -Phase 2.1 Floorplanning -Phase 2.1 Floorplanning | Checksum: 1a3a857f8 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.309 . Memory (MB): peak = 1325.379 ; gain = 0.000 - -Phase 2.2 Physical Synthesis In Placer -INFO: [Physopt 32-65] No nets found for high-fanout optimization. -INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. -INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell -INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed. -INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed. -INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed. -INFO: [Physopt 32-949] No candidate nets found for HD net replication -INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1325.379 ; gain = 0.000 - -Summary of Physical Synthesis Optimizations -============================================ - - ----------------------------------------------------------------------------------------------------------------------------------------- -| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------- -| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| HD Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| Total | 0 | 0 | 0 | 0 | 2 | 00:00:00 | ----------------------------------------------------------------------------------------------------------------------------------------- - - -Phase 2.2 Physical Synthesis In Placer | Checksum: 129d92158 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.535 . Memory (MB): peak = 1325.379 ; gain = 0.000 -Phase 2 Global Placement | Checksum: 15aff6cea - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.545 . Memory (MB): peak = 1325.379 ; gain = 0.000 - -Phase 3 Detail Placement - -Phase 3.1 Commit Multi Column Macros -Phase 3.1 Commit Multi Column Macros | Checksum: 15aff6cea - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.546 . Memory (MB): peak = 1325.379 ; gain = 0.000 - -Phase 3.2 Commit Most Macros & LUTRAMs -Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: e992437f - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.575 . Memory (MB): peak = 1325.379 ; gain = 0.000 - -Phase 3.3 Area Swap Optimization -Phase 3.3 Area Swap Optimization | Checksum: 125aa6a8c - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.577 . Memory (MB): peak = 1325.379 ; gain = 0.000 - -Phase 3.4 Pipeline Register Optimization -Phase 3.4 Pipeline Register Optimization | Checksum: 125aa6a8c - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.578 . Memory (MB): peak = 1325.379 ; gain = 0.000 - -Phase 3.5 Small Shape Detail Placement -Phase 3.5 Small Shape Detail Placement | Checksum: 9d3a0023 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.617 . Memory (MB): peak = 1325.379 ; gain = 0.000 - -Phase 3.6 Re-assign LUT pins -Phase 3.6 Re-assign LUT pins | Checksum: 100894d91 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.620 . Memory (MB): peak = 1325.379 ; gain = 0.000 - -Phase 3.7 Pipeline Register Optimization -Phase 3.7 Pipeline Register Optimization | Checksum: 100894d91 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.621 . Memory (MB): peak = 1325.379 ; gain = 0.000 -Phase 3 Detail Placement | Checksum: 100894d91 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.621 . Memory (MB): peak = 1325.379 ; gain = 0.000 - -Phase 4 Post Placement Optimization and Clean-Up - -Phase 4.1 Post Commit Optimization -INFO: [Timing 38-35] Done setting XDC timing constraints. - -Phase 4.1.1 Post Placement Optimization -Post Placement Optimization Initialization | Checksum: 1582d7486 - -Phase 4.1.1.1 BUFG Insertion -INFO: [Place 46-46] BUFG insertion identified 0 candidate nets, 0 success, 0 bufg driver replicated, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason -Phase 4.1.1.1 BUFG Insertion | Checksum: 1582d7486 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.652 . Memory (MB): peak = 1325.379 ; gain = 0.000 -INFO: [Place 30-746] Post Placement Timing Summary WNS=35.525. For the most accurate timing information please run report_timing. -Phase 4.1.1 Post Placement Optimization | Checksum: 1fb172a0a - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.652 . Memory (MB): peak = 1325.379 ; gain = 0.000 -Phase 4.1 Post Commit Optimization | Checksum: 1fb172a0a - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.653 . Memory (MB): peak = 1325.379 ; gain = 0.000 - -Phase 4.2 Post Placement Cleanup -Phase 4.2 Post Placement Cleanup | Checksum: 1fb172a0a - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.654 . Memory (MB): peak = 1325.379 ; gain = 0.000 - -Phase 4.3 Placer Reporting -Phase 4.3 Placer Reporting | Checksum: 1fb172a0a - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.655 . Memory (MB): peak = 1325.379 ; gain = 0.000 - -Phase 4.4 Final Placement Cleanup -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1325.379 ; gain = 0.000 -Phase 4.4 Final Placement Cleanup | Checksum: 1a5f08b61 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.657 . Memory (MB): peak = 1325.379 ; gain = 0.000 -Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1a5f08b61 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.657 . Memory (MB): peak = 1325.379 ; gain = 0.000 -Ending Placer Task | Checksum: ea220969 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.658 . Memory (MB): peak = 1325.379 ; gain = 0.000 -INFO: [Common 17-83] Releasing license: Implementation -57 Infos, 2 Warnings, 2 Critical Warnings and 0 Errors encountered. -place_design completed successfully -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1325.379 ; gain = 0.000 -INFO: [Timing 38-480] Writing timing data to binary archive. -Writing placer database... -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.037 . Memory (MB): peak = 1326.145 ; gain = 0.766 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1326.145 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_placed.dcp' has been generated. -INFO: [runtcl-4] Executing : report_io -file VGA_top_io_placed.rpt -report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 1329.160 ; gain = 0.000 -INFO: [runtcl-4] Executing : report_utilization -file VGA_top_utilization_placed.rpt -pb VGA_top_utilization_placed.pb -INFO: [runtcl-4] Executing : report_control_sets -verbose -file VGA_top_control_sets_placed.rpt -report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1329.160 ; gain = 0.000 -Command: route_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' -Running DRC as a precondition to command route_design -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. - - -Starting Routing Task -INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs -Checksum: PlaceDB: 659db238 ConstDB: 0 ShapeSum: 84845731 RouteDB: 0 - -Phase 1 Build RT Design -Phase 1 Build RT Design | Checksum: e41f4d51 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1401.383 ; gain = 72.223 -Post Restoration Checksum: NetGraph: 5c55eb1d NumContArr: 87c96234 Constraints: 0 Timing: 0 - -Phase 2 Router Initialization - -Phase 2.1 Create Timer -Phase 2.1 Create Timer | Checksum: e41f4d51 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1425.637 ; gain = 96.477 - -Phase 2.2 Fix Topology Constraints -Phase 2.2 Fix Topology Constraints | Checksum: e41f4d51 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1431.664 ; gain = 102.504 - -Phase 2.3 Pre Route Cleanup -Phase 2.3 Pre Route Cleanup | Checksum: e41f4d51 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1431.664 ; gain = 102.504 - Number of Nodes with overlaps = 0 - -Phase 2.4 Update Timing -Phase 2.4 Update Timing | Checksum: 6955b62d - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1434.438 ; gain = 105.277 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.474 | TNS=0.000 | WHS=-0.254 | THS=-3.685 | - -Phase 2 Router Initialization | Checksum: 95e944f1 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1434.438 ; gain = 105.277 - -Phase 3 Initial Routing -Phase 3 Initial Routing | Checksum: 73b087ef - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1434.438 ; gain = 105.277 - -Phase 4 Rip-up And Reroute - -Phase 4.1 Global Iteration 0 - Number of Nodes with overlaps = 2 - Number of Nodes with overlaps = 0 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=33.732 | TNS=0.000 | WHS=N/A | THS=N/A | - -Phase 4.1 Global Iteration 0 | Checksum: c2f4c059 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1434.438 ; gain = 105.277 -Phase 4 Rip-up And Reroute | Checksum: c2f4c059 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1434.438 ; gain = 105.277 - -Phase 5 Delay and Skew Optimization - -Phase 5.1 Delay CleanUp -Phase 5.1 Delay CleanUp | Checksum: c2f4c059 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1434.438 ; gain = 105.277 - -Phase 5.2 Clock Skew Optimization -Phase 5.2 Clock Skew Optimization | Checksum: c2f4c059 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1434.438 ; gain = 105.277 -Phase 5 Delay and Skew Optimization | Checksum: c2f4c059 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1434.438 ; gain = 105.277 - -Phase 6 Post Hold Fix - -Phase 6.1 Hold Fix Iter - -Phase 6.1.1 Update Timing -Phase 6.1.1 Update Timing | Checksum: 171f06df9 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1434.438 ; gain = 105.277 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=33.848 | TNS=0.000 | WHS=0.048 | THS=0.000 | - -Phase 6.1 Hold Fix Iter | Checksum: 16074e70e - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1434.438 ; gain = 105.277 -Phase 6 Post Hold Fix | Checksum: 16074e70e - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1434.438 ; gain = 105.277 - -Phase 7 Route finalize - -Router Utilization Summary - Global Vertical Routing Utilization = 0.0225225 % - Global Horizontal Routing Utilization = 0.0140165 % - Routable Net Status* - *Does not include unroutable nets such as driverless and loadless. - Run report_route_status for detailed report. - Number of Failed Nets = 0 - Number of Unrouted Nets = 0 - Number of Partially Routed Nets = 0 - Number of Node Overlaps = 0 - -Phase 7 Route finalize | Checksum: 16074e70e - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1434.438 ; gain = 105.277 - -Phase 8 Verifying routed nets - - Verification completed successfully -Phase 8 Verifying routed nets | Checksum: 16074e70e - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1436.086 ; gain = 106.926 - -Phase 9 Depositing Routes -Phase 9 Depositing Routes | Checksum: 1e005d2dc - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1436.086 ; gain = 106.926 - -Phase 10 Post Router Timing -INFO: [Route 35-57] Estimated Timing Summary | WNS=33.848 | TNS=0.000 | WHS=0.048 | THS=0.000 | - -INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. -Phase 10 Post Router Timing | Checksum: 1e005d2dc - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1436.086 ; gain = 106.926 -INFO: [Route 35-16] Router Completed Successfully - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1436.086 ; gain = 106.926 - -Routing Is Done. -INFO: [Common 17-83] Releasing license: Implementation -74 Infos, 2 Warnings, 2 Critical Warnings and 0 Errors encountered. -route_design completed successfully -route_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1436.086 ; gain = 106.926 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1436.086 ; gain = 0.000 -INFO: [Timing 38-480] Writing timing data to binary archive. -Writing placer database... -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1436.758 ; gain = 0.672 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1436.758 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_routed.dcp' has been generated. -INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx -Command: report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx -INFO: [IP_Flow 19-1839] IP Catalog is up to date. -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_routed.rpt. -report_drc completed successfully -INFO: [runtcl-4] Executing : report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx -Command: report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [DRC 23-133] Running Methodology with 2 threads -INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_methodology_drc_routed.rpt. -report_methodology completed successfully -INFO: [runtcl-4] Executing : report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx -Command: report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx -INFO: [Timing 38-35] Done setting XDC timing constraints. -Running Vector-less Activity Propagation... - -Finished Running Vector-less Activity Propagation -86 Infos, 2 Warnings, 2 Critical Warnings and 0 Errors encountered. -report_power completed successfully -INFO: [runtcl-4] Executing : report_route_status -file VGA_top_route_status.rpt -pb VGA_top_route_status.pb -INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file VGA_top_timing_summary_routed.rpt -pb VGA_top_timing_summary_routed.pb -rpx VGA_top_timing_summary_routed.rpx -warn_on_violation -INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. -INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs -INFO: [runtcl-4] Executing : report_incremental_reuse -file VGA_top_incremental_reuse_routed.rpt -INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. -INFO: [runtcl-4] Executing : report_clock_utilization -file VGA_top_clock_utilization_routed.rpt -INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file VGA_top_bus_skew_routed.rpt -pb VGA_top_bus_skew_routed.pb -rpx VGA_top_bus_skew_routed.rpx -INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. -INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs -INFO: [Common 17-206] Exiting Vivado at Tue Nov 23 10:21:35 2021... diff --git a/projet-vga.runs/impl_1/VGA_top_9384.backup.vdi b/projet-vga.runs/impl_1/VGA_top_9384.backup.vdi deleted file mode 100644 index 93f834c..0000000 --- a/projet-vga.runs/impl_1/VGA_top_9384.backup.vdi +++ /dev/null @@ -1,523 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Tue Dec 7 12:26:40 2021 -# Process ID: 9384 -# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1 -# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace -# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi -# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou -#----------------------------------------------------------- -source VGA_top.tcl -notrace -Command: link_design -top VGA_top -part xc7z010clg400-1 -Design is defaulting to srcset: sources_1 -Design is defaulting to constrset: constrs_1 -INFO: [Project 1-454] Reading design checkpoint 'c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.dcp' for cell 'U0' -INFO: [Netlist 29-17] Analyzing 3 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-479] Netlist was created with Vivado 2018.3 -INFO: [Device 21-403] Loading part xc7z010clg400-1 -INFO: [Project 1-570] Preparing netlist for logic optimization -Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst' -Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst' -Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst' -INFO: [Timing 38-35] Done setting XDC timing constraints. [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57] -INFO: [Timing 38-2] Deriving generated clocks [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57] -get_clocks: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1223.977 ; gain = 532.945 -Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst' -Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc] -Finished Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc] -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1223.977 ; gain = 0.000 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -link_design completed successfully -link_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:16 . Memory (MB): peak = 1223.977 ; gain = 860.727 -Command: opt_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' -Running DRC as a precondition to command opt_design - -Starting DRC Task -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Project 1-461] DRC finished with 0 Errors -INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.512 . Memory (MB): peak = 1223.977 ; gain = 0.000 - -Starting Cache Timing Information Task -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [Timing 38-2] Deriving generated clocks -Ending Cache Timing Information Task | Checksum: 1e73ff6cd - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1240.598 ; gain = 16.621 - -Starting Logic Optimization Task - -Phase 1 Retarget -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -INFO: [Opt 31-49] Retargeted 0 cell(s). -Phase 1 Retarget | Checksum: 1e73ff6cd - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1324.828 ; gain = 0.000 -INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells -INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. - -Phase 2 Constant propagation -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Phase 2 Constant propagation | Checksum: 1e73ff6cd - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1324.828 ; gain = 0.000 -INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells - -Phase 3 Sweep -Phase 3 Sweep | Checksum: 1b93fc096 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1324.828 ; gain = 0.000 -INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells - -Phase 4 BUFG optimization -INFO: [Opt 31-194] Inserted BUFG U0/inst/clk_out1_clk_wiz_1_BUFG_inst to drive 0 load(s) on clock net U0/inst/clk_out1_clk_wiz_1_BUFG -INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets -Phase 4 BUFG optimization | Checksum: 17548010c - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1324.828 ; gain = 0.000 -INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. - -Phase 5 Shift Register Optimization -Phase 5 Shift Register Optimization | Checksum: 112979ec5 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 1324.828 ; gain = 0.000 -INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells - -Phase 6 Post Processing Netlist -Phase 6 Post Processing Netlist | Checksum: dc7cd0a1 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 1324.828 ; gain = 0.000 -INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells -Opt_design Change Summary -========================= - - -------------------------------------------------------------------------------------------------------------------------- -| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | -------------------------------------------------------------------------------------------------------------------------- -| Retarget | 0 | 0 | 1 | -| Constant propagation | 0 | 0 | 0 | -| Sweep | 0 | 0 | 0 | -| BUFG optimization | 0 | 0 | 0 | -| Shift Register Optimization | 0 | 0 | 0 | -| Post Processing Netlist | 0 | 0 | 0 | -------------------------------------------------------------------------------------------------------------------------- - - - -Starting Connectivity Check Task - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1324.828 ; gain = 0.000 -Ending Logic Optimization Task | Checksum: 150d68caf - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 1324.828 ; gain = 0.000 - -Starting Power Optimization Task -INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. -Ending Power Optimization Task | Checksum: 150d68caf - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1324.828 ; gain = 0.000 - -Starting Final Cleanup Task -Ending Final Cleanup Task | Checksum: 150d68caf - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1324.828 ; gain = 0.000 - -Starting Netlist Obfuscation Task -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1324.828 ; gain = 0.000 -Ending Netlist Obfuscation Task | Checksum: 150d68caf - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1324.828 ; gain = 0.000 -INFO: [Common 17-83] Releasing license: Implementation -30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -opt_design completed successfully -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1324.828 ; gain = 0.000 -INFO: [Timing 38-480] Writing timing data to binary archive. -Writing placer database... -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1324.828 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1324.828 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_opt.dcp' has been generated. -INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx -Command: report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx -INFO: [IP_Flow 19-1839] IP Catalog is up to date. -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_opted.rpt. -report_drc completed successfully -Command: place_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. -Running DRC as a precondition to command place_design -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. - -Starting Placer Task -INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs - -Phase 1 Placer Initialization - -Phase 1.1 Placer Initialization Netlist Sorting -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1324.828 ; gain = 0.000 -Phase 1.1 Placer Initialization Netlist Sorting | Checksum: c1eb0453 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1324.828 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1324.828 ; gain = 0.000 - -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device -INFO: [Timing 38-35] Done setting XDC timing constraints. -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 140e33f71 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.241 . Memory (MB): peak = 1324.828 ; gain = 0.000 - -Phase 1.3 Build Placer Netlist Model -Phase 1.3 Build Placer Netlist Model | Checksum: 1adacafea - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.290 . Memory (MB): peak = 1324.828 ; gain = 0.000 - -Phase 1.4 Constrain Clocks/Macros -Phase 1.4 Constrain Clocks/Macros | Checksum: 1adacafea - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.291 . Memory (MB): peak = 1324.828 ; gain = 0.000 -Phase 1 Placer Initialization | Checksum: 1adacafea - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.292 . Memory (MB): peak = 1324.828 ; gain = 0.000 - -Phase 2 Global Placement - -Phase 2.1 Floorplanning -Phase 2.1 Floorplanning | Checksum: 1ee11f466 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.334 . Memory (MB): peak = 1324.828 ; gain = 0.000 - -Phase 2.2 Physical Synthesis In Placer -INFO: [Physopt 32-65] No nets found for high-fanout optimization. -INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. -INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell -INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed. -INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed. -INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed. -INFO: [Physopt 32-949] No candidate nets found for HD net replication -INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1324.828 ; gain = 0.000 - -Summary of Physical Synthesis Optimizations -============================================ - - ----------------------------------------------------------------------------------------------------------------------------------------- -| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------- -| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| HD Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| Total | 0 | 0 | 0 | 0 | 2 | 00:00:00 | ----------------------------------------------------------------------------------------------------------------------------------------- - - -Phase 2.2 Physical Synthesis In Placer | Checksum: 14964665c - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.673 . Memory (MB): peak = 1324.828 ; gain = 0.000 -Phase 2 Global Placement | Checksum: 1f3bcd8e6 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.683 . Memory (MB): peak = 1324.828 ; gain = 0.000 - -Phase 3 Detail Placement - -Phase 3.1 Commit Multi Column Macros -Phase 3.1 Commit Multi Column Macros | Checksum: 1f3bcd8e6 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.684 . Memory (MB): peak = 1324.828 ; gain = 0.000 - -Phase 3.2 Commit Most Macros & LUTRAMs -Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 101f41530 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.724 . Memory (MB): peak = 1324.828 ; gain = 0.000 - -Phase 3.3 Area Swap Optimization -Phase 3.3 Area Swap Optimization | Checksum: 1aa9f5064 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.726 . Memory (MB): peak = 1324.828 ; gain = 0.000 - -Phase 3.4 Pipeline Register Optimization -Phase 3.4 Pipeline Register Optimization | Checksum: 1aa9f5064 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.726 . Memory (MB): peak = 1324.828 ; gain = 0.000 - -Phase 3.5 Small Shape Detail Placement -Phase 3.5 Small Shape Detail Placement | Checksum: c56fd17b - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.782 . Memory (MB): peak = 1324.828 ; gain = 0.000 - -Phase 3.6 Re-assign LUT pins -Phase 3.6 Re-assign LUT pins | Checksum: 10748b914 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.786 . Memory (MB): peak = 1324.828 ; gain = 0.000 - -Phase 3.7 Pipeline Register Optimization -Phase 3.7 Pipeline Register Optimization | Checksum: 10748b914 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.786 . Memory (MB): peak = 1324.828 ; gain = 0.000 -Phase 3 Detail Placement | Checksum: 10748b914 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.787 . Memory (MB): peak = 1324.828 ; gain = 0.000 - -Phase 4 Post Placement Optimization and Clean-Up - -Phase 4.1 Post Commit Optimization -INFO: [Timing 38-35] Done setting XDC timing constraints. - -Phase 4.1.1 Post Placement Optimization -Post Placement Optimization Initialization | Checksum: 1b4de7b32 - -Phase 4.1.1.1 BUFG Insertion -INFO: [Place 46-46] BUFG insertion identified 0 candidate nets, 0 success, 0 bufg driver replicated, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason -Phase 4.1.1.1 BUFG Insertion | Checksum: 1b4de7b32 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.818 . Memory (MB): peak = 1324.828 ; gain = 0.000 -INFO: [Place 30-746] Post Placement Timing Summary WNS=35.374. For the most accurate timing information please run report_timing. -Phase 4.1.1 Post Placement Optimization | Checksum: 1221ff634 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.819 . Memory (MB): peak = 1324.828 ; gain = 0.000 -Phase 4.1 Post Commit Optimization | Checksum: 1221ff634 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.819 . Memory (MB): peak = 1324.828 ; gain = 0.000 - -Phase 4.2 Post Placement Cleanup -Phase 4.2 Post Placement Cleanup | Checksum: 1221ff634 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.821 . Memory (MB): peak = 1324.828 ; gain = 0.000 - -Phase 4.3 Placer Reporting -Phase 4.3 Placer Reporting | Checksum: 1221ff634 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.821 . Memory (MB): peak = 1324.828 ; gain = 0.000 - -Phase 4.4 Final Placement Cleanup -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1324.828 ; gain = 0.000 -Phase 4.4 Final Placement Cleanup | Checksum: 11b681dd6 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.823 . Memory (MB): peak = 1324.828 ; gain = 0.000 -Phase 4 Post Placement Optimization and Clean-Up | Checksum: 11b681dd6 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.824 . Memory (MB): peak = 1324.828 ; gain = 0.000 -Ending Placer Task | Checksum: c7f5b6fe - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.825 . Memory (MB): peak = 1324.828 ; gain = 0.000 -INFO: [Common 17-83] Releasing license: Implementation -57 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -place_design completed successfully -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1324.828 ; gain = 0.000 -INFO: [Timing 38-480] Writing timing data to binary archive. -Writing placer database... -Writing XDEF routing. -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1324.828 ; gain = 0.000 -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.058 . Memory (MB): peak = 1324.828 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_placed.dcp' has been generated. -INFO: [runtcl-4] Executing : report_io -file VGA_top_io_placed.rpt -report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 1324.828 ; gain = 0.000 -INFO: [runtcl-4] Executing : report_utilization -file VGA_top_utilization_placed.rpt -pb VGA_top_utilization_placed.pb -INFO: [runtcl-4] Executing : report_control_sets -verbose -file VGA_top_control_sets_placed.rpt -report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1324.828 ; gain = 0.000 -Command: route_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' -Running DRC as a precondition to command route_design -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. - - -Starting Routing Task -INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs -Checksum: PlaceDB: 4cd546ca ConstDB: 0 ShapeSum: 7b207034 RouteDB: 0 - -Phase 1 Build RT Design -Phase 1 Build RT Design | Checksum: 193e9b080 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1400.352 ; gain = 75.523 -Post Restoration Checksum: NetGraph: f603a583 NumContArr: 9de60afd Constraints: 0 Timing: 0 - -Phase 2 Router Initialization - -Phase 2.1 Create Timer -Phase 2.1 Create Timer | Checksum: 193e9b080 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1424.602 ; gain = 99.773 - -Phase 2.2 Fix Topology Constraints -Phase 2.2 Fix Topology Constraints | Checksum: 193e9b080 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1430.637 ; gain = 105.809 - -Phase 2.3 Pre Route Cleanup -Phase 2.3 Pre Route Cleanup | Checksum: 193e9b080 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1430.637 ; gain = 105.809 - Number of Nodes with overlaps = 0 - -Phase 2.4 Update Timing -Phase 2.4 Update Timing | Checksum: 14d287119 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.406 ; gain = 108.578 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.306 | TNS=0.000 | WHS=-0.280 | THS=-3.042 | - -Phase 2 Router Initialization | Checksum: 11c317e3b - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.406 ; gain = 108.578 - -Phase 3 Initial Routing -Phase 3 Initial Routing | Checksum: 13856f33e - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.406 ; gain = 108.578 - -Phase 4 Rip-up And Reroute - -Phase 4.1 Global Iteration 0 - Number of Nodes with overlaps = 4 - Number of Nodes with overlaps = 0 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.229 | TNS=0.000 | WHS=N/A | THS=N/A | - -Phase 4.1 Global Iteration 0 | Checksum: 130baabbd - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.406 ; gain = 108.578 -Phase 4 Rip-up And Reroute | Checksum: 130baabbd - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.406 ; gain = 108.578 - -Phase 5 Delay and Skew Optimization - -Phase 5.1 Delay CleanUp -Phase 5.1 Delay CleanUp | Checksum: 130baabbd - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.406 ; gain = 108.578 - -Phase 5.2 Clock Skew Optimization -Phase 5.2 Clock Skew Optimization | Checksum: 130baabbd - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.406 ; gain = 108.578 -Phase 5 Delay and Skew Optimization | Checksum: 130baabbd - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.406 ; gain = 108.578 - -Phase 6 Post Hold Fix - -Phase 6.1 Hold Fix Iter - -Phase 6.1.1 Update Timing -Phase 6.1.1 Update Timing | Checksum: 92f99af8 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.406 ; gain = 108.578 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.382 | TNS=0.000 | WHS=0.073 | THS=0.000 | - -Phase 6.1 Hold Fix Iter | Checksum: 92f99af8 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.406 ; gain = 108.578 -Phase 6 Post Hold Fix | Checksum: 92f99af8 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.406 ; gain = 108.578 - -Phase 7 Route finalize - -Router Utilization Summary - Global Vertical Routing Utilization = 0.019848 % - Global Horizontal Routing Utilization = 0.0151654 % - Routable Net Status* - *Does not include unroutable nets such as driverless and loadless. - Run report_route_status for detailed report. - Number of Failed Nets = 0 - Number of Unrouted Nets = 0 - Number of Partially Routed Nets = 0 - Number of Node Overlaps = 0 - -Phase 7 Route finalize | Checksum: 1561952c6 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1433.406 ; gain = 108.578 - -Phase 8 Verifying routed nets - - Verification completed successfully -Phase 8 Verifying routed nets | Checksum: 1561952c6 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1434.938 ; gain = 110.109 - -Phase 9 Depositing Routes -Phase 9 Depositing Routes | Checksum: 242e77cc4 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1434.938 ; gain = 110.109 - -Phase 10 Post Router Timing -INFO: [Route 35-57] Estimated Timing Summary | WNS=35.382 | TNS=0.000 | WHS=0.073 | THS=0.000 | - -INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. -Phase 10 Post Router Timing | Checksum: 242e77cc4 - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1434.938 ; gain = 110.109 -INFO: [Route 35-16] Router Completed Successfully - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1434.938 ; gain = 110.109 - -Routing Is Done. -INFO: [Common 17-83] Releasing license: Implementation -74 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -route_design completed successfully -route_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:23 . Memory (MB): peak = 1434.938 ; gain = 110.109 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1434.938 ; gain = 0.000 -INFO: [Timing 38-480] Writing timing data to binary archive. -Writing placer database... -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.040 . Memory (MB): peak = 1435.922 ; gain = 0.984 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1435.922 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_routed.dcp' has been generated. -INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx -Command: report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx -INFO: [IP_Flow 19-1839] IP Catalog is up to date. -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_routed.rpt. -report_drc completed successfully -INFO: [runtcl-4] Executing : report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx -Command: report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [DRC 23-133] Running Methodology with 2 threads -INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_methodology_drc_routed.rpt. -report_methodology completed successfully -INFO: [runtcl-4] Executing : report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx -Command: report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx -INFO: [Timing 38-35] Done setting XDC timing constraints. -Running Vector-less Activity Propagation... - -Finished Running Vector-less Activity Propagation -86 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -report_power completed successfully -INFO: [runtcl-4] Executing : report_route_status -file VGA_top_route_status.rpt -pb VGA_top_route_status.pb -INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file VGA_top_timing_summary_routed.rpt -pb VGA_top_timing_summary_routed.pb -rpx VGA_top_timing_summary_routed.rpx -warn_on_violation -INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. -INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs -INFO: [runtcl-4] Executing : report_incremental_reuse -file VGA_top_incremental_reuse_routed.rpt -INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. -INFO: [runtcl-4] Executing : report_clock_utilization -file VGA_top_clock_utilization_routed.rpt -INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file VGA_top_bus_skew_routed.rpt -pb VGA_top_bus_skew_routed.pb -rpx VGA_top_bus_skew_routed.rpx -INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. -INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs -INFO: [Common 17-206] Exiting Vivado at Tue Dec 7 12:27:29 2021... diff --git a/projet-vga.runs/impl_1/VGA_top_9960.backup.vdi b/projet-vga.runs/impl_1/VGA_top_9960.backup.vdi deleted file mode 100644 index 5768c51..0000000 --- a/projet-vga.runs/impl_1/VGA_top_9960.backup.vdi +++ /dev/null @@ -1,545 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Tue Nov 23 10:14:24 2021 -# Process ID: 9960 -# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1 -# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace -# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi -# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou -#----------------------------------------------------------- -source VGA_top.tcl -notrace -Command: link_design -top VGA_top -part xc7z010clg400-1 -Design is defaulting to srcset: sources_1 -Design is defaulting to constrset: constrs_1 -INFO: [Project 1-454] Reading design checkpoint 'c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.dcp' for cell 'U0' -INFO: [Netlist 29-17] Analyzing 11 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-479] Netlist was created with Vivado 2018.3 -INFO: [Device 21-403] Loading part xc7z010clg400-1 -INFO: [Project 1-570] Preparing netlist for logic optimization -Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst' -Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst' -Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst' -INFO: [Timing 38-35] Done setting XDC timing constraints. [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57] -INFO: [Timing 38-2] Deriving generated clocks [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57] -get_clocks: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1242.402 ; gain = 551.609 -Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst' -Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc] -Finished Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc] -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1242.402 ; gain = 0.000 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -link_design completed successfully -link_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:24 . Memory (MB): peak = 1242.402 ; gain = 879.289 -Command: opt_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' -Running DRC as a precondition to command opt_design - -Starting DRC Task -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Project 1-461] DRC finished with 0 Errors -INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.496 . Memory (MB): peak = 1242.402 ; gain = 0.000 - -Starting Cache Timing Information Task -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [Timing 38-2] Deriving generated clocks -Ending Cache Timing Information Task | Checksum: b8ea7a4e - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1257.285 ; gain = 14.883 - -Starting Logic Optimization Task - -Phase 1 Retarget -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -INFO: [Opt 31-49] Retargeted 0 cell(s). -Phase 1 Retarget | Checksum: b8ea7a4e - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1342.895 ; gain = 0.000 -INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells -INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. - -Phase 2 Constant propagation -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Phase 2 Constant propagation | Checksum: b8ea7a4e - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1342.895 ; gain = 0.000 -INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells - -Phase 3 Sweep -Phase 3 Sweep | Checksum: 69d8ab95 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1342.895 ; gain = 0.000 -INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells - -Phase 4 BUFG optimization -INFO: [Opt 31-194] Inserted BUFG U0/inst/clk_out1_clk_wiz_1_BUFG_inst to drive 0 load(s) on clock net U0/inst/clk_out1_clk_wiz_1_BUFG -INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets -Phase 4 BUFG optimization | Checksum: 13bee9dc1 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 1342.895 ; gain = 0.000 -INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. - -Phase 5 Shift Register Optimization -Phase 5 Shift Register Optimization | Checksum: 1a59d5459 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.037 . Memory (MB): peak = 1342.895 ; gain = 0.000 -INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells - -Phase 6 Post Processing Netlist -Phase 6 Post Processing Netlist | Checksum: 14a40c514 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 1342.895 ; gain = 0.000 -INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells -Opt_design Change Summary -========================= - - -------------------------------------------------------------------------------------------------------------------------- -| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | -------------------------------------------------------------------------------------------------------------------------- -| Retarget | 0 | 0 | 1 | -| Constant propagation | 0 | 0 | 0 | -| Sweep | 0 | 0 | 0 | -| BUFG optimization | 0 | 0 | 0 | -| Shift Register Optimization | 0 | 0 | 0 | -| Post Processing Netlist | 0 | 0 | 0 | -------------------------------------------------------------------------------------------------------------------------- - - - -Starting Connectivity Check Task - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1342.895 ; gain = 0.000 -Ending Logic Optimization Task | Checksum: 14dbbd0bc - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.040 . Memory (MB): peak = 1342.895 ; gain = 0.000 - -Starting Power Optimization Task -INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. -Ending Power Optimization Task | Checksum: 14dbbd0bc - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1342.895 ; gain = 0.000 - -Starting Final Cleanup Task -Ending Final Cleanup Task | Checksum: 14dbbd0bc - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.895 ; gain = 0.000 - -Starting Netlist Obfuscation Task -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.895 ; gain = 0.000 -Ending Netlist Obfuscation Task | Checksum: 14dbbd0bc - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.895 ; gain = 0.000 -INFO: [Common 17-83] Releasing license: Implementation -30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -opt_design completed successfully -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.895 ; gain = 0.000 -INFO: [Timing 38-480] Writing timing data to binary archive. -Writing placer database... -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.044 . Memory (MB): peak = 1342.895 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.895 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_opt.dcp' has been generated. -INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx -Command: report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx -INFO: [IP_Flow 19-1839] IP Catalog is up to date. -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_opted.rpt. -report_drc completed successfully -Command: place_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. -Running DRC as a precondition to command place_design -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. - -Starting Placer Task -INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs - -Phase 1 Placer Initialization - -Phase 1.1 Placer Initialization Netlist Sorting -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.895 ; gain = 0.000 -Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fa6d7a79 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1342.895 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.895 ; gain = 0.000 - -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device -INFO: [Timing 38-35] Done setting XDC timing constraints. -WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. - - bouton_down_IBUF_inst (IBUF.O) is locked to IOB_X0Y1 - bouton_down_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y1 -Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. -WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. - - bouton_right_IBUF_inst (IBUF.O) is locked to IOB_X0Y36 - bouton_right_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 -Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 12622357c - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.297 . Memory (MB): peak = 1342.895 ; gain = 0.000 - -Phase 1.3 Build Placer Netlist Model -Phase 1.3 Build Placer Netlist Model | Checksum: 1b3b55d5e - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.356 . Memory (MB): peak = 1342.895 ; gain = 0.000 - -Phase 1.4 Constrain Clocks/Macros -Phase 1.4 Constrain Clocks/Macros | Checksum: 1b3b55d5e - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.357 . Memory (MB): peak = 1342.895 ; gain = 0.000 -Phase 1 Placer Initialization | Checksum: 1b3b55d5e - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.357 . Memory (MB): peak = 1342.895 ; gain = 0.000 - -Phase 2 Global Placement - -Phase 2.1 Floorplanning -Phase 2.1 Floorplanning | Checksum: 1f34e0130 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.388 . Memory (MB): peak = 1342.895 ; gain = 0.000 - -Phase 2.2 Physical Synthesis In Placer -INFO: [Physopt 32-65] No nets found for high-fanout optimization. -INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. -INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell -INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed. -INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed. -INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed. -INFO: [Physopt 32-949] No candidate nets found for HD net replication -INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1342.895 ; gain = 0.000 - -Summary of Physical Synthesis Optimizations -============================================ - - ----------------------------------------------------------------------------------------------------------------------------------------- -| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------- -| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| HD Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| Total | 0 | 0 | 0 | 0 | 2 | 00:00:00 | ----------------------------------------------------------------------------------------------------------------------------------------- - - -Phase 2.2 Physical Synthesis In Placer | Checksum: 1f822ab4a - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.902 . Memory (MB): peak = 1342.895 ; gain = 0.000 -Phase 2 Global Placement | Checksum: 17fde1b87 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.913 . Memory (MB): peak = 1342.895 ; gain = 0.000 - -Phase 3 Detail Placement - -Phase 3.1 Commit Multi Column Macros -Phase 3.1 Commit Multi Column Macros | Checksum: 17fde1b87 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.914 . Memory (MB): peak = 1342.895 ; gain = 0.000 - -Phase 3.2 Commit Most Macros & LUTRAMs -Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 258919723 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.947 . Memory (MB): peak = 1342.895 ; gain = 0.000 - -Phase 3.3 Area Swap Optimization -Phase 3.3 Area Swap Optimization | Checksum: 1af65d909 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.949 . Memory (MB): peak = 1342.895 ; gain = 0.000 - -Phase 3.4 Pipeline Register Optimization -Phase 3.4 Pipeline Register Optimization | Checksum: 245deb5d9 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.950 . Memory (MB): peak = 1342.895 ; gain = 0.000 - -Phase 3.5 Small Shape Detail Placement -Phase 3.5 Small Shape Detail Placement | Checksum: 1dab8f54b - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.895 ; gain = 0.000 - -Phase 3.6 Re-assign LUT pins -Phase 3.6 Re-assign LUT pins | Checksum: 1e1eee966 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.895 ; gain = 0.000 - -Phase 3.7 Pipeline Register Optimization -Phase 3.7 Pipeline Register Optimization | Checksum: f76e0896 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.895 ; gain = 0.000 -Phase 3 Detail Placement | Checksum: f76e0896 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.895 ; gain = 0.000 - -Phase 4 Post Placement Optimization and Clean-Up - -Phase 4.1 Post Commit Optimization -INFO: [Timing 38-35] Done setting XDC timing constraints. - -Phase 4.1.1 Post Placement Optimization -Post Placement Optimization Initialization | Checksum: 13e7bd2c2 - -Phase 4.1.1.1 BUFG Insertion -INFO: [Place 46-46] BUFG insertion identified 0 candidate nets, 0 success, 0 bufg driver replicated, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason -Phase 4.1.1.1 BUFG Insertion | Checksum: 13e7bd2c2 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.895 ; gain = 0.000 -INFO: [Place 30-746] Post Placement Timing Summary WNS=35.645. For the most accurate timing information please run report_timing. -Phase 4.1.1 Post Placement Optimization | Checksum: 15c183492 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.895 ; gain = 0.000 -Phase 4.1 Post Commit Optimization | Checksum: 15c183492 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.895 ; gain = 0.000 - -Phase 4.2 Post Placement Cleanup -Phase 4.2 Post Placement Cleanup | Checksum: 15c183492 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.895 ; gain = 0.000 - -Phase 4.3 Placer Reporting -Phase 4.3 Placer Reporting | Checksum: 15c183492 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.895 ; gain = 0.000 - -Phase 4.4 Final Placement Cleanup -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.895 ; gain = 0.000 -Phase 4.4 Final Placement Cleanup | Checksum: 17d5ce04d - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.895 ; gain = 0.000 -Phase 4 Post Placement Optimization and Clean-Up | Checksum: 17d5ce04d - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.895 ; gain = 0.000 -Ending Placer Task | Checksum: d443f812 - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1342.895 ; gain = 0.000 -INFO: [Common 17-83] Releasing license: Implementation -57 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. -place_design completed successfully -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.895 ; gain = 0.000 -INFO: [Timing 38-480] Writing timing data to binary archive. -Writing placer database... -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.043 . Memory (MB): peak = 1342.895 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.895 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_placed.dcp' has been generated. -INFO: [runtcl-4] Executing : report_io -file VGA_top_io_placed.rpt -report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 1342.895 ; gain = 0.000 -INFO: [runtcl-4] Executing : report_utilization -file VGA_top_utilization_placed.rpt -pb VGA_top_utilization_placed.pb -INFO: [runtcl-4] Executing : report_control_sets -verbose -file VGA_top_control_sets_placed.rpt -report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1342.895 ; gain = 0.000 -Command: route_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' -Running DRC as a precondition to command route_design -INFO: [DRC 23-27] Running DRC with 2 threads -WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. -Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. - This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. - - bouton_down_IBUF_inst (IBUF.O) is locked to IOB_X0Y1 - bouton_down_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y1 -WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. -Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. - This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. - - bouton_right_IBUF_inst (IBUF.O) is locked to IOB_X0Y36 - bouton_right_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 2 Warnings -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. - - -Starting Routing Task -INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs -Checksum: PlaceDB: 52480e80 ConstDB: 0 ShapeSum: 81fbe992 RouteDB: 0 - -Phase 1 Build RT Design -Phase 1 Build RT Design | Checksum: fee31c87 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1411.523 ; gain = 68.629 -Post Restoration Checksum: NetGraph: e323ff66 NumContArr: 1bbf1d21 Constraints: 0 Timing: 0 - -Phase 2 Router Initialization - -Phase 2.1 Create Timer -Phase 2.1 Create Timer | Checksum: fee31c87 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1441.797 ; gain = 98.902 - -Phase 2.2 Fix Topology Constraints -Phase 2.2 Fix Topology Constraints | Checksum: fee31c87 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1447.852 ; gain = 104.957 - -Phase 2.3 Pre Route Cleanup -Phase 2.3 Pre Route Cleanup | Checksum: fee31c87 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1447.852 ; gain = 104.957 - Number of Nodes with overlaps = 0 - -Phase 2.4 Update Timing -Phase 2.4 Update Timing | Checksum: 1441c14dd - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1451.789 ; gain = 108.895 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.769 | TNS=0.000 | WHS=-0.258 | THS=-3.023 | - -Phase 2 Router Initialization | Checksum: 173a347ed - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1451.789 ; gain = 108.895 - -Phase 3 Initial Routing -Phase 3 Initial Routing | Checksum: 205eb8b74 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1452.559 ; gain = 109.664 - -Phase 4 Rip-up And Reroute - -Phase 4.1 Global Iteration 0 - Number of Nodes with overlaps = 17 - Number of Nodes with overlaps = 0 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.132 | TNS=0.000 | WHS=N/A | THS=N/A | - -Phase 4.1 Global Iteration 0 | Checksum: 2843d0f71 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1452.559 ; gain = 109.664 -Phase 4 Rip-up And Reroute | Checksum: 2843d0f71 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1452.559 ; gain = 109.664 - -Phase 5 Delay and Skew Optimization - -Phase 5.1 Delay CleanUp -Phase 5.1 Delay CleanUp | Checksum: 2843d0f71 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1452.559 ; gain = 109.664 - -Phase 5.2 Clock Skew Optimization -Phase 5.2 Clock Skew Optimization | Checksum: 2843d0f71 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1452.559 ; gain = 109.664 -Phase 5 Delay and Skew Optimization | Checksum: 2843d0f71 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1452.559 ; gain = 109.664 - -Phase 6 Post Hold Fix - -Phase 6.1 Hold Fix Iter - -Phase 6.1.1 Update Timing -Phase 6.1.1 Update Timing | Checksum: 1adede088 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1452.559 ; gain = 109.664 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.132 | TNS=0.000 | WHS=0.069 | THS=0.000 | - -Phase 6.1 Hold Fix Iter | Checksum: 1adede088 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1452.559 ; gain = 109.664 -Phase 6 Post Hold Fix | Checksum: 1adede088 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1452.559 ; gain = 109.664 - -Phase 7 Route finalize - -Router Utilization Summary - Global Vertical Routing Utilization = 0.0615146 % - Global Horizontal Routing Utilization = 0.0558364 % - Routable Net Status* - *Does not include unroutable nets such as driverless and loadless. - Run report_route_status for detailed report. - Number of Failed Nets = 0 - Number of Unrouted Nets = 0 - Number of Partially Routed Nets = 0 - Number of Node Overlaps = 0 - -Phase 7 Route finalize | Checksum: 2005f65b4 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1452.559 ; gain = 109.664 - -Phase 8 Verifying routed nets - - Verification completed successfully -Phase 8 Verifying routed nets | Checksum: 2005f65b4 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1453.578 ; gain = 110.684 - -Phase 9 Depositing Routes -Phase 9 Depositing Routes | Checksum: 18ba5fe80 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1453.578 ; gain = 110.684 - -Phase 10 Post Router Timing -INFO: [Route 35-57] Estimated Timing Summary | WNS=35.132 | TNS=0.000 | WHS=0.069 | THS=0.000 | - -INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. -Phase 10 Post Router Timing | Checksum: 18ba5fe80 - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1453.578 ; gain = 110.684 -INFO: [Route 35-16] Router Completed Successfully - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1453.578 ; gain = 110.684 - -Routing Is Done. -INFO: [Common 17-83] Releasing license: Implementation -74 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. -route_design completed successfully -route_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1453.578 ; gain = 110.684 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1453.578 ; gain = 0.000 -INFO: [Timing 38-480] Writing timing data to binary archive. -Writing placer database... -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.055 . Memory (MB): peak = 1454.922 ; gain = 1.344 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1454.922 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_routed.dcp' has been generated. -INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx -Command: report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx -INFO: [IP_Flow 19-1839] IP Catalog is up to date. -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_routed.rpt. -report_drc completed successfully -INFO: [runtcl-4] Executing : report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx -Command: report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [DRC 23-133] Running Methodology with 2 threads -INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_methodology_drc_routed.rpt. -report_methodology completed successfully -INFO: [runtcl-4] Executing : report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx -Command: report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx -INFO: [Timing 38-35] Done setting XDC timing constraints. -Running Vector-less Activity Propagation... - -Finished Running Vector-less Activity Propagation -86 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. -report_power completed successfully -INFO: [runtcl-4] Executing : report_route_status -file VGA_top_route_status.rpt -pb VGA_top_route_status.pb -INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file VGA_top_timing_summary_routed.rpt -pb VGA_top_timing_summary_routed.pb -rpx VGA_top_timing_summary_routed.rpx -warn_on_violation -INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. -INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs -INFO: [runtcl-4] Executing : report_incremental_reuse -file VGA_top_incremental_reuse_routed.rpt -INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. -INFO: [runtcl-4] Executing : report_clock_utilization -file VGA_top_clock_utilization_routed.rpt -INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file VGA_top_bus_skew_routed.rpt -pb VGA_top_bus_skew_routed.pb -rpx VGA_top_bus_skew_routed.rpx -INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. -INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs -INFO: [Common 17-206] Exiting Vivado at Tue Nov 23 10:15:11 2021... diff --git a/projet-vga.runs/impl_1/VGA_top_bus_skew_routed.rpt b/projet-vga.runs/impl_1/VGA_top_bus_skew_routed.rpt index 9e6334a..a084666 100644 --- a/projet-vga.runs/impl_1/VGA_top_bus_skew_routed.rpt +++ b/projet-vga.runs/impl_1/VGA_top_bus_skew_routed.rpt @@ -1,8 +1,8 @@ Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------------------------------------ | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 -| Date : Tue Dec 7 12:43:48 2021 -| Host : irb121-02-w running 64-bit major release (build 9200) +| Date : Tue Jan 4 12:21:25 2022 +| Host : irb121-12-w running 64-bit major release (build 9200) | Command : report_bus_skew -warn_on_violation -file VGA_top_bus_skew_routed.rpt -pb VGA_top_bus_skew_routed.pb -rpx VGA_top_bus_skew_routed.rpx | Design : VGA_top | Device : 7z010-clg400 diff --git a/projet-vga.runs/impl_1/VGA_top_bus_skew_routed.rpx b/projet-vga.runs/impl_1/VGA_top_bus_skew_routed.rpx index da94f91..e3f68b6 100644 Binary files a/projet-vga.runs/impl_1/VGA_top_bus_skew_routed.rpx and b/projet-vga.runs/impl_1/VGA_top_bus_skew_routed.rpx differ diff --git a/projet-vga.runs/impl_1/VGA_top_clock_utilization_routed.rpt b/projet-vga.runs/impl_1/VGA_top_clock_utilization_routed.rpt index 10b0037..16ebf64 100644 --- a/projet-vga.runs/impl_1/VGA_top_clock_utilization_routed.rpt +++ b/projet-vga.runs/impl_1/VGA_top_clock_utilization_routed.rpt @@ -1,8 +1,8 @@ Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------- | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 -| Date : Tue Dec 7 12:43:48 2021 -| Host : irb121-02-w running 64-bit major release (build 9200) +| Date : Tue Jan 4 12:21:25 2022 +| Host : irb121-12-w running 64-bit major release (build 9200) | Command : report_clock_utilization -file VGA_top_clock_utilization_routed.rpt | Design : VGA_top | Device : 7z010-clg400 @@ -16,12 +16,15 @@ Table of Contents 1. Clock Primitive Utilization 2. Global Clock Resources 3. Global Clock Source Details -4. Clock Regions: Key Resource Utilization -5. Clock Regions : Global Clock Summary -6. Device Cell Placement Summary for Global Clock g0 -7. Device Cell Placement Summary for Global Clock g1 -8. Clock Region Cell Placement per Global Clock: Region X1Y0 -9. Clock Region Cell Placement per Global Clock: Region X1Y1 +4. Local Clock Details +5. Clock Regions: Key Resource Utilization +6. Clock Regions : Global Clock Summary +7. Device Cell Placement Summary for Global Clock g0 +8. Device Cell Placement Summary for Global Clock g1 +9. Device Cell Placement Summary for Global Clock g2 +10. Clock Region Cell Placement per Global Clock: Region X0Y0 +11. Clock Region Cell Placement per Global Clock: Region X1Y0 +12. Clock Region Cell Placement per Global Clock: Region X1Y1 1. Clock Primitive Utilization ------------------------------ @@ -29,7 +32,7 @@ Table of Contents +----------+------+-----------+-----+--------------+--------+ | Type | Used | Available | LOC | Clock Region | Pblock | +----------+------+-----------+-----+--------------+--------+ -| BUFGCTRL | 2 | 32 | 0 | 0 | 0 | +| BUFGCTRL | 3 | 32 | 0 | 0 | 0 | | BUFH | 0 | 48 | 0 | 0 | 0 | | BUFIO | 0 | 8 | 0 | 0 | 0 | | BUFMR | 0 | 4 | 0 | 0 | 0 | @@ -42,12 +45,13 @@ Table of Contents 2. Global Clock Resources ------------------------- -+-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+----------+-----------------------+--------------------------------+ -| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | -+-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+----------+-----------------------+--------------------------------+ -| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y16 | n/a | 2 | 21 | 0 | 40.000 | Multiple | U0/inst/clkout1_buf/O | U0/inst/clk_out1 | -| g1 | src0 | BUFG/O | None | BUFGCTRL_X0Y17 | n/a | 1 | 1 | 0 | 40.000 | Multiple | U0/inst/clkf_buf/O | U0/inst/clkfbout_buf_clk_wiz_1 | -+-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+----------+-----------------------+--------------------------------+ ++-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+--------------------+--------------------------+--------------------------------+ +| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+--------------------+--------------------------+--------------------------------+ +| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y16 | n/a | 3 | 184 | 0 | 8.000 | sys_clk_pin | H125MHz_IBUF_BUFG_inst/O | H125MHz_IBUF_BUFG | +| g1 | src1 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 3 | 60 | 0 | 40.000 | clk_out1_clk_wiz_1 | U0/inst/clkout1_buf/O | U0/inst/clk_out1 | +| g2 | src1 | BUFG/O | None | BUFGCTRL_X0Y1 | n/a | 1 | 1 | 0 | 40.000 | clkfbout_clk_wiz_1 | U0/inst/clkf_buf/O | U0/inst/clkfbout_buf_clk_wiz_1 | ++-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+--------------------+--------------------------+--------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) @@ -55,17 +59,31 @@ Table of Contents 3. Global Clock Source Details ------------------------------ -+-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------+--------------------------------+----------------------------+ -| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | -+-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------+--------------------------------+----------------------------+ -| src0 | g0 | MMCME2_ADV/CLKOUT0 | None | MMCME2_ADV_X0Y1 | X1Y1 | 1 | 0 | 40.000 | Multiple | U0/inst/mmcm_adv_inst/CLKOUT0 | U0/inst/clk_out1_clk_wiz_1 | -| src0 | g1 | MMCME2_ADV/CLKFBOUT | None | MMCME2_ADV_X0Y1 | X1Y1 | 1 | 0 | 40.000 | Multiple | U0/inst/mmcm_adv_inst/CLKFBOUT | U0/inst/clkfbout_clk_wiz_1 | -+-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------+--------------------------------+----------------------------+ ++-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------------+--------------------------------+----------------------------+ +| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | ++-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------------+--------------------------------+----------------------------+ +| src0 | g0 | IBUF/O | IOB_X0Y78 | IOB_X0Y78 | X1Y1 | 1 | 0 | 8.000 | sys_clk_pin | H125MHz_IBUF_inst/O | H125MHz_IBUF | +| src1 | g1 | MMCME2_ADV/CLKOUT0 | None | MMCME2_ADV_X0Y0 | X1Y0 | 1 | 0 | 40.000 | clk_out1_clk_wiz_1 | U0/inst/mmcm_adv_inst/CLKOUT0 | U0/inst/clk_out1_clk_wiz_1 | +| src1 | g2 | MMCME2_ADV/CLKFBOUT | None | MMCME2_ADV_X0Y0 | X1Y0 | 1 | 0 | 40.000 | clkfbout_clk_wiz_1 | U0/inst/mmcm_adv_inst/CLKFBOUT | U0/inst/clkfbout_clk_wiz_1 | ++-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------------+--------------------------------+----------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) -4. Clock Regions: Key Resource Utilization +4. Local Clock Details +---------------------- + ++----------+-----------------+------------+------------------+--------------+-------------+-----------------+--------------+-------+------------------+------------+ +| Local Id | Driver Type/Pin | Constraint | Site/BEL | Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | ++----------+-----------------+------------+------------------+--------------+-------------+-----------------+--------------+-------+------------------+------------|| +| 0 | FDRE/Q | None | SLICE_X8Y34/A5FF | X0Y0 | 17 | 29 | | | UPD/update_reg/Q | UPD/update - Static - ++----------+-----------------+------------+------------------+--------------+-------------+-----------------+--------------+-------+------------------+------------|| +* Local Clocks in this context represents only clocks driven by non-global buffers +** Clock Loads column represents the clock pin loads (pin count) +*** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +5. Clock Regions: Key Resource Utilization ------------------------------------------ +-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ @@ -73,15 +91,15 @@ Table of Contents +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ | Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ -| X0Y0 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1100 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | -| X1Y0 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 3 | 1100 | 1 | 350 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y0 | 2 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 76 | 1100 | 63 | 400 | 1 | 20 | 6 | 10 | 0 | 20 | +| X1Y0 | 3 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 80 | 1100 | 29 | 350 | 3 | 40 | 12 | 20 | 0 | 20 | | X0Y1 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1100 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | -| X1Y1 | 2 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 18 | 1100 | 3 | 350 | 0 | 40 | 0 | 20 | 0 | 20 | +| X1Y1 | 2 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 33 | 1100 | 8 | 350 | 0 | 40 | 0 | 20 | 0 | 20 | +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ * Global Clock column represents track count; while other columns represents cell counts -5. Clock Regions : Global Clock Summary +6. Clock Regions : Global Clock Summary --------------------------------------- All Modules @@ -89,40 +107,62 @@ All Modules | | X0 | X1 | +----+----+----+ | Y1 | 0 | 2 | -| Y0 | 0 | 1 | +| Y0 | 2 | 3 | +----+----+----+ -6. Device Cell Placement Summary for Global Clock g0 +7. Device Cell Placement Summary for Global Clock g0 ---------------------------------------------------- -+-----------+-----------------+-------------------+----------+-------------+----------------+-------------+----------+----------------+----------+------------------+ -| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | -+-----------+-----------------+-------------------+----------+-------------+----------------+-------------+----------+----------------+----------+------------------+ -| g0 | BUFG/O | n/a | Multiple | 40.000 | {0.000 20.000} | 21 | 0 | 0 | 0 | U0/inst/clk_out1 | -+-----------+-----------------+-------------------+----------+-------------+----------------+-------------+----------+----------------+----------+------------------+ ++-----------+-----------------+-------------------+-------------+-------------+---------------+-------------+----------+----------------+----------+-------------------+ +| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | ++-----------+-----------------+-------------------+-------------+-------------+---------------+-------------+----------+----------------+----------+-------------------+ +| g0 | BUFG/O | n/a | sys_clk_pin | 8.000 | {0.000 4.000} | 156 | 0 | 1 | 0 | H125MHz_IBUF_BUFG | ++-----------+-----------------+-------------------+-------------+-------------+---------------+-------------+----------+----------------+----------+-------------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types -+----+----+-----+ -| | X0 | X1 | -+----+----+-----+ -| Y1 | 0 | 18 | -| Y0 | 0 | 3 | -+----+----+-----+ ++----+-----+-----+ +| | X0 | X1 | ++----+-----+-----+ +| Y1 | 0 | 8 | +| Y0 | 74 | 75 | ++----+-----+-----+ -7. Device Cell Placement Summary for Global Clock g1 +8. Device Cell Placement Summary for Global Clock g1 ---------------------------------------------------- -+-----------+-----------------+-------------------+----------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+ -| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | -+-----------+-----------------+-------------------+----------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+ -| g1 | BUFG/O | n/a | Multiple | 40.000 | {0.000 20.000} | 0 | 0 | 1 | 0 | U0/inst/clkfbout_buf_clk_wiz_1 | -+-----------+-----------------+-------------------+----------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+ ++-----------+-----------------+-------------------+--------------------+-------------+----------------+-------------+----------+----------------+----------+------------------+ +| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | ++-----------+-----------------+-------------------+--------------------+-------------+----------------+-------------+----------+----------------+----------+------------------+ +| g1 | BUFG/O | n/a | clk_out1_clk_wiz_1 | 40.000 | {0.000 20.000} | 60 | 0 | 0 | 0 | U0/inst/clk_out1 | ++-----------+-----------------+-------------------+--------------------+-------------+----------------+-------------+----------+----------------+----------+------------------+ +* Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources +** IO Loads column represents load cell count of IO types +*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) +**** GT Loads column represents load cell count of GT types + + ++----+-----+-----+ +| | X0 | X1 | ++----+-----+-----+ +| Y1 | 0 | 25 | +| Y0 | 10 | 25 | ++----+-----+-----+ + + +9. Device Cell Placement Summary for Global Clock g2 +---------------------------------------------------- + ++-----------+-----------------+-------------------+--------------------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+ +| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | ++-----------+-----------------+-------------------+--------------------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+ +| g2 | BUFG/O | n/a | clkfbout_clk_wiz_1 | 40.000 | {0.000 20.000} | 0 | 0 | 1 | 0 | U0/inst/clkfbout_buf_clk_wiz_1 | ++-----------+-----------------+-------------------+--------------------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) @@ -132,51 +172,75 @@ All Modules +----+----+----+ | | X0 | X1 | +----+----+----+ -| Y1 | 0 | 1 | -| Y0 | 0 | 0 | +| Y1 | 0 | 0 | +| Y0 | 0 | 1 | +----+----+----+ -8. Clock Region Cell Placement per Global Clock: Region X1Y0 ------------------------------------------------------------- +10. Clock Region Cell Placement per Global Clock: Region X0Y0 +------------------------------------------------------------- -+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+------------------+ -| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | -+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+------------------+ -| g0 | n/a | BUFG/O | None | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | U0/inst/clk_out1 | -+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+------------------+ ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------+ +| g0 | n/a | BUFG/O | None | 74 | 0 | 66 | 0 | 7 | 0 | 0 | 0 | 0 | 0 | H125MHz_IBUF_BUFG | +| g1 | n/a | BUFG/O | None | 10 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | U0/inst/clk_out1 | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts -9. Clock Region Cell Placement per Global Clock: Region X1Y1 ------------------------------------------------------------- +11. Clock Region Cell Placement per Global Clock: Region X1Y0 +------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+--------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+--------------------------------+ -| g0 | n/a | BUFG/O | None | 18 | 0 | 18 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | U0/inst/clk_out1 | -| g1 | n/a | BUFG/O | None | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | U0/inst/clkfbout_buf_clk_wiz_1 | +| g0 | n/a | BUFG/O | None | 75 | 0 | 55 | 0 | 15 | 0 | 0 | 1 | 0 | 0 | H125MHz_IBUF_BUFG | +| g1 | n/a | BUFG/O | None | 25 | 0 | 25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | U0/inst/clk_out1 | +| g2 | n/a | BUFG/O | None | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | U0/inst/clkfbout_buf_clk_wiz_1 | +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+--------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts +12. Clock Region Cell Placement per Global Clock: Region X1Y1 +------------------------------------------------------------- + ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------+ +| g0 | n/a | BUFG/O | None | 8 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | H125MHz_IBUF_BUFG | +| g1 | n/a | BUFG/O | None | 25 | 0 | 25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | U0/inst/clk_out1 | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) +*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts + + # Location of BUFG Primitives -set_property LOC BUFGCTRL_X0Y17 [get_cells U0/inst/clkf_buf] -set_property LOC BUFGCTRL_X0Y16 [get_cells U0/inst/clkout1_buf] +set_property LOC BUFGCTRL_X0Y1 [get_cells U0/inst/clkf_buf] +set_property LOC BUFGCTRL_X0Y0 [get_cells U0/inst/clkout1_buf] +set_property LOC BUFGCTRL_X0Y16 [get_cells H125MHz_IBUF_BUFG_inst] # Location of IO Primitives which is load of clock spine # Location of clock ports set_property LOC IOB_X0Y78 [get_ports H125MHz] -# Clock net "U0/inst/clk_out1" driven by instance "U0/inst/clkout1_buf" located at site "BUFGCTRL_X0Y16" +# Clock net "U0/inst/clk_out1" driven by instance "U0/inst/clkout1_buf" located at site "BUFGCTRL_X0Y0" #startgroup create_pblock {CLKAG_U0/inst/clk_out1} add_cells_to_pblock [get_pblocks {CLKAG_U0/inst/clk_out1}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="U0/inst/clk_out1"}]]] -resize_pblock [get_pblocks {CLKAG_U0/inst/clk_out1}] -add {CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1} +resize_pblock [get_pblocks {CLKAG_U0/inst/clk_out1}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1} +#endgroup + +# Clock net "H125MHz_IBUF_BUFG" driven by instance "H125MHz_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y16" +#startgroup +create_pblock {CLKAG_H125MHz_IBUF_BUFG} +add_cells_to_pblock [get_pblocks {CLKAG_H125MHz_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL && NAME!=U0/inst/mmcm_adv_inst} -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="H125MHz_IBUF_BUFG"}]]] +resize_pblock [get_pblocks {CLKAG_H125MHz_IBUF_BUFG}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1} #endgroup diff --git a/projet-vga.runs/impl_1/VGA_top_control_sets_placed.rpt b/projet-vga.runs/impl_1/VGA_top_control_sets_placed.rpt index 22eb69e..5fd1796 100644 --- a/projet-vga.runs/impl_1/VGA_top_control_sets_placed.rpt +++ b/projet-vga.runs/impl_1/VGA_top_control_sets_placed.rpt @@ -1,8 +1,8 @@ Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------ | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 -| Date : Tue Dec 7 12:43:23 2021 -| Host : irb121-02-w running 64-bit major release (build 9200) +| Date : Tue Jan 4 12:19:29 2022 +| Host : irb121-12-w running 64-bit major release (build 9200) | Command : report_control_sets -verbose -file VGA_top_control_sets_placed.rpt | Design : VGA_top | Device : xc7z010 @@ -23,8 +23,8 @@ Table of Contents +----------------------------------------------------------+-------+ | Status | Count | +----------------------------------------------------------+-------+ -| Number of unique control sets | 2 | -| Unused register locations in slices containing registers | 11 | +| Number of unique control sets | 31 | +| Unused register locations in slices containing registers | 180 | +----------------------------------------------------------+-------+ @@ -34,8 +34,14 @@ Table of Contents +--------+--------------+ | Fanout | Control Sets | +--------+--------------+ -| 10 | 1 | -| 11 | 1 | +| 1 | 17 | +| 3 | 2 | +| 4 | 2 | +| 10 | 2 | +| 11 | 2 | +| 13 | 1 | +| 14 | 1 | +| 16+ | 4 | +--------+--------------+ @@ -45,23 +51,52 @@ Table of Contents +--------------+-----------------------+------------------------+-----------------+--------------+ | Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices | +--------------+-----------------------+------------------------+-----------------+--------------+ -| No | No | No | 0 | 0 | -| No | No | Yes | 0 | 0 | -| No | Yes | No | 11 | 4 | -| Yes | No | No | 0 | 0 | -| Yes | No | Yes | 0 | 0 | -| Yes | Yes | No | 10 | 5 | +| No | No | No | 71 | 29 | +| No | No | Yes | 40 | 13 | +| No | Yes | No | 34 | 21 | +| Yes | No | No | 25 | 12 | +| Yes | No | Yes | 32 | 18 | +| Yes | Yes | No | 10 | 6 | +--------------+-----------------------+------------------------+-----------------+--------------+ 4. Detailed Control Set Information ----------------------------------- -+-------------------+---------------+------------------+------------------+----------------+ -| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | -+-------------------+---------------+------------------+------------------+----------------+ -| U0/inst/clk_out1 | U1/eqOp | U1/comptY | 5 | 10 | -| U0/inst/clk_out1 | | U1/clear | 4 | 11 | -+-------------------+---------------+------------------+------------------+----------------+ ++----------------------------------+------------------------+---------------------------------------+------------------+----------------+ +| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | ++----------------------------------+------------------------+---------------------------------------+------------------+----------------+ +| U0/inst/clk_out1 | | SNAKE/startUpdate_i_2_n_0 | 1 | 1 | +| UPD/dataOut_reg[19]_LDC_i_1_n_0 | | UPD/dataOut_reg[19]_LDC_i_2_n_0 | 1 | 1 | +| UPD/dataOut_reg[18]_LDC_i_1_n_0 | | UPD/dataOut_reg[18]_LDC_i_2_n_0 | 1 | 1 | +| UPD/dataOut_reg[1]_LDC_i_1_n_0 | | UPD/dataOut_reg[1]_LDC_i_2_n_0 | 1 | 1 | +| UPD/dataOut_reg[4]_LDC_i_1_n_0 | | UPD/dataOut_reg[4]_LDC_i_2_n_0 | 1 | 1 | +| UPD/dataOut_reg[21]_LDC_i_1_n_0 | | UPD/dataOut_reg[21]_LDC_i_2_n_0 | 1 | 1 | +| UPD/dataOut_reg[20]_LDC_i_1_n_0 | | UPD/dataOut_reg[20]_LDC_i_2_n_0 | 1 | 1 | +| H125MHz_IBUF_BUFG | UPD/dataOut[2]_i_1_n_0 | UPD/dataOut_reg[19]_LDC_i_1_n_0 | 1 | 1 | +| H125MHz_IBUF_BUFG | UPD/dataOut[2]_i_1_n_0 | UPD/dataOut_reg[18]_LDC_i_1_n_0 | 1 | 1 | +| H125MHz_IBUF_BUFG | UPD/dataOut[2]_i_1_n_0 | UPD/dataOut_reg[1]_LDC_i_1_n_0 | 1 | 1 | +| H125MHz_IBUF_BUFG | UPD/dataOut[2]_i_1_n_0 | UPD/dataOut_reg[21]_LDC_i_2_n_0 | 1 | 1 | +| H125MHz_IBUF_BUFG | UPD/dataOut[2]_i_1_n_0 | UPD/dataOut_reg[21]_LDC_i_1_n_0 | 1 | 1 | +| H125MHz_IBUF_BUFG | UPD/dataOut[2]_i_1_n_0 | UPD/dataOut_reg[20]_LDC_i_2_n_0 | 1 | 1 | +| H125MHz_IBUF_BUFG | UPD/dataOut[2]_i_1_n_0 | UPD/dataOut_reg[18]_LDC_i_2_n_0 | 1 | 1 | +| H125MHz_IBUF_BUFG | UPD/dataOut[2]_i_1_n_0 | UPD/dataOut_reg[19]_LDC_i_2_n_0 | 1 | 1 | +| H125MHz_IBUF_BUFG | UPD/dataOut[2]_i_1_n_0 | UPD/dataOut_reg[20]_LDC_i_1_n_0 | 1 | 1 | +| H125MHz_IBUF_BUFG | UPD/dataOut[2]_i_1_n_0 | UPD/dataOut_reg[1]_LDC_i_2_n_0 | 1 | 1 | +| H125MHz_IBUF_BUFG | UPD/dataOut[2]_i_1_n_0 | UPD/dataOut_reg[4]_LDC_i_1_n_0 | 1 | 3 | +| H125MHz_IBUF_BUFG | UPD/dataOut[2]_i_1_n_0 | UPD/dataOut_reg[4]_LDC_i_2_n_0 | 1 | 3 | +| H125MHz_IBUF_BUFG | | SNAKE/Q[0] | 4 | 4 | +| H125MHz_IBUF_BUFG | UPD/update | | 2 | 4 | +| U0/inst/clk_out1 | SYNC/eqOp | SYNC/comptY | 6 | 10 | +| H125MHz_IBUF_BUFG | RAMCTRL/SNAKE_RAM/E[0] | | 3 | 10 | +| U0/inst/clk_out1 | | SYNC/clear | 6 | 11 | +| H125MHz_IBUF_BUFG | SNAKE/cCaseX0 | | 7 | 11 | +| U0/inst/clk_out1 | | SNAKE/AR[0] | 4 | 13 | +| H125MHz_IBUF_BUFG | | SNAKE/AR[0] | 6 | 14 | +| H125MHz_IBUF_BUFG | UPD/dataOut[2]_i_1_n_0 | UPD/currentSnake_reg[dirY][0]_i_2_n_0 | 6 | 16 | +| ~UPD/update | | | 5 | 17 | +| U0/inst/clk_out1 | | UPD_CLK_DIV/temp[0]_i_2_n_0 | 7 | 25 | +| H125MHz_IBUF_BUFG | | | 24 | 54 | ++----------------------------------+------------------------+---------------------------------------+------------------+----------------+ diff --git a/projet-vga.runs/impl_1/VGA_top_drc_opted.rpt b/projet-vga.runs/impl_1/VGA_top_drc_opted.rpt index 3a757a1..b9cc418 100644 --- a/projet-vga.runs/impl_1/VGA_top_drc_opted.rpt +++ b/projet-vga.runs/impl_1/VGA_top_drc_opted.rpt @@ -1,8 +1,8 @@ Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------ | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 -| Date : Tue Dec 7 12:43:21 2021 -| Host : irb121-02-w running 64-bit major release (build 9200) +| Date : Tue Jan 4 12:19:12 2022 +| Host : irb121-12-w running 64-bit major release (build 9200) | Command : report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx | Design : VGA_top | Device : xc7z010clg400-1 diff --git a/projet-vga.runs/impl_1/VGA_top_drc_routed.pb b/projet-vga.runs/impl_1/VGA_top_drc_routed.pb index 70698d1..c507787 100644 Binary files a/projet-vga.runs/impl_1/VGA_top_drc_routed.pb and b/projet-vga.runs/impl_1/VGA_top_drc_routed.pb differ diff --git a/projet-vga.runs/impl_1/VGA_top_drc_routed.rpt b/projet-vga.runs/impl_1/VGA_top_drc_routed.rpt index b3c363b..438d272 100644 --- a/projet-vga.runs/impl_1/VGA_top_drc_routed.rpt +++ b/projet-vga.runs/impl_1/VGA_top_drc_routed.rpt @@ -1,8 +1,8 @@ Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 -| Date : Tue Dec 7 12:43:47 2021 -| Host : irb121-02-w running 64-bit major release (build 9200) +| Date : Tue Jan 4 12:21:22 2022 +| Host : irb121-12-w running 64-bit major release (build 9200) | Command : report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx | Design : VGA_top | Device : xc7z010clg400-1 @@ -24,15 +24,46 @@ Table of Contents Design limits: Ruledeck: default Max violations: - Violations found: 1 -+--------+----------+--------------------+------------+ -| Rule | Severity | Description | Violations | -+--------+----------+--------------------+------------+ -| ZPS7-1 | Warning | PS7 block required | 1 | -+--------+----------+--------------------+------------+ + Violations found: 7 ++----------+----------+--------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+----------+--------------------+------------+ +| PDRC-153 | Warning | Gated clock check | 6 | +| ZPS7-1 | Warning | PS7 block required | 1 | ++----------+----------+--------------------+------------+ 2. REPORT DETAILS ----------------- +PDRC-153#1 Warning +Gated clock check +Net UPD/dataOut_reg[18]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin UPD/dataOut_reg[18]_LDC_i_1/O, cell UPD/dataOut_reg[18]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#2 Warning +Gated clock check +Net UPD/dataOut_reg[19]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin UPD/dataOut_reg[19]_LDC_i_1/O, cell UPD/dataOut_reg[19]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#3 Warning +Gated clock check +Net UPD/dataOut_reg[1]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin UPD/dataOut_reg[1]_LDC_i_1/O, cell UPD/dataOut_reg[1]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#4 Warning +Gated clock check +Net UPD/dataOut_reg[20]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin UPD/dataOut_reg[20]_LDC_i_1/O, cell UPD/dataOut_reg[20]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#5 Warning +Gated clock check +Net UPD/dataOut_reg[21]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin UPD/dataOut_reg[21]_LDC_i_1/O, cell UPD/dataOut_reg[21]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#6 Warning +Gated clock check +Net UPD/dataOut_reg[4]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin UPD/dataOut_reg[4]_LDC_i_1/O, cell UPD/dataOut_reg[4]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + ZPS7-1#1 Warning PS7 block required The PS7 cell must be used in this Zynq design in order to enable correct default configuration. diff --git a/projet-vga.runs/impl_1/VGA_top_drc_routed.rpx b/projet-vga.runs/impl_1/VGA_top_drc_routed.rpx index 41563fa..5e32a3c 100644 Binary files a/projet-vga.runs/impl_1/VGA_top_drc_routed.rpx and b/projet-vga.runs/impl_1/VGA_top_drc_routed.rpx differ diff --git a/projet-vga.runs/impl_1/VGA_top_io_placed.rpt b/projet-vga.runs/impl_1/VGA_top_io_placed.rpt index 41c7492..b69abae 100644 --- a/projet-vga.runs/impl_1/VGA_top_io_placed.rpt +++ b/projet-vga.runs/impl_1/VGA_top_io_placed.rpt @@ -1,8 +1,8 @@ Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 -| Date : Tue Dec 7 12:43:23 2021 -| Host : irb121-02-w running 64-bit major release (build 9200) +| Date : Tue Jan 4 12:19:29 2022 +| Host : irb121-12-w running 64-bit major release (build 9200) | Command : report_io -file VGA_top_io_placed.rpt | Design : VGA_top | Device : xc7z010 @@ -112,7 +112,7 @@ Table of Contents | D15 | | | PS_MIO33_501 | PSS IO | | | | | | | | | | | | | | | | | D16 | | | PS_MIO46_501 | PSS IO | | | | | | | | | | | | | | | | | D17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| D18 | | High Range | IO_L3N_T0_DQS_AD1N_35 | User IO | | 35 | | | | | | | | | | | | | | +| D18 | led[3] | High Range | IO_L3N_T0_DQS_AD1N_35 | TRISTATE | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | | D19 | | High Range | IO_L4P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | | D20 | | High Range | IO_L4N_T0_35 | User IO | | 35 | | | | | | | | | | | | | | | E1 | | | PS_DDR_DQ7_502 | PSS IO | | | | | | | | | | | | | | | | @@ -168,7 +168,7 @@ Table of Contents | G11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | | G12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | G13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| G14 | | High Range | IO_0_35 | User IO | | 35 | | | | | | | | | | | | | | +| G14 | led[2] | High Range | IO_0_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | | G15 | resetGeneral | High Range | IO_L19N_T3_VREF_35 | INPUT | LVCMOS33 | 35 | | | | NONE | | FIXED | | | | NONE | | | | | G16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | G17 | | High Range | IO_L16P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | @@ -268,8 +268,8 @@ Table of Contents | M11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | M12 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | | M13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| M14 | | High Range | IO_L23P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | -| M15 | | High Range | IO_L23N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| M14 | led[0] | High Range | IO_L23P_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| M15 | led[1] | High Range | IO_L23N_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | | M16 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | | M17 | | High Range | IO_L8P_T1_AD10P_35 | User IO | | 35 | | | | | | | | | | | | | | | M18 | | High Range | IO_L8N_T1_AD10N_35 | User IO | | 35 | | | | | | | | | | | | | | @@ -310,7 +310,7 @@ Table of Contents | P13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | P14 | | High Range | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | | P15 | | High Range | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | -| P16 | bouton_down | High Range | IO_L24N_T3_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| P16 | | High Range | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | | P17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | P18 | | High Range | IO_L23N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | | P19 | vga_hs | High Range | IO_L13N_T2_MRCC_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | @@ -332,7 +332,7 @@ Table of Contents | R15 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | | R16 | | High Range | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | | R17 | | High Range | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | -| R18 | bouton_up | High Range | IO_L20N_T3_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| R18 | | High Range | IO_L20N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | | R19 | vga_vs | High Range | IO_0_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | | R20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | T1 | | | PS_DDR_DM2_502 | PSS IO | | | | | | | | | | | | | | | | @@ -390,7 +390,7 @@ Table of Contents | V13 | | High Range | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | | V14 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | | V15 | | High Range | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | -| V16 | bouton_left | High Range | IO_L18P_T2_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| V16 | | High Range | IO_L18P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | | V17 | | High Range | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | | V18 | | High Range | IO_L21N_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | | V19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | @@ -430,7 +430,7 @@ Table of Contents | Y13 | | | NC | Not Connected | | | | | | | | | | | | | | | | | Y14 | | High Range | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | | Y15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| Y16 | bouton_right | High Range | IO_L7P_T1_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| Y16 | | High Range | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | | Y17 | | High Range | IO_L7N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | | Y18 | | High Range | IO_L17P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | | Y19 | | High Range | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | diff --git a/projet-vga.runs/impl_1/VGA_top_methodology_drc_routed.pb b/projet-vga.runs/impl_1/VGA_top_methodology_drc_routed.pb index dd2b1ec..3c98bf3 100644 Binary files a/projet-vga.runs/impl_1/VGA_top_methodology_drc_routed.pb and b/projet-vga.runs/impl_1/VGA_top_methodology_drc_routed.pb differ diff --git a/projet-vga.runs/impl_1/VGA_top_methodology_drc_routed.rpt b/projet-vga.runs/impl_1/VGA_top_methodology_drc_routed.rpt index 45a523b..bf5c5de 100644 --- a/projet-vga.runs/impl_1/VGA_top_methodology_drc_routed.rpt +++ b/projet-vga.runs/impl_1/VGA_top_methodology_drc_routed.rpt @@ -1,8 +1,8 @@ Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 -| Date : Tue Dec 7 12:43:47 2021 -| Host : irb121-02-w running 64-bit major release (build 9200) +| Date : Tue Jan 4 12:21:24 2022 +| Host : irb121-12-w running 64-bit major release (build 9200) | Command : report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx | Design : VGA_top | Device : xc7z010clg400-1 @@ -23,23 +23,496 @@ Table of Contents Floorplan: design_1 Design limits: Max violations: - Violations found: 2 -+----------+----------+------------------------------------------------+------------+ -| Rule | Severity | Description | Violations | -+----------+----------+------------------------------------------------+------------+ -| TIMING-6 | Warning | No common primary clock between related clocks | 2 | -+----------+----------+------------------------------------------------+------------+ + Violations found: 95 ++-----------+----------+----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++-----------+----------+----------------------------------------------------+------------+ +| LUTAR-1 | Warning | LUT drives async reset alert | 14 | +| SYNTH-6 | Warning | Timing of a block RAM might be sub-optimal | 26 | +| TIMING-4 | Warning | Invalid primary clock redefinition on a clock tree | 1 | +| TIMING-6 | Warning | No common primary clock between related clocks | 2 | +| TIMING-7 | Warning | No common node between related clocks | 2 | +| TIMING-16 | Warning | Large setup violation | 21 | +| TIMING-18 | Warning | Missing input or output delay | 5 | +| TIMING-20 | Warning | Non-clocked latch | 23 | +| TIMING-27 | Warning | Invalid primary clock on hierarchical pin | 1 | ++-----------+----------+----------------------------------------------------+------------+ 2. REPORT DETAILS ----------------- +LUTAR-1#1 Warning +LUT drives async reset alert +LUT cell SNAKE/startUpdate_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) SNAKE/startUpdate_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#2 Warning +LUT drives async reset alert +LUT cell UPD/dataOut_reg[18]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) UPD/dataOut_reg[18]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#3 Warning +LUT drives async reset alert +LUT cell UPD/dataOut_reg[18]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) UPD/dataOut_reg[18]_C/CLR, UPD/dataOut_reg[18]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#4 Warning +LUT drives async reset alert +LUT cell UPD/dataOut_reg[19]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) UPD/dataOut_reg[19]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#5 Warning +LUT drives async reset alert +LUT cell UPD/dataOut_reg[19]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) UPD/dataOut_reg[19]_C/CLR, UPD/dataOut_reg[19]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#6 Warning +LUT drives async reset alert +LUT cell UPD/dataOut_reg[1]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) UPD/dataOut_reg[1]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#7 Warning +LUT drives async reset alert +LUT cell UPD/dataOut_reg[1]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) UPD/dataOut_reg[1]_C/CLR, UPD/dataOut_reg[1]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#8 Warning +LUT drives async reset alert +LUT cell UPD/dataOut_reg[20]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) UPD/dataOut_reg[20]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#9 Warning +LUT drives async reset alert +LUT cell UPD/dataOut_reg[20]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) UPD/dataOut_reg[20]_C/CLR, UPD/dataOut_reg[20]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#10 Warning +LUT drives async reset alert +LUT cell UPD/dataOut_reg[21]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) UPD/dataOut_reg[21]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#11 Warning +LUT drives async reset alert +LUT cell UPD/dataOut_reg[21]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) UPD/dataOut_reg[21]_C/CLR, UPD/dataOut_reg[21]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#12 Warning +LUT drives async reset alert +LUT cell UPD/dataOut_reg[4]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) UPD/dataOut_reg[0]_P/PRE, UPD/dataOut_reg[3]_P/PRE, UPD/dataOut_reg[4]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#13 Warning +LUT drives async reset alert +LUT cell UPD/dataOut_reg[4]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) UPD/dataOut_reg[0]_C/CLR, UPD/dataOut_reg[3]_C/CLR, UPD/dataOut_reg[4]_C/CLR, UPD/dataOut_reg[4]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#14 Warning +LUT drives async reset alert +LUT cell UPD_CLK_DIV/temp[0]_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) UPD_CLK_DIV/temp_reg[0]/CLR, UPD_CLK_DIV/temp_reg[10]/CLR, UPD_CLK_DIV/temp_reg[11]/CLR, UPD_CLK_DIV/temp_reg[12]/CLR, UPD_CLK_DIV/temp_reg[13]/CLR, UPD_CLK_DIV/temp_reg[14]/CLR, UPD_CLK_DIV/temp_reg[15]/CLR, UPD_CLK_DIV/temp_reg[16]/CLR, UPD_CLK_DIV/temp_reg[17]/CLR, UPD_CLK_DIV/temp_reg[18]/CLR, UPD_CLK_DIV/temp_reg[19]/CLR, UPD_CLK_DIV/temp_reg[1]/CLR, UPD_CLK_DIV/temp_reg[20]/CLR, UPD_CLK_DIV/temp_reg[21]/CLR, UPD_CLK_DIV/temp_reg[22]/CLR (the first 15 of 25 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +SYNTH-6#1 Warning +Timing of a block RAM might be sub-optimal +The timing for the instance RAMCTRL/MAT_RAM/mem_reg_1, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +Related violations: + +SYNTH-6#2 Warning +Timing of a block RAM might be sub-optimal +The timing for the instance RAMCTRL/MAT_RAM/mem_reg_2, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +Related violations: + +SYNTH-6#3 Warning +Timing of a block RAM might be sub-optimal +The timing for the instance RAMCTRL/MAT_RAM/mem_reg_3, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +Related violations: + +SYNTH-6#4 Warning +Timing of a block RAM might be sub-optimal +The timing for the instance RAMCTRL/MAT_RAM/mem_reg_4, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +Related violations: + +SYNTH-6#5 Warning +Timing of a block RAM might be sub-optimal +The timing for the instance RAMCTRL/MAT_RAM/mem_reg_6, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +Related violations: + +SYNTH-6#6 Warning +Timing of a block RAM might be sub-optimal +The timing for the instance RAMCTRL/MAT_RAM/mem_reg_7, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +Related violations: + +SYNTH-6#7 Warning +Timing of a block RAM might be sub-optimal +The timing for the instance RAMCTRL/MAT_RAM/mem_reg_8, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +Related violations: + +SYNTH-6#8 Warning +Timing of a block RAM might be sub-optimal +The timing for the instance RAMCTRL/MAT_RAM/mem_reg_9, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +Related violations: + +SYNTH-6#9 Warning +Timing of a block RAM might be sub-optimal +The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_1_0, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +Related violations: + +SYNTH-6#10 Warning +Timing of a block RAM might be sub-optimal +The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_1_1, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +Related violations: + +SYNTH-6#11 Warning +Timing of a block RAM might be sub-optimal +The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_2_0, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +Related violations: + +SYNTH-6#12 Warning +Timing of a block RAM might be sub-optimal +The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_2_1, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +Related violations: + +SYNTH-6#13 Warning +Timing of a block RAM might be sub-optimal +The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_3_0, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +Related violations: + +SYNTH-6#14 Warning +Timing of a block RAM might be sub-optimal +The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_3_1, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +Related violations: + +SYNTH-6#15 Warning +Timing of a block RAM might be sub-optimal +The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_4_0, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +Related violations: + +SYNTH-6#16 Warning +Timing of a block RAM might be sub-optimal +The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_4_1, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +Related violations: + +SYNTH-6#17 Warning +Timing of a block RAM might be sub-optimal +The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_5_0, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +Related violations: + +SYNTH-6#18 Warning +Timing of a block RAM might be sub-optimal +The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_5_1, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +Related violations: + +SYNTH-6#19 Warning +Timing of a block RAM might be sub-optimal +The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_6_0, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +Related violations: + +SYNTH-6#20 Warning +Timing of a block RAM might be sub-optimal +The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_6_1, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +Related violations: + +SYNTH-6#21 Warning +Timing of a block RAM might be sub-optimal +The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_7_0, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +Related violations: + +SYNTH-6#22 Warning +Timing of a block RAM might be sub-optimal +The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_7_1, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +Related violations: + +SYNTH-6#23 Warning +Timing of a block RAM might be sub-optimal +The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_8_0, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +Related violations: + +SYNTH-6#24 Warning +Timing of a block RAM might be sub-optimal +The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_8_1, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +Related violations: + +SYNTH-6#25 Warning +Timing of a block RAM might be sub-optimal +The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_9_0, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +Related violations: + +SYNTH-6#26 Warning +Timing of a block RAM might be sub-optimal +The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_9_1, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +Related violations: + +TIMING-4#1 Warning +Invalid primary clock redefinition on a clock tree +Invalid clock redefinition on a clock tree. The primary clock U0/inst/clk_in1 is defined downstream of clock sys_clk_pin and overrides its insertion delay and/or waveform definition +Related violations: + TIMING-6#1 Warning No common primary clock between related clocks -The clocks clk_out1_clk_wiz_1 and clk_out1_clk_wiz_1_1 are related (timed together) but they have no common primary clock. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks clk_out1_clk_wiz_1] -to [get_clocks clk_out1_clk_wiz_1_1] +The clocks clk_out1_clk_wiz_1 and sys_clk_pin are related (timed together) but they have no common primary clock. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks clk_out1_clk_wiz_1] -to [get_clocks sys_clk_pin] Related violations: TIMING-6#2 Warning No common primary clock between related clocks -The clocks clk_out1_clk_wiz_1_1 and clk_out1_clk_wiz_1 are related (timed together) but they have no common primary clock. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks clk_out1_clk_wiz_1_1] -to [get_clocks clk_out1_clk_wiz_1] +The clocks sys_clk_pin and clk_out1_clk_wiz_1 are related (timed together) but they have no common primary clock. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks sys_clk_pin] -to [get_clocks clk_out1_clk_wiz_1] +Related violations: + +TIMING-7#1 Warning +No common node between related clocks +The clocks clk_out1_clk_wiz_1 and sys_clk_pin are related (timed together) but they have no common node. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks clk_out1_clk_wiz_1] -to [get_clocks sys_clk_pin] +Related violations: + +TIMING-7#2 Warning +No common node between related clocks +The clocks sys_clk_pin and clk_out1_clk_wiz_1 are related (timed together) but they have no common node. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks sys_clk_pin] -to [get_clocks clk_out1_clk_wiz_1] +Related violations: + +TIMING-16#1 Warning +Large setup violation +There is a large setup violation of -2.757 ns between RAMCTRL/SNAKE_RAM/mem_reg_4_1/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/snakeHere_reg/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#2 Warning +Large setup violation +There is a large setup violation of -3.112 ns between RAMCTRL/SNAKE_RAM/mem_reg_5_1/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[0]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#3 Warning +Large setup violation +There is a large setup violation of -3.660 ns between RAMCTRL/SNAKE_RAM/mem_reg_7_0/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[1]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#4 Warning +Large setup violation +There is a large setup violation of -3.702 ns between RAMCTRL/SNAKE_RAM/mem_reg_4_1/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[0]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#5 Warning +Large setup violation +There is a large setup violation of -3.702 ns between RAMCTRL/SNAKE_RAM/mem_reg_4_1/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[1]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#6 Warning +Large setup violation +There is a large setup violation of -3.702 ns between RAMCTRL/SNAKE_RAM/mem_reg_4_1/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[2]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#7 Warning +Large setup violation +There is a large setup violation of -3.702 ns between RAMCTRL/SNAKE_RAM/mem_reg_4_1/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[3]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#8 Warning +Large setup violation +There is a large setup violation of -3.740 ns between RAMCTRL/SNAKE_RAM/mem_reg_4_1/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[8]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#9 Warning +Large setup violation +There is a large setup violation of -3.740 ns between RAMCTRL/SNAKE_RAM/mem_reg_4_1/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[9]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#10 Warning +Large setup violation +There is a large setup violation of -3.881 ns between RAMCTRL/SNAKE_RAM/mem_reg_4_1/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[4]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#11 Warning +Large setup violation +There is a large setup violation of -3.881 ns between RAMCTRL/SNAKE_RAM/mem_reg_4_1/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[5]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#12 Warning +Large setup violation +There is a large setup violation of -3.881 ns between RAMCTRL/SNAKE_RAM/mem_reg_4_1/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[6]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#13 Warning +Large setup violation +There is a large setup violation of -3.881 ns between RAMCTRL/SNAKE_RAM/mem_reg_4_1/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[7]/CE (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#14 Warning +Large setup violation +There is a large setup violation of -4.008 ns between RAMCTRL/SNAKE_RAM/mem_reg_7_0/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[2]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#15 Warning +Large setup violation +There is a large setup violation of -4.073 ns between RAMCTRL/SNAKE_RAM/mem_reg_7_0/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[3]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#16 Warning +Large setup violation +There is a large setup violation of -4.846 ns between RAMCTRL/SNAKE_RAM/mem_reg_7_0/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[4]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#17 Warning +Large setup violation +There is a large setup violation of -4.866 ns between RAMCTRL/SNAKE_RAM/mem_reg_7_0/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[6]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#18 Warning +Large setup violation +There is a large setup violation of -4.942 ns between RAMCTRL/SNAKE_RAM/mem_reg_7_0/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[7]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#19 Warning +Large setup violation +There is a large setup violation of -4.950 ns between RAMCTRL/SNAKE_RAM/mem_reg_7_0/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[5]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#20 Warning +Large setup violation +There is a large setup violation of -5.507 ns between RAMCTRL/SNAKE_RAM/mem_reg_5_0/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[8]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-16#21 Warning +Large setup violation +There is a large setup violation of -5.611 ns between RAMCTRL/SNAKE_RAM/mem_reg_5_0/CLKBWRCLK (clocked by sys_clk_pin) and SNAKE/ROMAddress_reg[9]/D (clocked by sys_clk_pin). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +Related violations: + +TIMING-18#1 Warning +Missing input or output delay +An input delay is missing on resetGeneral relative to clock(s) sys_clk_pin +Related violations: + +TIMING-18#2 Warning +Missing input or output delay +An output delay is missing on led[0] relative to clock(s) sys_clk_pin +Related violations: + +TIMING-18#3 Warning +Missing input or output delay +An output delay is missing on led[1] relative to clock(s) sys_clk_pin +Related violations: + +TIMING-18#4 Warning +Missing input or output delay +An output delay is missing on led[2] relative to clock(s) sys_clk_pin +Related violations: + +TIMING-18#5 Warning +Missing input or output delay +An output delay is missing on led[3] relative to clock(s) sys_clk_pin +Related violations: + +TIMING-20#1 Warning +Non-clocked latch +The latch UPD/currentSnake_reg[X][4] cannot be properly analyzed as its control pin UPD/currentSnake_reg[X][4]/G is not reached by a timing clock +Related violations: + +TIMING-20#2 Warning +Non-clocked latch +The latch UPD/currentSnake_reg[X][5] cannot be properly analyzed as its control pin UPD/currentSnake_reg[X][5]/G is not reached by a timing clock +Related violations: + +TIMING-20#3 Warning +Non-clocked latch +The latch UPD/currentSnake_reg[X][6] cannot be properly analyzed as its control pin UPD/currentSnake_reg[X][6]/G is not reached by a timing clock +Related violations: + +TIMING-20#4 Warning +Non-clocked latch +The latch UPD/currentSnake_reg[X][7] cannot be properly analyzed as its control pin UPD/currentSnake_reg[X][7]/G is not reached by a timing clock +Related violations: + +TIMING-20#5 Warning +Non-clocked latch +The latch UPD/currentSnake_reg[dirX][1] cannot be properly analyzed as its control pin UPD/currentSnake_reg[dirX][1]/G is not reached by a timing clock +Related violations: + +TIMING-20#6 Warning +Non-clocked latch +The latch UPD/currentSnake_reg[dirY][0] cannot be properly analyzed as its control pin UPD/currentSnake_reg[dirY][0]/G is not reached by a timing clock +Related violations: + +TIMING-20#7 Warning +Non-clocked latch +The latch UPD/dataOut_reg[18]_LDC cannot be properly analyzed as its control pin UPD/dataOut_reg[18]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#8 Warning +Non-clocked latch +The latch UPD/dataOut_reg[19]_LDC cannot be properly analyzed as its control pin UPD/dataOut_reg[19]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#9 Warning +Non-clocked latch +The latch UPD/dataOut_reg[1]_LDC cannot be properly analyzed as its control pin UPD/dataOut_reg[1]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#10 Warning +Non-clocked latch +The latch UPD/dataOut_reg[20]_LDC cannot be properly analyzed as its control pin UPD/dataOut_reg[20]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#11 Warning +Non-clocked latch +The latch UPD/dataOut_reg[21]_LDC cannot be properly analyzed as its control pin UPD/dataOut_reg[21]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#12 Warning +Non-clocked latch +The latch UPD/dataOut_reg[4]_LDC cannot be properly analyzed as its control pin UPD/dataOut_reg[4]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#13 Warning +Non-clocked latch +The latch UPD/matAddress_reg[0] cannot be properly analyzed as its control pin UPD/matAddress_reg[0]/G is not reached by a timing clock +Related violations: + +TIMING-20#14 Warning +Non-clocked latch +The latch UPD/matAddress_reg[10] cannot be properly analyzed as its control pin UPD/matAddress_reg[10]/G is not reached by a timing clock +Related violations: + +TIMING-20#15 Warning +Non-clocked latch +The latch UPD/matAddress_reg[1] cannot be properly analyzed as its control pin UPD/matAddress_reg[1]/G is not reached by a timing clock +Related violations: + +TIMING-20#16 Warning +Non-clocked latch +The latch UPD/matAddress_reg[2] cannot be properly analyzed as its control pin UPD/matAddress_reg[2]/G is not reached by a timing clock +Related violations: + +TIMING-20#17 Warning +Non-clocked latch +The latch UPD/matAddress_reg[3] cannot be properly analyzed as its control pin UPD/matAddress_reg[3]/G is not reached by a timing clock +Related violations: + +TIMING-20#18 Warning +Non-clocked latch +The latch UPD/matAddress_reg[4] cannot be properly analyzed as its control pin UPD/matAddress_reg[4]/G is not reached by a timing clock +Related violations: + +TIMING-20#19 Warning +Non-clocked latch +The latch UPD/matAddress_reg[5] cannot be properly analyzed as its control pin UPD/matAddress_reg[5]/G is not reached by a timing clock +Related violations: + +TIMING-20#20 Warning +Non-clocked latch +The latch UPD/matAddress_reg[6] cannot be properly analyzed as its control pin UPD/matAddress_reg[6]/G is not reached by a timing clock +Related violations: + +TIMING-20#21 Warning +Non-clocked latch +The latch UPD/matAddress_reg[7] cannot be properly analyzed as its control pin UPD/matAddress_reg[7]/G is not reached by a timing clock +Related violations: + +TIMING-20#22 Warning +Non-clocked latch +The latch UPD/matAddress_reg[8] cannot be properly analyzed as its control pin UPD/matAddress_reg[8]/G is not reached by a timing clock +Related violations: + +TIMING-20#23 Warning +Non-clocked latch +The latch UPD/matAddress_reg[9] cannot be properly analyzed as its control pin UPD/matAddress_reg[9]/G is not reached by a timing clock +Related violations: + +TIMING-27#1 Warning +Invalid primary clock on hierarchical pin +A primary clock U0/inst/clk_in1 is created on an inappropriate internal pin U0/inst/clk_in1. It is not recommended to create a primary clock on a hierarchical pin when its driver pin has a fanout connected to multiple clock pins Related violations: diff --git a/projet-vga.runs/impl_1/VGA_top_methodology_drc_routed.rpx b/projet-vga.runs/impl_1/VGA_top_methodology_drc_routed.rpx index 6284a5b..a3d185f 100644 Binary files a/projet-vga.runs/impl_1/VGA_top_methodology_drc_routed.rpx and b/projet-vga.runs/impl_1/VGA_top_methodology_drc_routed.rpx differ diff --git a/projet-vga.runs/impl_1/VGA_top_opt.dcp b/projet-vga.runs/impl_1/VGA_top_opt.dcp index f9d395d..f9230ce 100644 Binary files a/projet-vga.runs/impl_1/VGA_top_opt.dcp and b/projet-vga.runs/impl_1/VGA_top_opt.dcp differ diff --git a/projet-vga.runs/impl_1/VGA_top_placed.dcp b/projet-vga.runs/impl_1/VGA_top_placed.dcp index 18950d5..b1284ab 100644 Binary files a/projet-vga.runs/impl_1/VGA_top_placed.dcp and b/projet-vga.runs/impl_1/VGA_top_placed.dcp differ diff --git a/projet-vga.runs/impl_1/VGA_top_power_routed.rpt b/projet-vga.runs/impl_1/VGA_top_power_routed.rpt index 5a37a28..4535d43 100644 --- a/projet-vga.runs/impl_1/VGA_top_power_routed.rpt +++ b/projet-vga.runs/impl_1/VGA_top_power_routed.rpt @@ -1,8 +1,8 @@ Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 -| Date : Tue Dec 7 12:43:47 2021 -| Host : irb121-02-w running 64-bit major release (build 9200) +| Date : Tue Jan 4 12:21:24 2022 +| Host : irb121-12-w running 64-bit major release (build 9200) | Command : report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx | Design : VGA_top | Device : xc7z010clg400-1 @@ -30,14 +30,14 @@ Table of Contents ---------- +--------------------------+--------------+ -| Total On-Chip Power (W) | 0.210 | +| Total On-Chip Power (W) | 0.298 | | Design Power Budget (W) | Unspecified* | | Power Budget Margin (W) | NA | -| Dynamic (W) | 0.116 | -| Device Static (W) | 0.094 | +| Dynamic (W) | 0.201 | +| Device Static (W) | 0.097 | | Effective TJA (C/W) | 11.5 | -| Max Ambient (C) | 82.6 | -| Junction Temperature (C) | 27.4 | +| Max Ambient (C) | 81.6 | +| Junction Temperature (C) | 28.4 | | Confidence Level | Medium | | Setting File | --- | | Simulation Activity File | --- | @@ -52,17 +52,19 @@ Table of Contents +----------------+-----------+----------+-----------+-----------------+ | On-Chip | Power (W) | Used | Available | Utilization (%) | +----------------+-----------+----------+-----------+-----------------+ -| Clocks | <0.001 | 8 | --- | --- | -| Slice Logic | <0.001 | 272 | --- | --- | -| LUT as Logic | <0.001 | 168 | 17600 | 0.95 | -| CARRY4 | <0.001 | 34 | 4400 | 0.77 | -| Register | <0.001 | 21 | 35200 | 0.06 | -| Others | 0.000 | 4 | --- | --- | -| Signals | <0.001 | 149 | --- | --- | +| Clocks | 0.004 | 6 | --- | --- | +| Slice Logic | 0.002 | 2313 | --- | --- | +| LUT as Logic | 0.002 | 1491 | 17600 | 8.47 | +| CARRY4 | <0.001 | 266 | 4400 | 6.05 | +| Register | <0.001 | 212 | 35200 | 0.60 | +| F7/F8 Muxes | <0.001 | 20 | 17600 | 0.11 | +| Others | 0.000 | 26 | --- | --- | +| Signals | 0.004 | 1918 | --- | --- | +| Block RAM | 0.075 | 22.5 | 60 | 37.50 | | MMCM | 0.115 | 1 | 2 | 50.00 | -| I/O | <0.001 | 19 | 100 | 19.00 | -| Static Power | 0.094 | | | | -| Total | 0.210 | | | | +| I/O | 0.002 | 24 | 100 | 24.00 | +| Static Power | 0.097 | | | | +| Total | 0.298 | | | | +----------------+-----------+----------+-----------+-----------------+ @@ -72,20 +74,20 @@ Table of Contents +-----------+-------------+-----------+-------------+------------+ | Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | +-----------+-------------+-----------+-------------+------------+ -| Vccint | 1.000 | 0.004 | 0.001 | 0.004 | -| Vccaux | 1.800 | 0.069 | 0.064 | 0.005 | -| Vcco33 | 3.300 | 0.001 | 0.000 | 0.001 | +| Vccint | 1.000 | 0.083 | 0.078 | 0.005 | +| Vccaux | 1.800 | 0.070 | 0.064 | 0.006 | +| Vcco33 | 3.300 | 0.002 | 0.001 | 0.001 | | Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | | Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | | Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | | Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | | Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | | Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | -| Vccbram | 1.000 | 0.000 | 0.000 | 0.000 | +| Vccbram | 1.000 | 0.008 | 0.007 | 0.001 | | MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | | MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | | MGTVccaux | 1.800 | 0.000 | 0.000 | 0.000 | -| Vccpint | 1.000 | 0.017 | 0.000 | 0.017 | +| Vccpint | 1.000 | 0.018 | 0.000 | 0.018 | | Vccpaux | 1.800 | 0.010 | 0.000 | 0.010 | | Vccpll | 1.800 | 0.003 | 0.000 | 0.003 | | Vcco_ddr | 1.500 | 0.000 | 0.000 | 0.000 | @@ -98,17 +100,17 @@ Table of Contents 1.3 Confidence Level -------------------- -+-----------------------------+------------+------------------------------------------------+------------------------------------------------------------------------------------------------------------+ -| User Input Data | Confidence | Details | Action | -+-----------------------------+------------+------------------------------------------------+------------------------------------------------------------------------------------------------------------+ -| Design implementation state | High | Design is routed | | -| Clock nodes activity | High | User specified more than 95% of clocks | | -| I/O nodes activity | High | User specified more than 95% of inputs | | -| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views | -| Device models | High | Device models are Production | | -| | | | | -| Overall confidence level | Medium | | | -+-----------------------------+------------+------------------------------------------------+------------------------------------------------------------------------------------------------------------+ ++-----------------------------+------------+-------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ +| User Input Data | Confidence | Details | Action | ++-----------------------------+------------+-------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ +| Design implementation state | High | Design is routed | | +| Clock nodes activity | Medium | More than 5% of clocks are missing user specification | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view | +| I/O nodes activity | Medium | More than 5% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view | +| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views | +| Device models | High | Device models are Production | | +| | | | | +| Overall confidence level | Medium | | | ++-----------------------------+------------+-------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ 2. Settings @@ -132,16 +134,14 @@ Table of Contents 2.2 Clock Constraints --------------------- -+----------------------+----------------------------+-----------------+ -| Clock | Domain | Constraint (ns) | -+----------------------+----------------------------+-----------------+ -| H125MHz | H125MHz | 8.0 | -| clk_out1_clk_wiz_1 | U0/inst/clk_out1_clk_wiz_1 | 40.0 | -| clk_out1_clk_wiz_1_1 | U0/inst/clk_out1_clk_wiz_1 | 40.0 | -| clkfbout_clk_wiz_1 | U0/inst/clkfbout_clk_wiz_1 | 40.0 | -| clkfbout_clk_wiz_1_1 | U0/inst/clkfbout_clk_wiz_1 | 40.0 | -| sys_clk_pin | H125MHz | 8.0 | -+----------------------+----------------------------+-----------------+ ++--------------------+----------------------------+-----------------+ +| Clock | Domain | Constraint (ns) | ++--------------------+----------------------------+-----------------+ +| clk_out1_clk_wiz_1 | U0/inst/clk_out1_clk_wiz_1 | 40.0 | +| clkfbout_clk_wiz_1 | U0/inst/clkfbout_clk_wiz_1 | 40.0 | +| sys_clk_pin | H125MHz | 8.0 | +| sys_clk_pin | H125MHz_IBUF_BUFG | 8.0 | ++--------------------+----------------------------+-----------------+ 3. Detailed Reports @@ -150,12 +150,16 @@ Table of Contents 3.1 By Hierarchy ---------------- -+----------+-----------+ -| Name | Power (W) | -+----------+-----------+ -| VGA_top | 0.116 | -| U0 | 0.115 | -| inst | 0.115 | -+----------+-----------+ ++---------------+-----------+ +| Name | Power (W) | ++---------------+-----------+ +| VGA_top | 0.201 | +| RAMCTRL | 0.080 | +| MAT_RAM | 0.031 | +| SNAKE_RAM | 0.049 | +| U0 | 0.115 | +| inst | 0.115 | +| UPD | 0.002 | ++---------------+-----------+ diff --git a/projet-vga.runs/impl_1/VGA_top_power_routed.rpx b/projet-vga.runs/impl_1/VGA_top_power_routed.rpx index 71d687b..a12cfee 100644 Binary files a/projet-vga.runs/impl_1/VGA_top_power_routed.rpx and b/projet-vga.runs/impl_1/VGA_top_power_routed.rpx differ diff --git a/projet-vga.runs/impl_1/VGA_top_power_summary_routed.pb b/projet-vga.runs/impl_1/VGA_top_power_summary_routed.pb index a1bfbb5..a0e7362 100644 Binary files a/projet-vga.runs/impl_1/VGA_top_power_summary_routed.pb and b/projet-vga.runs/impl_1/VGA_top_power_summary_routed.pb differ diff --git a/projet-vga.runs/impl_1/VGA_top_route_status.pb b/projet-vga.runs/impl_1/VGA_top_route_status.pb index 5f693fa..0c7ed71 100644 Binary files a/projet-vga.runs/impl_1/VGA_top_route_status.pb and b/projet-vga.runs/impl_1/VGA_top_route_status.pb differ diff --git a/projet-vga.runs/impl_1/VGA_top_route_status.rpt b/projet-vga.runs/impl_1/VGA_top_route_status.rpt index d720e8e..66b8371 100644 --- a/projet-vga.runs/impl_1/VGA_top_route_status.rpt +++ b/projet-vga.runs/impl_1/VGA_top_route_status.rpt @@ -1,11 +1,11 @@ Design Route Status : # nets : ------------------------------------------- : ----------- : - # of logical nets.......................... : 294 : - # of nets not needing routing.......... : 138 : - # of internally routed nets........ : 138 : - # of routable nets..................... : 156 : - # of fully routed nets............. : 156 : + # of logical nets.......................... : 3111 : + # of nets not needing routing.......... : 1185 : + # of internally routed nets........ : 1185 : + # of routable nets..................... : 1926 : + # of fully routed nets............. : 1926 : # of nets with routing errors.......... : 0 : ------------------------------------------- : ----------- : diff --git a/projet-vga.runs/impl_1/VGA_top_routed.dcp b/projet-vga.runs/impl_1/VGA_top_routed.dcp index f117c8f..d211631 100644 Binary files a/projet-vga.runs/impl_1/VGA_top_routed.dcp and b/projet-vga.runs/impl_1/VGA_top_routed.dcp differ diff --git a/projet-vga.runs/impl_1/VGA_top_timing_summary_routed.pb b/projet-vga.runs/impl_1/VGA_top_timing_summary_routed.pb index 45cfd1a..1fd077e 100644 Binary files a/projet-vga.runs/impl_1/VGA_top_timing_summary_routed.pb and b/projet-vga.runs/impl_1/VGA_top_timing_summary_routed.pb differ diff --git a/projet-vga.runs/impl_1/VGA_top_timing_summary_routed.rpt b/projet-vga.runs/impl_1/VGA_top_timing_summary_routed.rpt index 1af9ad6..e379ee5 100644 --- a/projet-vga.runs/impl_1/VGA_top_timing_summary_routed.rpt +++ b/projet-vga.runs/impl_1/VGA_top_timing_summary_routed.rpt @@ -1,8 +1,8 @@ Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 -| Date : Tue Dec 7 12:43:48 2021 -| Host : irb121-02-w running 64-bit major release (build 9200) +| Date : Tue Jan 4 12:21:24 2022 +| Host : irb121-12-w running 64-bit major release (build 9200) | Command : report_timing_summary -max_paths 10 -file VGA_top_timing_summary_routed.rpt -pb VGA_top_timing_summary_routed.pb -rpx VGA_top_timing_summary_routed.rpx -warn_on_violation | Design : VGA_top | Device : 7z010-clg400 @@ -52,7 +52,19 @@ Table of Contents 1. checking no_clock -------------------- - There are 0 register/latch pins with no clock. + There is 1 register/latch pin with no clock driven by root clock pin: UPD/currentSnake_reg[X][4]/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: UPD/currentSnake_reg[X][5]/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: UPD/currentSnake_reg[X][6]/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: UPD/currentSnake_reg[X][7]/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: UPD/currentSnake_reg[dirX][1]/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: UPD/currentSnake_reg[dirY][0]/Q (HIGH) + + There are 23 register/latch pins with no clock driven by root clock pin: UPD/update_reg/Q (HIGH) 2. checking constant_clock @@ -67,14 +79,14 @@ Table of Contents 4. checking unconstrained_internal_endpoints -------------------------------------------- - There are 0 pins that are not constrained for maximum delay. + There are 23 pins that are not constrained for maximum delay. (HIGH) There are 0 pins that are not constrained for maximum delay due to constant clock. 5. checking no_input_delay -------------------------- - There are 0 input ports with no input delay specified. + There is 1 input port with no input delay specified. (HIGH) There are 0 input ports with no input delay but user has a false path constraint. @@ -90,7 +102,7 @@ Table of Contents 7. checking multiple_clock -------------------------- - There are 21 register/latch pins with multiple clocks. (HIGH) + There are 0 register/latch pins with multiple clocks. 8. checking generated_clocks @@ -126,10 +138,10 @@ Table of Contents WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- - 33.269 0.000 0 52 0.101 0.000 0 52 2.000 0.000 0 27 + -5.611 -86.314 22 1095 -0.025 -0.025 1 1095 2.000 0.000 0 250 -All user specified timing constraints are met. +Timing constraints are not met. ------------------------------------------------------------------------------------------------ @@ -137,14 +149,12 @@ All user specified timing constraints are met. | ------------- ------------------------------------------------------------------------------------------------ -Clock Waveform(ns) Period(ns) Frequency(MHz) ------ ------------ ---------- -------------- -H125MHz {0.000 4.000} 8.000 125.000 - clk_out1_clk_wiz_1 {0.000 20.000} 40.000 25.000 - clkfbout_clk_wiz_1 {0.000 20.000} 40.000 25.000 -sys_clk_pin {0.000 4.000} 8.000 125.000 - clk_out1_clk_wiz_1_1 {0.000 20.000} 40.000 25.000 - clkfbout_clk_wiz_1_1 {0.000 20.000} 40.000 25.000 +Clock Waveform(ns) Period(ns) Frequency(MHz) +----- ------------ ---------- -------------- +U0/inst/clk_in1 {0.000 4.000} 8.000 125.000 + clk_out1_clk_wiz_1 {0.000 20.000} 40.000 25.000 + clkfbout_clk_wiz_1 {0.000 20.000} 40.000 25.000 +sys_clk_pin {0.000 4.000} 8.000 125.000 ------------------------------------------------------------------------------------------------ @@ -152,14 +162,12 @@ sys_clk_pin {0.000 4.000} 8.000 125.000 | ----------------- ------------------------------------------------------------------------------------------------ -Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------ ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- -H125MHz 2.000 0.000 0 1 - clk_out1_clk_wiz_1 33.269 0.000 0 52 0.261 0.000 0 52 19.500 0.000 0 23 - clkfbout_clk_wiz_1 37.845 0.000 0 3 -sys_clk_pin 2.000 0.000 0 1 - clk_out1_clk_wiz_1_1 33.281 0.000 0 52 0.261 0.000 0 52 19.500 0.000 0 23 - clkfbout_clk_wiz_1_1 37.845 0.000 0 3 +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- +U0/inst/clk_in1 2.000 0.000 0 1 + clk_out1_clk_wiz_1 31.915 0.000 0 78 0.218 0.000 0 78 19.500 0.000 0 62 + clkfbout_clk_wiz_1 37.845 0.000 0 3 +sys_clk_pin -5.611 -86.314 22 923 0.078 0.000 0 923 3.500 0.000 0 184 ------------------------------------------------------------------------------------------------ @@ -167,10 +175,10 @@ sys_clk_pin | ----------------- ------------------------------------------------------------------------------------------------ -From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ----------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -clk_out1_clk_wiz_1_1 clk_out1_clk_wiz_1 33.269 0.000 0 52 0.101 0.000 0 52 -clk_out1_clk_wiz_1 clk_out1_clk_wiz_1_1 33.269 0.000 0 52 0.101 0.000 0 52 +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- +sys_clk_pin clk_out1_clk_wiz_1 1.397 0.000 0 13 0.418 0.000 0 13 +clk_out1_clk_wiz_1 sys_clk_pin -3.437 -39.544 21 45 -0.025 -0.025 1 45 ------------------------------------------------------------------------------------------------ @@ -178,8 +186,11 @@ clk_out1_clk_wiz_1 clk_out1_clk_wiz_1_1 33.269 0.000 | ----------------------- ------------------------------------------------------------------------------------------------ -Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ----------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- +**async_default** clk_out1_clk_wiz_1 clk_out1_clk_wiz_1 34.529 0.000 0 25 1.220 0.000 0 25 +**async_default** sys_clk_pin clk_out1_clk_wiz_1 2.088 0.000 0 1 0.745 0.000 0 1 +**async_default** sys_clk_pin sys_clk_pin 4.029 0.000 0 32 0.841 0.000 0 32 ------------------------------------------------------------------------------------------------ @@ -189,8 +200,8 @@ Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing --------------------------------------------------------------------------------------------------- -From Clock: H125MHz - To Clock: H125MHz +From Clock: U0/inst/clk_in1 + To Clock: U0/inst/clk_in1 Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA @@ -200,18 +211,18 @@ PW : 0 Failing Endpoints, Worst Slack 2.000ns, Total Vio Pulse Width Checks -------------------------------------------------------------------------------------- -Clock Name: H125MHz +Clock Name: U0/inst/clk_in1 Waveform(ns): { 0.000 4.000 } Period(ns): 8.000 -Sources: { H125MHz } +Sources: { U0/inst/clk_in1 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin -Min Period n/a MMCME2_ADV/CLKIN1 n/a 1.249 8.000 6.751 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKIN1 -Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 8.000 92.000 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKIN1 -Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 4.000 2.000 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKIN1 -Low Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 2.000 4.000 2.000 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKIN1 -High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 4.000 2.000 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKIN1 -High Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 2.000 4.000 2.000 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKIN1 +Min Period n/a MMCME2_ADV/CLKIN1 n/a 1.249 8.000 6.751 MMCME2_ADV_X0Y0 U0/inst/mmcm_adv_inst/CLKIN1 +Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 8.000 92.000 MMCME2_ADV_X0Y0 U0/inst/mmcm_adv_inst/CLKIN1 +Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 4.000 2.000 MMCME2_ADV_X0Y0 U0/inst/mmcm_adv_inst/CLKIN1 +Low Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 2.000 4.000 2.000 MMCME2_ADV_X0Y0 U0/inst/mmcm_adv_inst/CLKIN1 +High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 4.000 2.000 MMCME2_ADV_X0Y0 U0/inst/mmcm_adv_inst/CLKIN1 +High Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 2.000 4.000 2.000 MMCME2_ADV_X0Y0 U0/inst/mmcm_adv_inst/CLKIN1 @@ -219,28 +230,28 @@ High Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 2.000 4.000 From Clock: clk_out1_clk_wiz_1 To Clock: clk_out1_clk_wiz_1 -Setup : 0 Failing Endpoints, Worst Slack 33.269ns, Total Violation 0.000ns -Hold : 0 Failing Endpoints, Worst Slack 0.261ns, Total Violation 0.000ns +Setup : 0 Failing Endpoints, Worst Slack 31.915ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.218ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 19.500ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 33.269ns (required time - arrival time) - Source: U1/comptY_reg[5]/C +Slack (MET) : 31.915ns (required time - arrival time) + Source: SYNC/comptY_reg[9]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptY_reg[3]/R + Destination: SYNC/comptY_reg[0]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) - Data Path Delay: 6.142ns (logic 0.828ns (13.480%) route 5.314ns (86.520%)) - Logic Levels: 3 (LUT4=1 LUT6=2) - Clock Path Skew: 0.000ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.252ns = ( 38.748 - 40.000 ) - Source Clock Delay (SCD): -0.601ns - Clock Pessimism Removal (CPR): 0.651ns + Data Path Delay: 7.463ns (logic 1.058ns (14.176%) route 6.405ns (85.824%)) + Logic Levels: 3 (LUT5=1 LUT6=2) + Clock Path Skew: -0.032ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.488ns = ( 41.488 - 40.000 ) + Source Clock Delay (SCD): 1.659ns + Clock Pessimism Removal (CPR): 0.139ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns @@ -250,63 +261,59 @@ Slack (MET) : 33.269ns (required time - arrival time) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.758 -0.601 U1/CLK - SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.656 1.659 SYNC/clk_out1 + SLICE_X19Y26 FDRE r SYNC/comptY_reg[9]/C ------------------------------------------------------------------- ------------------- - SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q - net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5] - SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O - net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0 - SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O - net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0 - SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O - net (fo=10, routed) 1.866 5.542 U1/comptY - SLICE_X40Y49 FDRE r U1/comptY_reg[3]/R + SLICE_X19Y26 FDRE (Prop_fdre_C_Q) 0.456 2.115 r SYNC/comptY_reg[9]/Q + net (fo=10, routed) 2.756 4.871 SYNC/comptY_reg__0[9] + SLICE_X28Y23 LUT5 (Prop_lut5_I0_O) 0.150 5.021 r SYNC/comptY[9]_i_9/O + net (fo=1, routed) 0.989 6.010 SYNC/comptY[9]_i_9_n_0 + SLICE_X29Y25 LUT6 (Prop_lut6_I0_O) 0.328 6.338 r SYNC/comptY[9]_i_5/O + net (fo=1, routed) 0.845 7.183 SYNC/comptY[9]_i_5_n_0 + SLICE_X29Y25 LUT6 (Prop_lut6_I5_O) 0.124 7.307 r SYNC/comptY[9]_i_1/O + net (fo=10, routed) 1.816 9.122 SYNC/comptY + SLICE_X17Y26 FDRE r SYNC/comptY_reg[0]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r - L16 0.000 40.000 r H125MHz (IN) - net (fo=0) 0.000 40.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.580 38.748 U1/CLK - SLICE_X40Y49 FDRE r U1/comptY_reg[3]/C - clock pessimism 0.651 39.399 - clock uncertainty -0.160 39.239 - SLICE_X40Y49 FDRE (Setup_fdre_C_R) -0.429 38.810 U1/comptY_reg[3] + BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.485 41.488 SYNC/clk_out1 + SLICE_X17Y26 FDRE r SYNC/comptY_reg[0]/C + clock pessimism 0.139 41.627 + clock uncertainty -0.160 41.467 + SLICE_X17Y26 FDRE (Setup_fdre_C_R) -0.429 41.038 SYNC/comptY_reg[0] ------------------------------------------------------------------- - required time 38.810 - arrival time -5.542 + required time 41.038 + arrival time -9.122 ------------------------------------------------------------------- - slack 33.269 + slack 31.915 -Slack (MET) : 33.269ns (required time - arrival time) - Source: U1/comptY_reg[5]/C +Slack (MET) : 32.277ns (required time - arrival time) + Source: SYNC/comptY_reg[9]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptY_reg[5]/R + Destination: SYNC/comptY_reg[5]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) - Data Path Delay: 6.142ns (logic 0.828ns (13.480%) route 5.314ns (86.520%)) - Logic Levels: 3 (LUT4=1 LUT6=2) - Clock Path Skew: 0.000ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.252ns = ( 38.748 - 40.000 ) - Source Clock Delay (SCD): -0.601ns - Clock Pessimism Removal (CPR): 0.651ns + Data Path Delay: 6.972ns (logic 1.058ns (15.176%) route 5.914ns (84.824%)) + Logic Levels: 3 (LUT5=1 LUT6=2) + Clock Path Skew: -0.067ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.487ns = ( 41.487 - 40.000 ) + Source Clock Delay (SCD): 1.659ns + Clock Pessimism Removal (CPR): 0.105ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns @@ -316,63 +323,59 @@ Slack (MET) : 33.269ns (required time - arrival time) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.758 -0.601 U1/CLK - SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.656 1.659 SYNC/clk_out1 + SLICE_X19Y26 FDRE r SYNC/comptY_reg[9]/C ------------------------------------------------------------------- ------------------- - SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q - net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5] - SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O - net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0 - SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O - net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0 - SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O - net (fo=10, routed) 1.866 5.542 U1/comptY - SLICE_X40Y49 FDRE r U1/comptY_reg[5]/R + SLICE_X19Y26 FDRE (Prop_fdre_C_Q) 0.456 2.115 r SYNC/comptY_reg[9]/Q + net (fo=10, routed) 2.756 4.871 SYNC/comptY_reg__0[9] + SLICE_X28Y23 LUT5 (Prop_lut5_I0_O) 0.150 5.021 r SYNC/comptY[9]_i_9/O + net (fo=1, routed) 0.989 6.010 SYNC/comptY[9]_i_9_n_0 + SLICE_X29Y25 LUT6 (Prop_lut6_I0_O) 0.328 6.338 r SYNC/comptY[9]_i_5/O + net (fo=1, routed) 0.845 7.183 SYNC/comptY[9]_i_5_n_0 + SLICE_X29Y25 LUT6 (Prop_lut6_I5_O) 0.124 7.307 r SYNC/comptY[9]_i_1/O + net (fo=10, routed) 1.324 8.631 SYNC/comptY + SLICE_X20Y26 FDRE r SYNC/comptY_reg[5]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r - L16 0.000 40.000 r H125MHz (IN) - net (fo=0) 0.000 40.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.580 38.748 U1/CLK - SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C - clock pessimism 0.651 39.399 - clock uncertainty -0.160 39.239 - SLICE_X40Y49 FDRE (Setup_fdre_C_R) -0.429 38.810 U1/comptY_reg[5] + BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.484 41.487 SYNC/clk_out1 + SLICE_X20Y26 FDRE r SYNC/comptY_reg[5]/C + clock pessimism 0.105 41.592 + clock uncertainty -0.160 41.432 + SLICE_X20Y26 FDRE (Setup_fdre_C_R) -0.524 40.908 SYNC/comptY_reg[5] ------------------------------------------------------------------- - required time 38.810 - arrival time -5.542 + required time 40.908 + arrival time -8.631 ------------------------------------------------------------------- - slack 33.269 + slack 32.277 -Slack (MET) : 33.414ns (required time - arrival time) - Source: U1/comptY_reg[5]/C +Slack (MET) : 32.372ns (required time - arrival time) + Source: SYNC/comptY_reg[9]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptY_reg[4]/R + Destination: SYNC/comptY_reg[3]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) - Data Path Delay: 5.838ns (logic 0.828ns (14.184%) route 5.010ns (85.816%)) - Logic Levels: 3 (LUT4=1 LUT6=2) - Clock Path Skew: -0.064ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.253ns = ( 38.747 - 40.000 ) - Source Clock Delay (SCD): -0.601ns - Clock Pessimism Removal (CPR): 0.588ns + Data Path Delay: 6.972ns (logic 1.058ns (15.176%) route 5.914ns (84.824%)) + Logic Levels: 3 (LUT5=1 LUT6=2) + Clock Path Skew: -0.067ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.487ns = ( 41.487 - 40.000 ) + Source Clock Delay (SCD): 1.659ns + Clock Pessimism Removal (CPR): 0.105ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns @@ -382,63 +385,59 @@ Slack (MET) : 33.414ns (required time - arrival time) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.758 -0.601 U1/CLK - SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.656 1.659 SYNC/clk_out1 + SLICE_X19Y26 FDRE r SYNC/comptY_reg[9]/C ------------------------------------------------------------------- ------------------- - SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q - net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5] - SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O - net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0 - SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O - net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0 - SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O - net (fo=10, routed) 1.561 5.237 U1/comptY - SLICE_X38Y49 FDRE r U1/comptY_reg[4]/R + SLICE_X19Y26 FDRE (Prop_fdre_C_Q) 0.456 2.115 r SYNC/comptY_reg[9]/Q + net (fo=10, routed) 2.756 4.871 SYNC/comptY_reg__0[9] + SLICE_X28Y23 LUT5 (Prop_lut5_I0_O) 0.150 5.021 r SYNC/comptY[9]_i_9/O + net (fo=1, routed) 0.989 6.010 SYNC/comptY[9]_i_9_n_0 + SLICE_X29Y25 LUT6 (Prop_lut6_I0_O) 0.328 6.338 r SYNC/comptY[9]_i_5/O + net (fo=1, routed) 0.845 7.183 SYNC/comptY[9]_i_5_n_0 + SLICE_X29Y25 LUT6 (Prop_lut6_I5_O) 0.124 7.307 r SYNC/comptY[9]_i_1/O + net (fo=10, routed) 1.324 8.631 SYNC/comptY + SLICE_X21Y26 FDRE r SYNC/comptY_reg[3]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r - L16 0.000 40.000 r H125MHz (IN) - net (fo=0) 0.000 40.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.579 38.747 U1/CLK - SLICE_X38Y49 FDRE r U1/comptY_reg[4]/C - clock pessimism 0.588 39.335 - clock uncertainty -0.160 39.175 - SLICE_X38Y49 FDRE (Setup_fdre_C_R) -0.524 38.651 U1/comptY_reg[4] + BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.484 41.487 SYNC/clk_out1 + SLICE_X21Y26 FDRE r SYNC/comptY_reg[3]/C + clock pessimism 0.105 41.592 + clock uncertainty -0.160 41.432 + SLICE_X21Y26 FDRE (Setup_fdre_C_R) -0.429 41.003 SYNC/comptY_reg[3] ------------------------------------------------------------------- - required time 38.651 - arrival time -5.237 + required time 41.003 + arrival time -8.631 ------------------------------------------------------------------- - slack 33.414 + slack 32.372 -Slack (MET) : 33.600ns (required time - arrival time) - Source: U1/comptY_reg[5]/C +Slack (MET) : 32.372ns (required time - arrival time) + Source: SYNC/comptY_reg[9]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptY_reg[1]/R + Destination: SYNC/comptY_reg[4]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) - Data Path Delay: 5.616ns (logic 0.828ns (14.744%) route 4.788ns (85.256%)) - Logic Levels: 3 (LUT4=1 LUT6=2) - Clock Path Skew: -0.195ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.269ns = ( 38.731 - 40.000 ) - Source Clock Delay (SCD): -0.601ns - Clock Pessimism Removal (CPR): 0.473ns + Data Path Delay: 6.972ns (logic 1.058ns (15.176%) route 5.914ns (84.824%)) + Logic Levels: 3 (LUT5=1 LUT6=2) + Clock Path Skew: -0.067ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.487ns = ( 41.487 - 40.000 ) + Source Clock Delay (SCD): 1.659ns + Clock Pessimism Removal (CPR): 0.105ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns @@ -448,63 +447,59 @@ Slack (MET) : 33.600ns (required time - arrival time) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.758 -0.601 U1/CLK - SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.656 1.659 SYNC/clk_out1 + SLICE_X19Y26 FDRE r SYNC/comptY_reg[9]/C ------------------------------------------------------------------- ------------------- - SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q - net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5] - SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O - net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0 - SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O - net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0 - SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O - net (fo=10, routed) 1.340 5.015 U1/comptY - SLICE_X36Y51 FDRE r U1/comptY_reg[1]/R + SLICE_X19Y26 FDRE (Prop_fdre_C_Q) 0.456 2.115 r SYNC/comptY_reg[9]/Q + net (fo=10, routed) 2.756 4.871 SYNC/comptY_reg__0[9] + SLICE_X28Y23 LUT5 (Prop_lut5_I0_O) 0.150 5.021 r SYNC/comptY[9]_i_9/O + net (fo=1, routed) 0.989 6.010 SYNC/comptY[9]_i_9_n_0 + SLICE_X29Y25 LUT6 (Prop_lut6_I0_O) 0.328 6.338 r SYNC/comptY[9]_i_5/O + net (fo=1, routed) 0.845 7.183 SYNC/comptY[9]_i_5_n_0 + SLICE_X29Y25 LUT6 (Prop_lut6_I5_O) 0.124 7.307 r SYNC/comptY[9]_i_1/O + net (fo=10, routed) 1.324 8.631 SYNC/comptY + SLICE_X21Y26 FDRE r SYNC/comptY_reg[4]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r - L16 0.000 40.000 r H125MHz (IN) - net (fo=0) 0.000 40.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.563 38.731 U1/CLK - SLICE_X36Y51 FDRE r U1/comptY_reg[1]/C - clock pessimism 0.473 39.204 - clock uncertainty -0.160 39.044 - SLICE_X36Y51 FDRE (Setup_fdre_C_R) -0.429 38.615 U1/comptY_reg[1] + BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.484 41.487 SYNC/clk_out1 + SLICE_X21Y26 FDRE r SYNC/comptY_reg[4]/C + clock pessimism 0.105 41.592 + clock uncertainty -0.160 41.432 + SLICE_X21Y26 FDRE (Setup_fdre_C_R) -0.429 41.003 SYNC/comptY_reg[4] ------------------------------------------------------------------- - required time 38.615 - arrival time -5.015 + required time 41.003 + arrival time -8.631 ------------------------------------------------------------------- - slack 33.600 + slack 32.372 -Slack (MET) : 33.600ns (required time - arrival time) - Source: U1/comptY_reg[5]/C +Slack (MET) : 32.433ns (required time - arrival time) + Source: SYNC/comptY_reg[9]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptY_reg[2]/R + Destination: SYNC/comptY_reg[6]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) - Data Path Delay: 5.616ns (logic 0.828ns (14.744%) route 4.788ns (85.256%)) - Logic Levels: 3 (LUT4=1 LUT6=2) - Clock Path Skew: -0.195ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.269ns = ( 38.731 - 40.000 ) - Source Clock Delay (SCD): -0.601ns - Clock Pessimism Removal (CPR): 0.473ns + Data Path Delay: 6.945ns (logic 1.058ns (15.233%) route 5.887ns (84.767%)) + Logic Levels: 3 (LUT5=1 LUT6=2) + Clock Path Skew: -0.032ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.488ns = ( 41.488 - 40.000 ) + Source Clock Delay (SCD): 1.659ns + Clock Pessimism Removal (CPR): 0.139ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns @@ -514,63 +509,59 @@ Slack (MET) : 33.600ns (required time - arrival time) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.758 -0.601 U1/CLK - SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.656 1.659 SYNC/clk_out1 + SLICE_X19Y26 FDRE r SYNC/comptY_reg[9]/C ------------------------------------------------------------------- ------------------- - SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q - net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5] - SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O - net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0 - SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O - net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0 - SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O - net (fo=10, routed) 1.340 5.015 U1/comptY - SLICE_X36Y51 FDRE r U1/comptY_reg[2]/R + SLICE_X19Y26 FDRE (Prop_fdre_C_Q) 0.456 2.115 r SYNC/comptY_reg[9]/Q + net (fo=10, routed) 2.756 4.871 SYNC/comptY_reg__0[9] + SLICE_X28Y23 LUT5 (Prop_lut5_I0_O) 0.150 5.021 r SYNC/comptY[9]_i_9/O + net (fo=1, routed) 0.989 6.010 SYNC/comptY[9]_i_9_n_0 + SLICE_X29Y25 LUT6 (Prop_lut6_I0_O) 0.328 6.338 r SYNC/comptY[9]_i_5/O + net (fo=1, routed) 0.845 7.183 SYNC/comptY[9]_i_5_n_0 + SLICE_X29Y25 LUT6 (Prop_lut6_I5_O) 0.124 7.307 r SYNC/comptY[9]_i_1/O + net (fo=10, routed) 1.298 8.604 SYNC/comptY + SLICE_X18Y26 FDRE r SYNC/comptY_reg[6]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r - L16 0.000 40.000 r H125MHz (IN) - net (fo=0) 0.000 40.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.563 38.731 U1/CLK - SLICE_X36Y51 FDRE r U1/comptY_reg[2]/C - clock pessimism 0.473 39.204 - clock uncertainty -0.160 39.044 - SLICE_X36Y51 FDRE (Setup_fdre_C_R) -0.429 38.615 U1/comptY_reg[2] + BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.485 41.488 SYNC/clk_out1 + SLICE_X18Y26 FDRE r SYNC/comptY_reg[6]/C + clock pessimism 0.139 41.627 + clock uncertainty -0.160 41.467 + SLICE_X18Y26 FDRE (Setup_fdre_C_R) -0.429 41.038 SYNC/comptY_reg[6] ------------------------------------------------------------------- - required time 38.615 - arrival time -5.015 + required time 41.038 + arrival time -8.604 ------------------------------------------------------------------- - slack 33.600 + slack 32.433 -Slack (MET) : 33.600ns (required time - arrival time) - Source: U1/comptY_reg[5]/C +Slack (MET) : 32.460ns (required time - arrival time) + Source: SYNC/comptY_reg[9]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptY_reg[7]/R + Destination: SYNC/comptY_reg[7]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) - Data Path Delay: 5.616ns (logic 0.828ns (14.744%) route 4.788ns (85.256%)) - Logic Levels: 3 (LUT4=1 LUT6=2) - Clock Path Skew: -0.195ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.269ns = ( 38.731 - 40.000 ) - Source Clock Delay (SCD): -0.601ns - Clock Pessimism Removal (CPR): 0.473ns + Data Path Delay: 6.941ns (logic 1.058ns (15.243%) route 5.883ns (84.757%)) + Logic Levels: 3 (LUT5=1 LUT6=2) + Clock Path Skew: -0.010ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.488ns = ( 41.488 - 40.000 ) + Source Clock Delay (SCD): 1.659ns + Clock Pessimism Removal (CPR): 0.161ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns @@ -580,63 +571,59 @@ Slack (MET) : 33.600ns (required time - arrival time) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.758 -0.601 U1/CLK - SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.656 1.659 SYNC/clk_out1 + SLICE_X19Y26 FDRE r SYNC/comptY_reg[9]/C ------------------------------------------------------------------- ------------------- - SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q - net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5] - SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O - net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0 - SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O - net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0 - SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O - net (fo=10, routed) 1.340 5.015 U1/comptY - SLICE_X36Y51 FDRE r U1/comptY_reg[7]/R + SLICE_X19Y26 FDRE (Prop_fdre_C_Q) 0.456 2.115 r SYNC/comptY_reg[9]/Q + net (fo=10, routed) 2.756 4.871 SYNC/comptY_reg__0[9] + SLICE_X28Y23 LUT5 (Prop_lut5_I0_O) 0.150 5.021 r SYNC/comptY[9]_i_9/O + net (fo=1, routed) 0.989 6.010 SYNC/comptY[9]_i_9_n_0 + SLICE_X29Y25 LUT6 (Prop_lut6_I0_O) 0.328 6.338 r SYNC/comptY[9]_i_5/O + net (fo=1, routed) 0.845 7.183 SYNC/comptY[9]_i_5_n_0 + SLICE_X29Y25 LUT6 (Prop_lut6_I5_O) 0.124 7.307 r SYNC/comptY[9]_i_1/O + net (fo=10, routed) 1.293 8.600 SYNC/comptY + SLICE_X19Y26 FDRE r SYNC/comptY_reg[7]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r - L16 0.000 40.000 r H125MHz (IN) - net (fo=0) 0.000 40.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.563 38.731 U1/CLK - SLICE_X36Y51 FDRE r U1/comptY_reg[7]/C - clock pessimism 0.473 39.204 - clock uncertainty -0.160 39.044 - SLICE_X36Y51 FDRE (Setup_fdre_C_R) -0.429 38.615 U1/comptY_reg[7] + BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.485 41.488 SYNC/clk_out1 + SLICE_X19Y26 FDRE r SYNC/comptY_reg[7]/C + clock pessimism 0.161 41.649 + clock uncertainty -0.160 41.489 + SLICE_X19Y26 FDRE (Setup_fdre_C_R) -0.429 41.060 SYNC/comptY_reg[7] ------------------------------------------------------------------- - required time 38.615 - arrival time -5.015 + required time 41.060 + arrival time -8.600 ------------------------------------------------------------------- - slack 33.600 + slack 32.460 -Slack (MET) : 33.600ns (required time - arrival time) - Source: U1/comptY_reg[5]/C +Slack (MET) : 32.460ns (required time - arrival time) + Source: SYNC/comptY_reg[9]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptY_reg[8]/R + Destination: SYNC/comptY_reg[8]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) - Data Path Delay: 5.616ns (logic 0.828ns (14.744%) route 4.788ns (85.256%)) - Logic Levels: 3 (LUT4=1 LUT6=2) - Clock Path Skew: -0.195ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.269ns = ( 38.731 - 40.000 ) - Source Clock Delay (SCD): -0.601ns - Clock Pessimism Removal (CPR): 0.473ns + Data Path Delay: 6.941ns (logic 1.058ns (15.243%) route 5.883ns (84.757%)) + Logic Levels: 3 (LUT5=1 LUT6=2) + Clock Path Skew: -0.010ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.488ns = ( 41.488 - 40.000 ) + Source Clock Delay (SCD): 1.659ns + Clock Pessimism Removal (CPR): 0.161ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns @@ -646,63 +633,59 @@ Slack (MET) : 33.600ns (required time - arrival time) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.758 -0.601 U1/CLK - SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.656 1.659 SYNC/clk_out1 + SLICE_X19Y26 FDRE r SYNC/comptY_reg[9]/C ------------------------------------------------------------------- ------------------- - SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q - net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5] - SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O - net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0 - SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O - net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0 - SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O - net (fo=10, routed) 1.340 5.015 U1/comptY - SLICE_X36Y51 FDRE r U1/comptY_reg[8]/R + SLICE_X19Y26 FDRE (Prop_fdre_C_Q) 0.456 2.115 r SYNC/comptY_reg[9]/Q + net (fo=10, routed) 2.756 4.871 SYNC/comptY_reg__0[9] + SLICE_X28Y23 LUT5 (Prop_lut5_I0_O) 0.150 5.021 r SYNC/comptY[9]_i_9/O + net (fo=1, routed) 0.989 6.010 SYNC/comptY[9]_i_9_n_0 + SLICE_X29Y25 LUT6 (Prop_lut6_I0_O) 0.328 6.338 r SYNC/comptY[9]_i_5/O + net (fo=1, routed) 0.845 7.183 SYNC/comptY[9]_i_5_n_0 + SLICE_X29Y25 LUT6 (Prop_lut6_I5_O) 0.124 7.307 r SYNC/comptY[9]_i_1/O + net (fo=10, routed) 1.293 8.600 SYNC/comptY + SLICE_X19Y26 FDRE r SYNC/comptY_reg[8]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r - L16 0.000 40.000 r H125MHz (IN) - net (fo=0) 0.000 40.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.563 38.731 U1/CLK - SLICE_X36Y51 FDRE r U1/comptY_reg[8]/C - clock pessimism 0.473 39.204 - clock uncertainty -0.160 39.044 - SLICE_X36Y51 FDRE (Setup_fdre_C_R) -0.429 38.615 U1/comptY_reg[8] + BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.485 41.488 SYNC/clk_out1 + SLICE_X19Y26 FDRE r SYNC/comptY_reg[8]/C + clock pessimism 0.161 41.649 + clock uncertainty -0.160 41.489 + SLICE_X19Y26 FDRE (Setup_fdre_C_R) -0.429 41.060 SYNC/comptY_reg[8] ------------------------------------------------------------------- - required time 38.615 - arrival time -5.015 + required time 41.060 + arrival time -8.600 ------------------------------------------------------------------- - slack 33.600 + slack 32.460 -Slack (MET) : 33.600ns (required time - arrival time) - Source: U1/comptY_reg[5]/C +Slack (MET) : 32.460ns (required time - arrival time) + Source: SYNC/comptY_reg[9]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptY_reg[9]/R + Destination: SYNC/comptY_reg[9]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) - Data Path Delay: 5.616ns (logic 0.828ns (14.744%) route 4.788ns (85.256%)) - Logic Levels: 3 (LUT4=1 LUT6=2) - Clock Path Skew: -0.195ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.269ns = ( 38.731 - 40.000 ) - Source Clock Delay (SCD): -0.601ns - Clock Pessimism Removal (CPR): 0.473ns + Data Path Delay: 6.941ns (logic 1.058ns (15.243%) route 5.883ns (84.757%)) + Logic Levels: 3 (LUT5=1 LUT6=2) + Clock Path Skew: -0.010ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.488ns = ( 41.488 - 40.000 ) + Source Clock Delay (SCD): 1.659ns + Clock Pessimism Removal (CPR): 0.161ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns @@ -712,63 +695,59 @@ Slack (MET) : 33.600ns (required time - arrival time) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.758 -0.601 U1/CLK - SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.656 1.659 SYNC/clk_out1 + SLICE_X19Y26 FDRE r SYNC/comptY_reg[9]/C ------------------------------------------------------------------- ------------------- - SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q - net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5] - SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O - net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0 - SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O - net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0 - SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O - net (fo=10, routed) 1.340 5.015 U1/comptY - SLICE_X36Y51 FDRE r U1/comptY_reg[9]/R + SLICE_X19Y26 FDRE (Prop_fdre_C_Q) 0.456 2.115 r SYNC/comptY_reg[9]/Q + net (fo=10, routed) 2.756 4.871 SYNC/comptY_reg__0[9] + SLICE_X28Y23 LUT5 (Prop_lut5_I0_O) 0.150 5.021 r SYNC/comptY[9]_i_9/O + net (fo=1, routed) 0.989 6.010 SYNC/comptY[9]_i_9_n_0 + SLICE_X29Y25 LUT6 (Prop_lut6_I0_O) 0.328 6.338 r SYNC/comptY[9]_i_5/O + net (fo=1, routed) 0.845 7.183 SYNC/comptY[9]_i_5_n_0 + SLICE_X29Y25 LUT6 (Prop_lut6_I5_O) 0.124 7.307 r SYNC/comptY[9]_i_1/O + net (fo=10, routed) 1.293 8.600 SYNC/comptY + SLICE_X19Y26 FDRE r SYNC/comptY_reg[9]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r - L16 0.000 40.000 r H125MHz (IN) - net (fo=0) 0.000 40.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.563 38.731 U1/CLK - SLICE_X36Y51 FDRE r U1/comptY_reg[9]/C - clock pessimism 0.473 39.204 - clock uncertainty -0.160 39.044 - SLICE_X36Y51 FDRE (Setup_fdre_C_R) -0.429 38.615 U1/comptY_reg[9] + BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.485 41.488 SYNC/clk_out1 + SLICE_X19Y26 FDRE r SYNC/comptY_reg[9]/C + clock pessimism 0.161 41.649 + clock uncertainty -0.160 41.489 + SLICE_X19Y26 FDRE (Setup_fdre_C_R) -0.429 41.060 SYNC/comptY_reg[9] ------------------------------------------------------------------- - required time 38.615 - arrival time -5.015 + required time 41.060 + arrival time -8.600 ------------------------------------------------------------------- - slack 33.600 + slack 32.460 -Slack (MET) : 33.744ns (required time - arrival time) - Source: U1/comptY_reg[5]/C +Slack (MET) : 32.771ns (required time - arrival time) + Source: SYNC/comptY_reg[9]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptY_reg[6]/R + Destination: SYNC/comptY_reg[1]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) - Data Path Delay: 5.472ns (logic 0.828ns (15.132%) route 4.644ns (84.868%)) - Logic Levels: 3 (LUT4=1 LUT6=2) - Clock Path Skew: -0.195ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.269ns = ( 38.731 - 40.000 ) - Source Clock Delay (SCD): -0.601ns - Clock Pessimism Removal (CPR): 0.473ns + Data Path Delay: 6.605ns (logic 1.058ns (16.017%) route 5.547ns (83.983%)) + Logic Levels: 3 (LUT5=1 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.486ns = ( 41.486 - 40.000 ) + Source Clock Delay (SCD): 1.659ns + Clock Pessimism Removal (CPR): 0.139ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns @@ -778,63 +757,59 @@ Slack (MET) : 33.744ns (required time - arrival time) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.758 -0.601 U1/CLK - SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.656 1.659 SYNC/clk_out1 + SLICE_X19Y26 FDRE r SYNC/comptY_reg[9]/C ------------------------------------------------------------------- ------------------- - SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q - net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5] - SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O - net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0 - SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O - net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0 - SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O - net (fo=10, routed) 1.196 4.871 U1/comptY - SLICE_X36Y50 FDRE r U1/comptY_reg[6]/R + SLICE_X19Y26 FDRE (Prop_fdre_C_Q) 0.456 2.115 r SYNC/comptY_reg[9]/Q + net (fo=10, routed) 2.756 4.871 SYNC/comptY_reg__0[9] + SLICE_X28Y23 LUT5 (Prop_lut5_I0_O) 0.150 5.021 r SYNC/comptY[9]_i_9/O + net (fo=1, routed) 0.989 6.010 SYNC/comptY[9]_i_9_n_0 + SLICE_X29Y25 LUT6 (Prop_lut6_I0_O) 0.328 6.338 r SYNC/comptY[9]_i_5/O + net (fo=1, routed) 0.845 7.183 SYNC/comptY[9]_i_5_n_0 + SLICE_X29Y25 LUT6 (Prop_lut6_I5_O) 0.124 7.307 r SYNC/comptY[9]_i_1/O + net (fo=10, routed) 0.958 8.264 SYNC/comptY + SLICE_X19Y25 FDRE r SYNC/comptY_reg[1]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r - L16 0.000 40.000 r H125MHz (IN) - net (fo=0) 0.000 40.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.563 38.731 U1/CLK - SLICE_X36Y50 FDRE r U1/comptY_reg[6]/C - clock pessimism 0.473 39.204 - clock uncertainty -0.160 39.044 - SLICE_X36Y50 FDRE (Setup_fdre_C_R) -0.429 38.615 U1/comptY_reg[6] + BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.483 41.486 SYNC/clk_out1 + SLICE_X19Y25 FDRE r SYNC/comptY_reg[1]/C + clock pessimism 0.139 41.625 + clock uncertainty -0.160 41.465 + SLICE_X19Y25 FDRE (Setup_fdre_C_R) -0.429 41.036 SYNC/comptY_reg[1] ------------------------------------------------------------------- - required time 38.615 - arrival time -4.871 + required time 41.036 + arrival time -8.264 ------------------------------------------------------------------- - slack 33.744 + slack 32.771 -Slack (MET) : 33.981ns (required time - arrival time) - Source: U1/comptY_reg[5]/C +Slack (MET) : 32.771ns (required time - arrival time) + Source: SYNC/comptY_reg[9]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptY_reg[0]/R + Destination: SYNC/comptY_reg[2]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) - Data Path Delay: 5.139ns (logic 0.828ns (16.112%) route 4.311ns (83.888%)) - Logic Levels: 3 (LUT4=1 LUT6=2) - Clock Path Skew: -0.195ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.269ns = ( 38.731 - 40.000 ) - Source Clock Delay (SCD): -0.601ns - Clock Pessimism Removal (CPR): 0.473ns + Data Path Delay: 6.605ns (logic 1.058ns (16.017%) route 5.547ns (83.983%)) + Logic Levels: 3 (LUT5=1 LUT6=2) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.486ns = ( 41.486 - 40.000 ) + Source Clock Delay (SCD): 1.659ns + Clock Pessimism Removal (CPR): 0.139ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns @@ -844,48 +819,44 @@ Slack (MET) : 33.981ns (required time - arrival time) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.758 -0.601 U1/CLK - SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.656 1.659 SYNC/clk_out1 + SLICE_X19Y26 FDRE r SYNC/comptY_reg[9]/C ------------------------------------------------------------------- ------------------- - SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q - net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5] - SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O - net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0 - SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O - net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0 - SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O - net (fo=10, routed) 0.863 4.538 U1/comptY - SLICE_X38Y51 FDRE r U1/comptY_reg[0]/R + SLICE_X19Y26 FDRE (Prop_fdre_C_Q) 0.456 2.115 r SYNC/comptY_reg[9]/Q + net (fo=10, routed) 2.756 4.871 SYNC/comptY_reg__0[9] + SLICE_X28Y23 LUT5 (Prop_lut5_I0_O) 0.150 5.021 r SYNC/comptY[9]_i_9/O + net (fo=1, routed) 0.989 6.010 SYNC/comptY[9]_i_9_n_0 + SLICE_X29Y25 LUT6 (Prop_lut6_I0_O) 0.328 6.338 r SYNC/comptY[9]_i_5/O + net (fo=1, routed) 0.845 7.183 SYNC/comptY[9]_i_5_n_0 + SLICE_X29Y25 LUT6 (Prop_lut6_I5_O) 0.124 7.307 r SYNC/comptY[9]_i_1/O + net (fo=10, routed) 0.958 8.264 SYNC/comptY + SLICE_X19Y25 FDRE r SYNC/comptY_reg[2]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r - L16 0.000 40.000 r H125MHz (IN) - net (fo=0) 0.000 40.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.563 38.731 U1/CLK - SLICE_X38Y51 FDRE r U1/comptY_reg[0]/C - clock pessimism 0.473 39.204 - clock uncertainty -0.160 39.044 - SLICE_X38Y51 FDRE (Setup_fdre_C_R) -0.524 38.520 U1/comptY_reg[0] + BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.483 41.486 SYNC/clk_out1 + SLICE_X19Y25 FDRE r SYNC/comptY_reg[2]/C + clock pessimism 0.139 41.625 + clock uncertainty -0.160 41.465 + SLICE_X19Y25 FDRE (Setup_fdre_C_R) -0.429 41.036 SYNC/comptY_reg[2] ------------------------------------------------------------------- - required time 38.520 - arrival time -4.538 + required time 41.036 + arrival time -8.264 ------------------------------------------------------------------- - slack 33.981 + slack 32.771 @@ -893,575 +864,542 @@ Slack (MET) : 33.981ns (required time - arrival time) Min Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 0.261ns (arrival time - required time) - Source: U1/comptY_reg[1]/C +Slack (MET) : 0.218ns (arrival time - required time) + Source: SYNC/comptX_reg[4]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptY_reg[2]/D + Destination: SYNC/comptX_reg[5]/D (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) - Data Path Delay: 0.368ns (logic 0.183ns (49.756%) route 0.185ns (50.244%)) - Logic Levels: 1 (LUT3=1) - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.706ns - Source Clock Delay (SCD): -0.474ns - Clock Pessimism Removal (CPR): -0.232ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.587 -0.474 U1/CLK - SLICE_X36Y51 FDRE r U1/comptY_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X36Y51 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptY_reg[1]/Q - net (fo=29, routed) 0.185 -0.148 U1/comptY_reg__0[1] - SLICE_X36Y51 LUT3 (Prop_lut3_I0_O) 0.042 -0.106 r U1/comptY[2]_i_1/O - net (fo=1, routed) 0.000 -0.106 U1/comptY[2]_i_1_n_0 - SLICE_X36Y51 FDRE r U1/comptY_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_clk_wiz_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.857 -0.706 U1/CLK - SLICE_X36Y51 FDRE r U1/comptY_reg[2]/C - clock pessimism 0.232 -0.474 - SLICE_X36Y51 FDRE (Hold_fdre_C_D) 0.107 -0.367 U1/comptY_reg[2] - ------------------------------------------------------------------- - required time 0.367 - arrival time -0.106 - ------------------------------------------------------------------- - slack 0.261 - -Slack (MET) : 0.261ns (arrival time - required time) - Source: U1/comptX_reg[5]/C - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptX_reg[5]/D - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk_out1_clk_wiz_1 - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) - Data Path Delay: 0.353ns (logic 0.186ns (52.682%) route 0.167ns (47.318%)) + Data Path Delay: 0.310ns (logic 0.227ns (73.156%) route 0.083ns (26.844%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.705ns - Source Clock Delay (SCD): -0.473ns - Clock Pessimism Removal (CPR): -0.232ns + Destination Clock Delay (DCD): 0.821ns + Source Clock Delay (SCD): 0.555ns + Clock Pessimism Removal (CPR): 0.266ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.588 -0.473 U1/CLK - SLICE_X43Y54 FDRE r U1/comptX_reg[5]/C + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.548 0.548 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.053 -0.506 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.482 -0.024 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.002 r U0/inst/clkout1_buf/O + net (fo=60, routed) 0.553 0.555 SYNC/clk_out1 + SLICE_X29Y21 FDRE r SYNC/comptX_reg[4]/C ------------------------------------------------------------------- ------------------- - SLICE_X43Y54 FDRE (Prop_fdre_C_Q) 0.141 -0.332 r U1/comptX_reg[5]/Q - net (fo=25, routed) 0.167 -0.165 U1/comptX_reg__0[5] - SLICE_X43Y54 LUT6 (Prop_lut6_I5_O) 0.045 -0.120 r U1/comptX[5]_i_1/O - net (fo=1, routed) 0.000 -0.120 U1/plusOp[5] - SLICE_X43Y54 FDRE r U1/comptX_reg[5]/D + SLICE_X29Y21 FDRE (Prop_fdre_C_Q) 0.128 0.683 r SYNC/comptX_reg[4]/Q + net (fo=10, routed) 0.083 0.766 SYNC/comptX_reg__0[4] + SLICE_X29Y21 LUT6 (Prop_lut6_I0_O) 0.099 0.865 r SYNC/comptX[5]_i_1/O + net (fo=1, routed) 0.000 0.865 SYNC/p_0_in[5] + SLICE_X29Y21 FDRE r SYNC/comptX_reg[5]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.858 -0.705 U1/CLK - SLICE_X43Y54 FDRE r U1/comptX_reg[5]/C - clock pessimism 0.232 -0.473 - SLICE_X43Y54 FDRE (Hold_fdre_C_D) 0.092 -0.381 U1/comptX_reg[5] + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O + net (fo=60, routed) 0.819 0.821 SYNC/clk_out1 + SLICE_X29Y21 FDRE r SYNC/comptX_reg[5]/C + clock pessimism -0.266 0.555 + SLICE_X29Y21 FDRE (Hold_fdre_C_D) 0.092 0.647 SYNC/comptX_reg[5] ------------------------------------------------------------------- - required time 0.381 - arrival time -0.120 + required time -0.647 + arrival time 0.865 ------------------------------------------------------------------- - slack 0.261 + slack 0.218 -Slack (MET) : 0.280ns (arrival time - required time) - Source: U1/comptX_reg[7]/C - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptX_reg[8]/D - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) +Slack (MET) : 0.265ns (arrival time - required time) + Source: SNAKE/startUpdate_reg/C + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: SNAKE/startUpdate_reg/D + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) - Data Path Delay: 0.387ns (logic 0.183ns (47.319%) route 0.204ns (52.681%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.706ns - Source Clock Delay (SCD): -0.474ns - Clock Pessimism Removal (CPR): -0.232ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.587 -0.474 U1/CLK - SLICE_X41Y57 FDRE r U1/comptX_reg[7]/C - ------------------------------------------------------------------- ------------------- - SLICE_X41Y57 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptX_reg[7]/Q - net (fo=20, routed) 0.204 -0.129 U1/comptX_reg__0[7] - SLICE_X41Y57 LUT5 (Prop_lut5_I0_O) 0.042 -0.087 r U1/comptX[8]_i_1/O - net (fo=1, routed) 0.000 -0.087 U1/plusOp[8] - SLICE_X41Y57 FDRE r U1/comptX_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_clk_wiz_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.857 -0.706 U1/CLK - SLICE_X41Y57 FDRE r U1/comptX_reg[8]/C - clock pessimism 0.232 -0.474 - SLICE_X41Y57 FDRE (Hold_fdre_C_D) 0.107 -0.367 U1/comptX_reg[8] - ------------------------------------------------------------------- - required time 0.367 - arrival time -0.087 - ------------------------------------------------------------------- - slack 0.280 - -Slack (MET) : 0.280ns (arrival time - required time) - Source: U1/comptY_reg[1]/C - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptY_reg[1]/D - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk_out1_clk_wiz_1 - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) - Data Path Delay: 0.371ns (logic 0.186ns (50.162%) route 0.185ns (49.838%)) + Data Path Delay: 0.356ns (logic 0.186ns (52.178%) route 0.170ns (47.822%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.706ns - Source Clock Delay (SCD): -0.474ns - Clock Pessimism Removal (CPR): -0.232ns + Destination Clock Delay (DCD): 0.830ns + Source Clock Delay (SCD): 0.562ns + Clock Pessimism Removal (CPR): 0.268ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.587 -0.474 U1/CLK - SLICE_X36Y51 FDRE r U1/comptY_reg[1]/C + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.548 0.548 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.053 -0.506 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.482 -0.024 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.002 r U0/inst/clkout1_buf/O + net (fo=60, routed) 0.560 0.562 SNAKE/clk_out1 + SLICE_X23Y44 FDCE r SNAKE/startUpdate_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X36Y51 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptY_reg[1]/Q - net (fo=29, routed) 0.185 -0.148 U1/comptY_reg__0[1] - SLICE_X36Y51 LUT2 (Prop_lut2_I1_O) 0.045 -0.103 r U1/comptY[1]_i_1/O - net (fo=1, routed) 0.000 -0.103 U1/comptY[1]_i_1_n_0 - SLICE_X36Y51 FDRE r U1/comptY_reg[1]/D + SLICE_X23Y44 FDCE (Prop_fdce_C_Q) 0.141 0.703 r SNAKE/startUpdate_reg/Q + net (fo=4, routed) 0.170 0.873 SNAKE/startUpdate + SLICE_X23Y44 LUT2 (Prop_lut2_I1_O) 0.045 0.918 r SNAKE/startUpdate_i_1/O + net (fo=1, routed) 0.000 0.918 SNAKE/startUpdate_i_1_n_0 + SLICE_X23Y44 FDCE r SNAKE/startUpdate_reg/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.857 -0.706 U1/CLK - SLICE_X36Y51 FDRE r U1/comptY_reg[1]/C - clock pessimism 0.232 -0.474 - SLICE_X36Y51 FDRE (Hold_fdre_C_D) 0.091 -0.383 U1/comptY_reg[1] + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O + net (fo=60, routed) 0.828 0.830 SNAKE/clk_out1 + SLICE_X23Y44 FDCE r SNAKE/startUpdate_reg/C + clock pessimism -0.268 0.562 + SLICE_X23Y44 FDCE (Hold_fdce_C_D) 0.091 0.653 SNAKE/startUpdate_reg ------------------------------------------------------------------- - required time 0.383 - arrival time -0.103 + required time -0.653 + arrival time 0.918 ------------------------------------------------------------------- - slack 0.280 + slack 0.265 + +Slack (MET) : 0.281ns (arrival time - required time) + Source: UPD_CLK_DIV/temp_reg[22]/C + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: UPD_CLK_DIV/temp_reg[22]/D + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: clk_out1_clk_wiz_1 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) + Data Path Delay: 0.386ns (logic 0.252ns (65.354%) route 0.134ns (34.646%)) + Logic Levels: 1 (CARRY4=1) + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.849ns + Source Clock Delay (SCD): 0.582ns + Clock Pessimism Removal (CPR): 0.267ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_1 rise edge) + 0.000 0.000 r + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.548 0.548 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.053 -0.506 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.482 -0.024 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.002 r U0/inst/clkout1_buf/O + net (fo=60, routed) 0.580 0.582 UPD_CLK_DIV/clk_out1 + SLICE_X40Y72 FDCE r UPD_CLK_DIV/temp_reg[22]/C + ------------------------------------------------------------------- ------------------- + SLICE_X40Y72 FDCE (Prop_fdce_C_Q) 0.141 0.723 r UPD_CLK_DIV/temp_reg[22]/Q + net (fo=4, routed) 0.134 0.856 UPD_CLK_DIV/temp_reg[22] + SLICE_X40Y72 CARRY4 (Prop_carry4_S[2]_O[2]) + 0.111 0.967 r UPD_CLK_DIV/temp_reg[20]_i_1/O[2] + net (fo=1, routed) 0.000 0.967 UPD_CLK_DIV/temp_reg[20]_i_1_n_5 + SLICE_X40Y72 FDCE r UPD_CLK_DIV/temp_reg[22]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_1 rise edge) + 0.000 0.000 r + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O + net (fo=60, routed) 0.847 0.849 UPD_CLK_DIV/clk_out1 + SLICE_X40Y72 FDCE r UPD_CLK_DIV/temp_reg[22]/C + clock pessimism -0.267 0.582 + SLICE_X40Y72 FDCE (Hold_fdce_C_D) 0.105 0.687 UPD_CLK_DIV/temp_reg[22] + ------------------------------------------------------------------- + required time -0.687 + arrival time 0.967 + ------------------------------------------------------------------- + slack 0.281 Slack (MET) : 0.288ns (arrival time - required time) - Source: U1/comptX_reg[0]/C + Source: SYNC/comptY_reg[0]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptX_reg[1]/D + Destination: SYNC/comptY_reg[0]/D (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) - Data Path Delay: 0.419ns (logic 0.207ns (49.431%) route 0.212ns (50.569%)) - Logic Levels: 1 (LUT2=1) + Data Path Delay: 0.379ns (logic 0.186ns (49.124%) route 0.193ns (50.876%)) + Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.705ns - Source Clock Delay (SCD): -0.473ns - Clock Pessimism Removal (CPR): -0.232ns + Destination Clock Delay (DCD): 0.818ns + Source Clock Delay (SCD): 0.553ns + Clock Pessimism Removal (CPR): 0.265ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.588 -0.473 U1/CLK - SLICE_X42Y55 FDRE r U1/comptX_reg[0]/C + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.548 0.548 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.053 -0.506 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.482 -0.024 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.002 r U0/inst/clkout1_buf/O + net (fo=60, routed) 0.551 0.553 SYNC/clk_out1 + SLICE_X17Y26 FDRE r SYNC/comptY_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X42Y55 FDRE (Prop_fdre_C_Q) 0.164 -0.309 r U1/comptX_reg[0]/Q - net (fo=25, routed) 0.212 -0.097 U1/comptX_reg__0[0] - SLICE_X42Y55 LUT2 (Prop_lut2_I0_O) 0.043 -0.054 r U1/comptX[1]_i_1/O - net (fo=1, routed) 0.000 -0.054 U1/plusOp[1] - SLICE_X42Y55 FDRE r U1/comptX_reg[1]/D + SLICE_X17Y26 FDRE (Prop_fdre_C_Q) 0.141 0.694 f SYNC/comptY_reg[0]/Q + net (fo=58, routed) 0.193 0.886 SYNC/comptY_reg__0[0] + SLICE_X17Y26 LUT1 (Prop_lut1_I0_O) 0.045 0.931 r SYNC/comptY[0]_i_1/O + net (fo=1, routed) 0.000 0.931 SYNC/comptY[0]_i_1_n_0 + SLICE_X17Y26 FDRE r SYNC/comptY_reg[0]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.858 -0.705 U1/CLK - SLICE_X42Y55 FDRE r U1/comptX_reg[1]/C - clock pessimism 0.232 -0.473 - SLICE_X42Y55 FDRE (Hold_fdre_C_D) 0.131 -0.342 U1/comptX_reg[1] + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O + net (fo=60, routed) 0.816 0.818 SYNC/clk_out1 + SLICE_X17Y26 FDRE r SYNC/comptY_reg[0]/C + clock pessimism -0.265 0.553 + SLICE_X17Y26 FDRE (Hold_fdre_C_D) 0.091 0.644 SYNC/comptY_reg[0] ------------------------------------------------------------------- - required time 0.342 - arrival time -0.054 + required time -0.644 + arrival time 0.931 ------------------------------------------------------------------- slack 0.288 -Slack (MET) : 0.289ns (arrival time - required time) - Source: U1/comptX_reg[7]/C - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptX_reg[9]/D - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) +Slack (MET) : 0.292ns (arrival time - required time) + Source: UPD_CLK_DIV/temp_reg[14]/C + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: UPD_CLK_DIV/temp_reg[14]/D + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) - Data Path Delay: 0.398ns (logic 0.186ns (46.766%) route 0.212ns (53.234%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.705ns - Source Clock Delay (SCD): -0.474ns - Clock Pessimism Removal (CPR): -0.248ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.587 -0.474 U1/CLK - SLICE_X41Y57 FDRE r U1/comptX_reg[7]/C - ------------------------------------------------------------------- ------------------- - SLICE_X41Y57 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptX_reg[7]/Q - net (fo=20, routed) 0.212 -0.121 U1/comptX_reg__0[7] - SLICE_X41Y56 LUT6 (Prop_lut6_I3_O) 0.045 -0.076 r U1/comptX[9]_i_1/O - net (fo=1, routed) 0.000 -0.076 U1/plusOp[9] - SLICE_X41Y56 FDRE r U1/comptX_reg[9]/D - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_clk_wiz_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.858 -0.705 U1/CLK - SLICE_X41Y56 FDRE r U1/comptX_reg[9]/C - clock pessimism 0.248 -0.457 - SLICE_X41Y56 FDRE (Hold_fdre_C_D) 0.092 -0.365 U1/comptX_reg[9] - ------------------------------------------------------------------- - required time 0.365 - arrival time -0.076 - ------------------------------------------------------------------- - slack 0.289 - -Slack (MET) : 0.297ns (arrival time - required time) - Source: U1/comptY_reg[6]/C - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptY_reg[6]/D - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk_out1_clk_wiz_1 - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) - Data Path Delay: 0.402ns (logic 0.183ns (45.514%) route 0.219ns (54.486%)) - Logic Levels: 1 (LUT3=1) + Data Path Delay: 0.397ns (logic 0.252ns (63.525%) route 0.145ns (36.475%)) + Logic Levels: 1 (CARRY4=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.706ns - Source Clock Delay (SCD): -0.474ns - Clock Pessimism Removal (CPR): -0.232ns + Destination Clock Delay (DCD): 0.851ns + Source Clock Delay (SCD): 0.583ns + Clock Pessimism Removal (CPR): 0.268ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.587 -0.474 U1/CLK - SLICE_X36Y50 FDRE r U1/comptY_reg[6]/C + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.548 0.548 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.053 -0.506 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.482 -0.024 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.002 r U0/inst/clkout1_buf/O + net (fo=60, routed) 0.581 0.583 UPD_CLK_DIV/clk_out1 + SLICE_X40Y70 FDCE r UPD_CLK_DIV/temp_reg[14]/C ------------------------------------------------------------------- ------------------- - SLICE_X36Y50 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptY_reg[6]/Q - net (fo=21, routed) 0.219 -0.114 U1/comptY_reg__0[6] - SLICE_X36Y50 LUT3 (Prop_lut3_I2_O) 0.042 -0.072 r U1/comptY[6]_i_1/O - net (fo=1, routed) 0.000 -0.072 U1/plusOp__0[6] - SLICE_X36Y50 FDRE r U1/comptY_reg[6]/D + SLICE_X40Y70 FDCE (Prop_fdce_C_Q) 0.141 0.724 r UPD_CLK_DIV/temp_reg[14]/Q + net (fo=4, routed) 0.145 0.868 UPD_CLK_DIV/temp_reg[14] + SLICE_X40Y70 CARRY4 (Prop_carry4_S[2]_O[2]) + 0.111 0.979 r UPD_CLK_DIV/temp_reg[12]_i_1/O[2] + net (fo=1, routed) 0.000 0.979 UPD_CLK_DIV/temp_reg[12]_i_1_n_5 + SLICE_X40Y70 FDCE r UPD_CLK_DIV/temp_reg[14]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.857 -0.706 U1/CLK - SLICE_X36Y50 FDRE r U1/comptY_reg[6]/C - clock pessimism 0.232 -0.474 - SLICE_X36Y50 FDRE (Hold_fdre_C_D) 0.105 -0.369 U1/comptY_reg[6] + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O + net (fo=60, routed) 0.849 0.851 UPD_CLK_DIV/clk_out1 + SLICE_X40Y70 FDCE r UPD_CLK_DIV/temp_reg[14]/C + clock pessimism -0.268 0.583 + SLICE_X40Y70 FDCE (Hold_fdce_C_D) 0.105 0.688 UPD_CLK_DIV/temp_reg[14] ------------------------------------------------------------------- - required time 0.369 - arrival time -0.072 + required time -0.688 + arrival time 0.979 ------------------------------------------------------------------- - slack 0.297 + slack 0.292 -Slack (MET) : 0.299ns (arrival time - required time) - Source: U1/comptX_reg[7]/C - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptX_reg[7]/D - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) +Slack (MET) : 0.292ns (arrival time - required time) + Source: UPD_CLK_DIV/temp_reg[18]/C + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: UPD_CLK_DIV/temp_reg[18]/D + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) - Data Path Delay: 0.390ns (logic 0.186ns (47.724%) route 0.204ns (52.276%)) - Logic Levels: 1 (LUT4=1) + Data Path Delay: 0.397ns (logic 0.252ns (63.515%) route 0.145ns (36.485%)) + Logic Levels: 1 (CARRY4=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.706ns - Source Clock Delay (SCD): -0.474ns - Clock Pessimism Removal (CPR): -0.232ns + Destination Clock Delay (DCD): 0.850ns + Source Clock Delay (SCD): 0.582ns + Clock Pessimism Removal (CPR): 0.268ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.587 -0.474 U1/CLK - SLICE_X41Y57 FDRE r U1/comptX_reg[7]/C + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.548 0.548 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.053 -0.506 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.482 -0.024 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.002 r U0/inst/clkout1_buf/O + net (fo=60, routed) 0.580 0.582 UPD_CLK_DIV/clk_out1 + SLICE_X40Y71 FDCE r UPD_CLK_DIV/temp_reg[18]/C ------------------------------------------------------------------- ------------------- - SLICE_X41Y57 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptX_reg[7]/Q - net (fo=20, routed) 0.204 -0.129 U1/comptX_reg__0[7] - SLICE_X41Y57 LUT4 (Prop_lut4_I3_O) 0.045 -0.084 r U1/comptX[7]_i_1/O - net (fo=1, routed) 0.000 -0.084 U1/plusOp[7] - SLICE_X41Y57 FDRE r U1/comptX_reg[7]/D + SLICE_X40Y71 FDCE (Prop_fdce_C_Q) 0.141 0.723 r UPD_CLK_DIV/temp_reg[18]/Q + net (fo=3, routed) 0.145 0.867 UPD_CLK_DIV/temp_reg[18] + SLICE_X40Y71 CARRY4 (Prop_carry4_S[2]_O[2]) + 0.111 0.978 r UPD_CLK_DIV/temp_reg[16]_i_1/O[2] + net (fo=1, routed) 0.000 0.978 UPD_CLK_DIV/temp_reg[16]_i_1_n_5 + SLICE_X40Y71 FDCE r UPD_CLK_DIV/temp_reg[18]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.857 -0.706 U1/CLK - SLICE_X41Y57 FDRE r U1/comptX_reg[7]/C - clock pessimism 0.232 -0.474 - SLICE_X41Y57 FDRE (Hold_fdre_C_D) 0.091 -0.383 U1/comptX_reg[7] + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O + net (fo=60, routed) 0.848 0.850 UPD_CLK_DIV/clk_out1 + SLICE_X40Y71 FDCE r UPD_CLK_DIV/temp_reg[18]/C + clock pessimism -0.268 0.582 + SLICE_X40Y71 FDCE (Hold_fdce_C_D) 0.105 0.687 UPD_CLK_DIV/temp_reg[18] ------------------------------------------------------------------- - required time 0.383 - arrival time -0.084 + required time -0.687 + arrival time 0.978 ------------------------------------------------------------------- - slack 0.299 + slack 0.292 -Slack (MET) : 0.301ns (arrival time - required time) - Source: U1/comptY_reg[0]/C - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptY_reg[0]/D - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) +Slack (MET) : 0.293ns (arrival time - required time) + Source: UPD_CLK_DIV/temp_reg[10]/C + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: UPD_CLK_DIV/temp_reg[10]/D + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) - Data Path Delay: 0.421ns (logic 0.209ns (49.671%) route 0.212ns (50.329%)) - Logic Levels: 1 (LUT1=1) + Data Path Delay: 0.398ns (logic 0.252ns (63.360%) route 0.146ns (36.640%)) + Logic Levels: 1 (CARRY4=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.706ns - Source Clock Delay (SCD): -0.474ns - Clock Pessimism Removal (CPR): -0.232ns + Destination Clock Delay (DCD): 0.852ns + Source Clock Delay (SCD): 0.584ns + Clock Pessimism Removal (CPR): 0.268ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.587 -0.474 U1/CLK - SLICE_X38Y51 FDRE r U1/comptY_reg[0]/C + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.548 0.548 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.053 -0.506 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.482 -0.024 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.002 r U0/inst/clkout1_buf/O + net (fo=60, routed) 0.582 0.584 UPD_CLK_DIV/clk_out1 + SLICE_X40Y69 FDCE r UPD_CLK_DIV/temp_reg[10]/C ------------------------------------------------------------------- ------------------- - SLICE_X38Y51 FDRE (Prop_fdre_C_Q) 0.164 -0.310 f U1/comptY_reg[0]/Q - net (fo=29, routed) 0.212 -0.098 U1/comptY_reg__0[0] - SLICE_X38Y51 LUT1 (Prop_lut1_I0_O) 0.045 -0.053 r U1/comptY[0]_i_1/O - net (fo=1, routed) 0.000 -0.053 U1/comptY[0]_i_1_n_0 - SLICE_X38Y51 FDRE r U1/comptY_reg[0]/D + SLICE_X40Y69 FDCE (Prop_fdce_C_Q) 0.141 0.725 r UPD_CLK_DIV/temp_reg[10]/Q + net (fo=3, routed) 0.146 0.870 UPD_CLK_DIV/temp_reg[10] + SLICE_X40Y69 CARRY4 (Prop_carry4_S[2]_O[2]) + 0.111 0.981 r UPD_CLK_DIV/temp_reg[8]_i_1/O[2] + net (fo=1, routed) 0.000 0.981 UPD_CLK_DIV/temp_reg[8]_i_1_n_5 + SLICE_X40Y69 FDCE r UPD_CLK_DIV/temp_reg[10]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.857 -0.706 U1/CLK - SLICE_X38Y51 FDRE r U1/comptY_reg[0]/C - clock pessimism 0.232 -0.474 - SLICE_X38Y51 FDRE (Hold_fdre_C_D) 0.120 -0.354 U1/comptY_reg[0] + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O + net (fo=60, routed) 0.850 0.852 UPD_CLK_DIV/clk_out1 + SLICE_X40Y69 FDCE r UPD_CLK_DIV/temp_reg[10]/C + clock pessimism -0.268 0.584 + SLICE_X40Y69 FDCE (Hold_fdce_C_D) 0.105 0.689 UPD_CLK_DIV/temp_reg[10] ------------------------------------------------------------------- - required time 0.354 - arrival time -0.053 + required time -0.689 + arrival time 0.981 ------------------------------------------------------------------- - slack 0.301 + slack 0.293 -Slack (MET) : 0.301ns (arrival time - required time) - Source: U1/comptX_reg[0]/C - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptX_reg[0]/D - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) +Slack (MET) : 0.314ns (arrival time - required time) + Source: UPD_CLK_DIV/temp_reg[22]/C + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: UPD_CLK_DIV/temp_reg[23]/D + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) - Data Path Delay: 0.421ns (logic 0.209ns (49.671%) route 0.212ns (50.329%)) - Logic Levels: 1 (LUT1=1) + Data Path Delay: 0.419ns (logic 0.285ns (68.085%) route 0.134ns (31.915%)) + Logic Levels: 1 (CARRY4=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.705ns - Source Clock Delay (SCD): -0.473ns - Clock Pessimism Removal (CPR): -0.232ns + Destination Clock Delay (DCD): 0.849ns + Source Clock Delay (SCD): 0.582ns + Clock Pessimism Removal (CPR): 0.267ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.588 -0.473 U1/CLK - SLICE_X42Y55 FDRE r U1/comptX_reg[0]/C + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.548 0.548 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.053 -0.506 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.482 -0.024 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.002 r U0/inst/clkout1_buf/O + net (fo=60, routed) 0.580 0.582 UPD_CLK_DIV/clk_out1 + SLICE_X40Y72 FDCE r UPD_CLK_DIV/temp_reg[22]/C ------------------------------------------------------------------- ------------------- - SLICE_X42Y55 FDRE (Prop_fdre_C_Q) 0.164 -0.309 f U1/comptX_reg[0]/Q - net (fo=25, routed) 0.212 -0.097 U1/comptX_reg__0[0] - SLICE_X42Y55 LUT1 (Prop_lut1_I0_O) 0.045 -0.052 r U1/comptX[0]_i_1/O - net (fo=1, routed) 0.000 -0.052 U1/plusOp[0] - SLICE_X42Y55 FDRE r U1/comptX_reg[0]/D + SLICE_X40Y72 FDCE (Prop_fdce_C_Q) 0.141 0.723 r UPD_CLK_DIV/temp_reg[22]/Q + net (fo=4, routed) 0.134 0.856 UPD_CLK_DIV/temp_reg[22] + SLICE_X40Y72 CARRY4 (Prop_carry4_S[2]_O[3]) + 0.144 1.000 r UPD_CLK_DIV/temp_reg[20]_i_1/O[3] + net (fo=1, routed) 0.000 1.000 UPD_CLK_DIV/temp_reg[20]_i_1_n_4 + SLICE_X40Y72 FDCE r UPD_CLK_DIV/temp_reg[23]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.858 -0.705 U1/CLK - SLICE_X42Y55 FDRE r U1/comptX_reg[0]/C - clock pessimism 0.232 -0.473 - SLICE_X42Y55 FDRE (Hold_fdre_C_D) 0.120 -0.353 U1/comptX_reg[0] + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O + net (fo=60, routed) 0.847 0.849 UPD_CLK_DIV/clk_out1 + SLICE_X40Y72 FDCE r UPD_CLK_DIV/temp_reg[23]/C + clock pessimism -0.267 0.582 + SLICE_X40Y72 FDCE (Hold_fdce_C_D) 0.105 0.687 UPD_CLK_DIV/temp_reg[23] ------------------------------------------------------------------- - required time 0.353 - arrival time -0.052 + required time -0.687 + arrival time 1.000 ------------------------------------------------------------------- - slack 0.301 + slack 0.314 + +Slack (MET) : 0.325ns (arrival time - required time) + Source: UPD_CLK_DIV/temp_reg[14]/C + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: UPD_CLK_DIV/temp_reg[15]/D + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: clk_out1_clk_wiz_1 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) + Data Path Delay: 0.430ns (logic 0.285ns (66.326%) route 0.145ns (33.674%)) + Logic Levels: 1 (CARRY4=1) + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.851ns + Source Clock Delay (SCD): 0.583ns + Clock Pessimism Removal (CPR): 0.268ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_1 rise edge) + 0.000 0.000 r + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.548 0.548 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.053 -0.506 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.482 -0.024 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.002 r U0/inst/clkout1_buf/O + net (fo=60, routed) 0.581 0.583 UPD_CLK_DIV/clk_out1 + SLICE_X40Y70 FDCE r UPD_CLK_DIV/temp_reg[14]/C + ------------------------------------------------------------------- ------------------- + SLICE_X40Y70 FDCE (Prop_fdce_C_Q) 0.141 0.724 r UPD_CLK_DIV/temp_reg[14]/Q + net (fo=4, routed) 0.145 0.868 UPD_CLK_DIV/temp_reg[14] + SLICE_X40Y70 CARRY4 (Prop_carry4_S[2]_O[3]) + 0.144 1.012 r UPD_CLK_DIV/temp_reg[12]_i_1/O[3] + net (fo=1, routed) 0.000 1.012 UPD_CLK_DIV/temp_reg[12]_i_1_n_4 + SLICE_X40Y70 FDCE r UPD_CLK_DIV/temp_reg[15]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_1 rise edge) + 0.000 0.000 r + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O + net (fo=60, routed) 0.849 0.851 UPD_CLK_DIV/clk_out1 + SLICE_X40Y70 FDCE r UPD_CLK_DIV/temp_reg[15]/C + clock pessimism -0.268 0.583 + SLICE_X40Y70 FDCE (Hold_fdce_C_D) 0.105 0.688 UPD_CLK_DIV/temp_reg[15] + ------------------------------------------------------------------- + required time -0.688 + arrival time 1.012 + ------------------------------------------------------------------- + slack 0.325 + +Slack (MET) : 0.325ns (arrival time - required time) + Source: UPD_CLK_DIV/temp_reg[18]/C + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: UPD_CLK_DIV/temp_reg[19]/D + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: clk_out1_clk_wiz_1 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) + Data Path Delay: 0.430ns (logic 0.285ns (66.316%) route 0.145ns (33.684%)) + Logic Levels: 1 (CARRY4=1) + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.850ns + Source Clock Delay (SCD): 0.582ns + Clock Pessimism Removal (CPR): 0.268ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_1 rise edge) + 0.000 0.000 r + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.548 0.548 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.053 -0.506 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.482 -0.024 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.002 r U0/inst/clkout1_buf/O + net (fo=60, routed) 0.580 0.582 UPD_CLK_DIV/clk_out1 + SLICE_X40Y71 FDCE r UPD_CLK_DIV/temp_reg[18]/C + ------------------------------------------------------------------- ------------------- + SLICE_X40Y71 FDCE (Prop_fdce_C_Q) 0.141 0.723 r UPD_CLK_DIV/temp_reg[18]/Q + net (fo=3, routed) 0.145 0.867 UPD_CLK_DIV/temp_reg[18] + SLICE_X40Y71 CARRY4 (Prop_carry4_S[2]_O[3]) + 0.144 1.011 r UPD_CLK_DIV/temp_reg[16]_i_1/O[3] + net (fo=1, routed) 0.000 1.011 UPD_CLK_DIV/temp_reg[16]_i_1_n_4 + SLICE_X40Y71 FDCE r UPD_CLK_DIV/temp_reg[19]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_1 rise edge) + 0.000 0.000 r + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O + net (fo=60, routed) 0.848 0.850 UPD_CLK_DIV/clk_out1 + SLICE_X40Y71 FDCE r UPD_CLK_DIV/temp_reg[19]/C + clock pessimism -0.268 0.582 + SLICE_X40Y71 FDCE (Hold_fdce_C_D) 0.105 0.687 UPD_CLK_DIV/temp_reg[19] + ------------------------------------------------------------------- + required time -0.687 + arrival time 1.011 + ------------------------------------------------------------------- + slack 0.325 @@ -1475,37 +1413,37 @@ Period(ns): 40.000 Sources: { U0/inst/mmcm_adv_inst/CLKOUT0 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin -Min Period n/a BUFG/I n/a 2.155 40.000 37.845 BUFGCTRL_X0Y16 U0/inst/clkout1_buf/I -Min Period n/a MMCME2_ADV/CLKOUT0 n/a 1.249 40.000 38.751 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKOUT0 -Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X42Y55 U1/comptX_reg[0]/C -Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X41Y56 U1/comptX_reg[10]/C -Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X42Y55 U1/comptX_reg[1]/C -Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X43Y54 U1/comptX_reg[2]/C -Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X43Y54 U1/comptX_reg[3]/C -Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X41Y56 U1/comptX_reg[4]/C -Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X38Y51 U1/comptY_reg[0]/C -Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X36Y51 U1/comptY_reg[1]/C -Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 40.000 173.360 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKOUT0 -Low Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X42Y55 U1/comptX_reg[0]/C -Low Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X41Y56 U1/comptX_reg[10]/C -Low Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X42Y55 U1/comptX_reg[1]/C -Low Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X43Y54 U1/comptX_reg[2]/C -Low Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X43Y54 U1/comptX_reg[3]/C -Low Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X41Y56 U1/comptX_reg[4]/C -Low Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X38Y51 U1/comptY_reg[0]/C -Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X38Y51 U1/comptY_reg[0]/C -Low Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X36Y51 U1/comptY_reg[1]/C -Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X36Y51 U1/comptY_reg[1]/C -High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X42Y55 U1/comptX_reg[0]/C -High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X41Y56 U1/comptX_reg[10]/C -High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X42Y55 U1/comptX_reg[1]/C -High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X43Y54 U1/comptX_reg[2]/C -High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X43Y54 U1/comptX_reg[3]/C -High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X41Y56 U1/comptX_reg[4]/C -High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X38Y51 U1/comptY_reg[0]/C -High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X36Y51 U1/comptY_reg[1]/C -High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X36Y51 U1/comptY_reg[2]/C -High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X40Y49 U1/comptY_reg[3]/C +Min Period n/a BUFG/I n/a 2.155 40.000 37.845 BUFGCTRL_X0Y0 U0/inst/clkout1_buf/I +Min Period n/a MMCME2_ADV/CLKOUT0 n/a 1.249 40.000 38.751 MMCME2_ADV_X0Y0 U0/inst/mmcm_adv_inst/CLKOUT0 +Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X27Y24 SYNC/comptX_reg[0]/C +Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X27Y20 SYNC/comptX_reg[10]/C +Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X27Y24 SYNC/comptX_reg[1]/C +Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X29Y21 SYNC/comptX_reg[2]/C +Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X28Y23 SYNC/comptX_reg[3]/C +Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X29Y21 SYNC/comptX_reg[4]/C +Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X29Y21 SYNC/comptX_reg[5]/C +Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X29Y21 SYNC/comptX_reg[6]/C +Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 40.000 173.360 MMCME2_ADV_X0Y0 U0/inst/mmcm_adv_inst/CLKOUT0 +Low Pulse Width Fast FDCE/C n/a 0.500 20.000 19.500 SLICE_X40Y70 UPD_CLK_DIV/temp_reg[12]/C +Low Pulse Width Fast FDCE/C n/a 0.500 20.000 19.500 SLICE_X40Y70 UPD_CLK_DIV/temp_reg[13]/C +Low Pulse Width Fast FDCE/C n/a 0.500 20.000 19.500 SLICE_X40Y70 UPD_CLK_DIV/temp_reg[14]/C +Low Pulse Width Fast FDCE/C n/a 0.500 20.000 19.500 SLICE_X40Y70 UPD_CLK_DIV/temp_reg[15]/C +Low Pulse Width Fast FDCE/C n/a 0.500 20.000 19.500 SLICE_X40Y71 UPD_CLK_DIV/temp_reg[16]/C +Low Pulse Width Fast FDCE/C n/a 0.500 20.000 19.500 SLICE_X40Y71 UPD_CLK_DIV/temp_reg[17]/C +Low Pulse Width Fast FDCE/C n/a 0.500 20.000 19.500 SLICE_X40Y71 UPD_CLK_DIV/temp_reg[18]/C +Low Pulse Width Fast FDCE/C n/a 0.500 20.000 19.500 SLICE_X40Y71 UPD_CLK_DIV/temp_reg[19]/C +Low Pulse Width Fast FDCE/C n/a 0.500 20.000 19.500 SLICE_X40Y68 UPD_CLK_DIV/temp_reg[4]/C +Low Pulse Width Fast FDCE/C n/a 0.500 20.000 19.500 SLICE_X40Y68 UPD_CLK_DIV/temp_reg[5]/C +High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X27Y24 SYNC/comptX_reg[0]/C +High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X27Y20 SYNC/comptX_reg[10]/C +High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X27Y24 SYNC/comptX_reg[1]/C +High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X29Y21 SYNC/comptX_reg[2]/C +High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X28Y23 SYNC/comptX_reg[3]/C +High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X29Y21 SYNC/comptX_reg[4]/C +High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X29Y21 SYNC/comptX_reg[5]/C +High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X29Y21 SYNC/comptX_reg[6]/C +High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X27Y21 SYNC/comptX_reg[7]/C +High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X26Y21 SYNC/comptX_reg[8]/C @@ -1527,11 +1465,11 @@ Period(ns): 40.000 Sources: { U0/inst/mmcm_adv_inst/CLKFBOUT } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin -Min Period n/a BUFG/I n/a 2.155 40.000 37.845 BUFGCTRL_X0Y17 U0/inst/clkf_buf/I -Min Period n/a MMCME2_ADV/CLKFBOUT n/a 1.249 40.000 38.751 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKFBOUT -Min Period n/a MMCME2_ADV/CLKFBIN n/a 1.249 40.000 38.751 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKFBIN -Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 40.000 60.000 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKFBIN -Max Period n/a MMCME2_ADV/CLKFBOUT n/a 213.360 40.000 173.360 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKFBOUT +Min Period n/a BUFG/I n/a 2.155 40.000 37.845 BUFGCTRL_X0Y1 U0/inst/clkf_buf/I +Min Period n/a MMCME2_ADV/CLKFBOUT n/a 1.249 40.000 38.751 MMCME2_ADV_X0Y0 U0/inst/mmcm_adv_inst/CLKFBOUT +Min Period n/a MMCME2_ADV/CLKFBIN n/a 1.249 40.000 38.751 MMCME2_ADV_X0Y0 U0/inst/mmcm_adv_inst/CLKFBIN +Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 40.000 60.000 MMCME2_ADV_X0Y0 U0/inst/mmcm_adv_inst/CLKFBIN +Max Period n/a MMCME2_ADV/CLKFBOUT n/a 213.360 40.000 173.360 MMCME2_ADV_X0Y0 U0/inst/mmcm_adv_inst/CLKFBOUT @@ -1539,12 +1477,1362 @@ Max Period n/a MMCME2_ADV/CLKFBOUT n/a 213.360 40.000 From Clock: sys_clk_pin To Clock: sys_clk_pin -Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA -Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA -PW : 0 Failing Endpoints, Worst Slack 2.000ns, Total Violation 0.000ns +Setup : 22 Failing Endpoints, Worst Slack -5.611ns, Total Violation -86.314ns +Hold : 0 Failing Endpoints, Worst Slack 0.078ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 3.500ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (VIOLATED) : -5.611ns (required time - arrival time) + Source: RAMCTRL/SNAKE_RAM/mem_reg_5_0/CLKBWRCLK + (rising edge-triggered cell RAMB36E1 clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: SNAKE/ROMAddress_reg[9]/D + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: sys_clk_pin + Path Type: Setup (Max at Slow Process Corner) + Requirement: 8.000ns (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 13.483ns (logic 5.745ns (42.610%) route 7.738ns (57.390%)) + Logic Levels: 12 (CARRY4=4 LUT2=2 LUT4=1 LUT6=5) + Clock Path Skew: -0.202ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 4.883ns = ( 12.883 - 8.000 ) + Source Clock Delay (SCD): 5.376ns + Clock Pessimism Removal (CPR): 0.291ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O + net (fo=1, routed) 2.076 3.567 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.707 5.376 RAMCTRL/SNAKE_RAM/H125MHz + RAMB36_X1Y6 RAMB36E1 r RAMCTRL/SNAKE_RAM/mem_reg_5_0/CLKBWRCLK + ------------------------------------------------------------------- ------------------- + RAMB36_X1Y6 RAMB36E1 (Prop_ramb36e1_CLKBWRCLK_DOBDO[15]) + 2.454 7.830 r RAMCTRL/SNAKE_RAM/mem_reg_5_0/DOBDO[15] + net (fo=4, routed) 1.087 8.916 RAMCTRL/SNAKE_RAM/output_reg[4][4] + SLICE_X23Y28 LUT2 (Prop_lut2_I0_O) 0.124 9.040 r RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_307/O + net (fo=1, routed) 0.000 9.040 SYNC/ROMAddress[7]_i_108_0[1] + SLICE_X23Y28 CARRY4 (Prop_carry4_S[1]_O[2]) + 0.580 9.620 r SYNC/ROMAddress_reg[7]_i_252/O[2] + net (fo=5, routed) 1.352 10.972 RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_40_1[1] + SLICE_X22Y28 LUT4 (Prop_lut4_I3_O) 0.302 11.274 r RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_108/O + net (fo=1, routed) 0.000 11.274 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_108_n_0 + SLICE_X22Y28 CARRY4 (Prop_carry4_S[1]_O[3]) + 0.640 11.914 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_40/O[3] + net (fo=2, routed) 1.031 12.945 RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_40_n_4 + SLICE_X15Y29 LUT6 (Prop_lut6_I0_O) 0.306 13.251 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_214/O + net (fo=6, routed) 0.774 14.024 RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_214_n_0 + SLICE_X10Y29 LUT2 (Prop_lut2_I1_O) 0.124 14.148 r RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_263/O + net (fo=1, routed) 0.793 14.942 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_263_n_0 + SLICE_X17Y28 LUT6 (Prop_lut6_I2_O) 0.124 15.066 r RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_128/O + net (fo=1, routed) 0.658 15.724 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_128_n_0 + SLICE_X16Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.848 f RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_46/O + net (fo=1, routed) 0.559 16.407 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_46_n_0 + SLICE_X16Y29 LUT6 (Prop_lut6_I5_O) 0.124 16.531 f RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_15/O + net (fo=3, routed) 0.533 17.064 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_15_n_0 + SLICE_X16Y29 LUT6 (Prop_lut6_I5_O) 0.124 17.188 r RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_2/O + net (fo=1, routed) 0.951 18.139 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_2_n_0 + SLICE_X20Y29 CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.396 18.535 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.000 18.535 RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_1_n_0 + SLICE_X20Y30 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 18.858 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_2/O[1] + net (fo=1, routed) 0.000 18.858 SNAKE/D[9] + SLICE_X20Y30 FDRE r SNAKE/ROMAddress_reg[9]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 8.000 8.000 r + L16 0.000 8.000 r H125MHz (IN) + net (fo=0) 0.000 8.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O + net (fo=1, routed) 1.880 11.301 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.491 12.883 SNAKE/H125MHz + SLICE_X20Y30 FDRE r SNAKE/ROMAddress_reg[9]/C + clock pessimism 0.291 13.174 + clock uncertainty -0.035 13.138 + SLICE_X20Y30 FDRE (Setup_fdre_C_D) 0.109 13.247 SNAKE/ROMAddress_reg[9] + ------------------------------------------------------------------- + required time 13.247 + arrival time -18.858 + ------------------------------------------------------------------- + slack -5.611 + +Slack (VIOLATED) : -5.507ns (required time - arrival time) + Source: RAMCTRL/SNAKE_RAM/mem_reg_5_0/CLKBWRCLK + (rising edge-triggered cell RAMB36E1 clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: SNAKE/ROMAddress_reg[8]/D + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: sys_clk_pin + Path Type: Setup (Max at Slow Process Corner) + Requirement: 8.000ns (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 13.379ns (logic 5.641ns (42.164%) route 7.738ns (57.836%)) + Logic Levels: 12 (CARRY4=4 LUT2=2 LUT4=1 LUT6=5) + Clock Path Skew: -0.202ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 4.883ns = ( 12.883 - 8.000 ) + Source Clock Delay (SCD): 5.376ns + Clock Pessimism Removal (CPR): 0.291ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O + net (fo=1, routed) 2.076 3.567 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.707 5.376 RAMCTRL/SNAKE_RAM/H125MHz + RAMB36_X1Y6 RAMB36E1 r RAMCTRL/SNAKE_RAM/mem_reg_5_0/CLKBWRCLK + ------------------------------------------------------------------- ------------------- + RAMB36_X1Y6 RAMB36E1 (Prop_ramb36e1_CLKBWRCLK_DOBDO[15]) + 2.454 7.830 r RAMCTRL/SNAKE_RAM/mem_reg_5_0/DOBDO[15] + net (fo=4, routed) 1.087 8.916 RAMCTRL/SNAKE_RAM/output_reg[4][4] + SLICE_X23Y28 LUT2 (Prop_lut2_I0_O) 0.124 9.040 r RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_307/O + net (fo=1, routed) 0.000 9.040 SYNC/ROMAddress[7]_i_108_0[1] + SLICE_X23Y28 CARRY4 (Prop_carry4_S[1]_O[2]) + 0.580 9.620 r SYNC/ROMAddress_reg[7]_i_252/O[2] + net (fo=5, routed) 1.352 10.972 RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_40_1[1] + SLICE_X22Y28 LUT4 (Prop_lut4_I3_O) 0.302 11.274 r RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_108/O + net (fo=1, routed) 0.000 11.274 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_108_n_0 + SLICE_X22Y28 CARRY4 (Prop_carry4_S[1]_O[3]) + 0.640 11.914 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_40/O[3] + net (fo=2, routed) 1.031 12.945 RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_40_n_4 + SLICE_X15Y29 LUT6 (Prop_lut6_I0_O) 0.306 13.251 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_214/O + net (fo=6, routed) 0.774 14.024 RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_214_n_0 + SLICE_X10Y29 LUT2 (Prop_lut2_I1_O) 0.124 14.148 r RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_263/O + net (fo=1, routed) 0.793 14.942 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_263_n_0 + SLICE_X17Y28 LUT6 (Prop_lut6_I2_O) 0.124 15.066 r RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_128/O + net (fo=1, routed) 0.658 15.724 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_128_n_0 + SLICE_X16Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.848 f RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_46/O + net (fo=1, routed) 0.559 16.407 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_46_n_0 + SLICE_X16Y29 LUT6 (Prop_lut6_I5_O) 0.124 16.531 f RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_15/O + net (fo=3, routed) 0.533 17.064 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_15_n_0 + SLICE_X16Y29 LUT6 (Prop_lut6_I5_O) 0.124 17.188 r RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_2/O + net (fo=1, routed) 0.951 18.139 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_2_n_0 + SLICE_X20Y29 CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.396 18.535 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.000 18.535 RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_1_n_0 + SLICE_X20Y30 CARRY4 (Prop_carry4_CI_O[0]) + 0.219 18.754 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_2/O[0] + net (fo=1, routed) 0.000 18.754 SNAKE/D[8] + SLICE_X20Y30 FDRE r SNAKE/ROMAddress_reg[8]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 8.000 8.000 r + L16 0.000 8.000 r H125MHz (IN) + net (fo=0) 0.000 8.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O + net (fo=1, routed) 1.880 11.301 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.491 12.883 SNAKE/H125MHz + SLICE_X20Y30 FDRE r SNAKE/ROMAddress_reg[8]/C + clock pessimism 0.291 13.174 + clock uncertainty -0.035 13.138 + SLICE_X20Y30 FDRE (Setup_fdre_C_D) 0.109 13.247 SNAKE/ROMAddress_reg[8] + ------------------------------------------------------------------- + required time 13.247 + arrival time -18.754 + ------------------------------------------------------------------- + slack -5.507 + +Slack (VIOLATED) : -4.950ns (required time - arrival time) + Source: RAMCTRL/SNAKE_RAM/mem_reg_7_0/CLKBWRCLK + (rising edge-triggered cell RAMB36E1 clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: SNAKE/ROMAddress_reg[5]/D + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: sys_clk_pin + Path Type: Setup (Max at Slow Process Corner) + Requirement: 8.000ns (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 12.824ns (logic 5.086ns (39.661%) route 7.738ns (60.339%)) + Logic Levels: 12 (CARRY4=4 LUT3=1 LUT5=2 LUT6=5) + Clock Path Skew: -0.200ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 4.883ns = ( 12.883 - 8.000 ) + Source Clock Delay (SCD): 5.374ns + Clock Pessimism Removal (CPR): 0.291ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O + net (fo=1, routed) 2.076 3.567 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.705 5.374 RAMCTRL/SNAKE_RAM/H125MHz + RAMB36_X2Y4 RAMB36E1 r RAMCTRL/SNAKE_RAM/mem_reg_7_0/CLKBWRCLK + ------------------------------------------------------------------- ------------------- + RAMB36_X2Y4 RAMB36E1 (Prop_ramb36e1_CLKBWRCLK_DOBDO[8]) + 2.454 7.828 f RAMCTRL/SNAKE_RAM/mem_reg_7_0/DOBDO[8] + net (fo=17, routed) 1.255 9.083 RAMCTRL/SNAKE_RAM/output_reg[6][2] + SLICE_X31Y24 LUT3 (Prop_lut3_I1_O) 0.124 9.207 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_630/O + net (fo=4, routed) 1.037 10.243 RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_630_n_0 + SLICE_X25Y25 LUT5 (Prop_lut5_I3_O) 0.124 10.367 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_626/O + net (fo=1, routed) 0.000 10.367 RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_626_n_0 + SLICE_X25Y25 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.401 10.768 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_330/CO[3] + net (fo=1, routed) 0.000 10.768 RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_330_n_0 + SLICE_X25Y26 CARRY4 (Prop_carry4_CI_CO[0]) + 0.271 11.039 f RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_114/CO[0] + net (fo=1, routed) 0.820 11.859 RAMCTRL/SNAKE_RAM/SNAKE/snakeHere36_in + SLICE_X25Y27 LUT5 (Prop_lut5_I2_O) 0.373 12.232 f RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_35/O + net (fo=13, routed) 0.982 13.214 RAMCTRL/SNAKE_RAM/mem_reg_7_0_4 + SLICE_X25Y27 LUT6 (Prop_lut6_I5_O) 0.124 13.338 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_10/O + net (fo=10, routed) 0.705 14.043 RAMCTRL/SNAKE_RAM/mem_reg_8_0_4 + SLICE_X25Y30 LUT6 (Prop_lut6_I2_O) 0.124 14.167 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_72/O + net (fo=1, routed) 0.593 14.760 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_72_n_0 + SLICE_X24Y29 LUT6 (Prop_lut6_I4_O) 0.124 14.884 f RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_27/O + net (fo=2, routed) 0.761 15.645 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_27_n_0 + SLICE_X19Y27 LUT6 (Prop_lut6_I3_O) 0.124 15.769 f RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_10/O + net (fo=1, routed) 0.714 16.483 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_10_n_0 + SLICE_X19Y28 LUT6 (Prop_lut6_I0_O) 0.124 16.607 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_2/O + net (fo=1, routed) 0.871 17.479 RAMCTRL/SNAKE_RAM/SNAKE/p_11_out[3] + SLICE_X20Y28 CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.396 17.875 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 17.875 RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_1_n_0 + SLICE_X20Y29 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 18.198 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_1/O[1] + net (fo=1, routed) 0.000 18.198 SNAKE/D[5] + SLICE_X20Y29 FDRE r SNAKE/ROMAddress_reg[5]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 8.000 8.000 r + L16 0.000 8.000 r H125MHz (IN) + net (fo=0) 0.000 8.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O + net (fo=1, routed) 1.880 11.301 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.491 12.883 SNAKE/H125MHz + SLICE_X20Y29 FDRE r SNAKE/ROMAddress_reg[5]/C + clock pessimism 0.291 13.174 + clock uncertainty -0.035 13.138 + SLICE_X20Y29 FDRE (Setup_fdre_C_D) 0.109 13.247 SNAKE/ROMAddress_reg[5] + ------------------------------------------------------------------- + required time 13.247 + arrival time -18.198 + ------------------------------------------------------------------- + slack -4.950 + +Slack (VIOLATED) : -4.942ns (required time - arrival time) + Source: RAMCTRL/SNAKE_RAM/mem_reg_7_0/CLKBWRCLK + (rising edge-triggered cell RAMB36E1 clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: SNAKE/ROMAddress_reg[7]/D + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: sys_clk_pin + Path Type: Setup (Max at Slow Process Corner) + Requirement: 8.000ns (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 12.816ns (logic 5.078ns (39.623%) route 7.738ns (60.377%)) + Logic Levels: 12 (CARRY4=4 LUT3=1 LUT5=2 LUT6=5) + Clock Path Skew: -0.200ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 4.883ns = ( 12.883 - 8.000 ) + Source Clock Delay (SCD): 5.374ns + Clock Pessimism Removal (CPR): 0.291ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O + net (fo=1, routed) 2.076 3.567 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.705 5.374 RAMCTRL/SNAKE_RAM/H125MHz + RAMB36_X2Y4 RAMB36E1 r RAMCTRL/SNAKE_RAM/mem_reg_7_0/CLKBWRCLK + ------------------------------------------------------------------- ------------------- + RAMB36_X2Y4 RAMB36E1 (Prop_ramb36e1_CLKBWRCLK_DOBDO[8]) + 2.454 7.828 f RAMCTRL/SNAKE_RAM/mem_reg_7_0/DOBDO[8] + net (fo=17, routed) 1.255 9.083 RAMCTRL/SNAKE_RAM/output_reg[6][2] + SLICE_X31Y24 LUT3 (Prop_lut3_I1_O) 0.124 9.207 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_630/O + net (fo=4, routed) 1.037 10.243 RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_630_n_0 + SLICE_X25Y25 LUT5 (Prop_lut5_I3_O) 0.124 10.367 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_626/O + net (fo=1, routed) 0.000 10.367 RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_626_n_0 + SLICE_X25Y25 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.401 10.768 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_330/CO[3] + net (fo=1, routed) 0.000 10.768 RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_330_n_0 + SLICE_X25Y26 CARRY4 (Prop_carry4_CI_CO[0]) + 0.271 11.039 f RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_114/CO[0] + net (fo=1, routed) 0.820 11.859 RAMCTRL/SNAKE_RAM/SNAKE/snakeHere36_in + SLICE_X25Y27 LUT5 (Prop_lut5_I2_O) 0.373 12.232 f RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_35/O + net (fo=13, routed) 0.982 13.214 RAMCTRL/SNAKE_RAM/mem_reg_7_0_4 + SLICE_X25Y27 LUT6 (Prop_lut6_I5_O) 0.124 13.338 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_10/O + net (fo=10, routed) 0.705 14.043 RAMCTRL/SNAKE_RAM/mem_reg_8_0_4 + SLICE_X25Y30 LUT6 (Prop_lut6_I2_O) 0.124 14.167 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_72/O + net (fo=1, routed) 0.593 14.760 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_72_n_0 + SLICE_X24Y29 LUT6 (Prop_lut6_I4_O) 0.124 14.884 f RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_27/O + net (fo=2, routed) 0.761 15.645 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_27_n_0 + SLICE_X19Y27 LUT6 (Prop_lut6_I3_O) 0.124 15.769 f RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_10/O + net (fo=1, routed) 0.714 16.483 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_10_n_0 + SLICE_X19Y28 LUT6 (Prop_lut6_I0_O) 0.124 16.607 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_2/O + net (fo=1, routed) 0.871 17.479 RAMCTRL/SNAKE_RAM/SNAKE/p_11_out[3] + SLICE_X20Y28 CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.396 17.875 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 17.875 RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_1_n_0 + SLICE_X20Y29 CARRY4 (Prop_carry4_CI_O[3]) + 0.315 18.190 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_1/O[3] + net (fo=1, routed) 0.000 18.190 SNAKE/D[7] + SLICE_X20Y29 FDRE r SNAKE/ROMAddress_reg[7]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 8.000 8.000 r + L16 0.000 8.000 r H125MHz (IN) + net (fo=0) 0.000 8.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O + net (fo=1, routed) 1.880 11.301 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.491 12.883 SNAKE/H125MHz + SLICE_X20Y29 FDRE r SNAKE/ROMAddress_reg[7]/C + clock pessimism 0.291 13.174 + clock uncertainty -0.035 13.138 + SLICE_X20Y29 FDRE (Setup_fdre_C_D) 0.109 13.247 SNAKE/ROMAddress_reg[7] + ------------------------------------------------------------------- + required time 13.247 + arrival time -18.190 + ------------------------------------------------------------------- + slack -4.942 + +Slack (VIOLATED) : -4.866ns (required time - arrival time) + Source: RAMCTRL/SNAKE_RAM/mem_reg_7_0/CLKBWRCLK + (rising edge-triggered cell RAMB36E1 clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: SNAKE/ROMAddress_reg[6]/D + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: sys_clk_pin + Path Type: Setup (Max at Slow Process Corner) + Requirement: 8.000ns (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 12.740ns (logic 5.002ns (39.263%) route 7.738ns (60.737%)) + Logic Levels: 12 (CARRY4=4 LUT3=1 LUT5=2 LUT6=5) + Clock Path Skew: -0.200ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 4.883ns = ( 12.883 - 8.000 ) + Source Clock Delay (SCD): 5.374ns + Clock Pessimism Removal (CPR): 0.291ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O + net (fo=1, routed) 2.076 3.567 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.705 5.374 RAMCTRL/SNAKE_RAM/H125MHz + RAMB36_X2Y4 RAMB36E1 r RAMCTRL/SNAKE_RAM/mem_reg_7_0/CLKBWRCLK + ------------------------------------------------------------------- ------------------- + RAMB36_X2Y4 RAMB36E1 (Prop_ramb36e1_CLKBWRCLK_DOBDO[8]) + 2.454 7.828 f RAMCTRL/SNAKE_RAM/mem_reg_7_0/DOBDO[8] + net (fo=17, routed) 1.255 9.083 RAMCTRL/SNAKE_RAM/output_reg[6][2] + SLICE_X31Y24 LUT3 (Prop_lut3_I1_O) 0.124 9.207 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_630/O + net (fo=4, routed) 1.037 10.243 RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_630_n_0 + SLICE_X25Y25 LUT5 (Prop_lut5_I3_O) 0.124 10.367 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_626/O + net (fo=1, routed) 0.000 10.367 RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_626_n_0 + SLICE_X25Y25 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.401 10.768 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_330/CO[3] + net (fo=1, routed) 0.000 10.768 RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_330_n_0 + SLICE_X25Y26 CARRY4 (Prop_carry4_CI_CO[0]) + 0.271 11.039 f RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_114/CO[0] + net (fo=1, routed) 0.820 11.859 RAMCTRL/SNAKE_RAM/SNAKE/snakeHere36_in + SLICE_X25Y27 LUT5 (Prop_lut5_I2_O) 0.373 12.232 f RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_35/O + net (fo=13, routed) 0.982 13.214 RAMCTRL/SNAKE_RAM/mem_reg_7_0_4 + SLICE_X25Y27 LUT6 (Prop_lut6_I5_O) 0.124 13.338 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_10/O + net (fo=10, routed) 0.705 14.043 RAMCTRL/SNAKE_RAM/mem_reg_8_0_4 + SLICE_X25Y30 LUT6 (Prop_lut6_I2_O) 0.124 14.167 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_72/O + net (fo=1, routed) 0.593 14.760 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_72_n_0 + SLICE_X24Y29 LUT6 (Prop_lut6_I4_O) 0.124 14.884 f RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_27/O + net (fo=2, routed) 0.761 15.645 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_27_n_0 + SLICE_X19Y27 LUT6 (Prop_lut6_I3_O) 0.124 15.769 f RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_10/O + net (fo=1, routed) 0.714 16.483 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_10_n_0 + SLICE_X19Y28 LUT6 (Prop_lut6_I0_O) 0.124 16.607 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_2/O + net (fo=1, routed) 0.871 17.479 RAMCTRL/SNAKE_RAM/SNAKE/p_11_out[3] + SLICE_X20Y28 CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.396 17.875 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 17.875 RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_1_n_0 + SLICE_X20Y29 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 18.114 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_1/O[2] + net (fo=1, routed) 0.000 18.114 SNAKE/D[6] + SLICE_X20Y29 FDRE r SNAKE/ROMAddress_reg[6]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 8.000 8.000 r + L16 0.000 8.000 r H125MHz (IN) + net (fo=0) 0.000 8.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O + net (fo=1, routed) 1.880 11.301 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.491 12.883 SNAKE/H125MHz + SLICE_X20Y29 FDRE r SNAKE/ROMAddress_reg[6]/C + clock pessimism 0.291 13.174 + clock uncertainty -0.035 13.138 + SLICE_X20Y29 FDRE (Setup_fdre_C_D) 0.109 13.247 SNAKE/ROMAddress_reg[6] + ------------------------------------------------------------------- + required time 13.247 + arrival time -18.114 + ------------------------------------------------------------------- + slack -4.866 + +Slack (VIOLATED) : -4.846ns (required time - arrival time) + Source: RAMCTRL/SNAKE_RAM/mem_reg_7_0/CLKBWRCLK + (rising edge-triggered cell RAMB36E1 clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: SNAKE/ROMAddress_reg[4]/D + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: sys_clk_pin + Path Type: Setup (Max at Slow Process Corner) + Requirement: 8.000ns (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 12.720ns (logic 4.982ns (39.167%) route 7.738ns (60.833%)) + Logic Levels: 12 (CARRY4=4 LUT3=1 LUT5=2 LUT6=5) + Clock Path Skew: -0.200ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 4.883ns = ( 12.883 - 8.000 ) + Source Clock Delay (SCD): 5.374ns + Clock Pessimism Removal (CPR): 0.291ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O + net (fo=1, routed) 2.076 3.567 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.705 5.374 RAMCTRL/SNAKE_RAM/H125MHz + RAMB36_X2Y4 RAMB36E1 r RAMCTRL/SNAKE_RAM/mem_reg_7_0/CLKBWRCLK + ------------------------------------------------------------------- ------------------- + RAMB36_X2Y4 RAMB36E1 (Prop_ramb36e1_CLKBWRCLK_DOBDO[8]) + 2.454 7.828 f RAMCTRL/SNAKE_RAM/mem_reg_7_0/DOBDO[8] + net (fo=17, routed) 1.255 9.083 RAMCTRL/SNAKE_RAM/output_reg[6][2] + SLICE_X31Y24 LUT3 (Prop_lut3_I1_O) 0.124 9.207 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_630/O + net (fo=4, routed) 1.037 10.243 RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_630_n_0 + SLICE_X25Y25 LUT5 (Prop_lut5_I3_O) 0.124 10.367 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_626/O + net (fo=1, routed) 0.000 10.367 RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_626_n_0 + SLICE_X25Y25 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.401 10.768 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_330/CO[3] + net (fo=1, routed) 0.000 10.768 RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_330_n_0 + SLICE_X25Y26 CARRY4 (Prop_carry4_CI_CO[0]) + 0.271 11.039 f RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_114/CO[0] + net (fo=1, routed) 0.820 11.859 RAMCTRL/SNAKE_RAM/SNAKE/snakeHere36_in + SLICE_X25Y27 LUT5 (Prop_lut5_I2_O) 0.373 12.232 f RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_35/O + net (fo=13, routed) 0.982 13.214 RAMCTRL/SNAKE_RAM/mem_reg_7_0_4 + SLICE_X25Y27 LUT6 (Prop_lut6_I5_O) 0.124 13.338 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_10/O + net (fo=10, routed) 0.705 14.043 RAMCTRL/SNAKE_RAM/mem_reg_8_0_4 + SLICE_X25Y30 LUT6 (Prop_lut6_I2_O) 0.124 14.167 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_72/O + net (fo=1, routed) 0.593 14.760 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_72_n_0 + SLICE_X24Y29 LUT6 (Prop_lut6_I4_O) 0.124 14.884 f RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_27/O + net (fo=2, routed) 0.761 15.645 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_27_n_0 + SLICE_X19Y27 LUT6 (Prop_lut6_I3_O) 0.124 15.769 f RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_10/O + net (fo=1, routed) 0.714 16.483 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_10_n_0 + SLICE_X19Y28 LUT6 (Prop_lut6_I0_O) 0.124 16.607 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_2/O + net (fo=1, routed) 0.871 17.479 RAMCTRL/SNAKE_RAM/SNAKE/p_11_out[3] + SLICE_X20Y28 CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.396 17.875 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 17.875 RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_1_n_0 + SLICE_X20Y29 CARRY4 (Prop_carry4_CI_O[0]) + 0.219 18.094 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_1/O[0] + net (fo=1, routed) 0.000 18.094 SNAKE/D[4] + SLICE_X20Y29 FDRE r SNAKE/ROMAddress_reg[4]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 8.000 8.000 r + L16 0.000 8.000 r H125MHz (IN) + net (fo=0) 0.000 8.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O + net (fo=1, routed) 1.880 11.301 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.491 12.883 SNAKE/H125MHz + SLICE_X20Y29 FDRE r SNAKE/ROMAddress_reg[4]/C + clock pessimism 0.291 13.174 + clock uncertainty -0.035 13.138 + SLICE_X20Y29 FDRE (Setup_fdre_C_D) 0.109 13.247 SNAKE/ROMAddress_reg[4] + ------------------------------------------------------------------- + required time 13.247 + arrival time -18.094 + ------------------------------------------------------------------- + slack -4.846 + +Slack (VIOLATED) : -4.073ns (required time - arrival time) + Source: RAMCTRL/SNAKE_RAM/mem_reg_7_0/CLKBWRCLK + (rising edge-triggered cell RAMB36E1 clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: SNAKE/ROMAddress_reg[3]/D + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: sys_clk_pin + Path Type: Setup (Max at Slow Process Corner) + Requirement: 8.000ns (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 11.945ns (logic 5.010ns (41.941%) route 6.935ns (58.059%)) + Logic Levels: 11 (CARRY4=3 LUT3=1 LUT5=2 LUT6=5) + Clock Path Skew: -0.201ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 4.882ns = ( 12.882 - 8.000 ) + Source Clock Delay (SCD): 5.374ns + Clock Pessimism Removal (CPR): 0.291ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O + net (fo=1, routed) 2.076 3.567 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.705 5.374 RAMCTRL/SNAKE_RAM/H125MHz + RAMB36_X2Y4 RAMB36E1 r RAMCTRL/SNAKE_RAM/mem_reg_7_0/CLKBWRCLK + ------------------------------------------------------------------- ------------------- + RAMB36_X2Y4 RAMB36E1 (Prop_ramb36e1_CLKBWRCLK_DOBDO[8]) + 2.454 7.828 f RAMCTRL/SNAKE_RAM/mem_reg_7_0/DOBDO[8] + net (fo=17, routed) 1.255 9.083 RAMCTRL/SNAKE_RAM/output_reg[6][2] + SLICE_X31Y24 LUT3 (Prop_lut3_I1_O) 0.124 9.207 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_630/O + net (fo=4, routed) 1.037 10.243 RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_630_n_0 + SLICE_X25Y25 LUT5 (Prop_lut5_I3_O) 0.124 10.367 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_626/O + net (fo=1, routed) 0.000 10.367 RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_626_n_0 + SLICE_X25Y25 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.401 10.768 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_330/CO[3] + net (fo=1, routed) 0.000 10.768 RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_330_n_0 + SLICE_X25Y26 CARRY4 (Prop_carry4_CI_CO[0]) + 0.271 11.039 f RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_114/CO[0] + net (fo=1, routed) 0.820 11.859 RAMCTRL/SNAKE_RAM/SNAKE/snakeHere36_in + SLICE_X25Y27 LUT5 (Prop_lut5_I2_O) 0.373 12.232 f RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_35/O + net (fo=13, routed) 0.982 13.214 RAMCTRL/SNAKE_RAM/mem_reg_7_0_4 + SLICE_X25Y27 LUT6 (Prop_lut6_I5_O) 0.124 13.338 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_10/O + net (fo=10, routed) 0.533 13.871 RAMCTRL/SNAKE_RAM/mem_reg_8_0_4 + SLICE_X18Y27 LUT6 (Prop_lut6_I5_O) 0.124 13.995 f RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_63/O + net (fo=1, routed) 0.708 14.703 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_63_n_0 + SLICE_X18Y27 LUT6 (Prop_lut6_I3_O) 0.124 14.827 f RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_19/O + net (fo=1, routed) 0.736 15.564 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_19_n_0 + SLICE_X20Y27 LUT6 (Prop_lut6_I0_O) 0.124 15.688 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_4/O + net (fo=2, routed) 0.865 16.552 RAMCTRL/SNAKE_RAM/SNAKE/p_11_out[1] + SLICE_X20Y28 LUT6 (Prop_lut6_I0_O) 0.124 16.676 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_8/O + net (fo=1, routed) 0.000 16.676 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_8_n_0 + SLICE_X20Y28 CARRY4 (Prop_carry4_S[1]_O[3]) + 0.643 17.319 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_1/O[3] + net (fo=1, routed) 0.000 17.319 SNAKE/D[3] + SLICE_X20Y28 FDRE r SNAKE/ROMAddress_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 8.000 8.000 r + L16 0.000 8.000 r H125MHz (IN) + net (fo=0) 0.000 8.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O + net (fo=1, routed) 1.880 11.301 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.490 12.882 SNAKE/H125MHz + SLICE_X20Y28 FDRE r SNAKE/ROMAddress_reg[3]/C + clock pessimism 0.291 13.173 + clock uncertainty -0.035 13.137 + SLICE_X20Y28 FDRE (Setup_fdre_C_D) 0.109 13.246 SNAKE/ROMAddress_reg[3] + ------------------------------------------------------------------- + required time 13.246 + arrival time -17.319 + ------------------------------------------------------------------- + slack -4.073 + +Slack (VIOLATED) : -4.008ns (required time - arrival time) + Source: RAMCTRL/SNAKE_RAM/mem_reg_7_0/CLKBWRCLK + (rising edge-triggered cell RAMB36E1 clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: SNAKE/ROMAddress_reg[2]/D + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: sys_clk_pin + Path Type: Setup (Max at Slow Process Corner) + Requirement: 8.000ns (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 11.880ns (logic 4.945ns (41.623%) route 6.935ns (58.377%)) + Logic Levels: 11 (CARRY4=3 LUT3=1 LUT5=2 LUT6=5) + Clock Path Skew: -0.201ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 4.882ns = ( 12.882 - 8.000 ) + Source Clock Delay (SCD): 5.374ns + Clock Pessimism Removal (CPR): 0.291ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O + net (fo=1, routed) 2.076 3.567 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.705 5.374 RAMCTRL/SNAKE_RAM/H125MHz + RAMB36_X2Y4 RAMB36E1 r RAMCTRL/SNAKE_RAM/mem_reg_7_0/CLKBWRCLK + ------------------------------------------------------------------- ------------------- + RAMB36_X2Y4 RAMB36E1 (Prop_ramb36e1_CLKBWRCLK_DOBDO[8]) + 2.454 7.828 f RAMCTRL/SNAKE_RAM/mem_reg_7_0/DOBDO[8] + net (fo=17, routed) 1.255 9.083 RAMCTRL/SNAKE_RAM/output_reg[6][2] + SLICE_X31Y24 LUT3 (Prop_lut3_I1_O) 0.124 9.207 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_630/O + net (fo=4, routed) 1.037 10.243 RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_630_n_0 + SLICE_X25Y25 LUT5 (Prop_lut5_I3_O) 0.124 10.367 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_626/O + net (fo=1, routed) 0.000 10.367 RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_626_n_0 + SLICE_X25Y25 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.401 10.768 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_330/CO[3] + net (fo=1, routed) 0.000 10.768 RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_330_n_0 + SLICE_X25Y26 CARRY4 (Prop_carry4_CI_CO[0]) + 0.271 11.039 f RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_114/CO[0] + net (fo=1, routed) 0.820 11.859 RAMCTRL/SNAKE_RAM/SNAKE/snakeHere36_in + SLICE_X25Y27 LUT5 (Prop_lut5_I2_O) 0.373 12.232 f RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_35/O + net (fo=13, routed) 0.982 13.214 RAMCTRL/SNAKE_RAM/mem_reg_7_0_4 + SLICE_X25Y27 LUT6 (Prop_lut6_I5_O) 0.124 13.338 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_10/O + net (fo=10, routed) 0.533 13.871 RAMCTRL/SNAKE_RAM/mem_reg_8_0_4 + SLICE_X18Y27 LUT6 (Prop_lut6_I5_O) 0.124 13.995 f RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_63/O + net (fo=1, routed) 0.708 14.703 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_63_n_0 + SLICE_X18Y27 LUT6 (Prop_lut6_I3_O) 0.124 14.827 f RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_19/O + net (fo=1, routed) 0.736 15.564 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_19_n_0 + SLICE_X20Y27 LUT6 (Prop_lut6_I0_O) 0.124 15.688 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_4/O + net (fo=2, routed) 0.865 16.552 RAMCTRL/SNAKE_RAM/SNAKE/p_11_out[1] + SLICE_X20Y28 LUT6 (Prop_lut6_I0_O) 0.124 16.676 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_8/O + net (fo=1, routed) 0.000 16.676 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_8_n_0 + SLICE_X20Y28 CARRY4 (Prop_carry4_S[1]_O[2]) + 0.578 17.254 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_1/O[2] + net (fo=1, routed) 0.000 17.254 SNAKE/D[2] + SLICE_X20Y28 FDRE r SNAKE/ROMAddress_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 8.000 8.000 r + L16 0.000 8.000 r H125MHz (IN) + net (fo=0) 0.000 8.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O + net (fo=1, routed) 1.880 11.301 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.490 12.882 SNAKE/H125MHz + SLICE_X20Y28 FDRE r SNAKE/ROMAddress_reg[2]/C + clock pessimism 0.291 13.173 + clock uncertainty -0.035 13.137 + SLICE_X20Y28 FDRE (Setup_fdre_C_D) 0.109 13.246 SNAKE/ROMAddress_reg[2] + ------------------------------------------------------------------- + required time 13.246 + arrival time -17.254 + ------------------------------------------------------------------- + slack -4.008 + +Slack (VIOLATED) : -3.881ns (required time - arrival time) + Source: RAMCTRL/SNAKE_RAM/mem_reg_4_1/CLKBWRCLK + (rising edge-triggered cell RAMB18E1 clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: SNAKE/ROMAddress_reg[4]/CE + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: sys_clk_pin + Path Type: Setup (Max at Slow Process Corner) + Requirement: 8.000ns (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 11.467ns (logic 4.091ns (35.675%) route 7.376ns (64.325%)) + Logic Levels: 8 (CARRY4=2 LUT3=2 LUT4=1 LUT5=3) + Clock Path Skew: -0.209ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 4.883ns = ( 12.883 - 8.000 ) + Source Clock Delay (SCD): 5.383ns + Clock Pessimism Removal (CPR): 0.291ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O + net (fo=1, routed) 2.076 3.567 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.714 5.383 RAMCTRL/SNAKE_RAM/H125MHz + RAMB18_X2Y14 RAMB18E1 r RAMCTRL/SNAKE_RAM/mem_reg_4_1/CLKBWRCLK + ------------------------------------------------------------------- ------------------- + RAMB18_X2Y14 RAMB18E1 (Prop_ramb18e1_CLKBWRCLK_DOBDO[0]) + 2.454 7.837 f RAMCTRL/SNAKE_RAM/mem_reg_4_1/DOBDO[0] + net (fo=12, routed) 0.816 8.653 RAMCTRL/SNAKE_RAM/output_reg[3][6] + SLICE_X35Y35 LUT3 (Prop_lut3_I0_O) 0.124 8.777 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_363/O + net (fo=1, routed) 0.782 9.560 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_363_n_0 + SLICE_X35Y32 LUT5 (Prop_lut5_I1_O) 0.124 9.684 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_250/O + net (fo=1, routed) 0.629 10.312 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_250_n_0 + SLICE_X30Y32 CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.396 10.708 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_114/CO[3] + net (fo=1, routed) 0.000 10.708 RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_114_n_0 + SLICE_X30Y33 CARRY4 (Prop_carry4_CI_CO[0]) + 0.254 10.962 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_45/CO[0] + net (fo=3, routed) 1.015 11.977 RAMCTRL/SNAKE_RAM/SNAKE/snakeHere534_in + SLICE_X23Y32 LUT5 (Prop_lut5_I2_O) 0.367 12.344 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_21/O + net (fo=19, routed) 1.243 13.587 RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_21_n_0 + SLICE_X15Y32 LUT4 (Prop_lut4_I0_O) 0.124 13.711 f RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_7/O + net (fo=10, routed) 0.963 14.674 RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_7_n_0 + SLICE_X18Y34 LUT5 (Prop_lut5_I0_O) 0.124 14.798 f RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_3/O + net (fo=2, routed) 0.898 15.696 RAMCTRL/SNAKE_RAM/mem_reg_9_0_4 + SLICE_X18Y34 LUT3 (Prop_lut3_I2_O) 0.124 15.820 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_1/O + net (fo=10, routed) 1.030 16.850 SNAKE/E[0] + SLICE_X20Y29 FDRE r SNAKE/ROMAddress_reg[4]/CE + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 8.000 8.000 r + L16 0.000 8.000 r H125MHz (IN) + net (fo=0) 0.000 8.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O + net (fo=1, routed) 1.880 11.301 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.491 12.883 SNAKE/H125MHz + SLICE_X20Y29 FDRE r SNAKE/ROMAddress_reg[4]/C + clock pessimism 0.291 13.174 + clock uncertainty -0.035 13.138 + SLICE_X20Y29 FDRE (Setup_fdre_C_CE) -0.169 12.969 SNAKE/ROMAddress_reg[4] + ------------------------------------------------------------------- + required time 12.969 + arrival time -16.850 + ------------------------------------------------------------------- + slack -3.881 + +Slack (VIOLATED) : -3.881ns (required time - arrival time) + Source: RAMCTRL/SNAKE_RAM/mem_reg_4_1/CLKBWRCLK + (rising edge-triggered cell RAMB18E1 clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: SNAKE/ROMAddress_reg[5]/CE + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: sys_clk_pin + Path Type: Setup (Max at Slow Process Corner) + Requirement: 8.000ns (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 11.467ns (logic 4.091ns (35.675%) route 7.376ns (64.325%)) + Logic Levels: 8 (CARRY4=2 LUT3=2 LUT4=1 LUT5=3) + Clock Path Skew: -0.209ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 4.883ns = ( 12.883 - 8.000 ) + Source Clock Delay (SCD): 5.383ns + Clock Pessimism Removal (CPR): 0.291ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O + net (fo=1, routed) 2.076 3.567 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.714 5.383 RAMCTRL/SNAKE_RAM/H125MHz + RAMB18_X2Y14 RAMB18E1 r RAMCTRL/SNAKE_RAM/mem_reg_4_1/CLKBWRCLK + ------------------------------------------------------------------- ------------------- + RAMB18_X2Y14 RAMB18E1 (Prop_ramb18e1_CLKBWRCLK_DOBDO[0]) + 2.454 7.837 f RAMCTRL/SNAKE_RAM/mem_reg_4_1/DOBDO[0] + net (fo=12, routed) 0.816 8.653 RAMCTRL/SNAKE_RAM/output_reg[3][6] + SLICE_X35Y35 LUT3 (Prop_lut3_I0_O) 0.124 8.777 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_363/O + net (fo=1, routed) 0.782 9.560 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_363_n_0 + SLICE_X35Y32 LUT5 (Prop_lut5_I1_O) 0.124 9.684 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_250/O + net (fo=1, routed) 0.629 10.312 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_250_n_0 + SLICE_X30Y32 CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.396 10.708 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_114/CO[3] + net (fo=1, routed) 0.000 10.708 RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_114_n_0 + SLICE_X30Y33 CARRY4 (Prop_carry4_CI_CO[0]) + 0.254 10.962 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_45/CO[0] + net (fo=3, routed) 1.015 11.977 RAMCTRL/SNAKE_RAM/SNAKE/snakeHere534_in + SLICE_X23Y32 LUT5 (Prop_lut5_I2_O) 0.367 12.344 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_21/O + net (fo=19, routed) 1.243 13.587 RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_21_n_0 + SLICE_X15Y32 LUT4 (Prop_lut4_I0_O) 0.124 13.711 f RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_7/O + net (fo=10, routed) 0.963 14.674 RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_7_n_0 + SLICE_X18Y34 LUT5 (Prop_lut5_I0_O) 0.124 14.798 f RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_3/O + net (fo=2, routed) 0.898 15.696 RAMCTRL/SNAKE_RAM/mem_reg_9_0_4 + SLICE_X18Y34 LUT3 (Prop_lut3_I2_O) 0.124 15.820 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_1/O + net (fo=10, routed) 1.030 16.850 SNAKE/E[0] + SLICE_X20Y29 FDRE r SNAKE/ROMAddress_reg[5]/CE + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 8.000 8.000 r + L16 0.000 8.000 r H125MHz (IN) + net (fo=0) 0.000 8.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O + net (fo=1, routed) 1.880 11.301 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.491 12.883 SNAKE/H125MHz + SLICE_X20Y29 FDRE r SNAKE/ROMAddress_reg[5]/C + clock pessimism 0.291 13.174 + clock uncertainty -0.035 13.138 + SLICE_X20Y29 FDRE (Setup_fdre_C_CE) -0.169 12.969 SNAKE/ROMAddress_reg[5] + ------------------------------------------------------------------- + required time 12.969 + arrival time -16.850 + ------------------------------------------------------------------- + slack -3.881 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.078ns (arrival time - required time) + Source: UPD/dataOut_reg[13]/C + (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: RAMCTRL/SNAKE_RAM/mem_reg_6_0/DIADI[13] + (rising edge-triggered cell RAMB36E1 clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: sys_clk_pin + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 0.429ns (logic 0.141ns (32.829%) route 0.288ns (67.171%)) + Logic Levels: 0 + Clock Path Skew: 0.055ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 2.032ns + Source Clock Delay (SCD): 1.478ns + Clock Pessimism Removal (CPR): 0.499ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O + net (fo=1, routed) 0.627 0.886 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.566 1.478 UPD/H125MHz + SLICE_X26Y47 FDCE r UPD/dataOut_reg[13]/C + ------------------------------------------------------------------- ------------------- + SLICE_X26Y47 FDCE (Prop_fdce_C_Q) 0.141 1.619 r UPD/dataOut_reg[13]/Q + net (fo=9, routed) 0.288 1.907 RAMCTRL/SNAKE_RAM/updateRAMDataOut[13] + RAMB36_X1Y7 RAMB36E1 r RAMCTRL/SNAKE_RAM/mem_reg_6_0/DIADI[13] + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r H125MHz_IBUF_inst/O + net (fo=1, routed) 0.683 1.130 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.159 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.873 2.032 RAMCTRL/SNAKE_RAM/H125MHz + RAMB36_X1Y7 RAMB36E1 r RAMCTRL/SNAKE_RAM/mem_reg_6_0/CLKARDCLK + clock pessimism -0.499 1.533 + RAMB36_X1Y7 RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[13]) + 0.296 1.829 RAMCTRL/SNAKE_RAM/mem_reg_6_0 + ------------------------------------------------------------------- + required time -1.829 + arrival time 1.907 + ------------------------------------------------------------------- + slack 0.078 + +Slack (MET) : 0.088ns (arrival time - required time) + Source: UPD/dataOut_reg[1]_P/C + (rising edge-triggered cell FDPE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: RAMCTRL/SNAKE_RAM/mem_reg_2_0/DIADI[1] + (rising edge-triggered cell RAMB36E1 clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: sys_clk_pin + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 0.443ns (logic 0.186ns (41.977%) route 0.257ns (58.023%)) + Logic Levels: 1 (LUT3=1) + Clock Path Skew: 0.059ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 2.025ns + Source Clock Delay (SCD): 1.467ns + Clock Pessimism Removal (CPR): 0.499ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O + net (fo=1, routed) 0.627 0.886 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.555 1.467 UPD/H125MHz + SLICE_X7Y25 FDPE r UPD/dataOut_reg[1]_P/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y25 FDPE (Prop_fdpe_C_Q) 0.141 1.608 r UPD/dataOut_reg[1]_P/Q + net (fo=1, routed) 0.087 1.695 UPD/dataOut_reg[1]_P_n_0 + SLICE_X6Y25 LUT3 (Prop_lut3_I0_O) 0.045 1.740 r UPD/mem_reg_1_0_i_3/O + net (fo=9, routed) 0.170 1.910 RAMCTRL/SNAKE_RAM/updateRAMDataOut[1] + RAMB36_X0Y5 RAMB36E1 r RAMCTRL/SNAKE_RAM/mem_reg_2_0/DIADI[1] + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r H125MHz_IBUF_inst/O + net (fo=1, routed) 0.683 1.130 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.159 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.866 2.025 RAMCTRL/SNAKE_RAM/H125MHz + RAMB36_X0Y5 RAMB36E1 r RAMCTRL/SNAKE_RAM/mem_reg_2_0/CLKARDCLK + clock pessimism -0.499 1.526 + RAMB36_X0Y5 RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[1]) + 0.296 1.822 RAMCTRL/SNAKE_RAM/mem_reg_2_0 + ------------------------------------------------------------------- + required time -1.822 + arrival time 1.910 + ------------------------------------------------------------------- + slack 0.088 + +Slack (MET) : 0.095ns (arrival time - required time) + Source: RAMCTRL/clkCount_reg[22]/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: RAMCTRL/clkCount_reg[24]/D + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: sys_clk_pin + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 0.488ns (logic 0.373ns (76.423%) route 0.115ns (23.577%)) + Logic Levels: 2 (CARRY4=2) + Clock Path Skew: 0.263ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.985ns + Source Clock Delay (SCD): 1.475ns + Clock Pessimism Removal (CPR): 0.247ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O + net (fo=1, routed) 0.627 0.886 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.563 1.475 RAMCTRL/H125MHz + SLICE_X24Y49 FDRE r RAMCTRL/clkCount_reg[22]/C + ------------------------------------------------------------------- ------------------- + SLICE_X24Y49 FDRE (Prop_fdre_C_Q) 0.164 1.639 r RAMCTRL/clkCount_reg[22]/Q + net (fo=1, routed) 0.114 1.753 RAMCTRL/clkCount_reg_n_0_[22] + SLICE_X24Y49 CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.156 1.909 r RAMCTRL/clkCount_reg[23]_i_1/CO[3] + net (fo=1, routed) 0.001 1.910 RAMCTRL/clkCount_reg[23]_i_1_n_0 + SLICE_X24Y50 CARRY4 (Prop_carry4_CI_O[0]) + 0.053 1.963 r RAMCTRL/clkCount_reg[27]_i_1/O[0] + net (fo=2, routed) 0.000 1.963 RAMCTRL/sel0[24] + SLICE_X24Y50 FDRE r RAMCTRL/clkCount_reg[24]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r H125MHz_IBUF_inst/O + net (fo=1, routed) 0.683 1.130 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.159 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.826 1.985 RAMCTRL/H125MHz + SLICE_X24Y50 FDRE r RAMCTRL/clkCount_reg[24]/C + clock pessimism -0.247 1.738 + SLICE_X24Y50 FDRE (Hold_fdre_C_D) 0.130 1.868 RAMCTRL/clkCount_reg[24] + ------------------------------------------------------------------- + required time -1.868 + arrival time 1.963 + ------------------------------------------------------------------- + slack 0.095 + +Slack (MET) : 0.108ns (arrival time - required time) + Source: RAMCTRL/clkCount_reg[22]/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: RAMCTRL/clkCount_reg[26]/D + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: sys_clk_pin + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 0.501ns (logic 0.386ns (77.035%) route 0.115ns (22.965%)) + Logic Levels: 2 (CARRY4=2) + Clock Path Skew: 0.263ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.985ns + Source Clock Delay (SCD): 1.475ns + Clock Pessimism Removal (CPR): 0.247ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O + net (fo=1, routed) 0.627 0.886 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.563 1.475 RAMCTRL/H125MHz + SLICE_X24Y49 FDRE r RAMCTRL/clkCount_reg[22]/C + ------------------------------------------------------------------- ------------------- + SLICE_X24Y49 FDRE (Prop_fdre_C_Q) 0.164 1.639 r RAMCTRL/clkCount_reg[22]/Q + net (fo=1, routed) 0.114 1.753 RAMCTRL/clkCount_reg_n_0_[22] + SLICE_X24Y49 CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.156 1.909 r RAMCTRL/clkCount_reg[23]_i_1/CO[3] + net (fo=1, routed) 0.001 1.910 RAMCTRL/clkCount_reg[23]_i_1_n_0 + SLICE_X24Y50 CARRY4 (Prop_carry4_CI_O[2]) + 0.066 1.976 r RAMCTRL/clkCount_reg[27]_i_1/O[2] + net (fo=2, routed) 0.000 1.976 RAMCTRL/sel0[26] + SLICE_X24Y50 FDRE r RAMCTRL/clkCount_reg[26]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r H125MHz_IBUF_inst/O + net (fo=1, routed) 0.683 1.130 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.159 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.826 1.985 RAMCTRL/H125MHz + SLICE_X24Y50 FDRE r RAMCTRL/clkCount_reg[26]/C + clock pessimism -0.247 1.738 + SLICE_X24Y50 FDRE (Hold_fdre_C_D) 0.130 1.868 RAMCTRL/clkCount_reg[26] + ------------------------------------------------------------------- + required time -1.868 + arrival time 1.976 + ------------------------------------------------------------------- + slack 0.108 + +Slack (MET) : 0.111ns (arrival time - required time) + Source: UPD/dataOut_reg[16]/C + (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: RAMCTRL/SNAKE_RAM/mem_reg_3_0/DIPADIP[0] + (rising edge-triggered cell RAMB36E1 clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: sys_clk_pin + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 0.491ns (logic 0.164ns (33.370%) route 0.327ns (66.630%)) + Logic Levels: 0 + Clock Path Skew: 0.084ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 2.035ns + Source Clock Delay (SCD): 1.471ns + Clock Pessimism Removal (CPR): 0.480ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O + net (fo=1, routed) 0.627 0.886 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.559 1.471 UPD/H125MHz + SLICE_X8Y29 FDCE r UPD/dataOut_reg[16]/C + ------------------------------------------------------------------- ------------------- + SLICE_X8Y29 FDCE (Prop_fdce_C_Q) 0.164 1.635 r UPD/dataOut_reg[16]/Q + net (fo=9, routed) 0.327 1.962 RAMCTRL/SNAKE_RAM/updateRAMDataOut[16] + RAMB36_X0Y7 RAMB36E1 r RAMCTRL/SNAKE_RAM/mem_reg_3_0/DIPADIP[0] + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r H125MHz_IBUF_inst/O + net (fo=1, routed) 0.683 1.130 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.159 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.876 2.035 RAMCTRL/SNAKE_RAM/H125MHz + RAMB36_X0Y7 RAMB36E1 r RAMCTRL/SNAKE_RAM/mem_reg_3_0/CLKARDCLK + clock pessimism -0.480 1.555 + RAMB36_X0Y7 RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIPADIP[0]) + 0.296 1.851 RAMCTRL/SNAKE_RAM/mem_reg_3_0 + ------------------------------------------------------------------- + required time -1.851 + arrival time 1.962 + ------------------------------------------------------------------- + slack 0.111 + +Slack (MET) : 0.116ns (arrival time - required time) + Source: UPD/dataOut_reg[19]_P/C + (rising edge-triggered cell FDPE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: RAMCTRL/SNAKE_RAM/mem_reg_2_1/DIADI[1] + (rising edge-triggered cell RAMB18E1 clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: sys_clk_pin + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 0.470ns (logic 0.186ns (39.584%) route 0.284ns (60.416%)) + Logic Levels: 1 (LUT3=1) + Clock Path Skew: 0.057ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 2.030ns + Source Clock Delay (SCD): 1.474ns + Clock Pessimism Removal (CPR): 0.499ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O + net (fo=1, routed) 0.627 0.886 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.562 1.474 UPD/H125MHz + SLICE_X7Y32 FDPE r UPD/dataOut_reg[19]_P/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y32 FDPE (Prop_fdpe_C_Q) 0.141 1.615 r UPD/dataOut_reg[19]_P/Q + net (fo=1, routed) 0.156 1.771 UPD/dataOut_reg[19]_P_n_0 + SLICE_X7Y32 LUT3 (Prop_lut3_I0_O) 0.045 1.816 r UPD/mem_reg_1_1_i_3/O + net (fo=9, routed) 0.128 1.944 RAMCTRL/SNAKE_RAM/updateRAMDataOut[19] + RAMB18_X0Y13 RAMB18E1 r RAMCTRL/SNAKE_RAM/mem_reg_2_1/DIADI[1] + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r H125MHz_IBUF_inst/O + net (fo=1, routed) 0.683 1.130 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.159 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.871 2.030 RAMCTRL/SNAKE_RAM/H125MHz + RAMB18_X0Y13 RAMB18E1 r RAMCTRL/SNAKE_RAM/mem_reg_2_1/CLKARDCLK + clock pessimism -0.499 1.531 + RAMB18_X0Y13 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_DIADI[1]) + 0.296 1.827 RAMCTRL/SNAKE_RAM/mem_reg_2_1 + ------------------------------------------------------------------- + required time -1.827 + arrival time 1.944 + ------------------------------------------------------------------- + slack 0.116 + +Slack (MET) : 0.127ns (arrival time - required time) + Source: UPD/index_reg[8]/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: RAMCTRL/SNAKE_RAM/mem_reg_1_1/ADDRARDADDR[11] + (rising edge-triggered cell RAMB18E1 clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: sys_clk_pin + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 0.387ns (logic 0.141ns (36.448%) route 0.246ns (63.552%)) + Logic Levels: 0 + Clock Path Skew: 0.076ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 2.030ns + Source Clock Delay (SCD): 1.474ns + Clock Pessimism Removal (CPR): 0.480ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O + net (fo=1, routed) 0.627 0.886 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.562 1.474 UPD/H125MHz + SLICE_X9Y32 FDRE r UPD/index_reg[8]/C + ------------------------------------------------------------------- ------------------- + SLICE_X9Y32 FDRE (Prop_fdre_C_Q) 0.141 1.615 r UPD/index_reg[8]/Q + net (fo=24, routed) 0.246 1.861 RAMCTRL/SNAKE_RAM/Q[8] + RAMB18_X0Y12 RAMB18E1 r RAMCTRL/SNAKE_RAM/mem_reg_1_1/ADDRARDADDR[11] + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r H125MHz_IBUF_inst/O + net (fo=1, routed) 0.683 1.130 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.159 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.871 2.030 RAMCTRL/SNAKE_RAM/H125MHz + RAMB18_X0Y12 RAMB18E1 r RAMCTRL/SNAKE_RAM/mem_reg_1_1/CLKARDCLK + clock pessimism -0.480 1.550 + RAMB18_X0Y12 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[11]) + 0.183 1.733 RAMCTRL/SNAKE_RAM/mem_reg_1_1 + ------------------------------------------------------------------- + required time -1.733 + arrival time 1.861 + ------------------------------------------------------------------- + slack 0.127 + +Slack (MET) : 0.127ns (arrival time - required time) + Source: UPD/index_reg[8]/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: RAMCTRL/SNAKE_RAM/mem_reg_2_1/ADDRARDADDR[11] + (rising edge-triggered cell RAMB18E1 clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: sys_clk_pin + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 0.387ns (logic 0.141ns (36.448%) route 0.246ns (63.552%)) + Logic Levels: 0 + Clock Path Skew: 0.076ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 2.030ns + Source Clock Delay (SCD): 1.474ns + Clock Pessimism Removal (CPR): 0.480ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O + net (fo=1, routed) 0.627 0.886 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.562 1.474 UPD/H125MHz + SLICE_X9Y32 FDRE r UPD/index_reg[8]/C + ------------------------------------------------------------------- ------------------- + SLICE_X9Y32 FDRE (Prop_fdre_C_Q) 0.141 1.615 r UPD/index_reg[8]/Q + net (fo=24, routed) 0.246 1.861 RAMCTRL/SNAKE_RAM/Q[8] + RAMB18_X0Y13 RAMB18E1 r RAMCTRL/SNAKE_RAM/mem_reg_2_1/ADDRARDADDR[11] + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r H125MHz_IBUF_inst/O + net (fo=1, routed) 0.683 1.130 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.159 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.871 2.030 RAMCTRL/SNAKE_RAM/H125MHz + RAMB18_X0Y13 RAMB18E1 r RAMCTRL/SNAKE_RAM/mem_reg_2_1/CLKARDCLK + clock pessimism -0.480 1.550 + RAMB18_X0Y13 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[11]) + 0.183 1.733 RAMCTRL/SNAKE_RAM/mem_reg_2_1 + ------------------------------------------------------------------- + required time -1.733 + arrival time 1.861 + ------------------------------------------------------------------- + slack 0.127 + +Slack (MET) : 0.131ns (arrival time - required time) + Source: RAMCTRL/clkCount_reg[22]/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: RAMCTRL/clkCount_reg[25]/D + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: sys_clk_pin + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 0.524ns (logic 0.409ns (78.043%) route 0.115ns (21.957%)) + Logic Levels: 2 (CARRY4=2) + Clock Path Skew: 0.263ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.985ns + Source Clock Delay (SCD): 1.475ns + Clock Pessimism Removal (CPR): 0.247ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O + net (fo=1, routed) 0.627 0.886 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.563 1.475 RAMCTRL/H125MHz + SLICE_X24Y49 FDRE r RAMCTRL/clkCount_reg[22]/C + ------------------------------------------------------------------- ------------------- + SLICE_X24Y49 FDRE (Prop_fdre_C_Q) 0.164 1.639 r RAMCTRL/clkCount_reg[22]/Q + net (fo=1, routed) 0.114 1.753 RAMCTRL/clkCount_reg_n_0_[22] + SLICE_X24Y49 CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.156 1.909 r RAMCTRL/clkCount_reg[23]_i_1/CO[3] + net (fo=1, routed) 0.001 1.910 RAMCTRL/clkCount_reg[23]_i_1_n_0 + SLICE_X24Y50 CARRY4 (Prop_carry4_CI_O[1]) + 0.089 1.999 r RAMCTRL/clkCount_reg[27]_i_1/O[1] + net (fo=2, routed) 0.000 1.999 RAMCTRL/sel0[25] + SLICE_X24Y50 FDRE r RAMCTRL/clkCount_reg[25]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r H125MHz_IBUF_inst/O + net (fo=1, routed) 0.683 1.130 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.159 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.826 1.985 RAMCTRL/H125MHz + SLICE_X24Y50 FDRE r RAMCTRL/clkCount_reg[25]/C + clock pessimism -0.247 1.738 + SLICE_X24Y50 FDRE (Hold_fdre_C_D) 0.130 1.868 RAMCTRL/clkCount_reg[25] + ------------------------------------------------------------------- + required time -1.868 + arrival time 1.999 + ------------------------------------------------------------------- + slack 0.131 + +Slack (MET) : 0.133ns (arrival time - required time) + Source: RAMCTRL/clkCount_reg[22]/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: RAMCTRL/clkCount_reg[27]/D + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: sys_clk_pin + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 0.526ns (logic 0.411ns (78.126%) route 0.115ns (21.874%)) + Logic Levels: 2 (CARRY4=2) + Clock Path Skew: 0.263ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.985ns + Source Clock Delay (SCD): 1.475ns + Clock Pessimism Removal (CPR): 0.247ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O + net (fo=1, routed) 0.627 0.886 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.563 1.475 RAMCTRL/H125MHz + SLICE_X24Y49 FDRE r RAMCTRL/clkCount_reg[22]/C + ------------------------------------------------------------------- ------------------- + SLICE_X24Y49 FDRE (Prop_fdre_C_Q) 0.164 1.639 r RAMCTRL/clkCount_reg[22]/Q + net (fo=1, routed) 0.114 1.753 RAMCTRL/clkCount_reg_n_0_[22] + SLICE_X24Y49 CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.156 1.909 r RAMCTRL/clkCount_reg[23]_i_1/CO[3] + net (fo=1, routed) 0.001 1.910 RAMCTRL/clkCount_reg[23]_i_1_n_0 + SLICE_X24Y50 CARRY4 (Prop_carry4_CI_O[3]) + 0.091 2.001 r RAMCTRL/clkCount_reg[27]_i_1/O[3] + net (fo=2, routed) 0.000 2.001 RAMCTRL/sel0[27] + SLICE_X24Y50 FDRE r RAMCTRL/clkCount_reg[27]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r H125MHz_IBUF_inst/O + net (fo=1, routed) 0.683 1.130 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.159 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.826 1.985 RAMCTRL/H125MHz + SLICE_X24Y50 FDRE r RAMCTRL/clkCount_reg[27]/C + clock pessimism -0.247 1.738 + SLICE_X24Y50 FDRE (Hold_fdre_C_D) 0.130 1.868 RAMCTRL/clkCount_reg[27] + ------------------------------------------------------------------- + required time -1.868 + arrival time 2.001 + ------------------------------------------------------------------- + slack 0.133 + + + + + Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: sys_clk_pin @@ -1552,2016 +2840,630 @@ Waveform(ns): { 0.000 4.000 } Period(ns): 8.000 Sources: { H125MHz } -Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin -Min Period n/a MMCME2_ADV/CLKIN1 n/a 1.249 8.000 6.751 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKIN1 -Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 8.000 92.000 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKIN1 -Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 4.000 2.000 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKIN1 -Low Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 2.000 4.000 2.000 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKIN1 -High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 4.000 2.000 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKIN1 -High Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 2.000 4.000 2.000 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKIN1 +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 8.000 5.424 RAMB18_X0Y12 RAMCTRL/SNAKE_RAM/mem_reg_1_1/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 8.000 5.424 RAMB18_X0Y12 RAMCTRL/SNAKE_RAM/mem_reg_1_1/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 8.000 5.424 RAMB18_X1Y16 RAMCTRL/SNAKE_RAM/mem_reg_3_1/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 8.000 5.424 RAMB18_X1Y16 RAMCTRL/SNAKE_RAM/mem_reg_3_1/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 8.000 5.424 RAMB18_X1Y11 RAMCTRL/SNAKE_RAM/mem_reg_5_1/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 8.000 5.424 RAMB18_X1Y11 RAMCTRL/SNAKE_RAM/mem_reg_5_1/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 8.000 5.424 RAMB18_X2Y11 RAMCTRL/SNAKE_RAM/mem_reg_7_1/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 8.000 5.424 RAMB18_X2Y11 RAMCTRL/SNAKE_RAM/mem_reg_7_1/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 8.000 5.424 RAMB18_X2Y10 RAMCTRL/SNAKE_RAM/mem_reg_9_1/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 8.000 5.424 RAMB18_X2Y10 RAMCTRL/SNAKE_RAM/mem_reg_9_1/CLKBWRCLK +Low Pulse Width Slow FDRE/C n/a 0.500 4.000 3.500 SLICE_X25Y44 RAMCTRL/clkCount_reg[0]/C +Low Pulse Width Slow FDRE/C n/a 0.500 4.000 3.500 SLICE_X24Y46 RAMCTRL/clkCount_reg[10]/C +Low Pulse Width Slow FDRE/C n/a 0.500 4.000 3.500 SLICE_X24Y46 RAMCTRL/clkCount_reg[11]/C +Low Pulse Width Slow FDRE/C n/a 0.500 4.000 3.500 SLICE_X24Y47 RAMCTRL/clkCount_reg[12]/C +Low Pulse Width Slow FDRE/C n/a 0.500 4.000 3.500 SLICE_X24Y47 RAMCTRL/clkCount_reg[13]/C +Low Pulse Width Slow FDRE/C n/a 0.500 4.000 3.500 SLICE_X24Y47 RAMCTRL/clkCount_reg[14]/C +Low Pulse Width Slow FDRE/C n/a 0.500 4.000 3.500 SLICE_X24Y47 RAMCTRL/clkCount_reg[15]/C +Low Pulse Width Slow FDRE/C n/a 0.500 4.000 3.500 SLICE_X24Y48 RAMCTRL/clkCount_reg[16]/C +Low Pulse Width Slow FDRE/C n/a 0.500 4.000 3.500 SLICE_X24Y48 RAMCTRL/clkCount_reg[17]/C +Low Pulse Width Slow FDRE/C n/a 0.500 4.000 3.500 SLICE_X24Y48 RAMCTRL/clkCount_reg[18]/C +High Pulse Width Slow FDCE/C n/a 0.500 4.000 3.500 SLICE_X28Y18 RAMCTRL/MAT_RAM/RAMCTRL/MAT_RAM/mem_reg_1_cooolgate_en_gate_1_cooolDelFlop/C +High Pulse Width Fast FDCE/C n/a 0.500 4.000 3.500 SLICE_X28Y18 RAMCTRL/MAT_RAM/RAMCTRL/MAT_RAM/mem_reg_1_cooolgate_en_gate_1_cooolDelFlop/C +High Pulse Width Slow FDCE/C n/a 0.500 4.000 3.500 SLICE_X32Y18 RAMCTRL/MAT_RAM/RAMCTRL/MAT_RAM/mem_reg_1_cooolgate_en_gate_2_cooolDelFlop/C +High Pulse Width Fast FDCE/C n/a 0.500 4.000 3.500 SLICE_X32Y18 RAMCTRL/MAT_RAM/RAMCTRL/MAT_RAM/mem_reg_1_cooolgate_en_gate_2_cooolDelFlop/C +High Pulse Width Fast FDRE/C n/a 0.500 4.000 3.500 SLICE_X36Y36 ROM/data_reg[14]/C +High Pulse Width Slow FDRE/C n/a 0.500 4.000 3.500 SLICE_X39Y38 ROM/data_reg[15]/C +High Pulse Width Slow FDRE/C n/a 0.500 4.000 3.500 SLICE_X35Y38 ROM/data_reg[17]/C +High Pulse Width Slow FDRE/C n/a 0.500 4.000 3.500 SLICE_X38Y38 ROM/data_reg[20]/C +High Pulse Width Fast FDRE/C n/a 0.500 4.000 3.500 SLICE_X38Y36 ROM/data_reg[21]/C +High Pulse Width Fast FDRE/C n/a 0.500 4.000 3.500 SLICE_X39Y36 ROM/data_reg[22]/C --------------------------------------------------------------------------------------------------- -From Clock: clk_out1_clk_wiz_1_1 - To Clock: clk_out1_clk_wiz_1_1 - -Setup : 0 Failing Endpoints, Worst Slack 33.281ns, Total Violation 0.000ns -Hold : 0 Failing Endpoints, Worst Slack 0.261ns, Total Violation 0.000ns -PW : 0 Failing Endpoints, Worst Slack 19.500ns, Total Violation 0.000ns ---------------------------------------------------------------------------------------------------- - - -Max Delay Paths --------------------------------------------------------------------------------------- -Slack (MET) : 33.281ns (required time - arrival time) - Source: U1/comptY_reg[5]/C - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptY_reg[3]/R - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk_out1_clk_wiz_1_1 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) - Data Path Delay: 6.142ns (logic 0.828ns (13.480%) route 5.314ns (86.520%)) - Logic Levels: 3 (LUT4=1 LUT6=2) - Clock Path Skew: 0.000ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.252ns = ( 38.748 - 40.000 ) - Source Clock Delay (SCD): -0.601ns - Clock Pessimism Removal (CPR): 0.651ns - Clock Uncertainty: 0.147ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.286ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.758 -0.601 U1/CLK - SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q - net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5] - SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O - net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0 - SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O - net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0 - SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O - net (fo=10, routed) 1.866 5.542 U1/comptY - SLICE_X40Y49 FDRE r U1/comptY_reg[3]/R - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_clk_wiz_1_1 rise edge) - 40.000 40.000 r - L16 0.000 40.000 r H125MHz (IN) - net (fo=0) 0.000 40.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.580 38.748 U1/CLK - SLICE_X40Y49 FDRE r U1/comptY_reg[3]/C - clock pessimism 0.651 39.399 - clock uncertainty -0.147 39.252 - SLICE_X40Y49 FDRE (Setup_fdre_C_R) -0.429 38.823 U1/comptY_reg[3] - ------------------------------------------------------------------- - required time 38.823 - arrival time -5.542 - ------------------------------------------------------------------- - slack 33.281 - -Slack (MET) : 33.281ns (required time - arrival time) - Source: U1/comptY_reg[5]/C - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptY_reg[5]/R - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk_out1_clk_wiz_1_1 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) - Data Path Delay: 6.142ns (logic 0.828ns (13.480%) route 5.314ns (86.520%)) - Logic Levels: 3 (LUT4=1 LUT6=2) - Clock Path Skew: 0.000ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.252ns = ( 38.748 - 40.000 ) - Source Clock Delay (SCD): -0.601ns - Clock Pessimism Removal (CPR): 0.651ns - Clock Uncertainty: 0.147ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.286ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.758 -0.601 U1/CLK - SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q - net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5] - SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O - net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0 - SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O - net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0 - SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O - net (fo=10, routed) 1.866 5.542 U1/comptY - SLICE_X40Y49 FDRE r U1/comptY_reg[5]/R - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_clk_wiz_1_1 rise edge) - 40.000 40.000 r - L16 0.000 40.000 r H125MHz (IN) - net (fo=0) 0.000 40.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.580 38.748 U1/CLK - SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C - clock pessimism 0.651 39.399 - clock uncertainty -0.147 39.252 - SLICE_X40Y49 FDRE (Setup_fdre_C_R) -0.429 38.823 U1/comptY_reg[5] - ------------------------------------------------------------------- - required time 38.823 - arrival time -5.542 - ------------------------------------------------------------------- - slack 33.281 - -Slack (MET) : 33.427ns (required time - arrival time) - Source: U1/comptY_reg[5]/C - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptY_reg[4]/R - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk_out1_clk_wiz_1_1 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) - Data Path Delay: 5.838ns (logic 0.828ns (14.184%) route 5.010ns (85.816%)) - Logic Levels: 3 (LUT4=1 LUT6=2) - Clock Path Skew: -0.064ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.253ns = ( 38.747 - 40.000 ) - Source Clock Delay (SCD): -0.601ns - Clock Pessimism Removal (CPR): 0.588ns - Clock Uncertainty: 0.147ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.286ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.758 -0.601 U1/CLK - SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q - net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5] - SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O - net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0 - SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O - net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0 - SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O - net (fo=10, routed) 1.561 5.237 U1/comptY - SLICE_X38Y49 FDRE r U1/comptY_reg[4]/R - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_clk_wiz_1_1 rise edge) - 40.000 40.000 r - L16 0.000 40.000 r H125MHz (IN) - net (fo=0) 0.000 40.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.579 38.747 U1/CLK - SLICE_X38Y49 FDRE r U1/comptY_reg[4]/C - clock pessimism 0.588 39.335 - clock uncertainty -0.147 39.188 - SLICE_X38Y49 FDRE (Setup_fdre_C_R) -0.524 38.664 U1/comptY_reg[4] - ------------------------------------------------------------------- - required time 38.664 - arrival time -5.237 - ------------------------------------------------------------------- - slack 33.427 - -Slack (MET) : 33.613ns (required time - arrival time) - Source: U1/comptY_reg[5]/C - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptY_reg[1]/R - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk_out1_clk_wiz_1_1 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) - Data Path Delay: 5.616ns (logic 0.828ns (14.744%) route 4.788ns (85.256%)) - Logic Levels: 3 (LUT4=1 LUT6=2) - Clock Path Skew: -0.195ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.269ns = ( 38.731 - 40.000 ) - Source Clock Delay (SCD): -0.601ns - Clock Pessimism Removal (CPR): 0.473ns - Clock Uncertainty: 0.147ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.286ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.758 -0.601 U1/CLK - SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q - net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5] - SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O - net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0 - SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O - net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0 - SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O - net (fo=10, routed) 1.340 5.015 U1/comptY - SLICE_X36Y51 FDRE r U1/comptY_reg[1]/R - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_clk_wiz_1_1 rise edge) - 40.000 40.000 r - L16 0.000 40.000 r H125MHz (IN) - net (fo=0) 0.000 40.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.563 38.731 U1/CLK - SLICE_X36Y51 FDRE r U1/comptY_reg[1]/C - clock pessimism 0.473 39.204 - clock uncertainty -0.147 39.057 - SLICE_X36Y51 FDRE (Setup_fdre_C_R) -0.429 38.628 U1/comptY_reg[1] - ------------------------------------------------------------------- - required time 38.628 - arrival time -5.015 - ------------------------------------------------------------------- - slack 33.613 - -Slack (MET) : 33.613ns (required time - arrival time) - Source: U1/comptY_reg[5]/C - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptY_reg[2]/R - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk_out1_clk_wiz_1_1 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) - Data Path Delay: 5.616ns (logic 0.828ns (14.744%) route 4.788ns (85.256%)) - Logic Levels: 3 (LUT4=1 LUT6=2) - Clock Path Skew: -0.195ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.269ns = ( 38.731 - 40.000 ) - Source Clock Delay (SCD): -0.601ns - Clock Pessimism Removal (CPR): 0.473ns - Clock Uncertainty: 0.147ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.286ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.758 -0.601 U1/CLK - SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q - net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5] - SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O - net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0 - SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O - net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0 - SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O - net (fo=10, routed) 1.340 5.015 U1/comptY - SLICE_X36Y51 FDRE r U1/comptY_reg[2]/R - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_clk_wiz_1_1 rise edge) - 40.000 40.000 r - L16 0.000 40.000 r H125MHz (IN) - net (fo=0) 0.000 40.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.563 38.731 U1/CLK - SLICE_X36Y51 FDRE r U1/comptY_reg[2]/C - clock pessimism 0.473 39.204 - clock uncertainty -0.147 39.057 - SLICE_X36Y51 FDRE (Setup_fdre_C_R) -0.429 38.628 U1/comptY_reg[2] - ------------------------------------------------------------------- - required time 38.628 - arrival time -5.015 - ------------------------------------------------------------------- - slack 33.613 - -Slack (MET) : 33.613ns (required time - arrival time) - Source: U1/comptY_reg[5]/C - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptY_reg[7]/R - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk_out1_clk_wiz_1_1 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) - Data Path Delay: 5.616ns (logic 0.828ns (14.744%) route 4.788ns (85.256%)) - Logic Levels: 3 (LUT4=1 LUT6=2) - Clock Path Skew: -0.195ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.269ns = ( 38.731 - 40.000 ) - Source Clock Delay (SCD): -0.601ns - Clock Pessimism Removal (CPR): 0.473ns - Clock Uncertainty: 0.147ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.286ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.758 -0.601 U1/CLK - SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q - net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5] - SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O - net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0 - SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O - net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0 - SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O - net (fo=10, routed) 1.340 5.015 U1/comptY - SLICE_X36Y51 FDRE r U1/comptY_reg[7]/R - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_clk_wiz_1_1 rise edge) - 40.000 40.000 r - L16 0.000 40.000 r H125MHz (IN) - net (fo=0) 0.000 40.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.563 38.731 U1/CLK - SLICE_X36Y51 FDRE r U1/comptY_reg[7]/C - clock pessimism 0.473 39.204 - clock uncertainty -0.147 39.057 - SLICE_X36Y51 FDRE (Setup_fdre_C_R) -0.429 38.628 U1/comptY_reg[7] - ------------------------------------------------------------------- - required time 38.628 - arrival time -5.015 - ------------------------------------------------------------------- - slack 33.613 - -Slack (MET) : 33.613ns (required time - arrival time) - Source: U1/comptY_reg[5]/C - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptY_reg[8]/R - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk_out1_clk_wiz_1_1 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) - Data Path Delay: 5.616ns (logic 0.828ns (14.744%) route 4.788ns (85.256%)) - Logic Levels: 3 (LUT4=1 LUT6=2) - Clock Path Skew: -0.195ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.269ns = ( 38.731 - 40.000 ) - Source Clock Delay (SCD): -0.601ns - Clock Pessimism Removal (CPR): 0.473ns - Clock Uncertainty: 0.147ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.286ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.758 -0.601 U1/CLK - SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q - net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5] - SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O - net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0 - SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O - net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0 - SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O - net (fo=10, routed) 1.340 5.015 U1/comptY - SLICE_X36Y51 FDRE r U1/comptY_reg[8]/R - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_clk_wiz_1_1 rise edge) - 40.000 40.000 r - L16 0.000 40.000 r H125MHz (IN) - net (fo=0) 0.000 40.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.563 38.731 U1/CLK - SLICE_X36Y51 FDRE r U1/comptY_reg[8]/C - clock pessimism 0.473 39.204 - clock uncertainty -0.147 39.057 - SLICE_X36Y51 FDRE (Setup_fdre_C_R) -0.429 38.628 U1/comptY_reg[8] - ------------------------------------------------------------------- - required time 38.628 - arrival time -5.015 - ------------------------------------------------------------------- - slack 33.613 - -Slack (MET) : 33.613ns (required time - arrival time) - Source: U1/comptY_reg[5]/C - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptY_reg[9]/R - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk_out1_clk_wiz_1_1 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) - Data Path Delay: 5.616ns (logic 0.828ns (14.744%) route 4.788ns (85.256%)) - Logic Levels: 3 (LUT4=1 LUT6=2) - Clock Path Skew: -0.195ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.269ns = ( 38.731 - 40.000 ) - Source Clock Delay (SCD): -0.601ns - Clock Pessimism Removal (CPR): 0.473ns - Clock Uncertainty: 0.147ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.286ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.758 -0.601 U1/CLK - SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q - net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5] - SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O - net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0 - SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O - net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0 - SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O - net (fo=10, routed) 1.340 5.015 U1/comptY - SLICE_X36Y51 FDRE r U1/comptY_reg[9]/R - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_clk_wiz_1_1 rise edge) - 40.000 40.000 r - L16 0.000 40.000 r H125MHz (IN) - net (fo=0) 0.000 40.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.563 38.731 U1/CLK - SLICE_X36Y51 FDRE r U1/comptY_reg[9]/C - clock pessimism 0.473 39.204 - clock uncertainty -0.147 39.057 - SLICE_X36Y51 FDRE (Setup_fdre_C_R) -0.429 38.628 U1/comptY_reg[9] - ------------------------------------------------------------------- - required time 38.628 - arrival time -5.015 - ------------------------------------------------------------------- - slack 33.613 - -Slack (MET) : 33.756ns (required time - arrival time) - Source: U1/comptY_reg[5]/C - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptY_reg[6]/R - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk_out1_clk_wiz_1_1 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) - Data Path Delay: 5.472ns (logic 0.828ns (15.132%) route 4.644ns (84.868%)) - Logic Levels: 3 (LUT4=1 LUT6=2) - Clock Path Skew: -0.195ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.269ns = ( 38.731 - 40.000 ) - Source Clock Delay (SCD): -0.601ns - Clock Pessimism Removal (CPR): 0.473ns - Clock Uncertainty: 0.147ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.286ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.758 -0.601 U1/CLK - SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q - net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5] - SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O - net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0 - SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O - net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0 - SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O - net (fo=10, routed) 1.196 4.871 U1/comptY - SLICE_X36Y50 FDRE r U1/comptY_reg[6]/R - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_clk_wiz_1_1 rise edge) - 40.000 40.000 r - L16 0.000 40.000 r H125MHz (IN) - net (fo=0) 0.000 40.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.563 38.731 U1/CLK - SLICE_X36Y50 FDRE r U1/comptY_reg[6]/C - clock pessimism 0.473 39.204 - clock uncertainty -0.147 39.057 - SLICE_X36Y50 FDRE (Setup_fdre_C_R) -0.429 38.628 U1/comptY_reg[6] - ------------------------------------------------------------------- - required time 38.628 - arrival time -4.871 - ------------------------------------------------------------------- - slack 33.756 - -Slack (MET) : 33.994ns (required time - arrival time) - Source: U1/comptY_reg[5]/C - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptY_reg[0]/R - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk_out1_clk_wiz_1_1 - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) - Data Path Delay: 5.139ns (logic 0.828ns (16.112%) route 4.311ns (83.888%)) - Logic Levels: 3 (LUT4=1 LUT6=2) - Clock Path Skew: -0.195ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.269ns = ( 38.731 - 40.000 ) - Source Clock Delay (SCD): -0.601ns - Clock Pessimism Removal (CPR): 0.473ns - Clock Uncertainty: 0.147ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.286ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.758 -0.601 U1/CLK - SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q - net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5] - SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O - net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0 - SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O - net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0 - SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O - net (fo=10, routed) 0.863 4.538 U1/comptY - SLICE_X38Y51 FDRE r U1/comptY_reg[0]/R - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_clk_wiz_1_1 rise edge) - 40.000 40.000 r - L16 0.000 40.000 r H125MHz (IN) - net (fo=0) 0.000 40.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.563 38.731 U1/CLK - SLICE_X38Y51 FDRE r U1/comptY_reg[0]/C - clock pessimism 0.473 39.204 - clock uncertainty -0.147 39.057 - SLICE_X38Y51 FDRE (Setup_fdre_C_R) -0.524 38.533 U1/comptY_reg[0] - ------------------------------------------------------------------- - required time 38.533 - arrival time -4.538 - ------------------------------------------------------------------- - slack 33.994 - - - - - -Min Delay Paths --------------------------------------------------------------------------------------- -Slack (MET) : 0.261ns (arrival time - required time) - Source: U1/comptY_reg[1]/C - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptY_reg[2]/D - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk_out1_clk_wiz_1_1 - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) - Data Path Delay: 0.368ns (logic 0.183ns (49.756%) route 0.185ns (50.244%)) - Logic Levels: 1 (LUT3=1) - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.706ns - Source Clock Delay (SCD): -0.474ns - Clock Pessimism Removal (CPR): -0.232ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.587 -0.474 U1/CLK - SLICE_X36Y51 FDRE r U1/comptY_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X36Y51 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptY_reg[1]/Q - net (fo=29, routed) 0.185 -0.148 U1/comptY_reg__0[1] - SLICE_X36Y51 LUT3 (Prop_lut3_I0_O) 0.042 -0.106 r U1/comptY[2]_i_1/O - net (fo=1, routed) 0.000 -0.106 U1/comptY[2]_i_1_n_0 - SLICE_X36Y51 FDRE r U1/comptY_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_clk_wiz_1_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.857 -0.706 U1/CLK - SLICE_X36Y51 FDRE r U1/comptY_reg[2]/C - clock pessimism 0.232 -0.474 - SLICE_X36Y51 FDRE (Hold_fdre_C_D) 0.107 -0.367 U1/comptY_reg[2] - ------------------------------------------------------------------- - required time 0.367 - arrival time -0.106 - ------------------------------------------------------------------- - slack 0.261 - -Slack (MET) : 0.261ns (arrival time - required time) - Source: U1/comptX_reg[5]/C - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptX_reg[5]/D - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk_out1_clk_wiz_1_1 - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) - Data Path Delay: 0.353ns (logic 0.186ns (52.682%) route 0.167ns (47.318%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.705ns - Source Clock Delay (SCD): -0.473ns - Clock Pessimism Removal (CPR): -0.232ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.588 -0.473 U1/CLK - SLICE_X43Y54 FDRE r U1/comptX_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X43Y54 FDRE (Prop_fdre_C_Q) 0.141 -0.332 r U1/comptX_reg[5]/Q - net (fo=25, routed) 0.167 -0.165 U1/comptX_reg__0[5] - SLICE_X43Y54 LUT6 (Prop_lut6_I5_O) 0.045 -0.120 r U1/comptX[5]_i_1/O - net (fo=1, routed) 0.000 -0.120 U1/plusOp[5] - SLICE_X43Y54 FDRE r U1/comptX_reg[5]/D - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_clk_wiz_1_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.858 -0.705 U1/CLK - SLICE_X43Y54 FDRE r U1/comptX_reg[5]/C - clock pessimism 0.232 -0.473 - SLICE_X43Y54 FDRE (Hold_fdre_C_D) 0.092 -0.381 U1/comptX_reg[5] - ------------------------------------------------------------------- - required time 0.381 - arrival time -0.120 - ------------------------------------------------------------------- - slack 0.261 - -Slack (MET) : 0.280ns (arrival time - required time) - Source: U1/comptX_reg[7]/C - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptX_reg[8]/D - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk_out1_clk_wiz_1_1 - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) - Data Path Delay: 0.387ns (logic 0.183ns (47.319%) route 0.204ns (52.681%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.706ns - Source Clock Delay (SCD): -0.474ns - Clock Pessimism Removal (CPR): -0.232ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.587 -0.474 U1/CLK - SLICE_X41Y57 FDRE r U1/comptX_reg[7]/C - ------------------------------------------------------------------- ------------------- - SLICE_X41Y57 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptX_reg[7]/Q - net (fo=20, routed) 0.204 -0.129 U1/comptX_reg__0[7] - SLICE_X41Y57 LUT5 (Prop_lut5_I0_O) 0.042 -0.087 r U1/comptX[8]_i_1/O - net (fo=1, routed) 0.000 -0.087 U1/plusOp[8] - SLICE_X41Y57 FDRE r U1/comptX_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_clk_wiz_1_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.857 -0.706 U1/CLK - SLICE_X41Y57 FDRE r U1/comptX_reg[8]/C - clock pessimism 0.232 -0.474 - SLICE_X41Y57 FDRE (Hold_fdre_C_D) 0.107 -0.367 U1/comptX_reg[8] - ------------------------------------------------------------------- - required time 0.367 - arrival time -0.087 - ------------------------------------------------------------------- - slack 0.280 - -Slack (MET) : 0.280ns (arrival time - required time) - Source: U1/comptY_reg[1]/C - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptY_reg[1]/D - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk_out1_clk_wiz_1_1 - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) - Data Path Delay: 0.371ns (logic 0.186ns (50.162%) route 0.185ns (49.838%)) - Logic Levels: 1 (LUT2=1) - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.706ns - Source Clock Delay (SCD): -0.474ns - Clock Pessimism Removal (CPR): -0.232ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.587 -0.474 U1/CLK - SLICE_X36Y51 FDRE r U1/comptY_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X36Y51 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptY_reg[1]/Q - net (fo=29, routed) 0.185 -0.148 U1/comptY_reg__0[1] - SLICE_X36Y51 LUT2 (Prop_lut2_I1_O) 0.045 -0.103 r U1/comptY[1]_i_1/O - net (fo=1, routed) 0.000 -0.103 U1/comptY[1]_i_1_n_0 - SLICE_X36Y51 FDRE r U1/comptY_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_clk_wiz_1_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.857 -0.706 U1/CLK - SLICE_X36Y51 FDRE r U1/comptY_reg[1]/C - clock pessimism 0.232 -0.474 - SLICE_X36Y51 FDRE (Hold_fdre_C_D) 0.091 -0.383 U1/comptY_reg[1] - ------------------------------------------------------------------- - required time 0.383 - arrival time -0.103 - ------------------------------------------------------------------- - slack 0.280 - -Slack (MET) : 0.288ns (arrival time - required time) - Source: U1/comptX_reg[0]/C - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptX_reg[1]/D - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk_out1_clk_wiz_1_1 - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) - Data Path Delay: 0.419ns (logic 0.207ns (49.431%) route 0.212ns (50.569%)) - Logic Levels: 1 (LUT2=1) - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.705ns - Source Clock Delay (SCD): -0.473ns - Clock Pessimism Removal (CPR): -0.232ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.588 -0.473 U1/CLK - SLICE_X42Y55 FDRE r U1/comptX_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X42Y55 FDRE (Prop_fdre_C_Q) 0.164 -0.309 r U1/comptX_reg[0]/Q - net (fo=25, routed) 0.212 -0.097 U1/comptX_reg__0[0] - SLICE_X42Y55 LUT2 (Prop_lut2_I0_O) 0.043 -0.054 r U1/comptX[1]_i_1/O - net (fo=1, routed) 0.000 -0.054 U1/plusOp[1] - SLICE_X42Y55 FDRE r U1/comptX_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_clk_wiz_1_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.858 -0.705 U1/CLK - SLICE_X42Y55 FDRE r U1/comptX_reg[1]/C - clock pessimism 0.232 -0.473 - SLICE_X42Y55 FDRE (Hold_fdre_C_D) 0.131 -0.342 U1/comptX_reg[1] - ------------------------------------------------------------------- - required time 0.342 - arrival time -0.054 - ------------------------------------------------------------------- - slack 0.288 - -Slack (MET) : 0.289ns (arrival time - required time) - Source: U1/comptX_reg[7]/C - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptX_reg[9]/D - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk_out1_clk_wiz_1_1 - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) - Data Path Delay: 0.398ns (logic 0.186ns (46.766%) route 0.212ns (53.234%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.705ns - Source Clock Delay (SCD): -0.474ns - Clock Pessimism Removal (CPR): -0.248ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.587 -0.474 U1/CLK - SLICE_X41Y57 FDRE r U1/comptX_reg[7]/C - ------------------------------------------------------------------- ------------------- - SLICE_X41Y57 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptX_reg[7]/Q - net (fo=20, routed) 0.212 -0.121 U1/comptX_reg__0[7] - SLICE_X41Y56 LUT6 (Prop_lut6_I3_O) 0.045 -0.076 r U1/comptX[9]_i_1/O - net (fo=1, routed) 0.000 -0.076 U1/plusOp[9] - SLICE_X41Y56 FDRE r U1/comptX_reg[9]/D - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_clk_wiz_1_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.858 -0.705 U1/CLK - SLICE_X41Y56 FDRE r U1/comptX_reg[9]/C - clock pessimism 0.248 -0.457 - SLICE_X41Y56 FDRE (Hold_fdre_C_D) 0.092 -0.365 U1/comptX_reg[9] - ------------------------------------------------------------------- - required time 0.365 - arrival time -0.076 - ------------------------------------------------------------------- - slack 0.289 - -Slack (MET) : 0.297ns (arrival time - required time) - Source: U1/comptY_reg[6]/C - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptY_reg[6]/D - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk_out1_clk_wiz_1_1 - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) - Data Path Delay: 0.402ns (logic 0.183ns (45.514%) route 0.219ns (54.486%)) - Logic Levels: 1 (LUT3=1) - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.706ns - Source Clock Delay (SCD): -0.474ns - Clock Pessimism Removal (CPR): -0.232ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.587 -0.474 U1/CLK - SLICE_X36Y50 FDRE r U1/comptY_reg[6]/C - ------------------------------------------------------------------- ------------------- - SLICE_X36Y50 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptY_reg[6]/Q - net (fo=21, routed) 0.219 -0.114 U1/comptY_reg__0[6] - SLICE_X36Y50 LUT3 (Prop_lut3_I2_O) 0.042 -0.072 r U1/comptY[6]_i_1/O - net (fo=1, routed) 0.000 -0.072 U1/plusOp__0[6] - SLICE_X36Y50 FDRE r U1/comptY_reg[6]/D - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_clk_wiz_1_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.857 -0.706 U1/CLK - SLICE_X36Y50 FDRE r U1/comptY_reg[6]/C - clock pessimism 0.232 -0.474 - SLICE_X36Y50 FDRE (Hold_fdre_C_D) 0.105 -0.369 U1/comptY_reg[6] - ------------------------------------------------------------------- - required time 0.369 - arrival time -0.072 - ------------------------------------------------------------------- - slack 0.297 - -Slack (MET) : 0.299ns (arrival time - required time) - Source: U1/comptX_reg[7]/C - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptX_reg[7]/D - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk_out1_clk_wiz_1_1 - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) - Data Path Delay: 0.390ns (logic 0.186ns (47.724%) route 0.204ns (52.276%)) - Logic Levels: 1 (LUT4=1) - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.706ns - Source Clock Delay (SCD): -0.474ns - Clock Pessimism Removal (CPR): -0.232ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.587 -0.474 U1/CLK - SLICE_X41Y57 FDRE r U1/comptX_reg[7]/C - ------------------------------------------------------------------- ------------------- - SLICE_X41Y57 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptX_reg[7]/Q - net (fo=20, routed) 0.204 -0.129 U1/comptX_reg__0[7] - SLICE_X41Y57 LUT4 (Prop_lut4_I3_O) 0.045 -0.084 r U1/comptX[7]_i_1/O - net (fo=1, routed) 0.000 -0.084 U1/plusOp[7] - SLICE_X41Y57 FDRE r U1/comptX_reg[7]/D - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_clk_wiz_1_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.857 -0.706 U1/CLK - SLICE_X41Y57 FDRE r U1/comptX_reg[7]/C - clock pessimism 0.232 -0.474 - SLICE_X41Y57 FDRE (Hold_fdre_C_D) 0.091 -0.383 U1/comptX_reg[7] - ------------------------------------------------------------------- - required time 0.383 - arrival time -0.084 - ------------------------------------------------------------------- - slack 0.299 - -Slack (MET) : 0.301ns (arrival time - required time) - Source: U1/comptY_reg[0]/C - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptY_reg[0]/D - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk_out1_clk_wiz_1_1 - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) - Data Path Delay: 0.421ns (logic 0.209ns (49.671%) route 0.212ns (50.329%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.706ns - Source Clock Delay (SCD): -0.474ns - Clock Pessimism Removal (CPR): -0.232ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.587 -0.474 U1/CLK - SLICE_X38Y51 FDRE r U1/comptY_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X38Y51 FDRE (Prop_fdre_C_Q) 0.164 -0.310 f U1/comptY_reg[0]/Q - net (fo=29, routed) 0.212 -0.098 U1/comptY_reg__0[0] - SLICE_X38Y51 LUT1 (Prop_lut1_I0_O) 0.045 -0.053 r U1/comptY[0]_i_1/O - net (fo=1, routed) 0.000 -0.053 U1/comptY[0]_i_1_n_0 - SLICE_X38Y51 FDRE r U1/comptY_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_clk_wiz_1_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.857 -0.706 U1/CLK - SLICE_X38Y51 FDRE r U1/comptY_reg[0]/C - clock pessimism 0.232 -0.474 - SLICE_X38Y51 FDRE (Hold_fdre_C_D) 0.120 -0.354 U1/comptY_reg[0] - ------------------------------------------------------------------- - required time 0.354 - arrival time -0.053 - ------------------------------------------------------------------- - slack 0.301 - -Slack (MET) : 0.301ns (arrival time - required time) - Source: U1/comptX_reg[0]/C - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptX_reg[0]/D - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk_out1_clk_wiz_1_1 - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) - Data Path Delay: 0.421ns (logic 0.209ns (49.671%) route 0.212ns (50.329%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.705ns - Source Clock Delay (SCD): -0.473ns - Clock Pessimism Removal (CPR): -0.232ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.588 -0.473 U1/CLK - SLICE_X42Y55 FDRE r U1/comptX_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X42Y55 FDRE (Prop_fdre_C_Q) 0.164 -0.309 f U1/comptX_reg[0]/Q - net (fo=25, routed) 0.212 -0.097 U1/comptX_reg__0[0] - SLICE_X42Y55 LUT1 (Prop_lut1_I0_O) 0.045 -0.052 r U1/comptX[0]_i_1/O - net (fo=1, routed) 0.000 -0.052 U1/plusOp[0] - SLICE_X42Y55 FDRE r U1/comptX_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_clk_wiz_1_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.858 -0.705 U1/CLK - SLICE_X42Y55 FDRE r U1/comptX_reg[0]/C - clock pessimism 0.232 -0.473 - SLICE_X42Y55 FDRE (Hold_fdre_C_D) 0.120 -0.353 U1/comptX_reg[0] - ------------------------------------------------------------------- - required time 0.353 - arrival time -0.052 - ------------------------------------------------------------------- - slack 0.301 - - - - - -Pulse Width Checks --------------------------------------------------------------------------------------- -Clock Name: clk_out1_clk_wiz_1_1 -Waveform(ns): { 0.000 20.000 } -Period(ns): 40.000 -Sources: { U0/inst/mmcm_adv_inst/CLKOUT0 } - -Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin -Min Period n/a BUFG/I n/a 2.155 40.000 37.845 BUFGCTRL_X0Y16 U0/inst/clkout1_buf/I -Min Period n/a MMCME2_ADV/CLKOUT0 n/a 1.249 40.000 38.751 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKOUT0 -Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X42Y55 U1/comptX_reg[0]/C -Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X41Y56 U1/comptX_reg[10]/C -Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X42Y55 U1/comptX_reg[1]/C -Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X43Y54 U1/comptX_reg[2]/C -Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X43Y54 U1/comptX_reg[3]/C -Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X41Y56 U1/comptX_reg[4]/C -Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X38Y51 U1/comptY_reg[0]/C -Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X36Y51 U1/comptY_reg[1]/C -Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 40.000 173.360 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKOUT0 -Low Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X42Y55 U1/comptX_reg[0]/C -Low Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X41Y56 U1/comptX_reg[10]/C -Low Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X42Y55 U1/comptX_reg[1]/C -Low Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X43Y54 U1/comptX_reg[2]/C -Low Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X43Y54 U1/comptX_reg[3]/C -Low Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X41Y56 U1/comptX_reg[4]/C -Low Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X38Y51 U1/comptY_reg[0]/C -Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X38Y51 U1/comptY_reg[0]/C -Low Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X36Y51 U1/comptY_reg[1]/C -Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X36Y51 U1/comptY_reg[1]/C -High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X42Y55 U1/comptX_reg[0]/C -High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X41Y56 U1/comptX_reg[10]/C -High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X42Y55 U1/comptX_reg[1]/C -High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X43Y54 U1/comptX_reg[2]/C -High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X43Y54 U1/comptX_reg[3]/C -High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X41Y56 U1/comptX_reg[4]/C -High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X38Y51 U1/comptY_reg[0]/C -High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X36Y51 U1/comptY_reg[1]/C -High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X36Y51 U1/comptY_reg[2]/C -High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X40Y49 U1/comptY_reg[3]/C - - - ---------------------------------------------------------------------------------------------------- -From Clock: clkfbout_clk_wiz_1_1 - To Clock: clkfbout_clk_wiz_1_1 - -Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA -Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA -PW : 0 Failing Endpoints, Worst Slack 37.845ns, Total Violation 0.000ns ---------------------------------------------------------------------------------------------------- - - -Pulse Width Checks --------------------------------------------------------------------------------------- -Clock Name: clkfbout_clk_wiz_1_1 -Waveform(ns): { 0.000 20.000 } -Period(ns): 40.000 -Sources: { U0/inst/mmcm_adv_inst/CLKFBOUT } - -Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin -Min Period n/a BUFG/I n/a 2.155 40.000 37.845 BUFGCTRL_X0Y17 U0/inst/clkf_buf/I -Min Period n/a MMCME2_ADV/CLKFBOUT n/a 1.249 40.000 38.751 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKFBOUT -Min Period n/a MMCME2_ADV/CLKFBIN n/a 1.249 40.000 38.751 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKFBIN -Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 40.000 60.000 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKFBIN -Max Period n/a MMCME2_ADV/CLKFBOUT n/a 213.360 40.000 173.360 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKFBOUT - - - ---------------------------------------------------------------------------------------------------- -From Clock: clk_out1_clk_wiz_1_1 +From Clock: sys_clk_pin To Clock: clk_out1_clk_wiz_1 -Setup : 0 Failing Endpoints, Worst Slack 33.269ns, Total Violation 0.000ns -Hold : 0 Failing Endpoints, Worst Slack 0.101ns, Total Violation 0.000ns +Setup : 0 Failing Endpoints, Worst Slack 1.397ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.418ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 33.269ns (required time - arrival time) - Source: U1/comptY_reg[5]/C - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptY_reg[3]/R - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) +Slack (MET) : 1.397ns (required time - arrival time) + Source: SNAKE/snakeHere_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: SNAKE/snakeColor_reg[G][2]/D + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) - Data Path Delay: 6.142ns (logic 0.828ns (13.480%) route 5.314ns (86.520%)) - Logic Levels: 3 (LUT4=1 LUT6=2) - Clock Path Skew: 0.000ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.252ns = ( 38.748 - 40.000 ) - Source Clock Delay (SCD): -0.601ns - Clock Pessimism Removal (CPR): 0.651ns - Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 8.000ns (clk_out1_clk_wiz_1 rise@40.000ns - sys_clk_pin rise@32.000ns) + Data Path Delay: 2.462ns (logic 0.580ns (23.555%) route 1.882ns (76.445%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: -3.764ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.576ns = ( 41.576 - 40.000 ) + Source Clock Delay (SCD): 5.340ns = ( 37.340 - 32.000 ) + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns - Phase Error (PE): 0.000ns + Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.758 -0.601 U1/CLK - SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C + (clock sys_clk_pin rise edge) + 32.000 32.000 r + L16 0.000 32.000 r H125MHz (IN) + net (fo=0) 0.000 32.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.491 33.491 r H125MHz_IBUF_inst/O + net (fo=1, routed) 2.076 35.567 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 35.668 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.672 37.340 SNAKE/H125MHz + SLICE_X18Y36 FDCE r SNAKE/snakeHere_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q - net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5] - SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O - net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0 - SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O - net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0 - SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O - net (fo=10, routed) 1.866 5.542 U1/comptY - SLICE_X40Y49 FDRE r U1/comptY_reg[3]/R + SLICE_X18Y36 FDCE (Prop_fdce_C_Q) 0.456 37.796 r SNAKE/snakeHere_reg/Q + net (fo=14, routed) 1.882 39.679 SNAKE/snakeHere + SLICE_X40Y38 LUT2 (Prop_lut2_I0_O) 0.124 39.803 r SNAKE/snakeColor[G][2]_i_1/O + net (fo=1, routed) 0.000 39.803 SNAKE/snakeColor[G][2]_i_1_n_0 + SLICE_X40Y38 FDCE r SNAKE/snakeColor_reg[G][2]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r - L16 0.000 40.000 r H125MHz (IN) - net (fo=0) 0.000 40.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.580 38.748 U1/CLK - SLICE_X40Y49 FDRE r U1/comptY_reg[3]/C - clock pessimism 0.651 39.399 - clock uncertainty -0.160 39.239 - SLICE_X40Y49 FDRE (Setup_fdre_C_R) -0.429 38.810 U1/comptY_reg[3] + BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.573 41.576 SNAKE/clk_out1 + SLICE_X40Y38 FDCE r SNAKE/snakeColor_reg[G][2]/C + clock pessimism 0.000 41.576 + clock uncertainty -0.406 41.170 + SLICE_X40Y38 FDCE (Setup_fdce_C_D) 0.029 41.199 SNAKE/snakeColor_reg[G][2] ------------------------------------------------------------------- - required time 38.810 - arrival time -5.542 + required time 41.199 + arrival time -39.803 ------------------------------------------------------------------- - slack 33.269 + slack 1.397 -Slack (MET) : 33.269ns (required time - arrival time) - Source: U1/comptY_reg[5]/C - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptY_reg[5]/R - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) +Slack (MET) : 1.415ns (required time - arrival time) + Source: SNAKE/snakeHere_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: SNAKE/snakeColor_reg[R][1]/D + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) - Data Path Delay: 6.142ns (logic 0.828ns (13.480%) route 5.314ns (86.520%)) - Logic Levels: 3 (LUT4=1 LUT6=2) - Clock Path Skew: 0.000ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.252ns = ( 38.748 - 40.000 ) - Source Clock Delay (SCD): -0.601ns - Clock Pessimism Removal (CPR): 0.651ns - Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 8.000ns (clk_out1_clk_wiz_1 rise@40.000ns - sys_clk_pin rise@32.000ns) + Data Path Delay: 2.490ns (logic 0.608ns (24.414%) route 1.882ns (75.586%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: -3.764ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.576ns = ( 41.576 - 40.000 ) + Source Clock Delay (SCD): 5.340ns = ( 37.340 - 32.000 ) + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns - Phase Error (PE): 0.000ns + Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.758 -0.601 U1/CLK - SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C + (clock sys_clk_pin rise edge) + 32.000 32.000 r + L16 0.000 32.000 r H125MHz (IN) + net (fo=0) 0.000 32.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.491 33.491 r H125MHz_IBUF_inst/O + net (fo=1, routed) 2.076 35.567 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 35.668 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.672 37.340 SNAKE/H125MHz + SLICE_X18Y36 FDCE r SNAKE/snakeHere_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q - net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5] - SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O - net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0 - SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O - net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0 - SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O - net (fo=10, routed) 1.866 5.542 U1/comptY - SLICE_X40Y49 FDRE r U1/comptY_reg[5]/R + SLICE_X18Y36 FDCE (Prop_fdce_C_Q) 0.456 37.796 r SNAKE/snakeHere_reg/Q + net (fo=14, routed) 1.882 39.679 SNAKE/snakeHere + SLICE_X40Y38 LUT2 (Prop_lut2_I0_O) 0.152 39.831 r SNAKE/snakeColor[R][1]_i_1/O + net (fo=1, routed) 0.000 39.831 SNAKE/snakeColor[R][1]_i_1_n_0 + SLICE_X40Y38 FDCE r SNAKE/snakeColor_reg[R][1]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r - L16 0.000 40.000 r H125MHz (IN) - net (fo=0) 0.000 40.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.580 38.748 U1/CLK - SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C - clock pessimism 0.651 39.399 - clock uncertainty -0.160 39.239 - SLICE_X40Y49 FDRE (Setup_fdre_C_R) -0.429 38.810 U1/comptY_reg[5] + BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.573 41.576 SNAKE/clk_out1 + SLICE_X40Y38 FDCE r SNAKE/snakeColor_reg[R][1]/C + clock pessimism 0.000 41.576 + clock uncertainty -0.406 41.170 + SLICE_X40Y38 FDCE (Setup_fdce_C_D) 0.075 41.245 SNAKE/snakeColor_reg[R][1] ------------------------------------------------------------------- - required time 38.810 - arrival time -5.542 + required time 41.245 + arrival time -39.831 ------------------------------------------------------------------- - slack 33.269 + slack 1.415 -Slack (MET) : 33.414ns (required time - arrival time) - Source: U1/comptY_reg[5]/C - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptY_reg[4]/R - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) +Slack (MET) : 1.545ns (required time - arrival time) + Source: SNAKE/snakeHere_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: SNAKE/snakeColor_reg[G][5]/D + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) - Data Path Delay: 5.838ns (logic 0.828ns (14.184%) route 5.010ns (85.816%)) - Logic Levels: 3 (LUT4=1 LUT6=2) - Clock Path Skew: -0.064ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.253ns = ( 38.747 - 40.000 ) - Source Clock Delay (SCD): -0.601ns - Clock Pessimism Removal (CPR): 0.588ns - Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 8.000ns (clk_out1_clk_wiz_1 rise@40.000ns - sys_clk_pin rise@32.000ns) + Data Path Delay: 2.314ns (logic 0.580ns (25.068%) route 1.734ns (74.932%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: -3.766ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.574ns = ( 41.574 - 40.000 ) + Source Clock Delay (SCD): 5.340ns = ( 37.340 - 32.000 ) + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns - Phase Error (PE): 0.000ns + Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.758 -0.601 U1/CLK - SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C + (clock sys_clk_pin rise edge) + 32.000 32.000 r + L16 0.000 32.000 r H125MHz (IN) + net (fo=0) 0.000 32.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.491 33.491 r H125MHz_IBUF_inst/O + net (fo=1, routed) 2.076 35.567 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 35.668 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.672 37.340 SNAKE/H125MHz + SLICE_X18Y36 FDCE r SNAKE/snakeHere_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q - net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5] - SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O - net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0 - SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O - net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0 - SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O - net (fo=10, routed) 1.561 5.237 U1/comptY - SLICE_X38Y49 FDRE r U1/comptY_reg[4]/R + SLICE_X18Y36 FDCE (Prop_fdce_C_Q) 0.456 37.796 r SNAKE/snakeHere_reg/Q + net (fo=14, routed) 1.734 39.530 SNAKE/snakeHere + SLICE_X40Y36 LUT2 (Prop_lut2_I0_O) 0.124 39.654 r SNAKE/snakeColor[G][5]_i_1/O + net (fo=1, routed) 0.000 39.654 SNAKE/snakeColor[G][5]_i_1_n_0 + SLICE_X40Y36 FDCE r SNAKE/snakeColor_reg[G][5]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r - L16 0.000 40.000 r H125MHz (IN) - net (fo=0) 0.000 40.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.579 38.747 U1/CLK - SLICE_X38Y49 FDRE r U1/comptY_reg[4]/C - clock pessimism 0.588 39.335 - clock uncertainty -0.160 39.175 - SLICE_X38Y49 FDRE (Setup_fdre_C_R) -0.524 38.651 U1/comptY_reg[4] + BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.571 41.574 SNAKE/clk_out1 + SLICE_X40Y36 FDCE r SNAKE/snakeColor_reg[G][5]/C + clock pessimism 0.000 41.574 + clock uncertainty -0.406 41.168 + SLICE_X40Y36 FDCE (Setup_fdce_C_D) 0.031 41.199 SNAKE/snakeColor_reg[G][5] ------------------------------------------------------------------- - required time 38.651 - arrival time -5.237 + required time 41.199 + arrival time -39.654 ------------------------------------------------------------------- - slack 33.414 + slack 1.545 -Slack (MET) : 33.600ns (required time - arrival time) - Source: U1/comptY_reg[5]/C - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptY_reg[1]/R - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) +Slack (MET) : 1.561ns (required time - arrival time) + Source: SNAKE/snakeHere_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: SNAKE/snakeColor_reg[R][3]/D + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) - Data Path Delay: 5.616ns (logic 0.828ns (14.744%) route 4.788ns (85.256%)) - Logic Levels: 3 (LUT4=1 LUT6=2) - Clock Path Skew: -0.195ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.269ns = ( 38.731 - 40.000 ) - Source Clock Delay (SCD): -0.601ns - Clock Pessimism Removal (CPR): 0.473ns - Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 8.000ns (clk_out1_clk_wiz_1 rise@40.000ns - sys_clk_pin rise@32.000ns) + Data Path Delay: 2.342ns (logic 0.608ns (25.964%) route 1.734ns (74.036%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: -3.766ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.574ns = ( 41.574 - 40.000 ) + Source Clock Delay (SCD): 5.340ns = ( 37.340 - 32.000 ) + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns - Phase Error (PE): 0.000ns + Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.758 -0.601 U1/CLK - SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C + (clock sys_clk_pin rise edge) + 32.000 32.000 r + L16 0.000 32.000 r H125MHz (IN) + net (fo=0) 0.000 32.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.491 33.491 r H125MHz_IBUF_inst/O + net (fo=1, routed) 2.076 35.567 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 35.668 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.672 37.340 SNAKE/H125MHz + SLICE_X18Y36 FDCE r SNAKE/snakeHere_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q - net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5] - SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O - net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0 - SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O - net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0 - SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O - net (fo=10, routed) 1.340 5.015 U1/comptY - SLICE_X36Y51 FDRE r U1/comptY_reg[1]/R + SLICE_X18Y36 FDCE (Prop_fdce_C_Q) 0.456 37.796 r SNAKE/snakeHere_reg/Q + net (fo=14, routed) 1.734 39.530 SNAKE/snakeHere + SLICE_X40Y36 LUT2 (Prop_lut2_I0_O) 0.152 39.682 r SNAKE/snakeColor[R][3]_i_1/O + net (fo=1, routed) 0.000 39.682 SNAKE/snakeColor[R][3]_i_1_n_0 + SLICE_X40Y36 FDCE r SNAKE/snakeColor_reg[R][3]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r - L16 0.000 40.000 r H125MHz (IN) - net (fo=0) 0.000 40.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.563 38.731 U1/CLK - SLICE_X36Y51 FDRE r U1/comptY_reg[1]/C - clock pessimism 0.473 39.204 - clock uncertainty -0.160 39.044 - SLICE_X36Y51 FDRE (Setup_fdre_C_R) -0.429 38.615 U1/comptY_reg[1] + BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.571 41.574 SNAKE/clk_out1 + SLICE_X40Y36 FDCE r SNAKE/snakeColor_reg[R][3]/C + clock pessimism 0.000 41.574 + clock uncertainty -0.406 41.168 + SLICE_X40Y36 FDCE (Setup_fdce_C_D) 0.075 41.243 SNAKE/snakeColor_reg[R][3] ------------------------------------------------------------------- - required time 38.615 - arrival time -5.015 + required time 41.243 + arrival time -39.682 ------------------------------------------------------------------- - slack 33.600 + slack 1.561 -Slack (MET) : 33.600ns (required time - arrival time) - Source: U1/comptY_reg[5]/C - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptY_reg[2]/R - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) +Slack (MET) : 1.639ns (required time - arrival time) + Source: SNAKE/snakeHere_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: SNAKE/snakeColor_reg[G][4]/D + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) - Data Path Delay: 5.616ns (logic 0.828ns (14.744%) route 4.788ns (85.256%)) - Logic Levels: 3 (LUT4=1 LUT6=2) - Clock Path Skew: -0.195ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.269ns = ( 38.731 - 40.000 ) - Source Clock Delay (SCD): -0.601ns - Clock Pessimism Removal (CPR): 0.473ns - Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 8.000ns (clk_out1_clk_wiz_1 rise@40.000ns - sys_clk_pin rise@32.000ns) + Data Path Delay: 2.220ns (logic 0.580ns (26.131%) route 1.640ns (73.869%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: -3.765ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.575ns = ( 41.575 - 40.000 ) + Source Clock Delay (SCD): 5.340ns = ( 37.340 - 32.000 ) + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns - Phase Error (PE): 0.000ns + Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.758 -0.601 U1/CLK - SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C + (clock sys_clk_pin rise edge) + 32.000 32.000 r + L16 0.000 32.000 r H125MHz (IN) + net (fo=0) 0.000 32.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.491 33.491 r H125MHz_IBUF_inst/O + net (fo=1, routed) 2.076 35.567 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 35.668 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.672 37.340 SNAKE/H125MHz + SLICE_X18Y36 FDCE r SNAKE/snakeHere_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q - net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5] - SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O - net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0 - SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O - net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0 - SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O - net (fo=10, routed) 1.340 5.015 U1/comptY - SLICE_X36Y51 FDRE r U1/comptY_reg[2]/R + SLICE_X18Y36 FDCE (Prop_fdce_C_Q) 0.456 37.796 r SNAKE/snakeHere_reg/Q + net (fo=14, routed) 1.640 39.436 SNAKE/snakeHere + SLICE_X37Y38 LUT2 (Prop_lut2_I0_O) 0.124 39.560 r SNAKE/snakeColor[G][4]_i_1/O + net (fo=1, routed) 0.000 39.560 SNAKE/snakeColor[G][4]_i_1_n_0 + SLICE_X37Y38 FDCE r SNAKE/snakeColor_reg[G][4]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r - L16 0.000 40.000 r H125MHz (IN) - net (fo=0) 0.000 40.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.563 38.731 U1/CLK - SLICE_X36Y51 FDRE r U1/comptY_reg[2]/C - clock pessimism 0.473 39.204 - clock uncertainty -0.160 39.044 - SLICE_X36Y51 FDRE (Setup_fdre_C_R) -0.429 38.615 U1/comptY_reg[2] + BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.572 41.575 SNAKE/clk_out1 + SLICE_X37Y38 FDCE r SNAKE/snakeColor_reg[G][4]/C + clock pessimism 0.000 41.575 + clock uncertainty -0.406 41.169 + SLICE_X37Y38 FDCE (Setup_fdce_C_D) 0.029 41.198 SNAKE/snakeColor_reg[G][4] ------------------------------------------------------------------- - required time 38.615 - arrival time -5.015 + required time 41.198 + arrival time -39.560 ------------------------------------------------------------------- - slack 33.600 + slack 1.639 -Slack (MET) : 33.600ns (required time - arrival time) - Source: U1/comptY_reg[5]/C - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptY_reg[7]/R - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) +Slack (MET) : 1.691ns (required time - arrival time) + Source: SNAKE/snakeHere_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: SNAKE/snakeColor_reg[R][2]/D + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) - Data Path Delay: 5.616ns (logic 0.828ns (14.744%) route 4.788ns (85.256%)) - Logic Levels: 3 (LUT4=1 LUT6=2) - Clock Path Skew: -0.195ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.269ns = ( 38.731 - 40.000 ) - Source Clock Delay (SCD): -0.601ns - Clock Pessimism Removal (CPR): 0.473ns - Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 8.000ns (clk_out1_clk_wiz_1 rise@40.000ns - sys_clk_pin rise@32.000ns) + Data Path Delay: 2.214ns (logic 0.574ns (25.931%) route 1.640ns (74.069%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: -3.765ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.575ns = ( 41.575 - 40.000 ) + Source Clock Delay (SCD): 5.340ns = ( 37.340 - 32.000 ) + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns - Phase Error (PE): 0.000ns + Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.758 -0.601 U1/CLK - SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C + (clock sys_clk_pin rise edge) + 32.000 32.000 r + L16 0.000 32.000 r H125MHz (IN) + net (fo=0) 0.000 32.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.491 33.491 r H125MHz_IBUF_inst/O + net (fo=1, routed) 2.076 35.567 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 35.668 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.672 37.340 SNAKE/H125MHz + SLICE_X18Y36 FDCE r SNAKE/snakeHere_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q - net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5] - SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O - net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0 - SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O - net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0 - SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O - net (fo=10, routed) 1.340 5.015 U1/comptY - SLICE_X36Y51 FDRE r U1/comptY_reg[7]/R + SLICE_X18Y36 FDCE (Prop_fdce_C_Q) 0.456 37.796 r SNAKE/snakeHere_reg/Q + net (fo=14, routed) 1.640 39.436 SNAKE/snakeHere + SLICE_X37Y38 LUT2 (Prop_lut2_I0_O) 0.118 39.554 r SNAKE/snakeColor[R][2]_i_1/O + net (fo=1, routed) 0.000 39.554 SNAKE/snakeColor[R][2]_i_1_n_0 + SLICE_X37Y38 FDCE r SNAKE/snakeColor_reg[R][2]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r - L16 0.000 40.000 r H125MHz (IN) - net (fo=0) 0.000 40.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.563 38.731 U1/CLK - SLICE_X36Y51 FDRE r U1/comptY_reg[7]/C - clock pessimism 0.473 39.204 - clock uncertainty -0.160 39.044 - SLICE_X36Y51 FDRE (Setup_fdre_C_R) -0.429 38.615 U1/comptY_reg[7] + BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.572 41.575 SNAKE/clk_out1 + SLICE_X37Y38 FDCE r SNAKE/snakeColor_reg[R][2]/C + clock pessimism 0.000 41.575 + clock uncertainty -0.406 41.169 + SLICE_X37Y38 FDCE (Setup_fdce_C_D) 0.075 41.244 SNAKE/snakeColor_reg[R][2] ------------------------------------------------------------------- - required time 38.615 - arrival time -5.015 + required time 41.244 + arrival time -39.554 ------------------------------------------------------------------- - slack 33.600 + slack 1.691 -Slack (MET) : 33.600ns (required time - arrival time) - Source: U1/comptY_reg[5]/C - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptY_reg[8]/R - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) +Slack (MET) : 1.722ns (required time - arrival time) + Source: SNAKE/snakeHere_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: SNAKE/snakeColor_reg[B][1]/D + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) - Data Path Delay: 5.616ns (logic 0.828ns (14.744%) route 4.788ns (85.256%)) - Logic Levels: 3 (LUT4=1 LUT6=2) - Clock Path Skew: -0.195ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.269ns = ( 38.731 - 40.000 ) - Source Clock Delay (SCD): -0.601ns - Clock Pessimism Removal (CPR): 0.473ns - Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 8.000ns (clk_out1_clk_wiz_1 rise@40.000ns - sys_clk_pin rise@32.000ns) + Data Path Delay: 2.134ns (logic 0.580ns (27.176%) route 1.554ns (72.824%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: -3.767ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.573ns = ( 41.573 - 40.000 ) + Source Clock Delay (SCD): 5.340ns = ( 37.340 - 32.000 ) + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns - Phase Error (PE): 0.000ns + Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.758 -0.601 U1/CLK - SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C + (clock sys_clk_pin rise edge) + 32.000 32.000 r + L16 0.000 32.000 r H125MHz (IN) + net (fo=0) 0.000 32.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.491 33.491 r H125MHz_IBUF_inst/O + net (fo=1, routed) 2.076 35.567 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 35.668 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.672 37.340 SNAKE/H125MHz + SLICE_X18Y36 FDCE r SNAKE/snakeHere_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q - net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5] - SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O - net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0 - SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O - net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0 - SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O - net (fo=10, routed) 1.340 5.015 U1/comptY - SLICE_X36Y51 FDRE r U1/comptY_reg[8]/R + SLICE_X18Y36 FDCE (Prop_fdce_C_Q) 0.456 37.796 r SNAKE/snakeHere_reg/Q + net (fo=14, routed) 1.554 39.351 SNAKE/snakeHere + SLICE_X37Y36 LUT2 (Prop_lut2_I0_O) 0.124 39.475 r SNAKE/snakeColor[B][1]_i_1/O + net (fo=1, routed) 0.000 39.475 SNAKE/snakeColor[B][1]_i_1_n_0 + SLICE_X37Y36 FDCE r SNAKE/snakeColor_reg[B][1]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r - L16 0.000 40.000 r H125MHz (IN) - net (fo=0) 0.000 40.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.563 38.731 U1/CLK - SLICE_X36Y51 FDRE r U1/comptY_reg[8]/C - clock pessimism 0.473 39.204 - clock uncertainty -0.160 39.044 - SLICE_X36Y51 FDRE (Setup_fdre_C_R) -0.429 38.615 U1/comptY_reg[8] + BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.570 41.573 SNAKE/clk_out1 + SLICE_X37Y36 FDCE r SNAKE/snakeColor_reg[B][1]/C + clock pessimism 0.000 41.573 + clock uncertainty -0.406 41.167 + SLICE_X37Y36 FDCE (Setup_fdce_C_D) 0.029 41.196 SNAKE/snakeColor_reg[B][1] ------------------------------------------------------------------- - required time 38.615 - arrival time -5.015 + required time 41.196 + arrival time -39.475 ------------------------------------------------------------------- - slack 33.600 + slack 1.722 -Slack (MET) : 33.600ns (required time - arrival time) - Source: U1/comptY_reg[5]/C - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptY_reg[9]/R - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) +Slack (MET) : 1.725ns (required time - arrival time) + Source: SNAKE/snakeHere_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: SNAKE/snakeColor_reg[G][1]/D + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) - Data Path Delay: 5.616ns (logic 0.828ns (14.744%) route 4.788ns (85.256%)) - Logic Levels: 3 (LUT4=1 LUT6=2) - Clock Path Skew: -0.195ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.269ns = ( 38.731 - 40.000 ) - Source Clock Delay (SCD): -0.601ns - Clock Pessimism Removal (CPR): 0.473ns - Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 8.000ns (clk_out1_clk_wiz_1 rise@40.000ns - sys_clk_pin rise@32.000ns) + Data Path Delay: 2.133ns (logic 0.580ns (27.189%) route 1.553ns (72.811%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: -3.767ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.573ns = ( 41.573 - 40.000 ) + Source Clock Delay (SCD): 5.340ns = ( 37.340 - 32.000 ) + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns - Phase Error (PE): 0.000ns + Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.758 -0.601 U1/CLK - SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C + (clock sys_clk_pin rise edge) + 32.000 32.000 r + L16 0.000 32.000 r H125MHz (IN) + net (fo=0) 0.000 32.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.491 33.491 r H125MHz_IBUF_inst/O + net (fo=1, routed) 2.076 35.567 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 35.668 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.672 37.340 SNAKE/H125MHz + SLICE_X18Y36 FDCE r SNAKE/snakeHere_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q - net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5] - SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O - net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0 - SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O - net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0 - SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O - net (fo=10, routed) 1.340 5.015 U1/comptY - SLICE_X36Y51 FDRE r U1/comptY_reg[9]/R + SLICE_X18Y36 FDCE (Prop_fdce_C_Q) 0.456 37.796 r SNAKE/snakeHere_reg/Q + net (fo=14, routed) 1.553 39.350 SNAKE/snakeHere + SLICE_X37Y36 LUT2 (Prop_lut2_I0_O) 0.124 39.474 r SNAKE/snakeColor[G][1]_i_1/O + net (fo=1, routed) 0.000 39.474 SNAKE/snakeColor[G][1]_i_1_n_0 + SLICE_X37Y36 FDCE r SNAKE/snakeColor_reg[G][1]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r - L16 0.000 40.000 r H125MHz (IN) - net (fo=0) 0.000 40.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.563 38.731 U1/CLK - SLICE_X36Y51 FDRE r U1/comptY_reg[9]/C - clock pessimism 0.473 39.204 - clock uncertainty -0.160 39.044 - SLICE_X36Y51 FDRE (Setup_fdre_C_R) -0.429 38.615 U1/comptY_reg[9] + BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.570 41.573 SNAKE/clk_out1 + SLICE_X37Y36 FDCE r SNAKE/snakeColor_reg[G][1]/C + clock pessimism 0.000 41.573 + clock uncertainty -0.406 41.167 + SLICE_X37Y36 FDCE (Setup_fdce_C_D) 0.031 41.198 SNAKE/snakeColor_reg[G][1] ------------------------------------------------------------------- - required time 38.615 - arrival time -5.015 + required time 41.198 + arrival time -39.474 ------------------------------------------------------------------- - slack 33.600 + slack 1.725 -Slack (MET) : 33.744ns (required time - arrival time) - Source: U1/comptY_reg[5]/C - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptY_reg[6]/R - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) +Slack (MET) : 1.740ns (required time - arrival time) + Source: SNAKE/snakeHere_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: SNAKE/snakeColor_reg[G][0]/D + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) - Data Path Delay: 5.472ns (logic 0.828ns (15.132%) route 4.644ns (84.868%)) - Logic Levels: 3 (LUT4=1 LUT6=2) - Clock Path Skew: -0.195ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.269ns = ( 38.731 - 40.000 ) - Source Clock Delay (SCD): -0.601ns - Clock Pessimism Removal (CPR): 0.473ns - Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 8.000ns (clk_out1_clk_wiz_1 rise@40.000ns - sys_clk_pin rise@32.000ns) + Data Path Delay: 2.162ns (logic 0.608ns (28.119%) route 1.554ns (71.881%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: -3.767ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.573ns = ( 41.573 - 40.000 ) + Source Clock Delay (SCD): 5.340ns = ( 37.340 - 32.000 ) + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns - Phase Error (PE): 0.000ns + Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.758 -0.601 U1/CLK - SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C + (clock sys_clk_pin rise edge) + 32.000 32.000 r + L16 0.000 32.000 r H125MHz (IN) + net (fo=0) 0.000 32.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.491 33.491 r H125MHz_IBUF_inst/O + net (fo=1, routed) 2.076 35.567 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 35.668 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.672 37.340 SNAKE/H125MHz + SLICE_X18Y36 FDCE r SNAKE/snakeHere_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q - net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5] - SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O - net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0 - SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O - net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0 - SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O - net (fo=10, routed) 1.196 4.871 U1/comptY - SLICE_X36Y50 FDRE r U1/comptY_reg[6]/R + SLICE_X18Y36 FDCE (Prop_fdce_C_Q) 0.456 37.796 r SNAKE/snakeHere_reg/Q + net (fo=14, routed) 1.554 39.351 SNAKE/snakeHere + SLICE_X37Y36 LUT2 (Prop_lut2_I0_O) 0.152 39.503 r SNAKE/snakeColor[G][0]_i_1/O + net (fo=1, routed) 0.000 39.503 SNAKE/snakeColor[G][0]_i_1_n_0 + SLICE_X37Y36 FDCE r SNAKE/snakeColor_reg[G][0]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r - L16 0.000 40.000 r H125MHz (IN) - net (fo=0) 0.000 40.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.563 38.731 U1/CLK - SLICE_X36Y50 FDRE r U1/comptY_reg[6]/C - clock pessimism 0.473 39.204 - clock uncertainty -0.160 39.044 - SLICE_X36Y50 FDRE (Setup_fdre_C_R) -0.429 38.615 U1/comptY_reg[6] + BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.570 41.573 SNAKE/clk_out1 + SLICE_X37Y36 FDCE r SNAKE/snakeColor_reg[G][0]/C + clock pessimism 0.000 41.573 + clock uncertainty -0.406 41.167 + SLICE_X37Y36 FDCE (Setup_fdce_C_D) 0.075 41.242 SNAKE/snakeColor_reg[G][0] ------------------------------------------------------------------- - required time 38.615 - arrival time -4.871 + required time 41.242 + arrival time -39.503 ------------------------------------------------------------------- - slack 33.744 + slack 1.740 -Slack (MET) : 33.981ns (required time - arrival time) - Source: U1/comptY_reg[5]/C - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptY_reg[0]/R - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) +Slack (MET) : 1.741ns (required time - arrival time) + Source: SNAKE/snakeHere_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: SNAKE/snakeColor_reg[R][4]/D + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) - Data Path Delay: 5.139ns (logic 0.828ns (16.112%) route 4.311ns (83.888%)) - Logic Levels: 3 (LUT4=1 LUT6=2) - Clock Path Skew: -0.195ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.269ns = ( 38.731 - 40.000 ) - Source Clock Delay (SCD): -0.601ns - Clock Pessimism Removal (CPR): 0.473ns - Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 8.000ns (clk_out1_clk_wiz_1 rise@40.000ns - sys_clk_pin rise@32.000ns) + Data Path Delay: 2.161ns (logic 0.608ns (28.132%) route 1.553ns (71.868%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: -3.767ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.573ns = ( 41.573 - 40.000 ) + Source Clock Delay (SCD): 5.340ns = ( 37.340 - 32.000 ) + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns - Phase Error (PE): 0.000ns + Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.758 -0.601 U1/CLK - SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C + (clock sys_clk_pin rise edge) + 32.000 32.000 r + L16 0.000 32.000 r H125MHz (IN) + net (fo=0) 0.000 32.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.491 33.491 r H125MHz_IBUF_inst/O + net (fo=1, routed) 2.076 35.567 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 35.668 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.672 37.340 SNAKE/H125MHz + SLICE_X18Y36 FDCE r SNAKE/snakeHere_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q - net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5] - SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O - net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0 - SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O - net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0 - SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O - net (fo=10, routed) 0.863 4.538 U1/comptY - SLICE_X38Y51 FDRE r U1/comptY_reg[0]/R + SLICE_X18Y36 FDCE (Prop_fdce_C_Q) 0.456 37.796 r SNAKE/snakeHere_reg/Q + net (fo=14, routed) 1.553 39.350 SNAKE/snakeHere + SLICE_X37Y36 LUT2 (Prop_lut2_I0_O) 0.152 39.502 r SNAKE/snakeColor[R][4]_i_1/O + net (fo=1, routed) 0.000 39.502 SNAKE/snakeColor[R][4]_i_1_n_0 + SLICE_X37Y36 FDCE r SNAKE/snakeColor_reg[R][4]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r - L16 0.000 40.000 r H125MHz (IN) - net (fo=0) 0.000 40.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.563 38.731 U1/CLK - SLICE_X38Y51 FDRE r U1/comptY_reg[0]/C - clock pessimism 0.473 39.204 - clock uncertainty -0.160 39.044 - SLICE_X38Y51 FDRE (Setup_fdre_C_R) -0.524 38.520 U1/comptY_reg[0] + BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.570 41.573 SNAKE/clk_out1 + SLICE_X37Y36 FDCE r SNAKE/snakeColor_reg[R][4]/C + clock pessimism 0.000 41.573 + clock uncertainty -0.406 41.167 + SLICE_X37Y36 FDCE (Setup_fdce_C_D) 0.075 41.242 SNAKE/snakeColor_reg[R][4] ------------------------------------------------------------------- - required time 38.520 - arrival time -4.538 + required time 41.242 + arrival time -39.502 ------------------------------------------------------------------- - slack 33.981 + slack 1.741 @@ -3569,635 +3471,585 @@ Slack (MET) : 33.981ns (required time - arrival time) Min Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 0.101ns (arrival time - required time) - Source: U1/comptY_reg[1]/C - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptY_reg[2]/D - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) +Slack (MET) : 0.418ns (arrival time - required time) + Source: ROM/data_reg[14]/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: SNAKE/snakeColor_reg[G][1]/D + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) - Data Path Delay: 0.368ns (logic 0.183ns (49.756%) route 0.185ns (50.244%)) - Logic Levels: 1 (LUT3=1) - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.706ns - Source Clock Delay (SCD): -0.474ns - Clock Pessimism Removal (CPR): -0.232ns - Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.313ns - Phase Error (PE): 0.000ns - Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.587 -0.474 U1/CLK - SLICE_X36Y51 FDRE r U1/comptY_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X36Y51 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptY_reg[1]/Q - net (fo=29, routed) 0.185 -0.148 U1/comptY_reg__0[1] - SLICE_X36Y51 LUT3 (Prop_lut3_I0_O) 0.042 -0.106 r U1/comptY[2]_i_1/O - net (fo=1, routed) 0.000 -0.106 U1/comptY[2]_i_1_n_0 - SLICE_X36Y51 FDRE r U1/comptY_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_clk_wiz_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.857 -0.706 U1/CLK - SLICE_X36Y51 FDRE r U1/comptY_reg[2]/C - clock pessimism 0.232 -0.474 - clock uncertainty 0.160 -0.313 - SLICE_X36Y51 FDRE (Hold_fdre_C_D) 0.107 -0.206 U1/comptY_reg[2] - ------------------------------------------------------------------- - required time 0.206 - arrival time -0.106 - ------------------------------------------------------------------- - slack 0.101 - -Slack (MET) : 0.101ns (arrival time - required time) - Source: U1/comptX_reg[5]/C - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptX_reg[5]/D - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk_out1_clk_wiz_1 - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) - Data Path Delay: 0.353ns (logic 0.186ns (52.682%) route 0.167ns (47.318%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.705ns - Source Clock Delay (SCD): -0.473ns - Clock Pessimism Removal (CPR): -0.232ns - Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.313ns - Phase Error (PE): 0.000ns - Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.588 -0.473 U1/CLK - SLICE_X43Y54 FDRE r U1/comptX_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X43Y54 FDRE (Prop_fdre_C_Q) 0.141 -0.332 r U1/comptX_reg[5]/Q - net (fo=25, routed) 0.167 -0.165 U1/comptX_reg__0[5] - SLICE_X43Y54 LUT6 (Prop_lut6_I5_O) 0.045 -0.120 r U1/comptX[5]_i_1/O - net (fo=1, routed) 0.000 -0.120 U1/plusOp[5] - SLICE_X43Y54 FDRE r U1/comptX_reg[5]/D - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_clk_wiz_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.858 -0.705 U1/CLK - SLICE_X43Y54 FDRE r U1/comptX_reg[5]/C - clock pessimism 0.232 -0.473 - clock uncertainty 0.160 -0.312 - SLICE_X43Y54 FDRE (Hold_fdre_C_D) 0.092 -0.220 U1/comptX_reg[5] - ------------------------------------------------------------------- - required time 0.220 - arrival time -0.120 - ------------------------------------------------------------------- - slack 0.101 - -Slack (MET) : 0.119ns (arrival time - required time) - Source: U1/comptX_reg[7]/C - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptX_reg[8]/D - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk_out1_clk_wiz_1 - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) - Data Path Delay: 0.387ns (logic 0.183ns (47.319%) route 0.204ns (52.681%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.706ns - Source Clock Delay (SCD): -0.474ns - Clock Pessimism Removal (CPR): -0.232ns - Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.313ns - Phase Error (PE): 0.000ns - Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.587 -0.474 U1/CLK - SLICE_X41Y57 FDRE r U1/comptX_reg[7]/C - ------------------------------------------------------------------- ------------------- - SLICE_X41Y57 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptX_reg[7]/Q - net (fo=20, routed) 0.204 -0.129 U1/comptX_reg__0[7] - SLICE_X41Y57 LUT5 (Prop_lut5_I0_O) 0.042 -0.087 r U1/comptX[8]_i_1/O - net (fo=1, routed) 0.000 -0.087 U1/plusOp[8] - SLICE_X41Y57 FDRE r U1/comptX_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_clk_wiz_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.857 -0.706 U1/CLK - SLICE_X41Y57 FDRE r U1/comptX_reg[8]/C - clock pessimism 0.232 -0.474 - clock uncertainty 0.160 -0.313 - SLICE_X41Y57 FDRE (Hold_fdre_C_D) 0.107 -0.206 U1/comptX_reg[8] - ------------------------------------------------------------------- - required time 0.206 - arrival time -0.087 - ------------------------------------------------------------------- - slack 0.119 - -Slack (MET) : 0.120ns (arrival time - required time) - Source: U1/comptY_reg[1]/C - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptY_reg[1]/D - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk_out1_clk_wiz_1 - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) - Data Path Delay: 0.371ns (logic 0.186ns (50.162%) route 0.185ns (49.838%)) + Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 0.273ns (logic 0.186ns (68.212%) route 0.087ns (31.788%)) Logic Levels: 1 (LUT2=1) - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.706ns - Source Clock Delay (SCD): -0.474ns - Clock Pessimism Removal (CPR): -0.232ns - Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: -0.644ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.856ns + Source Clock Delay (SCD): 1.500ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns - Phase Error (PE): 0.000ns + Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) + (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.587 -0.474 U1/CLK - SLICE_X36Y51 FDRE r U1/comptY_reg[1]/C + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O + net (fo=1, routed) 0.627 0.886 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.588 1.500 ROM/H125MHz + SLICE_X36Y36 FDRE r ROM/data_reg[14]/C ------------------------------------------------------------------- ------------------- - SLICE_X36Y51 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptY_reg[1]/Q - net (fo=29, routed) 0.185 -0.148 U1/comptY_reg__0[1] - SLICE_X36Y51 LUT2 (Prop_lut2_I1_O) 0.045 -0.103 r U1/comptY[1]_i_1/O - net (fo=1, routed) 0.000 -0.103 U1/comptY[1]_i_1_n_0 - SLICE_X36Y51 FDRE r U1/comptY_reg[1]/D + SLICE_X36Y36 FDRE (Prop_fdre_C_Q) 0.141 1.641 r ROM/data_reg[14]/Q + net (fo=1, routed) 0.087 1.727 SNAKE/spritesROMData[4] + SLICE_X37Y36 LUT2 (Prop_lut2_I1_O) 0.045 1.772 r SNAKE/snakeColor[G][1]_i_1/O + net (fo=1, routed) 0.000 1.772 SNAKE/snakeColor[G][1]_i_1_n_0 + SLICE_X37Y36 FDCE r SNAKE/snakeColor_reg[G][1]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.857 -0.706 U1/CLK - SLICE_X36Y51 FDRE r U1/comptY_reg[1]/C - clock pessimism 0.232 -0.474 - clock uncertainty 0.160 -0.313 - SLICE_X36Y51 FDRE (Hold_fdre_C_D) 0.091 -0.222 U1/comptY_reg[1] + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O + net (fo=60, routed) 0.854 0.856 SNAKE/clk_out1 + SLICE_X37Y36 FDCE r SNAKE/snakeColor_reg[G][1]/C + clock pessimism 0.000 0.856 + clock uncertainty 0.406 1.262 + SLICE_X37Y36 FDCE (Hold_fdce_C_D) 0.092 1.354 SNAKE/snakeColor_reg[G][1] ------------------------------------------------------------------- - required time 0.222 - arrival time -0.103 + required time -1.354 + arrival time 1.772 ------------------------------------------------------------------- - slack 0.120 + slack 0.418 -Slack (MET) : 0.127ns (arrival time - required time) - Source: U1/comptX_reg[0]/C - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptX_reg[1]/D - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) +Slack (MET) : 0.470ns (arrival time - required time) + Source: ROM/data_reg[9]/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: SNAKE/snakeColor_reg[B][1]/D + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) - Data Path Delay: 0.419ns (logic 0.207ns (49.431%) route 0.212ns (50.569%)) + Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 0.322ns (logic 0.186ns (57.733%) route 0.136ns (42.267%)) Logic Levels: 1 (LUT2=1) - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.705ns - Source Clock Delay (SCD): -0.473ns - Clock Pessimism Removal (CPR): -0.232ns - Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: -0.645ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.856ns + Source Clock Delay (SCD): 1.501ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns - Phase Error (PE): 0.000ns + Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) + (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.588 -0.473 U1/CLK - SLICE_X42Y55 FDRE r U1/comptX_reg[0]/C + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O + net (fo=1, routed) 0.627 0.886 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.589 1.501 ROM/H125MHz + SLICE_X37Y37 FDRE r ROM/data_reg[9]/C ------------------------------------------------------------------- ------------------- - SLICE_X42Y55 FDRE (Prop_fdre_C_Q) 0.164 -0.309 r U1/comptX_reg[0]/Q - net (fo=25, routed) 0.212 -0.097 U1/comptX_reg__0[0] - SLICE_X42Y55 LUT2 (Prop_lut2_I0_O) 0.043 -0.054 r U1/comptX[1]_i_1/O - net (fo=1, routed) 0.000 -0.054 U1/plusOp[1] - SLICE_X42Y55 FDRE r U1/comptX_reg[1]/D + SLICE_X37Y37 FDRE (Prop_fdre_C_Q) 0.141 1.642 r ROM/data_reg[9]/Q + net (fo=1, routed) 0.136 1.778 SNAKE/spritesROMData[1] + SLICE_X37Y36 LUT2 (Prop_lut2_I1_O) 0.045 1.823 r SNAKE/snakeColor[B][1]_i_1/O + net (fo=1, routed) 0.000 1.823 SNAKE/snakeColor[B][1]_i_1_n_0 + SLICE_X37Y36 FDCE r SNAKE/snakeColor_reg[B][1]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.858 -0.705 U1/CLK - SLICE_X42Y55 FDRE r U1/comptX_reg[1]/C - clock pessimism 0.232 -0.473 - clock uncertainty 0.160 -0.312 - SLICE_X42Y55 FDRE (Hold_fdre_C_D) 0.131 -0.181 U1/comptX_reg[1] + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O + net (fo=60, routed) 0.854 0.856 SNAKE/clk_out1 + SLICE_X37Y36 FDCE r SNAKE/snakeColor_reg[B][1]/C + clock pessimism 0.000 0.856 + clock uncertainty 0.406 1.262 + SLICE_X37Y36 FDCE (Hold_fdce_C_D) 0.091 1.353 SNAKE/snakeColor_reg[B][1] ------------------------------------------------------------------- - required time 0.181 - arrival time -0.054 + required time -1.353 + arrival time 1.823 ------------------------------------------------------------------- - slack 0.127 + slack 0.470 -Slack (MET) : 0.128ns (arrival time - required time) - Source: U1/comptX_reg[7]/C - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptX_reg[9]/D - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) +Slack (MET) : 0.485ns (arrival time - required time) + Source: ROM/data_reg[7]/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: SNAKE/snakeColor_reg[A][7]/D + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) - Data Path Delay: 0.398ns (logic 0.186ns (46.766%) route 0.212ns (53.234%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.705ns - Source Clock Delay (SCD): -0.474ns - Clock Pessimism Removal (CPR): -0.248ns - Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 0.340ns (logic 0.186ns (54.731%) route 0.154ns (45.269%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: -0.642ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.858ns + Source Clock Delay (SCD): 1.500ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns - Phase Error (PE): 0.000ns + Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) + (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.587 -0.474 U1/CLK - SLICE_X41Y57 FDRE r U1/comptX_reg[7]/C + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O + net (fo=1, routed) 0.627 0.886 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.588 1.500 ROM/H125MHz + SLICE_X39Y36 FDRE r ROM/data_reg[7]/C ------------------------------------------------------------------- ------------------- - SLICE_X41Y57 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptX_reg[7]/Q - net (fo=20, routed) 0.212 -0.121 U1/comptX_reg__0[7] - SLICE_X41Y56 LUT6 (Prop_lut6_I3_O) 0.045 -0.076 r U1/comptX[9]_i_1/O - net (fo=1, routed) 0.000 -0.076 U1/plusOp[9] - SLICE_X41Y56 FDRE r U1/comptX_reg[9]/D + SLICE_X39Y36 FDRE (Prop_fdre_C_Q) 0.141 1.641 r ROM/data_reg[7]/Q + net (fo=1, routed) 0.154 1.795 SNAKE/spritesROMData[0] + SLICE_X40Y36 LUT2 (Prop_lut2_I1_O) 0.045 1.840 r SNAKE/snakeColor[A][7]_i_1/O + net (fo=1, routed) 0.000 1.840 SNAKE/snakeColor[A][7]_i_1_n_0 + SLICE_X40Y36 FDCE r SNAKE/snakeColor_reg[A][7]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.858 -0.705 U1/CLK - SLICE_X41Y56 FDRE r U1/comptX_reg[9]/C - clock pessimism 0.248 -0.457 - clock uncertainty 0.160 -0.296 - SLICE_X41Y56 FDRE (Hold_fdre_C_D) 0.092 -0.204 U1/comptX_reg[9] + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O + net (fo=60, routed) 0.856 0.858 SNAKE/clk_out1 + SLICE_X40Y36 FDCE r SNAKE/snakeColor_reg[A][7]/C + clock pessimism 0.000 0.858 + clock uncertainty 0.406 1.264 + SLICE_X40Y36 FDCE (Hold_fdce_C_D) 0.091 1.355 SNAKE/snakeColor_reg[A][7] ------------------------------------------------------------------- - required time 0.204 - arrival time -0.076 + required time -1.355 + arrival time 1.840 ------------------------------------------------------------------- - slack 0.128 + slack 0.485 -Slack (MET) : 0.137ns (arrival time - required time) - Source: U1/comptY_reg[6]/C - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptY_reg[6]/D - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) +Slack (MET) : 0.537ns (arrival time - required time) + Source: ROM/data_reg[15]/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: SNAKE/snakeColor_reg[G][2]/D + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) - Data Path Delay: 0.402ns (logic 0.183ns (45.514%) route 0.219ns (54.486%)) - Logic Levels: 1 (LUT3=1) - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.706ns - Source Clock Delay (SCD): -0.474ns - Clock Pessimism Removal (CPR): -0.232ns - Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 0.393ns (logic 0.186ns (47.328%) route 0.207ns (52.672%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: -0.641ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.861ns + Source Clock Delay (SCD): 1.502ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns - Phase Error (PE): 0.000ns + Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) + (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.587 -0.474 U1/CLK - SLICE_X36Y50 FDRE r U1/comptY_reg[6]/C + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O + net (fo=1, routed) 0.627 0.886 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.590 1.502 ROM/H125MHz + SLICE_X39Y38 FDRE r ROM/data_reg[15]/C ------------------------------------------------------------------- ------------------- - SLICE_X36Y50 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptY_reg[6]/Q - net (fo=21, routed) 0.219 -0.114 U1/comptY_reg__0[6] - SLICE_X36Y50 LUT3 (Prop_lut3_I2_O) 0.042 -0.072 r U1/comptY[6]_i_1/O - net (fo=1, routed) 0.000 -0.072 U1/plusOp__0[6] - SLICE_X36Y50 FDRE r U1/comptY_reg[6]/D + SLICE_X39Y38 FDRE (Prop_fdre_C_Q) 0.141 1.643 r ROM/data_reg[15]/Q + net (fo=1, routed) 0.207 1.850 SNAKE/spritesROMData[5] + SLICE_X40Y38 LUT2 (Prop_lut2_I1_O) 0.045 1.895 r SNAKE/snakeColor[G][2]_i_1/O + net (fo=1, routed) 0.000 1.895 SNAKE/snakeColor[G][2]_i_1_n_0 + SLICE_X40Y38 FDCE r SNAKE/snakeColor_reg[G][2]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.857 -0.706 U1/CLK - SLICE_X36Y50 FDRE r U1/comptY_reg[6]/C - clock pessimism 0.232 -0.474 - clock uncertainty 0.160 -0.313 - SLICE_X36Y50 FDRE (Hold_fdre_C_D) 0.105 -0.208 U1/comptY_reg[6] + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O + net (fo=60, routed) 0.859 0.861 SNAKE/clk_out1 + SLICE_X40Y38 FDCE r SNAKE/snakeColor_reg[G][2]/C + clock pessimism 0.000 0.861 + clock uncertainty 0.406 1.267 + SLICE_X40Y38 FDCE (Hold_fdce_C_D) 0.091 1.358 SNAKE/snakeColor_reg[G][2] ------------------------------------------------------------------- - required time 0.208 - arrival time -0.072 + required time -1.358 + arrival time 1.895 ------------------------------------------------------------------- - slack 0.137 + slack 0.537 -Slack (MET) : 0.138ns (arrival time - required time) - Source: U1/comptX_reg[7]/C - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptX_reg[7]/D - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) +Slack (MET) : 0.570ns (arrival time - required time) + Source: ROM/data_reg[21]/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: SNAKE/snakeColor_reg[R][2]/D + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) - Data Path Delay: 0.390ns (logic 0.186ns (47.724%) route 0.204ns (52.276%)) - Logic Levels: 1 (LUT4=1) - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.706ns - Source Clock Delay (SCD): -0.474ns - Clock Pessimism Removal (CPR): -0.232ns - Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 0.442ns (logic 0.210ns (47.481%) route 0.232ns (52.519%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: -0.641ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.859ns + Source Clock Delay (SCD): 1.500ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns - Phase Error (PE): 0.000ns + Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) + (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.587 -0.474 U1/CLK - SLICE_X41Y57 FDRE r U1/comptX_reg[7]/C + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O + net (fo=1, routed) 0.627 0.886 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.588 1.500 ROM/H125MHz + SLICE_X38Y36 FDRE r ROM/data_reg[21]/C ------------------------------------------------------------------- ------------------- - SLICE_X41Y57 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptX_reg[7]/Q - net (fo=20, routed) 0.204 -0.129 U1/comptX_reg__0[7] - SLICE_X41Y57 LUT4 (Prop_lut4_I3_O) 0.045 -0.084 r U1/comptX[7]_i_1/O - net (fo=1, routed) 0.000 -0.084 U1/plusOp[7] - SLICE_X41Y57 FDRE r U1/comptX_reg[7]/D + SLICE_X38Y36 FDRE (Prop_fdre_C_Q) 0.164 1.664 r ROM/data_reg[21]/Q + net (fo=1, routed) 0.232 1.896 SNAKE/spritesROMData[10] + SLICE_X37Y38 LUT2 (Prop_lut2_I1_O) 0.046 1.942 r SNAKE/snakeColor[R][2]_i_1/O + net (fo=1, routed) 0.000 1.942 SNAKE/snakeColor[R][2]_i_1_n_0 + SLICE_X37Y38 FDCE r SNAKE/snakeColor_reg[R][2]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.857 -0.706 U1/CLK - SLICE_X41Y57 FDRE r U1/comptX_reg[7]/C - clock pessimism 0.232 -0.474 - clock uncertainty 0.160 -0.313 - SLICE_X41Y57 FDRE (Hold_fdre_C_D) 0.091 -0.222 U1/comptX_reg[7] + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O + net (fo=60, routed) 0.857 0.859 SNAKE/clk_out1 + SLICE_X37Y38 FDCE r SNAKE/snakeColor_reg[R][2]/C + clock pessimism 0.000 0.859 + clock uncertainty 0.406 1.265 + SLICE_X37Y38 FDCE (Hold_fdce_C_D) 0.107 1.372 SNAKE/snakeColor_reg[R][2] ------------------------------------------------------------------- - required time 0.222 - arrival time -0.084 + required time -1.372 + arrival time 1.942 ------------------------------------------------------------------- - slack 0.138 + slack 0.570 -Slack (MET) : 0.140ns (arrival time - required time) - Source: U1/comptY_reg[0]/C - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptY_reg[0]/D - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) +Slack (MET) : 0.594ns (arrival time - required time) + Source: ROM/data_reg[18]/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: SNAKE/snakeColor_reg[G][5]/D + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) - Data Path Delay: 0.421ns (logic 0.209ns (49.671%) route 0.212ns (50.329%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.706ns - Source Clock Delay (SCD): -0.474ns - Clock Pessimism Removal (CPR): -0.232ns - Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 0.451ns (logic 0.186ns (41.243%) route 0.265ns (58.757%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: -0.641ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.858ns + Source Clock Delay (SCD): 1.499ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns - Phase Error (PE): 0.000ns + Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) + (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.587 -0.474 U1/CLK - SLICE_X38Y51 FDRE r U1/comptY_reg[0]/C + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O + net (fo=1, routed) 0.627 0.886 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.587 1.499 ROM/H125MHz + SLICE_X39Y33 FDRE r ROM/data_reg[18]/C ------------------------------------------------------------------- ------------------- - SLICE_X38Y51 FDRE (Prop_fdre_C_Q) 0.164 -0.310 f U1/comptY_reg[0]/Q - net (fo=29, routed) 0.212 -0.098 U1/comptY_reg__0[0] - SLICE_X38Y51 LUT1 (Prop_lut1_I0_O) 0.045 -0.053 r U1/comptY[0]_i_1/O - net (fo=1, routed) 0.000 -0.053 U1/comptY[0]_i_1_n_0 - SLICE_X38Y51 FDRE r U1/comptY_reg[0]/D + SLICE_X39Y33 FDRE (Prop_fdre_C_Q) 0.141 1.640 r ROM/data_reg[18]/Q + net (fo=1, routed) 0.265 1.905 SNAKE/spritesROMData[8] + SLICE_X40Y36 LUT2 (Prop_lut2_I1_O) 0.045 1.950 r SNAKE/snakeColor[G][5]_i_1/O + net (fo=1, routed) 0.000 1.950 SNAKE/snakeColor[G][5]_i_1_n_0 + SLICE_X40Y36 FDCE r SNAKE/snakeColor_reg[G][5]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.857 -0.706 U1/CLK - SLICE_X38Y51 FDRE r U1/comptY_reg[0]/C - clock pessimism 0.232 -0.474 - clock uncertainty 0.160 -0.313 - SLICE_X38Y51 FDRE (Hold_fdre_C_D) 0.120 -0.193 U1/comptY_reg[0] + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O + net (fo=60, routed) 0.856 0.858 SNAKE/clk_out1 + SLICE_X40Y36 FDCE r SNAKE/snakeColor_reg[G][5]/C + clock pessimism 0.000 0.858 + clock uncertainty 0.406 1.264 + SLICE_X40Y36 FDCE (Hold_fdce_C_D) 0.092 1.356 SNAKE/snakeColor_reg[G][5] ------------------------------------------------------------------- - required time 0.193 - arrival time -0.053 + required time -1.356 + arrival time 1.950 ------------------------------------------------------------------- - slack 0.140 + slack 0.594 -Slack (MET) : 0.140ns (arrival time - required time) - Source: U1/comptX_reg[0]/C - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptX_reg[0]/D - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) +Slack (MET) : 0.595ns (arrival time - required time) + Source: ROM/data_reg[16]/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: SNAKE/snakeColor_reg[G][3]/D + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) - Data Path Delay: 0.421ns (logic 0.209ns (49.671%) route 0.212ns (50.329%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.705ns - Source Clock Delay (SCD): -0.473ns - Clock Pessimism Removal (CPR): -0.232ns - Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 0.466ns (logic 0.183ns (39.248%) route 0.283ns (60.752%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: -0.642ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.858ns + Source Clock Delay (SCD): 1.500ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns - Phase Error (PE): 0.000ns + Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) + (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.588 -0.473 U1/CLK - SLICE_X42Y55 FDRE r U1/comptX_reg[0]/C + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O + net (fo=1, routed) 0.627 0.886 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.588 1.500 ROM/H125MHz + SLICE_X39Y34 FDRE r ROM/data_reg[16]/C ------------------------------------------------------------------- ------------------- - SLICE_X42Y55 FDRE (Prop_fdre_C_Q) 0.164 -0.309 f U1/comptX_reg[0]/Q - net (fo=25, routed) 0.212 -0.097 U1/comptX_reg__0[0] - SLICE_X42Y55 LUT1 (Prop_lut1_I0_O) 0.045 -0.052 r U1/comptX[0]_i_1/O - net (fo=1, routed) 0.000 -0.052 U1/plusOp[0] - SLICE_X42Y55 FDRE r U1/comptX_reg[0]/D + SLICE_X39Y34 FDRE (Prop_fdre_C_Q) 0.141 1.641 r ROM/data_reg[16]/Q + net (fo=1, routed) 0.283 1.924 SNAKE/spritesROMData[6] + SLICE_X40Y36 LUT2 (Prop_lut2_I1_O) 0.042 1.966 r SNAKE/snakeColor[G][3]_i_1/O + net (fo=1, routed) 0.000 1.966 SNAKE/snakeColor[G][3]_i_1_n_0 + SLICE_X40Y36 FDCE r SNAKE/snakeColor_reg[G][3]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O + net (fo=60, routed) 0.856 0.858 SNAKE/clk_out1 + SLICE_X40Y36 FDCE r SNAKE/snakeColor_reg[G][3]/C + clock pessimism 0.000 0.858 + clock uncertainty 0.406 1.264 + SLICE_X40Y36 FDCE (Hold_fdce_C_D) 0.107 1.371 SNAKE/snakeColor_reg[G][3] + ------------------------------------------------------------------- + required time -1.371 + arrival time 1.966 + ------------------------------------------------------------------- + slack 0.595 + +Slack (MET) : 0.607ns (arrival time - required time) + Source: ROM/data_reg[13]/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: SNAKE/snakeColor_reg[G][0]/D + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: clk_out1_clk_wiz_1 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 0.502ns (logic 0.187ns (37.223%) route 0.315ns (62.777%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: -0.618ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.856ns + Source Clock Delay (SCD): 1.474ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.313ns + Phase Error (PE): 0.246ns + Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.858 -0.705 U1/CLK - SLICE_X42Y55 FDRE r U1/comptX_reg[0]/C - clock pessimism 0.232 -0.473 - clock uncertainty 0.160 -0.312 - SLICE_X42Y55 FDRE (Hold_fdre_C_D) 0.120 -0.192 U1/comptX_reg[0] + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O + net (fo=1, routed) 0.627 0.886 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.562 1.474 ROM/H125MHz + SLICE_X35Y37 FDRE r ROM/data_reg[13]/C + ------------------------------------------------------------------- ------------------- + SLICE_X35Y37 FDRE (Prop_fdre_C_Q) 0.141 1.615 r ROM/data_reg[13]/Q + net (fo=1, routed) 0.315 1.930 SNAKE/spritesROMData[3] + SLICE_X37Y36 LUT2 (Prop_lut2_I1_O) 0.046 1.976 r SNAKE/snakeColor[G][0]_i_1/O + net (fo=1, routed) 0.000 1.976 SNAKE/snakeColor[G][0]_i_1_n_0 + SLICE_X37Y36 FDCE r SNAKE/snakeColor_reg[G][0]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_1 rise edge) + 0.000 0.000 r + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O + net (fo=60, routed) 0.854 0.856 SNAKE/clk_out1 + SLICE_X37Y36 FDCE r SNAKE/snakeColor_reg[G][0]/C + clock pessimism 0.000 0.856 + clock uncertainty 0.406 1.262 + SLICE_X37Y36 FDCE (Hold_fdce_C_D) 0.107 1.369 SNAKE/snakeColor_reg[G][0] ------------------------------------------------------------------- - required time 0.192 - arrival time -0.052 + required time -1.369 + arrival time 1.976 ------------------------------------------------------------------- - slack 0.140 + slack 0.607 + +Slack (MET) : 0.645ns (arrival time - required time) + Source: ROM/data_reg[17]/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: SNAKE/snakeColor_reg[G][4]/D + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: clk_out1_clk_wiz_1 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 0.527ns (logic 0.186ns (35.324%) route 0.341ns (64.676%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: -0.616ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.859ns + Source Clock Delay (SCD): 1.475ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.313ns + Phase Error (PE): 0.246ns + Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O + net (fo=1, routed) 0.627 0.886 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.563 1.475 ROM/H125MHz + SLICE_X35Y38 FDRE r ROM/data_reg[17]/C + ------------------------------------------------------------------- ------------------- + SLICE_X35Y38 FDRE (Prop_fdre_C_Q) 0.141 1.616 r ROM/data_reg[17]/Q + net (fo=1, routed) 0.341 1.956 SNAKE/spritesROMData[7] + SLICE_X37Y38 LUT2 (Prop_lut2_I1_O) 0.045 2.001 r SNAKE/snakeColor[G][4]_i_1/O + net (fo=1, routed) 0.000 2.001 SNAKE/snakeColor[G][4]_i_1_n_0 + SLICE_X37Y38 FDCE r SNAKE/snakeColor_reg[G][4]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_1 rise edge) + 0.000 0.000 r + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O + net (fo=60, routed) 0.857 0.859 SNAKE/clk_out1 + SLICE_X37Y38 FDCE r SNAKE/snakeColor_reg[G][4]/C + clock pessimism 0.000 0.859 + clock uncertainty 0.406 1.265 + SLICE_X37Y38 FDCE (Hold_fdce_C_D) 0.091 1.356 SNAKE/snakeColor_reg[G][4] + ------------------------------------------------------------------- + required time -1.356 + arrival time 2.001 + ------------------------------------------------------------------- + slack 0.645 + +Slack (MET) : 0.648ns (arrival time - required time) + Source: ROM/data_reg[22]/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: SNAKE/snakeColor_reg[R][3]/D + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: clk_out1_clk_wiz_1 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 0.519ns (logic 0.186ns (35.838%) route 0.333ns (64.162%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: -0.642ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.858ns + Source Clock Delay (SCD): 1.500ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.313ns + Phase Error (PE): 0.246ns + Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O + net (fo=1, routed) 0.627 0.886 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.588 1.500 ROM/H125MHz + SLICE_X39Y36 FDRE r ROM/data_reg[22]/C + ------------------------------------------------------------------- ------------------- + SLICE_X39Y36 FDRE (Prop_fdre_C_Q) 0.141 1.641 r ROM/data_reg[22]/Q + net (fo=1, routed) 0.333 1.974 SNAKE/spritesROMData[11] + SLICE_X40Y36 LUT2 (Prop_lut2_I1_O) 0.045 2.019 r SNAKE/snakeColor[R][3]_i_1/O + net (fo=1, routed) 0.000 2.019 SNAKE/snakeColor[R][3]_i_1_n_0 + SLICE_X40Y36 FDCE r SNAKE/snakeColor_reg[R][3]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_1 rise edge) + 0.000 0.000 r + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O + net (fo=60, routed) 0.856 0.858 SNAKE/clk_out1 + SLICE_X40Y36 FDCE r SNAKE/snakeColor_reg[R][3]/C + clock pessimism 0.000 0.858 + clock uncertainty 0.406 1.264 + SLICE_X40Y36 FDCE (Hold_fdce_C_D) 0.107 1.371 SNAKE/snakeColor_reg[R][3] + ------------------------------------------------------------------- + required time -1.371 + arrival time 2.019 + ------------------------------------------------------------------- + slack 0.648 @@ -4205,684 +4057,850 @@ Slack (MET) : 0.140ns (arrival time - required time) --------------------------------------------------------------------------------------------------- From Clock: clk_out1_clk_wiz_1 - To Clock: clk_out1_clk_wiz_1_1 + To Clock: sys_clk_pin -Setup : 0 Failing Endpoints, Worst Slack 33.269ns, Total Violation 0.000ns -Hold : 0 Failing Endpoints, Worst Slack 0.101ns, Total Violation 0.000ns +Setup : 21 Failing Endpoints, Worst Slack -3.437ns, Total Violation -39.544ns +Hold : 1 Failing Endpoint , Worst Slack -0.025ns, Total Violation -0.025ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 33.269ns (required time - arrival time) - Source: U1/comptY_reg[5]/C +Slack (VIOLATED) : -3.437ns (required time - arrival time) + Source: SYNC/comptX_reg[4]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptY_reg[3]/R - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk_out1_clk_wiz_1_1 + Destination: SNAKE/ROMAddress_reg[9]/D + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: sys_clk_pin Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) - Data Path Delay: 6.142ns (logic 0.828ns (13.480%) route 5.314ns (86.520%)) - Logic Levels: 3 (LUT4=1 LUT6=2) - Clock Path Skew: 0.000ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.252ns = ( 38.748 - 40.000 ) - Source Clock Delay (SCD): -0.601ns - Clock Pessimism Removal (CPR): 0.651ns - Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 8.000ns (sys_clk_pin rise@8.000ns - clk_out1_clk_wiz_1 rise@0.000ns) + Data Path Delay: 14.360ns (logic 3.985ns (27.750%) route 10.375ns (72.250%)) + Logic Levels: 13 (CARRY4=4 LUT2=1 LUT3=1 LUT4=1 LUT6=6) + Clock Path Skew: 3.220ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 4.883ns = ( 12.883 - 8.000 ) + Source Clock Delay (SCD): 1.663ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns - Phase Error (PE): 0.000ns + Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.758 -0.601 U1/CLK - SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.660 1.663 SYNC/clk_out1 + SLICE_X29Y21 FDRE r SYNC/comptX_reg[4]/C ------------------------------------------------------------------- ------------------- - SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q - net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5] - SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O - net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0 - SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O - net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0 - SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O - net (fo=10, routed) 1.866 5.542 U1/comptY - SLICE_X40Y49 FDRE r U1/comptY_reg[3]/R + SLICE_X29Y21 FDRE (Prop_fdre_C_Q) 0.419 2.082 r SYNC/comptX_reg[4]/Q + net (fo=10, routed) 1.606 3.688 SYNC/comptX_reg__0[4] + SLICE_X28Y20 LUT3 (Prop_lut3_I1_O) 0.299 3.987 r SYNC/comptY[9]_i_4/O + net (fo=10, routed) 1.071 5.058 SYNC/comptY[9]_i_4_n_0 + SLICE_X27Y24 LUT6 (Prop_lut6_I4_O) 0.124 5.182 r SYNC/ROMAddress[7]_i_113/O + net (fo=54, routed) 1.047 6.229 SYNC/Xi[0] + SLICE_X23Y28 CARRY4 (Prop_carry4_DI[0]_O[2]) + 0.556 6.785 r SYNC/ROMAddress_reg[7]_i_252/O[2] + net (fo=5, routed) 1.352 8.137 RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_40_1[1] + SLICE_X22Y28 LUT4 (Prop_lut4_I3_O) 0.302 8.439 r RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_108/O + net (fo=1, routed) 0.000 8.439 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_108_n_0 + SLICE_X22Y28 CARRY4 (Prop_carry4_S[1]_O[3]) + 0.640 9.079 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_40/O[3] + net (fo=2, routed) 1.031 10.110 RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_40_n_4 + SLICE_X15Y29 LUT6 (Prop_lut6_I0_O) 0.306 10.416 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_214/O + net (fo=6, routed) 0.774 11.189 RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_214_n_0 + SLICE_X10Y29 LUT2 (Prop_lut2_I1_O) 0.124 11.313 r RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_263/O + net (fo=1, routed) 0.793 12.107 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_263_n_0 + SLICE_X17Y28 LUT6 (Prop_lut6_I2_O) 0.124 12.231 r RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_128/O + net (fo=1, routed) 0.658 12.889 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_128_n_0 + SLICE_X16Y29 LUT6 (Prop_lut6_I5_O) 0.124 13.013 f RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_46/O + net (fo=1, routed) 0.559 13.572 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_46_n_0 + SLICE_X16Y29 LUT6 (Prop_lut6_I5_O) 0.124 13.696 f RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_15/O + net (fo=3, routed) 0.533 14.229 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_15_n_0 + SLICE_X16Y29 LUT6 (Prop_lut6_I5_O) 0.124 14.353 r RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_2/O + net (fo=1, routed) 0.951 15.304 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_2_n_0 + SLICE_X20Y29 CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.396 15.700 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.000 15.700 RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_1_n_0 + SLICE_X20Y30 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 16.023 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_2/O[1] + net (fo=1, routed) 0.000 16.023 SNAKE/D[9] + SLICE_X20Y30 FDRE r SNAKE/ROMAddress_reg[9]/D ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) - 40.000 40.000 r - L16 0.000 40.000 r H125MHz (IN) - net (fo=0) 0.000 40.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.580 38.748 U1/CLK - SLICE_X40Y49 FDRE r U1/comptY_reg[3]/C - clock pessimism 0.651 39.399 - clock uncertainty -0.160 39.239 - SLICE_X40Y49 FDRE (Setup_fdre_C_R) -0.429 38.810 U1/comptY_reg[3] + (clock sys_clk_pin rise edge) + 8.000 8.000 r + L16 0.000 8.000 r H125MHz (IN) + net (fo=0) 0.000 8.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O + net (fo=1, routed) 1.880 11.301 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.491 12.883 SNAKE/H125MHz + SLICE_X20Y30 FDRE r SNAKE/ROMAddress_reg[9]/C + clock pessimism 0.000 12.883 + clock uncertainty -0.406 12.477 + SLICE_X20Y30 FDRE (Setup_fdre_C_D) 0.109 12.586 SNAKE/ROMAddress_reg[9] ------------------------------------------------------------------- - required time 38.810 - arrival time -5.542 + required time 12.586 + arrival time -16.023 ------------------------------------------------------------------- - slack 33.269 + slack -3.437 -Slack (MET) : 33.269ns (required time - arrival time) - Source: U1/comptY_reg[5]/C +Slack (VIOLATED) : -3.333ns (required time - arrival time) + Source: SYNC/comptX_reg[4]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptY_reg[5]/R - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk_out1_clk_wiz_1_1 + Destination: SNAKE/ROMAddress_reg[8]/D + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: sys_clk_pin Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) - Data Path Delay: 6.142ns (logic 0.828ns (13.480%) route 5.314ns (86.520%)) - Logic Levels: 3 (LUT4=1 LUT6=2) - Clock Path Skew: 0.000ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.252ns = ( 38.748 - 40.000 ) - Source Clock Delay (SCD): -0.601ns - Clock Pessimism Removal (CPR): 0.651ns - Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 8.000ns (sys_clk_pin rise@8.000ns - clk_out1_clk_wiz_1 rise@0.000ns) + Data Path Delay: 14.256ns (logic 3.881ns (27.223%) route 10.375ns (72.777%)) + Logic Levels: 13 (CARRY4=4 LUT2=1 LUT3=1 LUT4=1 LUT6=6) + Clock Path Skew: 3.220ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 4.883ns = ( 12.883 - 8.000 ) + Source Clock Delay (SCD): 1.663ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns - Phase Error (PE): 0.000ns + Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.758 -0.601 U1/CLK - SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.660 1.663 SYNC/clk_out1 + SLICE_X29Y21 FDRE r SYNC/comptX_reg[4]/C ------------------------------------------------------------------- ------------------- - SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q - net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5] - SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O - net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0 - SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O - net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0 - SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O - net (fo=10, routed) 1.866 5.542 U1/comptY - SLICE_X40Y49 FDRE r U1/comptY_reg[5]/R + SLICE_X29Y21 FDRE (Prop_fdre_C_Q) 0.419 2.082 r SYNC/comptX_reg[4]/Q + net (fo=10, routed) 1.606 3.688 SYNC/comptX_reg__0[4] + SLICE_X28Y20 LUT3 (Prop_lut3_I1_O) 0.299 3.987 r SYNC/comptY[9]_i_4/O + net (fo=10, routed) 1.071 5.058 SYNC/comptY[9]_i_4_n_0 + SLICE_X27Y24 LUT6 (Prop_lut6_I4_O) 0.124 5.182 r SYNC/ROMAddress[7]_i_113/O + net (fo=54, routed) 1.047 6.229 SYNC/Xi[0] + SLICE_X23Y28 CARRY4 (Prop_carry4_DI[0]_O[2]) + 0.556 6.785 r SYNC/ROMAddress_reg[7]_i_252/O[2] + net (fo=5, routed) 1.352 8.137 RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_40_1[1] + SLICE_X22Y28 LUT4 (Prop_lut4_I3_O) 0.302 8.439 r RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_108/O + net (fo=1, routed) 0.000 8.439 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_108_n_0 + SLICE_X22Y28 CARRY4 (Prop_carry4_S[1]_O[3]) + 0.640 9.079 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_40/O[3] + net (fo=2, routed) 1.031 10.110 RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_40_n_4 + SLICE_X15Y29 LUT6 (Prop_lut6_I0_O) 0.306 10.416 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_214/O + net (fo=6, routed) 0.774 11.189 RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_214_n_0 + SLICE_X10Y29 LUT2 (Prop_lut2_I1_O) 0.124 11.313 r RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_263/O + net (fo=1, routed) 0.793 12.107 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_263_n_0 + SLICE_X17Y28 LUT6 (Prop_lut6_I2_O) 0.124 12.231 r RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_128/O + net (fo=1, routed) 0.658 12.889 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_128_n_0 + SLICE_X16Y29 LUT6 (Prop_lut6_I5_O) 0.124 13.013 f RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_46/O + net (fo=1, routed) 0.559 13.572 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_46_n_0 + SLICE_X16Y29 LUT6 (Prop_lut6_I5_O) 0.124 13.696 f RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_15/O + net (fo=3, routed) 0.533 14.229 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_15_n_0 + SLICE_X16Y29 LUT6 (Prop_lut6_I5_O) 0.124 14.353 r RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_2/O + net (fo=1, routed) 0.951 15.304 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_2_n_0 + SLICE_X20Y29 CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.396 15.700 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_1/CO[3] + net (fo=1, routed) 0.000 15.700 RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_1_n_0 + SLICE_X20Y30 CARRY4 (Prop_carry4_CI_O[0]) + 0.219 15.919 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_2/O[0] + net (fo=1, routed) 0.000 15.919 SNAKE/D[8] + SLICE_X20Y30 FDRE r SNAKE/ROMAddress_reg[8]/D ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) - 40.000 40.000 r - L16 0.000 40.000 r H125MHz (IN) - net (fo=0) 0.000 40.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.580 38.748 U1/CLK - SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C - clock pessimism 0.651 39.399 - clock uncertainty -0.160 39.239 - SLICE_X40Y49 FDRE (Setup_fdre_C_R) -0.429 38.810 U1/comptY_reg[5] + (clock sys_clk_pin rise edge) + 8.000 8.000 r + L16 0.000 8.000 r H125MHz (IN) + net (fo=0) 0.000 8.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O + net (fo=1, routed) 1.880 11.301 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.491 12.883 SNAKE/H125MHz + SLICE_X20Y30 FDRE r SNAKE/ROMAddress_reg[8]/C + clock pessimism 0.000 12.883 + clock uncertainty -0.406 12.477 + SLICE_X20Y30 FDRE (Setup_fdre_C_D) 0.109 12.586 SNAKE/ROMAddress_reg[8] ------------------------------------------------------------------- - required time 38.810 - arrival time -5.542 + required time 12.586 + arrival time -15.919 ------------------------------------------------------------------- - slack 33.269 + slack -3.333 -Slack (MET) : 33.414ns (required time - arrival time) - Source: U1/comptY_reg[5]/C +Slack (VIOLATED) : -2.495ns (required time - arrival time) + Source: SYNC/comptX_reg[4]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptY_reg[4]/R - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk_out1_clk_wiz_1_1 + Destination: SNAKE/ROMAddress_reg[7]/D + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: sys_clk_pin Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) - Data Path Delay: 5.838ns (logic 0.828ns (14.184%) route 5.010ns (85.816%)) - Logic Levels: 3 (LUT4=1 LUT6=2) - Clock Path Skew: -0.064ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.253ns = ( 38.747 - 40.000 ) - Source Clock Delay (SCD): -0.601ns - Clock Pessimism Removal (CPR): 0.588ns - Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 8.000ns (sys_clk_pin rise@8.000ns - clk_out1_clk_wiz_1 rise@0.000ns) + Data Path Delay: 13.418ns (logic 3.618ns (26.963%) route 9.800ns (73.037%)) + Logic Levels: 12 (CARRY4=3 LUT2=1 LUT3=1 LUT4=1 LUT5=1 LUT6=5) + Clock Path Skew: 3.220ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 4.883ns = ( 12.883 - 8.000 ) + Source Clock Delay (SCD): 1.663ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns - Phase Error (PE): 0.000ns + Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.758 -0.601 U1/CLK - SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.660 1.663 SYNC/clk_out1 + SLICE_X29Y21 FDRE r SYNC/comptX_reg[4]/C ------------------------------------------------------------------- ------------------- - SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q - net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5] - SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O - net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0 - SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O - net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0 - SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O - net (fo=10, routed) 1.561 5.237 U1/comptY - SLICE_X38Y49 FDRE r U1/comptY_reg[4]/R + SLICE_X29Y21 FDRE (Prop_fdre_C_Q) 0.419 2.082 r SYNC/comptX_reg[4]/Q + net (fo=10, routed) 1.606 3.688 SYNC/comptX_reg__0[4] + SLICE_X28Y20 LUT3 (Prop_lut3_I1_O) 0.299 3.987 r SYNC/comptY[9]_i_4/O + net (fo=10, routed) 1.071 5.058 SYNC/comptY[9]_i_4_n_0 + SLICE_X27Y24 LUT6 (Prop_lut6_I4_O) 0.124 5.182 r SYNC/ROMAddress[7]_i_113/O + net (fo=54, routed) 1.047 6.229 SYNC/Xi[0] + SLICE_X23Y28 CARRY4 (Prop_carry4_DI[0]_O[2]) + 0.556 6.785 r SYNC/ROMAddress_reg[7]_i_252/O[2] + net (fo=5, routed) 1.352 8.137 RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_40_1[1] + SLICE_X22Y28 LUT4 (Prop_lut4_I3_O) 0.302 8.439 r RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_108/O + net (fo=1, routed) 0.000 8.439 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_108_n_0 + SLICE_X22Y28 CARRY4 (Prop_carry4_S[1]_O[3]) + 0.640 9.079 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_40/O[3] + net (fo=2, routed) 1.031 10.110 RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_40_n_4 + SLICE_X15Y29 LUT6 (Prop_lut6_I0_O) 0.306 10.416 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_214/O + net (fo=6, routed) 0.774 11.189 RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_214_n_0 + SLICE_X10Y29 LUT2 (Prop_lut2_I1_O) 0.124 11.313 r RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_263/O + net (fo=1, routed) 0.793 12.107 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_263_n_0 + SLICE_X17Y28 LUT6 (Prop_lut6_I2_O) 0.124 12.231 f RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_128/O + net (fo=1, routed) 0.658 12.889 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_128_n_0 + SLICE_X16Y29 LUT6 (Prop_lut6_I5_O) 0.124 13.013 r RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_46/O + net (fo=1, routed) 0.559 13.572 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_46_n_0 + SLICE_X16Y29 LUT6 (Prop_lut6_I5_O) 0.124 13.696 r RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_15/O + net (fo=3, routed) 0.909 14.605 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_15_n_0 + SLICE_X20Y29 LUT5 (Prop_lut5_I3_O) 0.124 14.729 r RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_7/O + net (fo=1, routed) 0.000 14.729 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_7_n_0 + SLICE_X20Y29 CARRY4 (Prop_carry4_S[2]_O[3]) + 0.352 15.081 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_1/O[3] + net (fo=1, routed) 0.000 15.081 SNAKE/D[7] + SLICE_X20Y29 FDRE r SNAKE/ROMAddress_reg[7]/D ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) - 40.000 40.000 r - L16 0.000 40.000 r H125MHz (IN) - net (fo=0) 0.000 40.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.579 38.747 U1/CLK - SLICE_X38Y49 FDRE r U1/comptY_reg[4]/C - clock pessimism 0.588 39.335 - clock uncertainty -0.160 39.175 - SLICE_X38Y49 FDRE (Setup_fdre_C_R) -0.524 38.651 U1/comptY_reg[4] + (clock sys_clk_pin rise edge) + 8.000 8.000 r + L16 0.000 8.000 r H125MHz (IN) + net (fo=0) 0.000 8.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O + net (fo=1, routed) 1.880 11.301 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.491 12.883 SNAKE/H125MHz + SLICE_X20Y29 FDRE r SNAKE/ROMAddress_reg[7]/C + clock pessimism 0.000 12.883 + clock uncertainty -0.406 12.477 + SLICE_X20Y29 FDRE (Setup_fdre_C_D) 0.109 12.586 SNAKE/ROMAddress_reg[7] ------------------------------------------------------------------- - required time 38.651 - arrival time -5.237 + required time 12.586 + arrival time -15.081 ------------------------------------------------------------------- - slack 33.414 + slack -2.495 -Slack (MET) : 33.600ns (required time - arrival time) - Source: U1/comptY_reg[5]/C +Slack (VIOLATED) : -2.393ns (required time - arrival time) + Source: SYNC/comptX_reg[4]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptY_reg[1]/R - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk_out1_clk_wiz_1_1 + Destination: SNAKE/ROMAddress_reg[6]/D + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: sys_clk_pin Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) - Data Path Delay: 5.616ns (logic 0.828ns (14.744%) route 4.788ns (85.256%)) - Logic Levels: 3 (LUT4=1 LUT6=2) - Clock Path Skew: -0.195ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.269ns = ( 38.731 - 40.000 ) - Source Clock Delay (SCD): -0.601ns - Clock Pessimism Removal (CPR): 0.473ns - Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 8.000ns (sys_clk_pin rise@8.000ns - clk_out1_clk_wiz_1 rise@0.000ns) + Data Path Delay: 13.316ns (logic 3.516ns (26.403%) route 9.800ns (73.597%)) + Logic Levels: 12 (CARRY4=3 LUT2=1 LUT3=1 LUT4=1 LUT5=1 LUT6=5) + Clock Path Skew: 3.220ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 4.883ns = ( 12.883 - 8.000 ) + Source Clock Delay (SCD): 1.663ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns - Phase Error (PE): 0.000ns + Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.758 -0.601 U1/CLK - SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.660 1.663 SYNC/clk_out1 + SLICE_X29Y21 FDRE r SYNC/comptX_reg[4]/C ------------------------------------------------------------------- ------------------- - SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q - net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5] - SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O - net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0 - SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O - net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0 - SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O - net (fo=10, routed) 1.340 5.015 U1/comptY - SLICE_X36Y51 FDRE r U1/comptY_reg[1]/R + SLICE_X29Y21 FDRE (Prop_fdre_C_Q) 0.419 2.082 r SYNC/comptX_reg[4]/Q + net (fo=10, routed) 1.606 3.688 SYNC/comptX_reg__0[4] + SLICE_X28Y20 LUT3 (Prop_lut3_I1_O) 0.299 3.987 r SYNC/comptY[9]_i_4/O + net (fo=10, routed) 1.071 5.058 SYNC/comptY[9]_i_4_n_0 + SLICE_X27Y24 LUT6 (Prop_lut6_I4_O) 0.124 5.182 r SYNC/ROMAddress[7]_i_113/O + net (fo=54, routed) 1.047 6.229 SYNC/Xi[0] + SLICE_X23Y28 CARRY4 (Prop_carry4_DI[0]_O[2]) + 0.556 6.785 r SYNC/ROMAddress_reg[7]_i_252/O[2] + net (fo=5, routed) 1.352 8.137 RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_40_1[1] + SLICE_X22Y28 LUT4 (Prop_lut4_I3_O) 0.302 8.439 r RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_108/O + net (fo=1, routed) 0.000 8.439 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_108_n_0 + SLICE_X22Y28 CARRY4 (Prop_carry4_S[1]_O[3]) + 0.640 9.079 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_40/O[3] + net (fo=2, routed) 1.031 10.110 RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_40_n_4 + SLICE_X15Y29 LUT6 (Prop_lut6_I0_O) 0.306 10.416 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_214/O + net (fo=6, routed) 0.774 11.189 RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_214_n_0 + SLICE_X10Y29 LUT2 (Prop_lut2_I1_O) 0.124 11.313 r RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_263/O + net (fo=1, routed) 0.793 12.107 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_263_n_0 + SLICE_X17Y28 LUT6 (Prop_lut6_I2_O) 0.124 12.231 f RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_128/O + net (fo=1, routed) 0.658 12.889 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_128_n_0 + SLICE_X16Y29 LUT6 (Prop_lut6_I5_O) 0.124 13.013 r RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_46/O + net (fo=1, routed) 0.559 13.572 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_46_n_0 + SLICE_X16Y29 LUT6 (Prop_lut6_I5_O) 0.124 13.696 r RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_15/O + net (fo=3, routed) 0.909 14.605 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_15_n_0 + SLICE_X20Y29 LUT5 (Prop_lut5_I3_O) 0.124 14.729 r RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_7/O + net (fo=1, routed) 0.000 14.729 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_7_n_0 + SLICE_X20Y29 CARRY4 (Prop_carry4_S[2]_O[2]) + 0.250 14.979 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_1/O[2] + net (fo=1, routed) 0.000 14.979 SNAKE/D[6] + SLICE_X20Y29 FDRE r SNAKE/ROMAddress_reg[6]/D ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) - 40.000 40.000 r - L16 0.000 40.000 r H125MHz (IN) - net (fo=0) 0.000 40.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.563 38.731 U1/CLK - SLICE_X36Y51 FDRE r U1/comptY_reg[1]/C - clock pessimism 0.473 39.204 - clock uncertainty -0.160 39.044 - SLICE_X36Y51 FDRE (Setup_fdre_C_R) -0.429 38.615 U1/comptY_reg[1] + (clock sys_clk_pin rise edge) + 8.000 8.000 r + L16 0.000 8.000 r H125MHz (IN) + net (fo=0) 0.000 8.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O + net (fo=1, routed) 1.880 11.301 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.491 12.883 SNAKE/H125MHz + SLICE_X20Y29 FDRE r SNAKE/ROMAddress_reg[6]/C + clock pessimism 0.000 12.883 + clock uncertainty -0.406 12.477 + SLICE_X20Y29 FDRE (Setup_fdre_C_D) 0.109 12.586 SNAKE/ROMAddress_reg[6] ------------------------------------------------------------------- - required time 38.615 - arrival time -5.015 + required time 12.586 + arrival time -14.979 ------------------------------------------------------------------- - slack 33.600 + slack -2.393 -Slack (MET) : 33.600ns (required time - arrival time) - Source: U1/comptY_reg[5]/C +Slack (VIOLATED) : -2.382ns (required time - arrival time) + Source: SYNC/comptX_reg[10]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptY_reg[2]/R - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk_out1_clk_wiz_1_1 + Destination: SNAKE/ROMAddress_reg[5]/D + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: sys_clk_pin Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) - Data Path Delay: 5.616ns (logic 0.828ns (14.744%) route 4.788ns (85.256%)) - Logic Levels: 3 (LUT4=1 LUT6=2) - Clock Path Skew: -0.195ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.269ns = ( 38.731 - 40.000 ) - Source Clock Delay (SCD): -0.601ns - Clock Pessimism Removal (CPR): 0.473ns - Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 8.000ns (sys_clk_pin rise@8.000ns - clk_out1_clk_wiz_1 rise@0.000ns) + Data Path Delay: 13.305ns (logic 3.333ns (25.050%) route 9.972ns (74.950%)) + Logic Levels: 14 (CARRY4=4 LUT2=1 LUT5=3 LUT6=6) + Clock Path Skew: 3.220ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 4.883ns = ( 12.883 - 8.000 ) + Source Clock Delay (SCD): 1.663ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns - Phase Error (PE): 0.000ns + Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.758 -0.601 U1/CLK - SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.660 1.663 SYNC/clk_out1 + SLICE_X27Y20 FDRE r SYNC/comptX_reg[10]/C ------------------------------------------------------------------- ------------------- - SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q - net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5] - SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O - net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0 - SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O - net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0 - SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O - net (fo=10, routed) 1.340 5.015 U1/comptY - SLICE_X36Y51 FDRE r U1/comptY_reg[2]/R + SLICE_X27Y20 FDRE (Prop_fdre_C_Q) 0.456 2.119 f SYNC/comptX_reg[10]/Q + net (fo=19, routed) 1.176 3.295 SYNC/comptX_reg__0[10] + SLICE_X26Y20 LUT2 (Prop_lut2_I1_O) 0.124 3.419 f SYNC/cCaseX[0]_i_3/O + net (fo=2, routed) 1.479 4.898 SYNC/cCaseX[0]_i_3_n_0 + SLICE_X26Y25 LUT6 (Prop_lut6_I1_O) 0.124 5.022 r SYNC/cCaseX[1]_i_2/O + net (fo=1, routed) 0.586 5.608 SYNC/cCaseX[1]_i_2_n_0 + SLICE_X26Y25 LUT5 (Prop_lut5_I4_O) 0.124 5.732 r SYNC/cCaseX[1]_i_1/O + net (fo=55, routed) 1.269 7.001 RAMCTRL/SNAKE_RAM/Xi[5] + SLICE_X31Y25 LUT5 (Prop_lut5_I1_O) 0.124 7.125 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_618/O + net (fo=1, routed) 0.000 7.125 RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_618_n_0 + SLICE_X31Y25 CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.398 7.523 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_327/CO[3] + net (fo=1, routed) 0.000 7.523 RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_327_n_0 + SLICE_X31Y26 CARRY4 (Prop_carry4_CI_CO[0]) + 0.271 7.794 f RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_113/CO[0] + net (fo=1, routed) 0.836 8.630 RAMCTRL/SNAKE_RAM/SNAKE/snakeHere5 + SLICE_X25Y27 LUT5 (Prop_lut5_I1_O) 0.373 9.003 f RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_35/O + net (fo=13, routed) 0.982 9.985 RAMCTRL/SNAKE_RAM/mem_reg_7_0_4 + SLICE_X25Y27 LUT6 (Prop_lut6_I5_O) 0.124 10.109 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_10/O + net (fo=10, routed) 0.705 10.814 RAMCTRL/SNAKE_RAM/mem_reg_8_0_4 + SLICE_X25Y30 LUT6 (Prop_lut6_I2_O) 0.124 10.938 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_72/O + net (fo=1, routed) 0.593 11.531 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_72_n_0 + SLICE_X24Y29 LUT6 (Prop_lut6_I4_O) 0.124 11.655 f RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_27/O + net (fo=2, routed) 0.761 12.416 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_27_n_0 + SLICE_X19Y27 LUT6 (Prop_lut6_I3_O) 0.124 12.540 f RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_10/O + net (fo=1, routed) 0.714 13.254 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_10_n_0 + SLICE_X19Y28 LUT6 (Prop_lut6_I0_O) 0.124 13.378 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_2/O + net (fo=1, routed) 0.871 14.249 RAMCTRL/SNAKE_RAM/SNAKE/p_11_out[3] + SLICE_X20Y28 CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.396 14.645 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 14.645 RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_1_n_0 + SLICE_X20Y29 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 14.968 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_1/O[1] + net (fo=1, routed) 0.000 14.968 SNAKE/D[5] + SLICE_X20Y29 FDRE r SNAKE/ROMAddress_reg[5]/D ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) - 40.000 40.000 r - L16 0.000 40.000 r H125MHz (IN) - net (fo=0) 0.000 40.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.563 38.731 U1/CLK - SLICE_X36Y51 FDRE r U1/comptY_reg[2]/C - clock pessimism 0.473 39.204 - clock uncertainty -0.160 39.044 - SLICE_X36Y51 FDRE (Setup_fdre_C_R) -0.429 38.615 U1/comptY_reg[2] + (clock sys_clk_pin rise edge) + 8.000 8.000 r + L16 0.000 8.000 r H125MHz (IN) + net (fo=0) 0.000 8.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O + net (fo=1, routed) 1.880 11.301 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.491 12.883 SNAKE/H125MHz + SLICE_X20Y29 FDRE r SNAKE/ROMAddress_reg[5]/C + clock pessimism 0.000 12.883 + clock uncertainty -0.406 12.477 + SLICE_X20Y29 FDRE (Setup_fdre_C_D) 0.109 12.586 SNAKE/ROMAddress_reg[5] ------------------------------------------------------------------- - required time 38.615 - arrival time -5.015 + required time 12.586 + arrival time -14.968 ------------------------------------------------------------------- - slack 33.600 + slack -2.382 -Slack (MET) : 33.600ns (required time - arrival time) - Source: U1/comptY_reg[5]/C +Slack (VIOLATED) : -2.278ns (required time - arrival time) + Source: SYNC/comptX_reg[10]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptY_reg[7]/R - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk_out1_clk_wiz_1_1 + Destination: SNAKE/ROMAddress_reg[4]/D + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: sys_clk_pin Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) - Data Path Delay: 5.616ns (logic 0.828ns (14.744%) route 4.788ns (85.256%)) - Logic Levels: 3 (LUT4=1 LUT6=2) - Clock Path Skew: -0.195ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.269ns = ( 38.731 - 40.000 ) - Source Clock Delay (SCD): -0.601ns - Clock Pessimism Removal (CPR): 0.473ns - Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 8.000ns (sys_clk_pin rise@8.000ns - clk_out1_clk_wiz_1 rise@0.000ns) + Data Path Delay: 13.201ns (logic 3.229ns (24.459%) route 9.972ns (75.541%)) + Logic Levels: 14 (CARRY4=4 LUT2=1 LUT5=3 LUT6=6) + Clock Path Skew: 3.220ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 4.883ns = ( 12.883 - 8.000 ) + Source Clock Delay (SCD): 1.663ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns - Phase Error (PE): 0.000ns + Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.758 -0.601 U1/CLK - SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.660 1.663 SYNC/clk_out1 + SLICE_X27Y20 FDRE r SYNC/comptX_reg[10]/C ------------------------------------------------------------------- ------------------- - SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q - net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5] - SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O - net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0 - SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O - net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0 - SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O - net (fo=10, routed) 1.340 5.015 U1/comptY - SLICE_X36Y51 FDRE r U1/comptY_reg[7]/R + SLICE_X27Y20 FDRE (Prop_fdre_C_Q) 0.456 2.119 f SYNC/comptX_reg[10]/Q + net (fo=19, routed) 1.176 3.295 SYNC/comptX_reg__0[10] + SLICE_X26Y20 LUT2 (Prop_lut2_I1_O) 0.124 3.419 f SYNC/cCaseX[0]_i_3/O + net (fo=2, routed) 1.479 4.898 SYNC/cCaseX[0]_i_3_n_0 + SLICE_X26Y25 LUT6 (Prop_lut6_I1_O) 0.124 5.022 r SYNC/cCaseX[1]_i_2/O + net (fo=1, routed) 0.586 5.608 SYNC/cCaseX[1]_i_2_n_0 + SLICE_X26Y25 LUT5 (Prop_lut5_I4_O) 0.124 5.732 r SYNC/cCaseX[1]_i_1/O + net (fo=55, routed) 1.269 7.001 RAMCTRL/SNAKE_RAM/Xi[5] + SLICE_X31Y25 LUT5 (Prop_lut5_I1_O) 0.124 7.125 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_618/O + net (fo=1, routed) 0.000 7.125 RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_618_n_0 + SLICE_X31Y25 CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.398 7.523 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_327/CO[3] + net (fo=1, routed) 0.000 7.523 RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_327_n_0 + SLICE_X31Y26 CARRY4 (Prop_carry4_CI_CO[0]) + 0.271 7.794 f RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_113/CO[0] + net (fo=1, routed) 0.836 8.630 RAMCTRL/SNAKE_RAM/SNAKE/snakeHere5 + SLICE_X25Y27 LUT5 (Prop_lut5_I1_O) 0.373 9.003 f RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_35/O + net (fo=13, routed) 0.982 9.985 RAMCTRL/SNAKE_RAM/mem_reg_7_0_4 + SLICE_X25Y27 LUT6 (Prop_lut6_I5_O) 0.124 10.109 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_10/O + net (fo=10, routed) 0.705 10.814 RAMCTRL/SNAKE_RAM/mem_reg_8_0_4 + SLICE_X25Y30 LUT6 (Prop_lut6_I2_O) 0.124 10.938 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_72/O + net (fo=1, routed) 0.593 11.531 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_72_n_0 + SLICE_X24Y29 LUT6 (Prop_lut6_I4_O) 0.124 11.655 f RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_27/O + net (fo=2, routed) 0.761 12.416 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_27_n_0 + SLICE_X19Y27 LUT6 (Prop_lut6_I3_O) 0.124 12.540 f RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_10/O + net (fo=1, routed) 0.714 13.254 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_10_n_0 + SLICE_X19Y28 LUT6 (Prop_lut6_I0_O) 0.124 13.378 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_2/O + net (fo=1, routed) 0.871 14.249 RAMCTRL/SNAKE_RAM/SNAKE/p_11_out[3] + SLICE_X20Y28 CARRY4 (Prop_carry4_DI[3]_CO[3]) + 0.396 14.645 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_1/CO[3] + net (fo=1, routed) 0.000 14.645 RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_1_n_0 + SLICE_X20Y29 CARRY4 (Prop_carry4_CI_O[0]) + 0.219 14.864 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_1/O[0] + net (fo=1, routed) 0.000 14.864 SNAKE/D[4] + SLICE_X20Y29 FDRE r SNAKE/ROMAddress_reg[4]/D ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) - 40.000 40.000 r - L16 0.000 40.000 r H125MHz (IN) - net (fo=0) 0.000 40.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.563 38.731 U1/CLK - SLICE_X36Y51 FDRE r U1/comptY_reg[7]/C - clock pessimism 0.473 39.204 - clock uncertainty -0.160 39.044 - SLICE_X36Y51 FDRE (Setup_fdre_C_R) -0.429 38.615 U1/comptY_reg[7] + (clock sys_clk_pin rise edge) + 8.000 8.000 r + L16 0.000 8.000 r H125MHz (IN) + net (fo=0) 0.000 8.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O + net (fo=1, routed) 1.880 11.301 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.491 12.883 SNAKE/H125MHz + SLICE_X20Y29 FDRE r SNAKE/ROMAddress_reg[4]/C + clock pessimism 0.000 12.883 + clock uncertainty -0.406 12.477 + SLICE_X20Y29 FDRE (Setup_fdre_C_D) 0.109 12.586 SNAKE/ROMAddress_reg[4] ------------------------------------------------------------------- - required time 38.615 - arrival time -5.015 + required time 12.586 + arrival time -14.864 ------------------------------------------------------------------- - slack 33.600 + slack -2.278 -Slack (MET) : 33.600ns (required time - arrival time) - Source: U1/comptY_reg[5]/C +Slack (VIOLATED) : -1.898ns (required time - arrival time) + Source: SYNC/comptX_reg[4]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptY_reg[8]/R - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk_out1_clk_wiz_1_1 + Destination: SNAKE/ROMAddress_reg[3]/D + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: sys_clk_pin Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) - Data Path Delay: 5.616ns (logic 0.828ns (14.744%) route 4.788ns (85.256%)) - Logic Levels: 3 (LUT4=1 LUT6=2) - Clock Path Skew: -0.195ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.269ns = ( 38.731 - 40.000 ) - Source Clock Delay (SCD): -0.601ns - Clock Pessimism Removal (CPR): 0.473ns - Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 8.000ns (sys_clk_pin rise@8.000ns - clk_out1_clk_wiz_1 rise@0.000ns) + Data Path Delay: 12.820ns (logic 2.983ns (23.268%) route 9.837ns (76.732%)) + Logic Levels: 12 (CARRY4=3 LUT3=1 LUT4=1 LUT5=3 LUT6=4) + Clock Path Skew: 3.219ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 4.882ns = ( 12.882 - 8.000 ) + Source Clock Delay (SCD): 1.663ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns - Phase Error (PE): 0.000ns + Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.758 -0.601 U1/CLK - SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.660 1.663 SYNC/clk_out1 + SLICE_X29Y21 FDRE r SYNC/comptX_reg[4]/C ------------------------------------------------------------------- ------------------- - SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q - net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5] - SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O - net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0 - SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O - net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0 - SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O - net (fo=10, routed) 1.340 5.015 U1/comptY - SLICE_X36Y51 FDRE r U1/comptY_reg[8]/R + SLICE_X29Y21 FDRE (Prop_fdre_C_Q) 0.419 2.082 r SYNC/comptX_reg[4]/Q + net (fo=10, routed) 1.606 3.688 SYNC/comptX_reg__0[4] + SLICE_X28Y20 LUT3 (Prop_lut3_I1_O) 0.299 3.987 r SYNC/comptY[9]_i_4/O + net (fo=10, routed) 1.017 5.004 SYNC/comptY[9]_i_4_n_0 + SLICE_X27Y20 LUT5 (Prop_lut5_I4_O) 0.124 5.128 r SYNC/cCaseX[3]_i_1/O + net (fo=55, routed) 1.817 6.945 RAMCTRL/SNAKE_RAM/Xi[7] + SLICE_X11Y30 LUT6 (Prop_lut6_I0_O) 0.124 7.069 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_376/O + net (fo=1, routed) 0.394 7.463 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_376_n_0 + SLICE_X13Y29 LUT6 (Prop_lut6_I0_O) 0.124 7.587 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_275/O + net (fo=1, routed) 0.000 7.587 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_275_n_0 + SLICE_X13Y29 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.401 7.988 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_125/CO[3] + net (fo=1, routed) 0.000 7.988 RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_125_n_0 + SLICE_X13Y30 CARRY4 (Prop_carry4_CI_CO[0]) + 0.271 8.259 f RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_49/CO[0] + net (fo=1, routed) 0.844 9.104 RAMCTRL/SNAKE_RAM/SNAKE/snakeHere524_in + SLICE_X14Y28 LUT5 (Prop_lut5_I2_O) 0.373 9.477 f RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_14/O + net (fo=25, routed) 1.167 10.644 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_14_n_0 + SLICE_X18Y33 LUT6 (Prop_lut6_I0_O) 0.124 10.768 f RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_26/O + net (fo=11, routed) 1.228 11.996 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_26_n_0 + SLICE_X20Y26 LUT5 (Prop_lut5_I0_O) 0.124 12.120 f RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_16/O + net (fo=1, routed) 0.900 13.020 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_16_n_0 + SLICE_X21Y28 LUT6 (Prop_lut6_I2_O) 0.124 13.144 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_3/O + net (fo=2, routed) 0.864 14.007 RAMCTRL/SNAKE_RAM/SNAKE/p_11_out[2] + SLICE_X20Y28 LUT4 (Prop_lut4_I0_O) 0.124 14.131 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_7/O + net (fo=1, routed) 0.000 14.131 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_7_n_0 + SLICE_X20Y28 CARRY4 (Prop_carry4_S[2]_O[3]) + 0.352 14.483 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_1/O[3] + net (fo=1, routed) 0.000 14.483 SNAKE/D[3] + SLICE_X20Y28 FDRE r SNAKE/ROMAddress_reg[3]/D ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) - 40.000 40.000 r - L16 0.000 40.000 r H125MHz (IN) - net (fo=0) 0.000 40.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.563 38.731 U1/CLK - SLICE_X36Y51 FDRE r U1/comptY_reg[8]/C - clock pessimism 0.473 39.204 - clock uncertainty -0.160 39.044 - SLICE_X36Y51 FDRE (Setup_fdre_C_R) -0.429 38.615 U1/comptY_reg[8] + (clock sys_clk_pin rise edge) + 8.000 8.000 r + L16 0.000 8.000 r H125MHz (IN) + net (fo=0) 0.000 8.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O + net (fo=1, routed) 1.880 11.301 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.490 12.882 SNAKE/H125MHz + SLICE_X20Y28 FDRE r SNAKE/ROMAddress_reg[3]/C + clock pessimism 0.000 12.882 + clock uncertainty -0.406 12.476 + SLICE_X20Y28 FDRE (Setup_fdre_C_D) 0.109 12.585 SNAKE/ROMAddress_reg[3] ------------------------------------------------------------------- - required time 38.615 - arrival time -5.015 + required time 12.585 + arrival time -14.483 ------------------------------------------------------------------- - slack 33.600 + slack -1.898 -Slack (MET) : 33.600ns (required time - arrival time) - Source: U1/comptY_reg[5]/C +Slack (VIOLATED) : -1.833ns (required time - arrival time) + Source: SYNC/comptX_reg[4]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptY_reg[9]/R - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk_out1_clk_wiz_1_1 + Destination: SNAKE/ROMAddress_reg[2]/D + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: sys_clk_pin Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) - Data Path Delay: 5.616ns (logic 0.828ns (14.744%) route 4.788ns (85.256%)) - Logic Levels: 3 (LUT4=1 LUT6=2) - Clock Path Skew: -0.195ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.269ns = ( 38.731 - 40.000 ) - Source Clock Delay (SCD): -0.601ns - Clock Pessimism Removal (CPR): 0.473ns - Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 8.000ns (sys_clk_pin rise@8.000ns - clk_out1_clk_wiz_1 rise@0.000ns) + Data Path Delay: 12.755ns (logic 3.209ns (25.158%) route 9.546ns (74.842%)) + Logic Levels: 12 (CARRY4=3 LUT3=1 LUT5=2 LUT6=6) + Clock Path Skew: 3.219ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 4.882ns = ( 12.882 - 8.000 ) + Source Clock Delay (SCD): 1.663ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns - Phase Error (PE): 0.000ns + Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.758 -0.601 U1/CLK - SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.660 1.663 SYNC/clk_out1 + SLICE_X29Y21 FDRE r SYNC/comptX_reg[4]/C ------------------------------------------------------------------- ------------------- - SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q - net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5] - SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O - net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0 - SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O - net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0 - SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O - net (fo=10, routed) 1.340 5.015 U1/comptY - SLICE_X36Y51 FDRE r U1/comptY_reg[9]/R + SLICE_X29Y21 FDRE (Prop_fdre_C_Q) 0.419 2.082 r SYNC/comptX_reg[4]/Q + net (fo=10, routed) 1.606 3.688 SYNC/comptX_reg__0[4] + SLICE_X28Y20 LUT3 (Prop_lut3_I1_O) 0.299 3.987 r SYNC/comptY[9]_i_4/O + net (fo=10, routed) 1.017 5.004 SYNC/comptY[9]_i_4_n_0 + SLICE_X27Y20 LUT5 (Prop_lut5_I4_O) 0.124 5.128 r SYNC/cCaseX[3]_i_1/O + net (fo=55, routed) 1.817 6.945 RAMCTRL/SNAKE_RAM/Xi[7] + SLICE_X11Y30 LUT6 (Prop_lut6_I0_O) 0.124 7.069 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_376/O + net (fo=1, routed) 0.394 7.463 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_376_n_0 + SLICE_X13Y29 LUT6 (Prop_lut6_I0_O) 0.124 7.587 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_275/O + net (fo=1, routed) 0.000 7.587 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_275_n_0 + SLICE_X13Y29 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.401 7.988 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_125/CO[3] + net (fo=1, routed) 0.000 7.988 RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_125_n_0 + SLICE_X13Y30 CARRY4 (Prop_carry4_CI_CO[0]) + 0.271 8.259 f RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_49/CO[0] + net (fo=1, routed) 0.844 9.104 RAMCTRL/SNAKE_RAM/SNAKE/snakeHere524_in + SLICE_X14Y28 LUT5 (Prop_lut5_I2_O) 0.373 9.477 f RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_14/O + net (fo=25, routed) 1.167 10.644 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_14_n_0 + SLICE_X18Y33 LUT6 (Prop_lut6_I0_O) 0.124 10.768 f RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_26/O + net (fo=11, routed) 1.099 11.867 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_26_n_0 + SLICE_X18Y27 LUT6 (Prop_lut6_I0_O) 0.124 11.991 f RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_19/O + net (fo=1, routed) 0.736 12.728 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_19_n_0 + SLICE_X20Y27 LUT6 (Prop_lut6_I0_O) 0.124 12.852 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_4/O + net (fo=2, routed) 0.865 13.716 RAMCTRL/SNAKE_RAM/SNAKE/p_11_out[1] + SLICE_X20Y28 LUT6 (Prop_lut6_I0_O) 0.124 13.840 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_8/O + net (fo=1, routed) 0.000 13.840 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_8_n_0 + SLICE_X20Y28 CARRY4 (Prop_carry4_S[1]_O[2]) + 0.578 14.418 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_1/O[2] + net (fo=1, routed) 0.000 14.418 SNAKE/D[2] + SLICE_X20Y28 FDRE r SNAKE/ROMAddress_reg[2]/D ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) - 40.000 40.000 r - L16 0.000 40.000 r H125MHz (IN) - net (fo=0) 0.000 40.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.563 38.731 U1/CLK - SLICE_X36Y51 FDRE r U1/comptY_reg[9]/C - clock pessimism 0.473 39.204 - clock uncertainty -0.160 39.044 - SLICE_X36Y51 FDRE (Setup_fdre_C_R) -0.429 38.615 U1/comptY_reg[9] + (clock sys_clk_pin rise edge) + 8.000 8.000 r + L16 0.000 8.000 r H125MHz (IN) + net (fo=0) 0.000 8.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O + net (fo=1, routed) 1.880 11.301 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.490 12.882 SNAKE/H125MHz + SLICE_X20Y28 FDRE r SNAKE/ROMAddress_reg[2]/C + clock pessimism 0.000 12.882 + clock uncertainty -0.406 12.476 + SLICE_X20Y28 FDRE (Setup_fdre_C_D) 0.109 12.585 SNAKE/ROMAddress_reg[2] ------------------------------------------------------------------- - required time 38.615 - arrival time -5.015 + required time 12.585 + arrival time -14.418 ------------------------------------------------------------------- - slack 33.600 + slack -1.833 -Slack (MET) : 33.744ns (required time - arrival time) - Source: U1/comptY_reg[5]/C +Slack (VIOLATED) : -1.756ns (required time - arrival time) + Source: SYNC/comptX_reg[4]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptY_reg[6]/R - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk_out1_clk_wiz_1_1 + Destination: SNAKE/ROMAddress_reg[4]/CE + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: sys_clk_pin Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) - Data Path Delay: 5.472ns (logic 0.828ns (15.132%) route 4.644ns (84.868%)) - Logic Levels: 3 (LUT4=1 LUT6=2) - Clock Path Skew: -0.195ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.269ns = ( 38.731 - 40.000 ) - Source Clock Delay (SCD): -0.601ns - Clock Pessimism Removal (CPR): 0.473ns - Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 8.000ns (sys_clk_pin rise@8.000ns - clk_out1_clk_wiz_1 rise@0.000ns) + Data Path Delay: 12.401ns (logic 2.507ns (20.216%) route 9.894ns (79.784%)) + Logic Levels: 10 (CARRY4=2 LUT3=2 LUT4=1 LUT5=3 LUT6=2) + Clock Path Skew: 3.220ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 4.883ns = ( 12.883 - 8.000 ) + Source Clock Delay (SCD): 1.663ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns - Phase Error (PE): 0.000ns + Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.758 -0.601 U1/CLK - SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.660 1.663 SYNC/clk_out1 + SLICE_X29Y21 FDRE r SYNC/comptX_reg[4]/C ------------------------------------------------------------------- ------------------- - SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q - net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5] - SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O - net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0 - SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O - net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0 - SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O - net (fo=10, routed) 1.196 4.871 U1/comptY - SLICE_X36Y50 FDRE r U1/comptY_reg[6]/R + SLICE_X29Y21 FDRE (Prop_fdre_C_Q) 0.419 2.082 r SYNC/comptX_reg[4]/Q + net (fo=10, routed) 1.606 3.688 SYNC/comptX_reg__0[4] + SLICE_X28Y20 LUT3 (Prop_lut3_I1_O) 0.299 3.987 r SYNC/comptY[9]_i_4/O + net (fo=10, routed) 1.017 5.004 SYNC/comptY[9]_i_4_n_0 + SLICE_X27Y20 LUT5 (Prop_lut5_I4_O) 0.124 5.128 r SYNC/cCaseX[3]_i_1/O + net (fo=55, routed) 1.817 6.945 RAMCTRL/SNAKE_RAM/Xi[7] + SLICE_X11Y30 LUT6 (Prop_lut6_I0_O) 0.124 7.069 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_376/O + net (fo=1, routed) 0.394 7.463 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_376_n_0 + SLICE_X13Y29 LUT6 (Prop_lut6_I0_O) 0.124 7.587 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_275/O + net (fo=1, routed) 0.000 7.587 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_275_n_0 + SLICE_X13Y29 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.401 7.988 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_125/CO[3] + net (fo=1, routed) 0.000 7.988 RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_125_n_0 + SLICE_X13Y30 CARRY4 (Prop_carry4_CI_CO[0]) + 0.271 8.259 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_49/CO[0] + net (fo=1, routed) 0.844 9.104 RAMCTRL/SNAKE_RAM/SNAKE/snakeHere524_in + SLICE_X14Y28 LUT5 (Prop_lut5_I2_O) 0.373 9.477 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_14/O + net (fo=25, routed) 1.325 10.802 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_14_n_0 + SLICE_X15Y32 LUT4 (Prop_lut4_I3_O) 0.124 10.926 f RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_7/O + net (fo=10, routed) 0.963 11.889 RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_7_n_0 + SLICE_X18Y34 LUT5 (Prop_lut5_I0_O) 0.124 12.013 f RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_3/O + net (fo=2, routed) 0.898 12.910 RAMCTRL/SNAKE_RAM/mem_reg_9_0_4 + SLICE_X18Y34 LUT3 (Prop_lut3_I2_O) 0.124 13.034 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_1/O + net (fo=10, routed) 1.030 14.064 SNAKE/E[0] + SLICE_X20Y29 FDRE r SNAKE/ROMAddress_reg[4]/CE ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) - 40.000 40.000 r - L16 0.000 40.000 r H125MHz (IN) - net (fo=0) 0.000 40.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.563 38.731 U1/CLK - SLICE_X36Y50 FDRE r U1/comptY_reg[6]/C - clock pessimism 0.473 39.204 - clock uncertainty -0.160 39.044 - SLICE_X36Y50 FDRE (Setup_fdre_C_R) -0.429 38.615 U1/comptY_reg[6] + (clock sys_clk_pin rise edge) + 8.000 8.000 r + L16 0.000 8.000 r H125MHz (IN) + net (fo=0) 0.000 8.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O + net (fo=1, routed) 1.880 11.301 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.491 12.883 SNAKE/H125MHz + SLICE_X20Y29 FDRE r SNAKE/ROMAddress_reg[4]/C + clock pessimism 0.000 12.883 + clock uncertainty -0.406 12.477 + SLICE_X20Y29 FDRE (Setup_fdre_C_CE) -0.169 12.308 SNAKE/ROMAddress_reg[4] ------------------------------------------------------------------- - required time 38.615 - arrival time -4.871 + required time 12.308 + arrival time -14.064 ------------------------------------------------------------------- - slack 33.744 + slack -1.756 -Slack (MET) : 33.981ns (required time - arrival time) - Source: U1/comptY_reg[5]/C +Slack (VIOLATED) : -1.756ns (required time - arrival time) + Source: SYNC/comptX_reg[4]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptY_reg[0]/R - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk_out1_clk_wiz_1_1 + Destination: SNAKE/ROMAddress_reg[5]/CE + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: sys_clk_pin Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) - Data Path Delay: 5.139ns (logic 0.828ns (16.112%) route 4.311ns (83.888%)) - Logic Levels: 3 (LUT4=1 LUT6=2) - Clock Path Skew: -0.195ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.269ns = ( 38.731 - 40.000 ) - Source Clock Delay (SCD): -0.601ns - Clock Pessimism Removal (CPR): 0.473ns - Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Requirement: 8.000ns (sys_clk_pin rise@8.000ns - clk_out1_clk_wiz_1 rise@0.000ns) + Data Path Delay: 12.401ns (logic 2.507ns (20.216%) route 9.894ns (79.784%)) + Logic Levels: 10 (CARRY4=2 LUT3=2 LUT4=1 LUT5=3 LUT6=2) + Clock Path Skew: 3.220ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 4.883ns = ( 12.883 - 8.000 ) + Source Clock Delay (SCD): 1.663ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns - Phase Error (PE): 0.000ns + Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.758 -0.601 U1/CLK - SLICE_X40Y49 FDRE r U1/comptY_reg[5]/C + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.660 1.663 SYNC/clk_out1 + SLICE_X29Y21 FDRE r SYNC/comptX_reg[4]/C ------------------------------------------------------------------- ------------------- - SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.456 -0.145 r U1/comptY_reg[5]/Q - net (fo=22, routed) 1.582 1.437 U1/comptY_reg__0[5] - SLICE_X36Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.561 r U1/vga_vs_OBUF_inst_i_2/O - net (fo=9, routed) 0.841 2.403 U1/vga_vs_OBUF_inst_i_2_n_0 - SLICE_X40Y49 LUT6 (Prop_lut6_I5_O) 0.124 2.527 r U1/comptY[9]_i_5/O - net (fo=1, routed) 1.025 3.551 U1/comptY[9]_i_5_n_0 - SLICE_X39Y56 LUT6 (Prop_lut6_I5_O) 0.124 3.675 r U1/comptY[9]_i_1/O - net (fo=10, routed) 0.863 4.538 U1/comptY - SLICE_X38Y51 FDRE r U1/comptY_reg[0]/R + SLICE_X29Y21 FDRE (Prop_fdre_C_Q) 0.419 2.082 r SYNC/comptX_reg[4]/Q + net (fo=10, routed) 1.606 3.688 SYNC/comptX_reg__0[4] + SLICE_X28Y20 LUT3 (Prop_lut3_I1_O) 0.299 3.987 r SYNC/comptY[9]_i_4/O + net (fo=10, routed) 1.017 5.004 SYNC/comptY[9]_i_4_n_0 + SLICE_X27Y20 LUT5 (Prop_lut5_I4_O) 0.124 5.128 r SYNC/cCaseX[3]_i_1/O + net (fo=55, routed) 1.817 6.945 RAMCTRL/SNAKE_RAM/Xi[7] + SLICE_X11Y30 LUT6 (Prop_lut6_I0_O) 0.124 7.069 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_376/O + net (fo=1, routed) 0.394 7.463 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_376_n_0 + SLICE_X13Y29 LUT6 (Prop_lut6_I0_O) 0.124 7.587 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_275/O + net (fo=1, routed) 0.000 7.587 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_275_n_0 + SLICE_X13Y29 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.401 7.988 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_125/CO[3] + net (fo=1, routed) 0.000 7.988 RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_125_n_0 + SLICE_X13Y30 CARRY4 (Prop_carry4_CI_CO[0]) + 0.271 8.259 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_49/CO[0] + net (fo=1, routed) 0.844 9.104 RAMCTRL/SNAKE_RAM/SNAKE/snakeHere524_in + SLICE_X14Y28 LUT5 (Prop_lut5_I2_O) 0.373 9.477 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_14/O + net (fo=25, routed) 1.325 10.802 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_14_n_0 + SLICE_X15Y32 LUT4 (Prop_lut4_I3_O) 0.124 10.926 f RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_7/O + net (fo=10, routed) 0.963 11.889 RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_7_n_0 + SLICE_X18Y34 LUT5 (Prop_lut5_I0_O) 0.124 12.013 f RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_3/O + net (fo=2, routed) 0.898 12.910 RAMCTRL/SNAKE_RAM/mem_reg_9_0_4 + SLICE_X18Y34 LUT3 (Prop_lut3_I2_O) 0.124 13.034 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_1/O + net (fo=10, routed) 1.030 14.064 SNAKE/E[0] + SLICE_X20Y29 FDRE r SNAKE/ROMAddress_reg[5]/CE ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) - 40.000 40.000 r - L16 0.000 40.000 r H125MHz (IN) - net (fo=0) 0.000 40.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O - net (fo=21, routed) 1.563 38.731 U1/CLK - SLICE_X38Y51 FDRE r U1/comptY_reg[0]/C - clock pessimism 0.473 39.204 - clock uncertainty -0.160 39.044 - SLICE_X38Y51 FDRE (Setup_fdre_C_R) -0.524 38.520 U1/comptY_reg[0] + (clock sys_clk_pin rise edge) + 8.000 8.000 r + L16 0.000 8.000 r H125MHz (IN) + net (fo=0) 0.000 8.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O + net (fo=1, routed) 1.880 11.301 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.491 12.883 SNAKE/H125MHz + SLICE_X20Y29 FDRE r SNAKE/ROMAddress_reg[5]/C + clock pessimism 0.000 12.883 + clock uncertainty -0.406 12.477 + SLICE_X20Y29 FDRE (Setup_fdre_C_CE) -0.169 12.308 SNAKE/ROMAddress_reg[5] ------------------------------------------------------------------- - required time 38.520 - arrival time -4.538 + required time 12.308 + arrival time -14.064 ------------------------------------------------------------------- - slack 33.981 + slack -1.756 @@ -4890,635 +4908,3097 @@ Slack (MET) : 33.981ns (required time - arrival time) Min Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 0.101ns (arrival time - required time) - Source: U1/comptY_reg[1]/C +Slack (VIOLATED) : -0.025ns (arrival time - required time) + Source: SYNC/comptY_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptY_reg[2]/D - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk_out1_clk_wiz_1_1 - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) - Data Path Delay: 0.368ns (logic 0.183ns (49.756%) route 0.185ns (50.244%)) - Logic Levels: 1 (LUT3=1) - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.706ns - Source Clock Delay (SCD): -0.474ns - Clock Pessimism Removal (CPR): -0.232ns - Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.313ns - Phase Error (PE): 0.000ns - Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.587 -0.474 U1/CLK - SLICE_X36Y51 FDRE r U1/comptY_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X36Y51 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptY_reg[1]/Q - net (fo=29, routed) 0.185 -0.148 U1/comptY_reg__0[1] - SLICE_X36Y51 LUT3 (Prop_lut3_I0_O) 0.042 -0.106 r U1/comptY[2]_i_1/O - net (fo=1, routed) 0.000 -0.106 U1/comptY[2]_i_1_n_0 - SLICE_X36Y51 FDRE r U1/comptY_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_clk_wiz_1_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.857 -0.706 U1/CLK - SLICE_X36Y51 FDRE r U1/comptY_reg[2]/C - clock pessimism 0.232 -0.474 - clock uncertainty 0.160 -0.313 - SLICE_X36Y51 FDRE (Hold_fdre_C_D) 0.107 -0.206 U1/comptY_reg[2] - ------------------------------------------------------------------- - required time 0.206 - arrival time -0.106 - ------------------------------------------------------------------- - slack 0.101 - -Slack (MET) : 0.101ns (arrival time - required time) - Source: U1/comptX_reg[5]/C - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptX_reg[5]/D - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk_out1_clk_wiz_1_1 - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) - Data Path Delay: 0.353ns (logic 0.186ns (52.682%) route 0.167ns (47.318%)) + Destination: SNAKE/cCaseY_reg[3]/D + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: sys_clk_pin + Path Type: Hold (Min at Slow Process Corner) + Requirement: 0.000ns (sys_clk_pin rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) + Data Path Delay: 4.437ns (logic 0.467ns (10.525%) route 3.970ns (89.475%)) Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.705ns - Source Clock Delay (SCD): -0.473ns - Clock Pessimism Removal (CPR): -0.232ns - Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: 3.838ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 5.326ns + Source Clock Delay (SCD): 1.488ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns - Phase Error (PE): 0.000ns + Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.588 -0.473 U1/CLK - SLICE_X43Y54 FDRE r U1/comptX_reg[5]/C + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.490 1.490 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.177 -1.687 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.599 -0.088 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 0.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.485 1.488 SYNC/clk_out1 + SLICE_X19Y26 FDRE r SYNC/comptY_reg[7]/C ------------------------------------------------------------------- ------------------- - SLICE_X43Y54 FDRE (Prop_fdre_C_Q) 0.141 -0.332 r U1/comptX_reg[5]/Q - net (fo=25, routed) 0.167 -0.165 U1/comptX_reg__0[5] - SLICE_X43Y54 LUT6 (Prop_lut6_I5_O) 0.045 -0.120 r U1/comptX[5]_i_1/O - net (fo=1, routed) 0.000 -0.120 U1/plusOp[5] - SLICE_X43Y54 FDRE r U1/comptX_reg[5]/D + SLICE_X19Y26 FDRE (Prop_fdre_C_Q) 0.367 1.855 r SYNC/comptY_reg[7]/Q + net (fo=11, routed) 1.151 3.007 SYNC/comptY_reg__0[7] + SLICE_X27Y27 LUT6 (Prop_lut6_I4_O) 0.100 3.107 r SYNC/cCaseY[3]_i_1/O + net (fo=55, routed) 2.819 5.925 SNAKE/Yi[3] + SLICE_X20Y23 FDRE r SNAKE/cCaseY_reg[3]/D ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) + (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.858 -0.705 U1/CLK - SLICE_X43Y54 FDRE r U1/comptX_reg[5]/C - clock pessimism 0.232 -0.473 - clock uncertainty 0.160 -0.312 - SLICE_X43Y54 FDRE (Hold_fdre_C_D) 0.092 -0.220 U1/comptX_reg[5] + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O + net (fo=1, routed) 2.076 3.567 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.658 5.326 SNAKE/H125MHz + SLICE_X20Y23 FDRE r SNAKE/cCaseY_reg[3]/C + clock pessimism 0.000 5.326 + clock uncertainty 0.406 5.732 + SLICE_X20Y23 FDRE (Hold_fdre_C_D) 0.218 5.950 SNAKE/cCaseY_reg[3] ------------------------------------------------------------------- - required time 0.220 - arrival time -0.120 + required time -5.950 + arrival time 5.925 ------------------------------------------------------------------- - slack 0.101 + slack -0.025 -Slack (MET) : 0.119ns (arrival time - required time) - Source: U1/comptX_reg[7]/C +Slack (MET) : 0.106ns (arrival time - required time) + Source: SYNC/comptX_reg[8]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptX_reg[8]/D - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk_out1_clk_wiz_1_1 - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) - Data Path Delay: 0.387ns (logic 0.183ns (47.319%) route 0.204ns (52.681%)) + Destination: SNAKE/cCaseX_reg[1]/D + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: sys_clk_pin + Path Type: Hold (Min at Slow Process Corner) + Requirement: 0.000ns (sys_clk_pin rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) + Data Path Delay: 4.547ns (logic 0.467ns (10.271%) route 4.080ns (89.729%)) Logic Levels: 1 (LUT5=1) - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.706ns - Source Clock Delay (SCD): -0.474ns - Clock Pessimism Removal (CPR): -0.232ns - Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: 3.843ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 5.333ns + Source Clock Delay (SCD): 1.490ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns - Phase Error (PE): 0.000ns + Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.587 -0.474 U1/CLK - SLICE_X41Y57 FDRE r U1/comptX_reg[7]/C + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.490 1.490 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.177 -1.687 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.599 -0.088 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 0.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.487 1.490 SYNC/clk_out1 + SLICE_X26Y21 FDRE r SYNC/comptX_reg[8]/C ------------------------------------------------------------------- ------------------- - SLICE_X41Y57 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptX_reg[7]/Q - net (fo=20, routed) 0.204 -0.129 U1/comptX_reg__0[7] - SLICE_X41Y57 LUT5 (Prop_lut5_I0_O) 0.042 -0.087 r U1/comptX[8]_i_1/O - net (fo=1, routed) 0.000 -0.087 U1/plusOp[8] - SLICE_X41Y57 FDRE r U1/comptX_reg[8]/D + SLICE_X26Y21 FDRE (Prop_fdre_C_Q) 0.367 1.857 r SYNC/comptX_reg[8]/Q + net (fo=22, routed) 1.161 3.019 SYNC/comptX_reg__0[8] + SLICE_X26Y25 LUT5 (Prop_lut5_I2_O) 0.100 3.119 r SYNC/cCaseX[1]_i_1/O + net (fo=55, routed) 2.918 6.037 SNAKE/Xi[1] + SLICE_X29Y19 FDRE r SNAKE/cCaseX_reg[1]/D ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) + (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.857 -0.706 U1/CLK - SLICE_X41Y57 FDRE r U1/comptX_reg[8]/C - clock pessimism 0.232 -0.474 - clock uncertainty 0.160 -0.313 - SLICE_X41Y57 FDRE (Hold_fdre_C_D) 0.107 -0.206 U1/comptX_reg[8] + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O + net (fo=1, routed) 2.076 3.567 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.665 5.333 SNAKE/H125MHz + SLICE_X29Y19 FDRE r SNAKE/cCaseX_reg[1]/C + clock pessimism 0.000 5.333 + clock uncertainty 0.406 5.739 + SLICE_X29Y19 FDRE (Hold_fdre_C_D) 0.192 5.931 SNAKE/cCaseX_reg[1] ------------------------------------------------------------------- - required time 0.206 - arrival time -0.087 + required time -5.931 + arrival time 6.037 ------------------------------------------------------------------- - slack 0.119 - -Slack (MET) : 0.120ns (arrival time - required time) - Source: U1/comptY_reg[1]/C - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptY_reg[1]/D - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk_out1_clk_wiz_1_1 - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) - Data Path Delay: 0.371ns (logic 0.186ns (50.162%) route 0.185ns (49.838%)) - Logic Levels: 1 (LUT2=1) - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.706ns - Source Clock Delay (SCD): -0.474ns - Clock Pessimism Removal (CPR): -0.232ns - Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.313ns - Phase Error (PE): 0.000ns - Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.587 -0.474 U1/CLK - SLICE_X36Y51 FDRE r U1/comptY_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X36Y51 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptY_reg[1]/Q - net (fo=29, routed) 0.185 -0.148 U1/comptY_reg__0[1] - SLICE_X36Y51 LUT2 (Prop_lut2_I1_O) 0.045 -0.103 r U1/comptY[1]_i_1/O - net (fo=1, routed) 0.000 -0.103 U1/comptY[1]_i_1_n_0 - SLICE_X36Y51 FDRE r U1/comptY_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_clk_wiz_1_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.857 -0.706 U1/CLK - SLICE_X36Y51 FDRE r U1/comptY_reg[1]/C - clock pessimism 0.232 -0.474 - clock uncertainty 0.160 -0.313 - SLICE_X36Y51 FDRE (Hold_fdre_C_D) 0.091 -0.222 U1/comptY_reg[1] - ------------------------------------------------------------------- - required time 0.222 - arrival time -0.103 - ------------------------------------------------------------------- - slack 0.120 - -Slack (MET) : 0.127ns (arrival time - required time) - Source: U1/comptX_reg[0]/C - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptX_reg[1]/D - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk_out1_clk_wiz_1_1 - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) - Data Path Delay: 0.419ns (logic 0.207ns (49.431%) route 0.212ns (50.569%)) - Logic Levels: 1 (LUT2=1) - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.705ns - Source Clock Delay (SCD): -0.473ns - Clock Pessimism Removal (CPR): -0.232ns - Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.313ns - Phase Error (PE): 0.000ns - Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.588 -0.473 U1/CLK - SLICE_X42Y55 FDRE r U1/comptX_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X42Y55 FDRE (Prop_fdre_C_Q) 0.164 -0.309 r U1/comptX_reg[0]/Q - net (fo=25, routed) 0.212 -0.097 U1/comptX_reg__0[0] - SLICE_X42Y55 LUT2 (Prop_lut2_I0_O) 0.043 -0.054 r U1/comptX[1]_i_1/O - net (fo=1, routed) 0.000 -0.054 U1/plusOp[1] - SLICE_X42Y55 FDRE r U1/comptX_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_clk_wiz_1_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.858 -0.705 U1/CLK - SLICE_X42Y55 FDRE r U1/comptX_reg[1]/C - clock pessimism 0.232 -0.473 - clock uncertainty 0.160 -0.312 - SLICE_X42Y55 FDRE (Hold_fdre_C_D) 0.131 -0.181 U1/comptX_reg[1] - ------------------------------------------------------------------- - required time 0.181 - arrival time -0.054 - ------------------------------------------------------------------- - slack 0.127 + slack 0.106 Slack (MET) : 0.128ns (arrival time - required time) - Source: U1/comptX_reg[7]/C + Source: SYNC/comptX_reg[6]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptX_reg[9]/D - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk_out1_clk_wiz_1_1 - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) - Data Path Delay: 0.398ns (logic 0.186ns (46.766%) route 0.212ns (53.234%)) + Destination: SNAKE/cCaseX_reg[2]/D + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: sys_clk_pin + Path Type: Hold (Min at Slow Process Corner) + Requirement: 0.000ns (sys_clk_pin rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) + Data Path Delay: 4.568ns (logic 0.467ns (10.224%) route 4.101ns (89.776%)) Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.705ns - Source Clock Delay (SCD): -0.474ns - Clock Pessimism Removal (CPR): -0.248ns - Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: 3.842ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 5.332ns + Source Clock Delay (SCD): 1.490ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns - Phase Error (PE): 0.000ns + Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.587 -0.474 U1/CLK - SLICE_X41Y57 FDRE r U1/comptX_reg[7]/C + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.490 1.490 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.177 -1.687 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.599 -0.088 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 0.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.487 1.490 SYNC/clk_out1 + SLICE_X29Y21 FDRE r SYNC/comptX_reg[6]/C ------------------------------------------------------------------- ------------------- - SLICE_X41Y57 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptX_reg[7]/Q - net (fo=20, routed) 0.212 -0.121 U1/comptX_reg__0[7] - SLICE_X41Y56 LUT6 (Prop_lut6_I3_O) 0.045 -0.076 r U1/comptX[9]_i_1/O - net (fo=1, routed) 0.000 -0.076 U1/plusOp[9] - SLICE_X41Y56 FDRE r U1/comptX_reg[9]/D + SLICE_X29Y21 FDRE (Prop_fdre_C_Q) 0.367 1.857 r SYNC/comptX_reg[6]/Q + net (fo=13, routed) 1.123 2.980 SYNC/comptX_reg__0[6] + SLICE_X27Y20 LUT6 (Prop_lut6_I4_O) 0.100 3.080 r SYNC/cCaseX[2]_i_1/O + net (fo=55, routed) 2.978 6.058 SNAKE/Xi[2] + SLICE_X18Y20 FDRE r SNAKE/cCaseX_reg[2]/D ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) + (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.858 -0.705 U1/CLK - SLICE_X41Y56 FDRE r U1/comptX_reg[9]/C - clock pessimism 0.248 -0.457 - clock uncertainty 0.160 -0.296 - SLICE_X41Y56 FDRE (Hold_fdre_C_D) 0.092 -0.204 U1/comptX_reg[9] + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O + net (fo=1, routed) 2.076 3.567 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.664 5.332 SNAKE/H125MHz + SLICE_X18Y20 FDRE r SNAKE/cCaseX_reg[2]/C + clock pessimism 0.000 5.332 + clock uncertainty 0.406 5.738 + SLICE_X18Y20 FDRE (Hold_fdre_C_D) 0.192 5.930 SNAKE/cCaseX_reg[2] ------------------------------------------------------------------- - required time 0.204 - arrival time -0.076 + required time -5.930 + arrival time 6.058 ------------------------------------------------------------------- slack 0.128 -Slack (MET) : 0.137ns (arrival time - required time) - Source: U1/comptY_reg[6]/C +Slack (MET) : 0.159ns (arrival time - required time) + Source: SYNC/comptY_reg[9]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptY_reg[6]/D - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk_out1_clk_wiz_1_1 - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) - Data Path Delay: 0.402ns (logic 0.183ns (45.514%) route 0.219ns (54.486%)) - Logic Levels: 1 (LUT3=1) - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.706ns - Source Clock Delay (SCD): -0.474ns - Clock Pessimism Removal (CPR): -0.232ns - Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Destination: SNAKE/cCaseY_reg[2]/D + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: sys_clk_pin + Path Type: Hold (Min at Slow Process Corner) + Requirement: 0.000ns (sys_clk_pin rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) + Data Path Delay: 4.598ns (logic 0.467ns (10.156%) route 4.131ns (89.844%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 3.838ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 5.326ns + Source Clock Delay (SCD): 1.488ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns - Phase Error (PE): 0.000ns + Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.587 -0.474 U1/CLK - SLICE_X36Y50 FDRE r U1/comptY_reg[6]/C + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.490 1.490 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.177 -1.687 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.599 -0.088 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 0.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.485 1.488 SYNC/clk_out1 + SLICE_X19Y26 FDRE r SYNC/comptY_reg[9]/C ------------------------------------------------------------------- ------------------- - SLICE_X36Y50 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptY_reg[6]/Q - net (fo=21, routed) 0.219 -0.114 U1/comptY_reg__0[6] - SLICE_X36Y50 LUT3 (Prop_lut3_I2_O) 0.042 -0.072 r U1/comptY[6]_i_1/O - net (fo=1, routed) 0.000 -0.072 U1/plusOp__0[6] - SLICE_X36Y50 FDRE r U1/comptY_reg[6]/D + SLICE_X19Y26 FDRE (Prop_fdre_C_Q) 0.367 1.855 f SYNC/comptY_reg[9]/Q + net (fo=10, routed) 1.330 3.185 SYNC/comptY_reg__0[9] + SLICE_X25Y27 LUT6 (Prop_lut6_I5_O) 0.100 3.285 r SYNC/cCaseY[2]_i_1/O + net (fo=55, routed) 2.801 6.087 SNAKE/Yi[2] + SLICE_X21Y23 FDRE r SNAKE/cCaseY_reg[2]/D ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) + (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.857 -0.706 U1/CLK - SLICE_X36Y50 FDRE r U1/comptY_reg[6]/C - clock pessimism 0.232 -0.474 - clock uncertainty 0.160 -0.313 - SLICE_X36Y50 FDRE (Hold_fdre_C_D) 0.105 -0.208 U1/comptY_reg[6] + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O + net (fo=1, routed) 2.076 3.567 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.658 5.326 SNAKE/H125MHz + SLICE_X21Y23 FDRE r SNAKE/cCaseY_reg[2]/C + clock pessimism 0.000 5.326 + clock uncertainty 0.406 5.732 + SLICE_X21Y23 FDRE (Hold_fdre_C_D) 0.196 5.928 SNAKE/cCaseY_reg[2] ------------------------------------------------------------------- - required time 0.208 - arrival time -0.072 + required time -5.928 + arrival time 6.087 ------------------------------------------------------------------- - slack 0.137 + slack 0.159 -Slack (MET) : 0.138ns (arrival time - required time) - Source: U1/comptX_reg[7]/C +Slack (MET) : 0.219ns (arrival time - required time) + Source: SYNC/comptX_reg[8]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptX_reg[7]/D - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk_out1_clk_wiz_1_1 - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) - Data Path Delay: 0.390ns (logic 0.186ns (47.724%) route 0.204ns (52.276%)) - Logic Levels: 1 (LUT4=1) - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.706ns - Source Clock Delay (SCD): -0.474ns - Clock Pessimism Removal (CPR): -0.232ns - Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Destination: SNAKE/cCaseX_reg[5]/D + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: sys_clk_pin + Path Type: Hold (Min at Slow Process Corner) + Requirement: 0.000ns (sys_clk_pin rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) + Data Path Delay: 4.663ns (logic 0.467ns (10.015%) route 4.196ns (89.985%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 3.846ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 5.336ns + Source Clock Delay (SCD): 1.490ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns - Phase Error (PE): 0.000ns + Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.587 -0.474 U1/CLK - SLICE_X41Y57 FDRE r U1/comptX_reg[7]/C + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.490 1.490 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.177 -1.687 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.599 -0.088 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 0.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.487 1.490 SYNC/clk_out1 + SLICE_X26Y21 FDRE r SYNC/comptX_reg[8]/C ------------------------------------------------------------------- ------------------- - SLICE_X41Y57 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptX_reg[7]/Q - net (fo=20, routed) 0.204 -0.129 U1/comptX_reg__0[7] - SLICE_X41Y57 LUT4 (Prop_lut4_I3_O) 0.045 -0.084 r U1/comptX[7]_i_1/O - net (fo=1, routed) 0.000 -0.084 U1/plusOp[7] - SLICE_X41Y57 FDRE r U1/comptX_reg[7]/D + SLICE_X26Y21 FDRE (Prop_fdre_C_Q) 0.367 1.857 r SYNC/comptX_reg[8]/Q + net (fo=22, routed) 0.935 2.792 SYNC/comptX_reg__0[8] + SLICE_X30Y21 LUT5 (Prop_lut5_I4_O) 0.100 2.892 r SYNC/cCaseX[5]_i_2/O + net (fo=46, routed) 3.261 6.153 SNAKE/Xi[5] + SLICE_X18Y17 FDRE r SNAKE/cCaseX_reg[5]/D ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) + (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.857 -0.706 U1/CLK - SLICE_X41Y57 FDRE r U1/comptX_reg[7]/C - clock pessimism 0.232 -0.474 - clock uncertainty 0.160 -0.313 - SLICE_X41Y57 FDRE (Hold_fdre_C_D) 0.091 -0.222 U1/comptX_reg[7] + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O + net (fo=1, routed) 2.076 3.567 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.668 5.336 SNAKE/H125MHz + SLICE_X18Y17 FDRE r SNAKE/cCaseX_reg[5]/C + clock pessimism 0.000 5.336 + clock uncertainty 0.406 5.742 + SLICE_X18Y17 FDRE (Hold_fdre_C_D) 0.192 5.934 SNAKE/cCaseX_reg[5] ------------------------------------------------------------------- - required time 0.222 - arrival time -0.084 + required time -5.934 + arrival time 6.153 ------------------------------------------------------------------- - slack 0.138 + slack 0.219 -Slack (MET) : 0.140ns (arrival time - required time) - Source: U1/comptY_reg[0]/C +Slack (MET) : 0.223ns (arrival time - required time) + Source: SYNC/comptX_reg[8]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptY_reg[0]/D - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk_out1_clk_wiz_1_1 - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) - Data Path Delay: 0.421ns (logic 0.209ns (49.671%) route 0.212ns (50.329%)) + Destination: SNAKE/cCaseX_reg[3]/D + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: sys_clk_pin + Path Type: Hold (Min at Slow Process Corner) + Requirement: 0.000ns (sys_clk_pin rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) + Data Path Delay: 4.667ns (logic 0.467ns (10.007%) route 4.200ns (89.993%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 3.846ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 5.336ns + Source Clock Delay (SCD): 1.490ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.313ns + Phase Error (PE): 0.246ns + Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_1 rise edge) + 0.000 0.000 r + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.490 1.490 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.177 -1.687 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.599 -0.088 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 0.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.487 1.490 SYNC/clk_out1 + SLICE_X26Y21 FDRE r SYNC/comptX_reg[8]/C + ------------------------------------------------------------------- ------------------- + SLICE_X26Y21 FDRE (Prop_fdre_C_Q) 0.367 1.857 r SYNC/comptX_reg[8]/Q + net (fo=22, routed) 1.126 2.983 SYNC/comptX_reg__0[8] + SLICE_X27Y20 LUT5 (Prop_lut5_I1_O) 0.100 3.083 r SYNC/cCaseX[3]_i_1/O + net (fo=55, routed) 3.074 6.157 SNAKE/Xi[3] + SLICE_X29Y17 FDRE r SNAKE/cCaseX_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O + net (fo=1, routed) 2.076 3.567 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.668 5.336 SNAKE/H125MHz + SLICE_X29Y17 FDRE r SNAKE/cCaseX_reg[3]/C + clock pessimism 0.000 5.336 + clock uncertainty 0.406 5.742 + SLICE_X29Y17 FDRE (Hold_fdre_C_D) 0.192 5.934 SNAKE/cCaseX_reg[3] + ------------------------------------------------------------------- + required time -5.934 + arrival time 6.157 + ------------------------------------------------------------------- + slack 0.223 + +Slack (MET) : 0.239ns (arrival time - required time) + Source: SYNC/comptY_reg[8]/C + (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: SNAKE/cCaseY_reg[1]/D + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: sys_clk_pin + Path Type: Hold (Min at Slow Process Corner) + Requirement: 0.000ns (sys_clk_pin rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) + Data Path Delay: 4.663ns (logic 0.578ns (12.397%) route 4.085ns (87.603%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 3.838ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 5.326ns + Source Clock Delay (SCD): 1.488ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.313ns + Phase Error (PE): 0.246ns + Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_1 rise edge) + 0.000 0.000 r + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.490 1.490 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.177 -1.687 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.599 -0.088 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 0.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.485 1.488 SYNC/clk_out1 + SLICE_X19Y26 FDRE r SYNC/comptY_reg[8]/C + ------------------------------------------------------------------- ------------------- + SLICE_X19Y26 FDRE (Prop_fdre_C_Q) 0.337 1.825 r SYNC/comptY_reg[8]/Q + net (fo=10, routed) 1.069 2.895 SYNC/comptY_reg__0[8] + SLICE_X21Y26 LUT6 (Prop_lut6_I4_O) 0.241 3.136 r SYNC/cCaseY[1]_i_1/O + net (fo=55, routed) 3.015 6.151 SNAKE/Yi[1] + SLICE_X21Y23 FDRE r SNAKE/cCaseY_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O + net (fo=1, routed) 2.076 3.567 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.658 5.326 SNAKE/H125MHz + SLICE_X21Y23 FDRE r SNAKE/cCaseY_reg[1]/C + clock pessimism 0.000 5.326 + clock uncertainty 0.406 5.732 + SLICE_X21Y23 FDRE (Hold_fdre_C_D) 0.180 5.912 SNAKE/cCaseY_reg[1] + ------------------------------------------------------------------- + required time -5.912 + arrival time 6.151 + ------------------------------------------------------------------- + slack 0.239 + +Slack (MET) : 0.275ns (arrival time - required time) + Source: SYNC/comptY_reg[5]/C + (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: SNAKE/cCaseY_reg[4]/D + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: sys_clk_pin + Path Type: Hold (Min at Slow Process Corner) + Requirement: 0.000ns (sys_clk_pin rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) + Data Path Delay: 4.719ns (logic 0.518ns (10.976%) route 4.201ns (89.024%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 3.839ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 5.326ns + Source Clock Delay (SCD): 1.487ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.313ns + Phase Error (PE): 0.246ns + Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_1 rise edge) + 0.000 0.000 r + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.490 1.490 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.177 -1.687 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.599 -0.088 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 0.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.484 1.487 SYNC/clk_out1 + SLICE_X20Y26 FDRE r SYNC/comptY_reg[5]/C + ------------------------------------------------------------------- ------------------- + SLICE_X20Y26 FDRE (Prop_fdre_C_Q) 0.418 1.905 r SYNC/comptY_reg[5]/Q + net (fo=13, routed) 1.194 3.099 SYNC/comptY_reg__0[5] + SLICE_X23Y31 LUT6 (Prop_lut6_I3_O) 0.100 3.199 r SYNC/cCaseY[4]_i_1/O + net (fo=55, routed) 3.007 6.207 SNAKE/Yi[4] + SLICE_X21Y23 FDRE r SNAKE/cCaseY_reg[4]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O + net (fo=1, routed) 2.076 3.567 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.658 5.326 SNAKE/H125MHz + SLICE_X21Y23 FDRE r SNAKE/cCaseY_reg[4]/C + clock pessimism 0.000 5.326 + clock uncertainty 0.406 5.732 + SLICE_X21Y23 FDRE (Hold_fdre_C_D) 0.199 5.931 SNAKE/cCaseY_reg[4] + ------------------------------------------------------------------- + required time -5.931 + arrival time 6.207 + ------------------------------------------------------------------- + slack 0.275 + +Slack (MET) : 0.326ns (arrival time - required time) + Source: SYNC/comptY_reg[3]/C + (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: SNAKE/cCaseY_reg[0]/D + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: sys_clk_pin + Path Type: Hold (Min at Slow Process Corner) + Requirement: 0.000ns (sys_clk_pin rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) + Data Path Delay: 4.794ns (logic 0.467ns (9.742%) route 4.327ns (90.258%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 3.839ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 5.326ns + Source Clock Delay (SCD): 1.487ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.313ns + Phase Error (PE): 0.246ns + Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_1 rise edge) + 0.000 0.000 r + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.490 1.490 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.177 -1.687 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.599 -0.088 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 0.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.484 1.487 SYNC/clk_out1 + SLICE_X21Y26 FDRE r SYNC/comptY_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X21Y26 FDRE (Prop_fdre_C_Q) 0.367 1.854 r SYNC/comptY_reg[3]/Q + net (fo=8, routed) 1.209 3.064 SYNC/comptY_reg__0[3] + SLICE_X20Y27 LUT6 (Prop_lut6_I4_O) 0.100 3.164 r SYNC/cCaseY[0]_i_1/O + net (fo=55, routed) 3.117 6.281 SNAKE/Yi[0] + SLICE_X20Y23 FDRE r SNAKE/cCaseY_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O + net (fo=1, routed) 2.076 3.567 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.658 5.326 SNAKE/H125MHz + SLICE_X20Y23 FDRE r SNAKE/cCaseY_reg[0]/C + clock pessimism 0.000 5.326 + clock uncertainty 0.406 5.732 + SLICE_X20Y23 FDRE (Hold_fdre_C_D) 0.223 5.955 SNAKE/cCaseY_reg[0] + ------------------------------------------------------------------- + required time -5.955 + arrival time 6.281 + ------------------------------------------------------------------- + slack 0.326 + +Slack (MET) : 0.337ns (arrival time - required time) + Source: SYNC/comptX_reg[8]/C + (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: SNAKE/cCaseX_reg[4]/D + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: sys_clk_pin + Path Type: Hold (Min at Slow Process Corner) + Requirement: 0.000ns (sys_clk_pin rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) + Data Path Delay: 4.777ns (logic 0.467ns (9.775%) route 4.310ns (90.225%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 3.843ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 5.333ns + Source Clock Delay (SCD): 1.490ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.313ns + Phase Error (PE): 0.246ns + Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_1 rise edge) + 0.000 0.000 r + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.490 1.490 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.177 -1.687 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.599 -0.088 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 0.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.487 1.490 SYNC/clk_out1 + SLICE_X26Y21 FDRE r SYNC/comptX_reg[8]/C + ------------------------------------------------------------------- ------------------- + SLICE_X26Y21 FDRE (Prop_fdre_C_Q) 0.367 1.857 r SYNC/comptX_reg[8]/Q + net (fo=22, routed) 1.138 2.995 SYNC/comptX_reg__0[8] + SLICE_X30Y25 LUT5 (Prop_lut5_I3_O) 0.100 3.095 r SYNC/cCaseX[4]_i_1/O + net (fo=55, routed) 3.172 6.268 SNAKE/Xi[4] + SLICE_X18Y19 FDRE r SNAKE/cCaseX_reg[4]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O + net (fo=1, routed) 2.076 3.567 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.665 5.333 SNAKE/H125MHz + SLICE_X18Y19 FDRE r SNAKE/cCaseX_reg[4]/C + clock pessimism 0.000 5.333 + clock uncertainty 0.406 5.739 + SLICE_X18Y19 FDRE (Hold_fdre_C_D) 0.192 5.931 SNAKE/cCaseX_reg[4] + ------------------------------------------------------------------- + required time -5.931 + arrival time 6.268 + ------------------------------------------------------------------- + slack 0.337 + + + + + +--------------------------------------------------------------------------------------------------- +Path Group: **async_default** +From Clock: clk_out1_clk_wiz_1 + To Clock: clk_out1_clk_wiz_1 + +Setup : 0 Failing Endpoints, Worst Slack 34.529ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 1.220ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 34.529ns (required time - arrival time) + Source: UPD_CLK_DIV/temp_reg[2]/C + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: UPD_CLK_DIV/temp_reg[0]/CLR + (recovery check against rising-edge clock clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) + Data Path Delay: 4.896ns (logic 1.831ns (37.397%) route 3.065ns (62.603%)) + Logic Levels: 5 (CARRY4=3 LUT2=1 LUT3=1) + Clock Path Skew: -0.010ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.561ns = ( 41.561 - 40.000 ) + Source Clock Delay (SCD): 1.737ns + Clock Pessimism Removal (CPR): 0.166ns + Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.313ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_1 rise edge) + 0.000 0.000 r + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.734 1.737 UPD_CLK_DIV/clk_out1 + SLICE_X40Y67 FDCE r UPD_CLK_DIV/temp_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X40Y67 FDCE (Prop_fdce_C_Q) 0.456 2.193 f UPD_CLK_DIV/temp_reg[2]/Q + net (fo=4, routed) 1.200 3.393 UPD_CLK_DIV/temp_reg[2] + SLICE_X42Y69 LUT3 (Prop_lut3_I0_O) 0.124 3.517 r UPD_CLK_DIV/temp[0]_i_14/O + net (fo=1, routed) 0.000 3.517 UPD_CLK_DIV/temp[0]_i_14_n_0 + SLICE_X42Y69 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 4.030 r UPD_CLK_DIV/temp_reg[0]_i_6/CO[3] + net (fo=1, routed) 0.000 4.030 UPD_CLK_DIV/temp_reg[0]_i_6_n_0 + SLICE_X42Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 4.147 r UPD_CLK_DIV/temp_reg[0]_i_5/CO[3] + net (fo=1, routed) 0.000 4.147 UPD_CLK_DIV/temp_reg[0]_i_5_n_0 + SLICE_X42Y71 CARRY4 (Prop_carry4_CI_CO[0]) + 0.254 4.401 f UPD_CLK_DIV/temp_reg[0]_i_4/CO[0] + net (fo=1, routed) 0.685 5.086 UPD_CLK_DIV/temp_reg[0]_i_4_n_3 + SLICE_X43Y71 LUT2 (Prop_lut2_I0_O) 0.367 5.453 f UPD_CLK_DIV/temp[0]_i_2/O + net (fo=25, routed) 1.180 6.633 UPD_CLK_DIV/temp[0]_i_2_n_0 + SLICE_X40Y67 FDCE f UPD_CLK_DIV/temp_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_1 rise edge) + 40.000 40.000 r + BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.558 41.561 UPD_CLK_DIV/clk_out1 + SLICE_X40Y67 FDCE r UPD_CLK_DIV/temp_reg[0]/C + clock pessimism 0.166 41.727 + clock uncertainty -0.160 41.567 + SLICE_X40Y67 FDCE (Recov_fdce_C_CLR) -0.405 41.162 UPD_CLK_DIV/temp_reg[0] + ------------------------------------------------------------------- + required time 41.162 + arrival time -6.633 + ------------------------------------------------------------------- + slack 34.529 + +Slack (MET) : 34.529ns (required time - arrival time) + Source: UPD_CLK_DIV/temp_reg[2]/C + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: UPD_CLK_DIV/temp_reg[1]/CLR + (recovery check against rising-edge clock clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) + Data Path Delay: 4.896ns (logic 1.831ns (37.397%) route 3.065ns (62.603%)) + Logic Levels: 5 (CARRY4=3 LUT2=1 LUT3=1) + Clock Path Skew: -0.010ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.561ns = ( 41.561 - 40.000 ) + Source Clock Delay (SCD): 1.737ns + Clock Pessimism Removal (CPR): 0.166ns + Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.313ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_1 rise edge) + 0.000 0.000 r + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.734 1.737 UPD_CLK_DIV/clk_out1 + SLICE_X40Y67 FDCE r UPD_CLK_DIV/temp_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X40Y67 FDCE (Prop_fdce_C_Q) 0.456 2.193 f UPD_CLK_DIV/temp_reg[2]/Q + net (fo=4, routed) 1.200 3.393 UPD_CLK_DIV/temp_reg[2] + SLICE_X42Y69 LUT3 (Prop_lut3_I0_O) 0.124 3.517 r UPD_CLK_DIV/temp[0]_i_14/O + net (fo=1, routed) 0.000 3.517 UPD_CLK_DIV/temp[0]_i_14_n_0 + SLICE_X42Y69 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 4.030 r UPD_CLK_DIV/temp_reg[0]_i_6/CO[3] + net (fo=1, routed) 0.000 4.030 UPD_CLK_DIV/temp_reg[0]_i_6_n_0 + SLICE_X42Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 4.147 r UPD_CLK_DIV/temp_reg[0]_i_5/CO[3] + net (fo=1, routed) 0.000 4.147 UPD_CLK_DIV/temp_reg[0]_i_5_n_0 + SLICE_X42Y71 CARRY4 (Prop_carry4_CI_CO[0]) + 0.254 4.401 f UPD_CLK_DIV/temp_reg[0]_i_4/CO[0] + net (fo=1, routed) 0.685 5.086 UPD_CLK_DIV/temp_reg[0]_i_4_n_3 + SLICE_X43Y71 LUT2 (Prop_lut2_I0_O) 0.367 5.453 f UPD_CLK_DIV/temp[0]_i_2/O + net (fo=25, routed) 1.180 6.633 UPD_CLK_DIV/temp[0]_i_2_n_0 + SLICE_X40Y67 FDCE f UPD_CLK_DIV/temp_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_1 rise edge) + 40.000 40.000 r + BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.558 41.561 UPD_CLK_DIV/clk_out1 + SLICE_X40Y67 FDCE r UPD_CLK_DIV/temp_reg[1]/C + clock pessimism 0.166 41.727 + clock uncertainty -0.160 41.567 + SLICE_X40Y67 FDCE (Recov_fdce_C_CLR) -0.405 41.162 UPD_CLK_DIV/temp_reg[1] + ------------------------------------------------------------------- + required time 41.162 + arrival time -6.633 + ------------------------------------------------------------------- + slack 34.529 + +Slack (MET) : 34.529ns (required time - arrival time) + Source: UPD_CLK_DIV/temp_reg[2]/C + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: UPD_CLK_DIV/temp_reg[2]/CLR + (recovery check against rising-edge clock clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) + Data Path Delay: 4.896ns (logic 1.831ns (37.397%) route 3.065ns (62.603%)) + Logic Levels: 5 (CARRY4=3 LUT2=1 LUT3=1) + Clock Path Skew: -0.010ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.561ns = ( 41.561 - 40.000 ) + Source Clock Delay (SCD): 1.737ns + Clock Pessimism Removal (CPR): 0.166ns + Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.313ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_1 rise edge) + 0.000 0.000 r + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.734 1.737 UPD_CLK_DIV/clk_out1 + SLICE_X40Y67 FDCE r UPD_CLK_DIV/temp_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X40Y67 FDCE (Prop_fdce_C_Q) 0.456 2.193 f UPD_CLK_DIV/temp_reg[2]/Q + net (fo=4, routed) 1.200 3.393 UPD_CLK_DIV/temp_reg[2] + SLICE_X42Y69 LUT3 (Prop_lut3_I0_O) 0.124 3.517 r UPD_CLK_DIV/temp[0]_i_14/O + net (fo=1, routed) 0.000 3.517 UPD_CLK_DIV/temp[0]_i_14_n_0 + SLICE_X42Y69 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 4.030 r UPD_CLK_DIV/temp_reg[0]_i_6/CO[3] + net (fo=1, routed) 0.000 4.030 UPD_CLK_DIV/temp_reg[0]_i_6_n_0 + SLICE_X42Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 4.147 r UPD_CLK_DIV/temp_reg[0]_i_5/CO[3] + net (fo=1, routed) 0.000 4.147 UPD_CLK_DIV/temp_reg[0]_i_5_n_0 + SLICE_X42Y71 CARRY4 (Prop_carry4_CI_CO[0]) + 0.254 4.401 f UPD_CLK_DIV/temp_reg[0]_i_4/CO[0] + net (fo=1, routed) 0.685 5.086 UPD_CLK_DIV/temp_reg[0]_i_4_n_3 + SLICE_X43Y71 LUT2 (Prop_lut2_I0_O) 0.367 5.453 f UPD_CLK_DIV/temp[0]_i_2/O + net (fo=25, routed) 1.180 6.633 UPD_CLK_DIV/temp[0]_i_2_n_0 + SLICE_X40Y67 FDCE f UPD_CLK_DIV/temp_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_1 rise edge) + 40.000 40.000 r + BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.558 41.561 UPD_CLK_DIV/clk_out1 + SLICE_X40Y67 FDCE r UPD_CLK_DIV/temp_reg[2]/C + clock pessimism 0.166 41.727 + clock uncertainty -0.160 41.567 + SLICE_X40Y67 FDCE (Recov_fdce_C_CLR) -0.405 41.162 UPD_CLK_DIV/temp_reg[2] + ------------------------------------------------------------------- + required time 41.162 + arrival time -6.633 + ------------------------------------------------------------------- + slack 34.529 + +Slack (MET) : 34.529ns (required time - arrival time) + Source: UPD_CLK_DIV/temp_reg[2]/C + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: UPD_CLK_DIV/temp_reg[3]/CLR + (recovery check against rising-edge clock clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) + Data Path Delay: 4.896ns (logic 1.831ns (37.397%) route 3.065ns (62.603%)) + Logic Levels: 5 (CARRY4=3 LUT2=1 LUT3=1) + Clock Path Skew: -0.010ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.561ns = ( 41.561 - 40.000 ) + Source Clock Delay (SCD): 1.737ns + Clock Pessimism Removal (CPR): 0.166ns + Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.313ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_1 rise edge) + 0.000 0.000 r + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.734 1.737 UPD_CLK_DIV/clk_out1 + SLICE_X40Y67 FDCE r UPD_CLK_DIV/temp_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X40Y67 FDCE (Prop_fdce_C_Q) 0.456 2.193 f UPD_CLK_DIV/temp_reg[2]/Q + net (fo=4, routed) 1.200 3.393 UPD_CLK_DIV/temp_reg[2] + SLICE_X42Y69 LUT3 (Prop_lut3_I0_O) 0.124 3.517 r UPD_CLK_DIV/temp[0]_i_14/O + net (fo=1, routed) 0.000 3.517 UPD_CLK_DIV/temp[0]_i_14_n_0 + SLICE_X42Y69 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 4.030 r UPD_CLK_DIV/temp_reg[0]_i_6/CO[3] + net (fo=1, routed) 0.000 4.030 UPD_CLK_DIV/temp_reg[0]_i_6_n_0 + SLICE_X42Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 4.147 r UPD_CLK_DIV/temp_reg[0]_i_5/CO[3] + net (fo=1, routed) 0.000 4.147 UPD_CLK_DIV/temp_reg[0]_i_5_n_0 + SLICE_X42Y71 CARRY4 (Prop_carry4_CI_CO[0]) + 0.254 4.401 f UPD_CLK_DIV/temp_reg[0]_i_4/CO[0] + net (fo=1, routed) 0.685 5.086 UPD_CLK_DIV/temp_reg[0]_i_4_n_3 + SLICE_X43Y71 LUT2 (Prop_lut2_I0_O) 0.367 5.453 f UPD_CLK_DIV/temp[0]_i_2/O + net (fo=25, routed) 1.180 6.633 UPD_CLK_DIV/temp[0]_i_2_n_0 + SLICE_X40Y67 FDCE f UPD_CLK_DIV/temp_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_1 rise edge) + 40.000 40.000 r + BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.558 41.561 UPD_CLK_DIV/clk_out1 + SLICE_X40Y67 FDCE r UPD_CLK_DIV/temp_reg[3]/C + clock pessimism 0.166 41.727 + clock uncertainty -0.160 41.567 + SLICE_X40Y67 FDCE (Recov_fdce_C_CLR) -0.405 41.162 UPD_CLK_DIV/temp_reg[3] + ------------------------------------------------------------------- + required time 41.162 + arrival time -6.633 + ------------------------------------------------------------------- + slack 34.529 + +Slack (MET) : 34.595ns (required time - arrival time) + Source: UPD_CLK_DIV/temp_reg[2]/C + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: UPD_CLK_DIV/temp_reg[4]/CLR + (recovery check against rising-edge clock clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) + Data Path Delay: 4.804ns (logic 1.831ns (38.114%) route 2.973ns (61.886%)) + Logic Levels: 5 (CARRY4=3 LUT2=1 LUT3=1) + Clock Path Skew: -0.036ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.559ns = ( 41.559 - 40.000 ) + Source Clock Delay (SCD): 1.737ns + Clock Pessimism Removal (CPR): 0.142ns + Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.313ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_1 rise edge) + 0.000 0.000 r + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.734 1.737 UPD_CLK_DIV/clk_out1 + SLICE_X40Y67 FDCE r UPD_CLK_DIV/temp_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X40Y67 FDCE (Prop_fdce_C_Q) 0.456 2.193 f UPD_CLK_DIV/temp_reg[2]/Q + net (fo=4, routed) 1.200 3.393 UPD_CLK_DIV/temp_reg[2] + SLICE_X42Y69 LUT3 (Prop_lut3_I0_O) 0.124 3.517 r UPD_CLK_DIV/temp[0]_i_14/O + net (fo=1, routed) 0.000 3.517 UPD_CLK_DIV/temp[0]_i_14_n_0 + SLICE_X42Y69 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 4.030 r UPD_CLK_DIV/temp_reg[0]_i_6/CO[3] + net (fo=1, routed) 0.000 4.030 UPD_CLK_DIV/temp_reg[0]_i_6_n_0 + SLICE_X42Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 4.147 r UPD_CLK_DIV/temp_reg[0]_i_5/CO[3] + net (fo=1, routed) 0.000 4.147 UPD_CLK_DIV/temp_reg[0]_i_5_n_0 + SLICE_X42Y71 CARRY4 (Prop_carry4_CI_CO[0]) + 0.254 4.401 f UPD_CLK_DIV/temp_reg[0]_i_4/CO[0] + net (fo=1, routed) 0.685 5.086 UPD_CLK_DIV/temp_reg[0]_i_4_n_3 + SLICE_X43Y71 LUT2 (Prop_lut2_I0_O) 0.367 5.453 f UPD_CLK_DIV/temp[0]_i_2/O + net (fo=25, routed) 1.088 6.541 UPD_CLK_DIV/temp[0]_i_2_n_0 + SLICE_X40Y68 FDCE f UPD_CLK_DIV/temp_reg[4]/CLR + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_1 rise edge) + 40.000 40.000 r + BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.556 41.559 UPD_CLK_DIV/clk_out1 + SLICE_X40Y68 FDCE r UPD_CLK_DIV/temp_reg[4]/C + clock pessimism 0.142 41.701 + clock uncertainty -0.160 41.541 + SLICE_X40Y68 FDCE (Recov_fdce_C_CLR) -0.405 41.136 UPD_CLK_DIV/temp_reg[4] + ------------------------------------------------------------------- + required time 41.136 + arrival time -6.541 + ------------------------------------------------------------------- + slack 34.595 + +Slack (MET) : 34.595ns (required time - arrival time) + Source: UPD_CLK_DIV/temp_reg[2]/C + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: UPD_CLK_DIV/temp_reg[5]/CLR + (recovery check against rising-edge clock clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) + Data Path Delay: 4.804ns (logic 1.831ns (38.114%) route 2.973ns (61.886%)) + Logic Levels: 5 (CARRY4=3 LUT2=1 LUT3=1) + Clock Path Skew: -0.036ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.559ns = ( 41.559 - 40.000 ) + Source Clock Delay (SCD): 1.737ns + Clock Pessimism Removal (CPR): 0.142ns + Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.313ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_1 rise edge) + 0.000 0.000 r + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.734 1.737 UPD_CLK_DIV/clk_out1 + SLICE_X40Y67 FDCE r UPD_CLK_DIV/temp_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X40Y67 FDCE (Prop_fdce_C_Q) 0.456 2.193 f UPD_CLK_DIV/temp_reg[2]/Q + net (fo=4, routed) 1.200 3.393 UPD_CLK_DIV/temp_reg[2] + SLICE_X42Y69 LUT3 (Prop_lut3_I0_O) 0.124 3.517 r UPD_CLK_DIV/temp[0]_i_14/O + net (fo=1, routed) 0.000 3.517 UPD_CLK_DIV/temp[0]_i_14_n_0 + SLICE_X42Y69 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 4.030 r UPD_CLK_DIV/temp_reg[0]_i_6/CO[3] + net (fo=1, routed) 0.000 4.030 UPD_CLK_DIV/temp_reg[0]_i_6_n_0 + SLICE_X42Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 4.147 r UPD_CLK_DIV/temp_reg[0]_i_5/CO[3] + net (fo=1, routed) 0.000 4.147 UPD_CLK_DIV/temp_reg[0]_i_5_n_0 + SLICE_X42Y71 CARRY4 (Prop_carry4_CI_CO[0]) + 0.254 4.401 f UPD_CLK_DIV/temp_reg[0]_i_4/CO[0] + net (fo=1, routed) 0.685 5.086 UPD_CLK_DIV/temp_reg[0]_i_4_n_3 + SLICE_X43Y71 LUT2 (Prop_lut2_I0_O) 0.367 5.453 f UPD_CLK_DIV/temp[0]_i_2/O + net (fo=25, routed) 1.088 6.541 UPD_CLK_DIV/temp[0]_i_2_n_0 + SLICE_X40Y68 FDCE f UPD_CLK_DIV/temp_reg[5]/CLR + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_1 rise edge) + 40.000 40.000 r + BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.556 41.559 UPD_CLK_DIV/clk_out1 + SLICE_X40Y68 FDCE r UPD_CLK_DIV/temp_reg[5]/C + clock pessimism 0.142 41.701 + clock uncertainty -0.160 41.541 + SLICE_X40Y68 FDCE (Recov_fdce_C_CLR) -0.405 41.136 UPD_CLK_DIV/temp_reg[5] + ------------------------------------------------------------------- + required time 41.136 + arrival time -6.541 + ------------------------------------------------------------------- + slack 34.595 + +Slack (MET) : 34.595ns (required time - arrival time) + Source: UPD_CLK_DIV/temp_reg[2]/C + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: UPD_CLK_DIV/temp_reg[6]/CLR + (recovery check against rising-edge clock clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) + Data Path Delay: 4.804ns (logic 1.831ns (38.114%) route 2.973ns (61.886%)) + Logic Levels: 5 (CARRY4=3 LUT2=1 LUT3=1) + Clock Path Skew: -0.036ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.559ns = ( 41.559 - 40.000 ) + Source Clock Delay (SCD): 1.737ns + Clock Pessimism Removal (CPR): 0.142ns + Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.313ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_1 rise edge) + 0.000 0.000 r + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.734 1.737 UPD_CLK_DIV/clk_out1 + SLICE_X40Y67 FDCE r UPD_CLK_DIV/temp_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X40Y67 FDCE (Prop_fdce_C_Q) 0.456 2.193 f UPD_CLK_DIV/temp_reg[2]/Q + net (fo=4, routed) 1.200 3.393 UPD_CLK_DIV/temp_reg[2] + SLICE_X42Y69 LUT3 (Prop_lut3_I0_O) 0.124 3.517 r UPD_CLK_DIV/temp[0]_i_14/O + net (fo=1, routed) 0.000 3.517 UPD_CLK_DIV/temp[0]_i_14_n_0 + SLICE_X42Y69 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 4.030 r UPD_CLK_DIV/temp_reg[0]_i_6/CO[3] + net (fo=1, routed) 0.000 4.030 UPD_CLK_DIV/temp_reg[0]_i_6_n_0 + SLICE_X42Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 4.147 r UPD_CLK_DIV/temp_reg[0]_i_5/CO[3] + net (fo=1, routed) 0.000 4.147 UPD_CLK_DIV/temp_reg[0]_i_5_n_0 + SLICE_X42Y71 CARRY4 (Prop_carry4_CI_CO[0]) + 0.254 4.401 f UPD_CLK_DIV/temp_reg[0]_i_4/CO[0] + net (fo=1, routed) 0.685 5.086 UPD_CLK_DIV/temp_reg[0]_i_4_n_3 + SLICE_X43Y71 LUT2 (Prop_lut2_I0_O) 0.367 5.453 f UPD_CLK_DIV/temp[0]_i_2/O + net (fo=25, routed) 1.088 6.541 UPD_CLK_DIV/temp[0]_i_2_n_0 + SLICE_X40Y68 FDCE f UPD_CLK_DIV/temp_reg[6]/CLR + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_1 rise edge) + 40.000 40.000 r + BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.556 41.559 UPD_CLK_DIV/clk_out1 + SLICE_X40Y68 FDCE r UPD_CLK_DIV/temp_reg[6]/C + clock pessimism 0.142 41.701 + clock uncertainty -0.160 41.541 + SLICE_X40Y68 FDCE (Recov_fdce_C_CLR) -0.405 41.136 UPD_CLK_DIV/temp_reg[6] + ------------------------------------------------------------------- + required time 41.136 + arrival time -6.541 + ------------------------------------------------------------------- + slack 34.595 + +Slack (MET) : 34.595ns (required time - arrival time) + Source: UPD_CLK_DIV/temp_reg[2]/C + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: UPD_CLK_DIV/temp_reg[7]/CLR + (recovery check against rising-edge clock clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) + Data Path Delay: 4.804ns (logic 1.831ns (38.114%) route 2.973ns (61.886%)) + Logic Levels: 5 (CARRY4=3 LUT2=1 LUT3=1) + Clock Path Skew: -0.036ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.559ns = ( 41.559 - 40.000 ) + Source Clock Delay (SCD): 1.737ns + Clock Pessimism Removal (CPR): 0.142ns + Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.313ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_1 rise edge) + 0.000 0.000 r + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.734 1.737 UPD_CLK_DIV/clk_out1 + SLICE_X40Y67 FDCE r UPD_CLK_DIV/temp_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X40Y67 FDCE (Prop_fdce_C_Q) 0.456 2.193 f UPD_CLK_DIV/temp_reg[2]/Q + net (fo=4, routed) 1.200 3.393 UPD_CLK_DIV/temp_reg[2] + SLICE_X42Y69 LUT3 (Prop_lut3_I0_O) 0.124 3.517 r UPD_CLK_DIV/temp[0]_i_14/O + net (fo=1, routed) 0.000 3.517 UPD_CLK_DIV/temp[0]_i_14_n_0 + SLICE_X42Y69 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 4.030 r UPD_CLK_DIV/temp_reg[0]_i_6/CO[3] + net (fo=1, routed) 0.000 4.030 UPD_CLK_DIV/temp_reg[0]_i_6_n_0 + SLICE_X42Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 4.147 r UPD_CLK_DIV/temp_reg[0]_i_5/CO[3] + net (fo=1, routed) 0.000 4.147 UPD_CLK_DIV/temp_reg[0]_i_5_n_0 + SLICE_X42Y71 CARRY4 (Prop_carry4_CI_CO[0]) + 0.254 4.401 f UPD_CLK_DIV/temp_reg[0]_i_4/CO[0] + net (fo=1, routed) 0.685 5.086 UPD_CLK_DIV/temp_reg[0]_i_4_n_3 + SLICE_X43Y71 LUT2 (Prop_lut2_I0_O) 0.367 5.453 f UPD_CLK_DIV/temp[0]_i_2/O + net (fo=25, routed) 1.088 6.541 UPD_CLK_DIV/temp[0]_i_2_n_0 + SLICE_X40Y68 FDCE f UPD_CLK_DIV/temp_reg[7]/CLR + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_1 rise edge) + 40.000 40.000 r + BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.556 41.559 UPD_CLK_DIV/clk_out1 + SLICE_X40Y68 FDCE r UPD_CLK_DIV/temp_reg[7]/C + clock pessimism 0.142 41.701 + clock uncertainty -0.160 41.541 + SLICE_X40Y68 FDCE (Recov_fdce_C_CLR) -0.405 41.136 UPD_CLK_DIV/temp_reg[7] + ------------------------------------------------------------------- + required time 41.136 + arrival time -6.541 + ------------------------------------------------------------------- + slack 34.595 + +Slack (MET) : 34.643ns (required time - arrival time) + Source: UPD_CLK_DIV/temp_reg[2]/C + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: UPD_CLK_DIV/temp_reg[10]/CLR + (recovery check against rising-edge clock clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) + Data Path Delay: 4.755ns (logic 1.831ns (38.506%) route 2.924ns (61.493%)) + Logic Levels: 5 (CARRY4=3 LUT2=1 LUT3=1) + Clock Path Skew: -0.037ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.558ns = ( 41.558 - 40.000 ) + Source Clock Delay (SCD): 1.737ns + Clock Pessimism Removal (CPR): 0.142ns + Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.313ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_1 rise edge) + 0.000 0.000 r + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.734 1.737 UPD_CLK_DIV/clk_out1 + SLICE_X40Y67 FDCE r UPD_CLK_DIV/temp_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X40Y67 FDCE (Prop_fdce_C_Q) 0.456 2.193 f UPD_CLK_DIV/temp_reg[2]/Q + net (fo=4, routed) 1.200 3.393 UPD_CLK_DIV/temp_reg[2] + SLICE_X42Y69 LUT3 (Prop_lut3_I0_O) 0.124 3.517 r UPD_CLK_DIV/temp[0]_i_14/O + net (fo=1, routed) 0.000 3.517 UPD_CLK_DIV/temp[0]_i_14_n_0 + SLICE_X42Y69 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 4.030 r UPD_CLK_DIV/temp_reg[0]_i_6/CO[3] + net (fo=1, routed) 0.000 4.030 UPD_CLK_DIV/temp_reg[0]_i_6_n_0 + SLICE_X42Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 4.147 r UPD_CLK_DIV/temp_reg[0]_i_5/CO[3] + net (fo=1, routed) 0.000 4.147 UPD_CLK_DIV/temp_reg[0]_i_5_n_0 + SLICE_X42Y71 CARRY4 (Prop_carry4_CI_CO[0]) + 0.254 4.401 f UPD_CLK_DIV/temp_reg[0]_i_4/CO[0] + net (fo=1, routed) 0.685 5.086 UPD_CLK_DIV/temp_reg[0]_i_4_n_3 + SLICE_X43Y71 LUT2 (Prop_lut2_I0_O) 0.367 5.453 f UPD_CLK_DIV/temp[0]_i_2/O + net (fo=25, routed) 1.039 6.492 UPD_CLK_DIV/temp[0]_i_2_n_0 + SLICE_X40Y69 FDCE f UPD_CLK_DIV/temp_reg[10]/CLR + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_1 rise edge) + 40.000 40.000 r + BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.555 41.558 UPD_CLK_DIV/clk_out1 + SLICE_X40Y69 FDCE r UPD_CLK_DIV/temp_reg[10]/C + clock pessimism 0.142 41.700 + clock uncertainty -0.160 41.540 + SLICE_X40Y69 FDCE (Recov_fdce_C_CLR) -0.405 41.135 UPD_CLK_DIV/temp_reg[10] + ------------------------------------------------------------------- + required time 41.135 + arrival time -6.492 + ------------------------------------------------------------------- + slack 34.643 + +Slack (MET) : 34.643ns (required time - arrival time) + Source: UPD_CLK_DIV/temp_reg[2]/C + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: UPD_CLK_DIV/temp_reg[11]/CLR + (recovery check against rising-edge clock clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) + Data Path Delay: 4.755ns (logic 1.831ns (38.506%) route 2.924ns (61.493%)) + Logic Levels: 5 (CARRY4=3 LUT2=1 LUT3=1) + Clock Path Skew: -0.037ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.558ns = ( 41.558 - 40.000 ) + Source Clock Delay (SCD): 1.737ns + Clock Pessimism Removal (CPR): 0.142ns + Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.313ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_1 rise edge) + 0.000 0.000 r + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.734 1.737 UPD_CLK_DIV/clk_out1 + SLICE_X40Y67 FDCE r UPD_CLK_DIV/temp_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X40Y67 FDCE (Prop_fdce_C_Q) 0.456 2.193 f UPD_CLK_DIV/temp_reg[2]/Q + net (fo=4, routed) 1.200 3.393 UPD_CLK_DIV/temp_reg[2] + SLICE_X42Y69 LUT3 (Prop_lut3_I0_O) 0.124 3.517 r UPD_CLK_DIV/temp[0]_i_14/O + net (fo=1, routed) 0.000 3.517 UPD_CLK_DIV/temp[0]_i_14_n_0 + SLICE_X42Y69 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 4.030 r UPD_CLK_DIV/temp_reg[0]_i_6/CO[3] + net (fo=1, routed) 0.000 4.030 UPD_CLK_DIV/temp_reg[0]_i_6_n_0 + SLICE_X42Y70 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 4.147 r UPD_CLK_DIV/temp_reg[0]_i_5/CO[3] + net (fo=1, routed) 0.000 4.147 UPD_CLK_DIV/temp_reg[0]_i_5_n_0 + SLICE_X42Y71 CARRY4 (Prop_carry4_CI_CO[0]) + 0.254 4.401 f UPD_CLK_DIV/temp_reg[0]_i_4/CO[0] + net (fo=1, routed) 0.685 5.086 UPD_CLK_DIV/temp_reg[0]_i_4_n_3 + SLICE_X43Y71 LUT2 (Prop_lut2_I0_O) 0.367 5.453 f UPD_CLK_DIV/temp[0]_i_2/O + net (fo=25, routed) 1.039 6.492 UPD_CLK_DIV/temp[0]_i_2_n_0 + SLICE_X40Y69 FDCE f UPD_CLK_DIV/temp_reg[11]/CLR + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_1 rise edge) + 40.000 40.000 r + BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.555 41.558 UPD_CLK_DIV/clk_out1 + SLICE_X40Y69 FDCE r UPD_CLK_DIV/temp_reg[11]/C + clock pessimism 0.142 41.700 + clock uncertainty -0.160 41.540 + SLICE_X40Y69 FDCE (Recov_fdce_C_CLR) -0.405 41.135 UPD_CLK_DIV/temp_reg[11] + ------------------------------------------------------------------- + required time 41.135 + arrival time -6.492 + ------------------------------------------------------------------- + slack 34.643 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 1.220ns (arrival time - required time) + Source: UPD_CLK_DIV/temp_reg[24]/C + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: UPD_CLK_DIV/temp_reg[16]/CLR + (removal check against rising-edge clock clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) + Data Path Delay: 1.144ns (logic 0.407ns (35.576%) route 0.737ns (64.424%)) + Logic Levels: 2 (CARRY4=1 LUT2=1) + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.850ns + Source Clock Delay (SCD): 0.580ns + Clock Pessimism Removal (CPR): 0.254ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_1 rise edge) + 0.000 0.000 r + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.548 0.548 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.053 -0.506 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.482 -0.024 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.002 r U0/inst/clkout1_buf/O + net (fo=60, routed) 0.578 0.580 UPD_CLK_DIV/clk_out1 + SLICE_X40Y73 FDCE r UPD_CLK_DIV/temp_reg[24]/C + ------------------------------------------------------------------- ------------------- + SLICE_X40Y73 FDCE (Prop_fdce_C_Q) 0.141 0.721 r UPD_CLK_DIV/temp_reg[24]/Q + net (fo=4, routed) 0.245 0.966 UPD_CLK_DIV/temp_reg[24] + SLICE_X42Y71 CARRY4 (Prop_carry4_S[0]_CO[0]) + 0.142 1.108 f UPD_CLK_DIV/temp_reg[0]_i_4/CO[0] + net (fo=1, routed) 0.219 1.328 UPD_CLK_DIV/temp_reg[0]_i_4_n_3 + SLICE_X43Y71 LUT2 (Prop_lut2_I0_O) 0.124 1.452 f UPD_CLK_DIV/temp[0]_i_2/O + net (fo=25, routed) 0.272 1.724 UPD_CLK_DIV/temp[0]_i_2_n_0 + SLICE_X40Y71 FDCE f UPD_CLK_DIV/temp_reg[16]/CLR + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_1 rise edge) + 0.000 0.000 r + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O + net (fo=60, routed) 0.848 0.850 UPD_CLK_DIV/clk_out1 + SLICE_X40Y71 FDCE r UPD_CLK_DIV/temp_reg[16]/C + clock pessimism -0.254 0.596 + SLICE_X40Y71 FDCE (Remov_fdce_C_CLR) -0.092 0.504 UPD_CLK_DIV/temp_reg[16] + ------------------------------------------------------------------- + required time -0.504 + arrival time 1.724 + ------------------------------------------------------------------- + slack 1.220 + +Slack (MET) : 1.220ns (arrival time - required time) + Source: UPD_CLK_DIV/temp_reg[24]/C + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: UPD_CLK_DIV/temp_reg[17]/CLR + (removal check against rising-edge clock clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) + Data Path Delay: 1.144ns (logic 0.407ns (35.576%) route 0.737ns (64.424%)) + Logic Levels: 2 (CARRY4=1 LUT2=1) + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.850ns + Source Clock Delay (SCD): 0.580ns + Clock Pessimism Removal (CPR): 0.254ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_1 rise edge) + 0.000 0.000 r + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.548 0.548 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.053 -0.506 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.482 -0.024 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.002 r U0/inst/clkout1_buf/O + net (fo=60, routed) 0.578 0.580 UPD_CLK_DIV/clk_out1 + SLICE_X40Y73 FDCE r UPD_CLK_DIV/temp_reg[24]/C + ------------------------------------------------------------------- ------------------- + SLICE_X40Y73 FDCE (Prop_fdce_C_Q) 0.141 0.721 r UPD_CLK_DIV/temp_reg[24]/Q + net (fo=4, routed) 0.245 0.966 UPD_CLK_DIV/temp_reg[24] + SLICE_X42Y71 CARRY4 (Prop_carry4_S[0]_CO[0]) + 0.142 1.108 f UPD_CLK_DIV/temp_reg[0]_i_4/CO[0] + net (fo=1, routed) 0.219 1.328 UPD_CLK_DIV/temp_reg[0]_i_4_n_3 + SLICE_X43Y71 LUT2 (Prop_lut2_I0_O) 0.124 1.452 f UPD_CLK_DIV/temp[0]_i_2/O + net (fo=25, routed) 0.272 1.724 UPD_CLK_DIV/temp[0]_i_2_n_0 + SLICE_X40Y71 FDCE f UPD_CLK_DIV/temp_reg[17]/CLR + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_1 rise edge) + 0.000 0.000 r + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O + net (fo=60, routed) 0.848 0.850 UPD_CLK_DIV/clk_out1 + SLICE_X40Y71 FDCE r UPD_CLK_DIV/temp_reg[17]/C + clock pessimism -0.254 0.596 + SLICE_X40Y71 FDCE (Remov_fdce_C_CLR) -0.092 0.504 UPD_CLK_DIV/temp_reg[17] + ------------------------------------------------------------------- + required time -0.504 + arrival time 1.724 + ------------------------------------------------------------------- + slack 1.220 + +Slack (MET) : 1.220ns (arrival time - required time) + Source: UPD_CLK_DIV/temp_reg[24]/C + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: UPD_CLK_DIV/temp_reg[18]/CLR + (removal check against rising-edge clock clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) + Data Path Delay: 1.144ns (logic 0.407ns (35.576%) route 0.737ns (64.424%)) + Logic Levels: 2 (CARRY4=1 LUT2=1) + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.850ns + Source Clock Delay (SCD): 0.580ns + Clock Pessimism Removal (CPR): 0.254ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_1 rise edge) + 0.000 0.000 r + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.548 0.548 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.053 -0.506 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.482 -0.024 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.002 r U0/inst/clkout1_buf/O + net (fo=60, routed) 0.578 0.580 UPD_CLK_DIV/clk_out1 + SLICE_X40Y73 FDCE r UPD_CLK_DIV/temp_reg[24]/C + ------------------------------------------------------------------- ------------------- + SLICE_X40Y73 FDCE (Prop_fdce_C_Q) 0.141 0.721 r UPD_CLK_DIV/temp_reg[24]/Q + net (fo=4, routed) 0.245 0.966 UPD_CLK_DIV/temp_reg[24] + SLICE_X42Y71 CARRY4 (Prop_carry4_S[0]_CO[0]) + 0.142 1.108 f UPD_CLK_DIV/temp_reg[0]_i_4/CO[0] + net (fo=1, routed) 0.219 1.328 UPD_CLK_DIV/temp_reg[0]_i_4_n_3 + SLICE_X43Y71 LUT2 (Prop_lut2_I0_O) 0.124 1.452 f UPD_CLK_DIV/temp[0]_i_2/O + net (fo=25, routed) 0.272 1.724 UPD_CLK_DIV/temp[0]_i_2_n_0 + SLICE_X40Y71 FDCE f UPD_CLK_DIV/temp_reg[18]/CLR + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_1 rise edge) + 0.000 0.000 r + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O + net (fo=60, routed) 0.848 0.850 UPD_CLK_DIV/clk_out1 + SLICE_X40Y71 FDCE r UPD_CLK_DIV/temp_reg[18]/C + clock pessimism -0.254 0.596 + SLICE_X40Y71 FDCE (Remov_fdce_C_CLR) -0.092 0.504 UPD_CLK_DIV/temp_reg[18] + ------------------------------------------------------------------- + required time -0.504 + arrival time 1.724 + ------------------------------------------------------------------- + slack 1.220 + +Slack (MET) : 1.220ns (arrival time - required time) + Source: UPD_CLK_DIV/temp_reg[24]/C + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: UPD_CLK_DIV/temp_reg[19]/CLR + (removal check against rising-edge clock clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) + Data Path Delay: 1.144ns (logic 0.407ns (35.576%) route 0.737ns (64.424%)) + Logic Levels: 2 (CARRY4=1 LUT2=1) + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.850ns + Source Clock Delay (SCD): 0.580ns + Clock Pessimism Removal (CPR): 0.254ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_1 rise edge) + 0.000 0.000 r + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.548 0.548 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.053 -0.506 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.482 -0.024 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.002 r U0/inst/clkout1_buf/O + net (fo=60, routed) 0.578 0.580 UPD_CLK_DIV/clk_out1 + SLICE_X40Y73 FDCE r UPD_CLK_DIV/temp_reg[24]/C + ------------------------------------------------------------------- ------------------- + SLICE_X40Y73 FDCE (Prop_fdce_C_Q) 0.141 0.721 r UPD_CLK_DIV/temp_reg[24]/Q + net (fo=4, routed) 0.245 0.966 UPD_CLK_DIV/temp_reg[24] + SLICE_X42Y71 CARRY4 (Prop_carry4_S[0]_CO[0]) + 0.142 1.108 f UPD_CLK_DIV/temp_reg[0]_i_4/CO[0] + net (fo=1, routed) 0.219 1.328 UPD_CLK_DIV/temp_reg[0]_i_4_n_3 + SLICE_X43Y71 LUT2 (Prop_lut2_I0_O) 0.124 1.452 f UPD_CLK_DIV/temp[0]_i_2/O + net (fo=25, routed) 0.272 1.724 UPD_CLK_DIV/temp[0]_i_2_n_0 + SLICE_X40Y71 FDCE f UPD_CLK_DIV/temp_reg[19]/CLR + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_1 rise edge) + 0.000 0.000 r + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O + net (fo=60, routed) 0.848 0.850 UPD_CLK_DIV/clk_out1 + SLICE_X40Y71 FDCE r UPD_CLK_DIV/temp_reg[19]/C + clock pessimism -0.254 0.596 + SLICE_X40Y71 FDCE (Remov_fdce_C_CLR) -0.092 0.504 UPD_CLK_DIV/temp_reg[19] + ------------------------------------------------------------------- + required time -0.504 + arrival time 1.724 + ------------------------------------------------------------------- + slack 1.220 + +Slack (MET) : 1.228ns (arrival time - required time) + Source: UPD_CLK_DIV/temp_reg[24]/C + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: UPD_CLK_DIV/temp_reg[20]/CLR + (removal check against rising-edge clock clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) + Data Path Delay: 1.151ns (logic 0.407ns (35.369%) route 0.744ns (64.631%)) + Logic Levels: 2 (CARRY4=1 LUT2=1) + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.849ns + Source Clock Delay (SCD): 0.580ns + Clock Pessimism Removal (CPR): 0.254ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_1 rise edge) + 0.000 0.000 r + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.548 0.548 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.053 -0.506 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.482 -0.024 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.002 r U0/inst/clkout1_buf/O + net (fo=60, routed) 0.578 0.580 UPD_CLK_DIV/clk_out1 + SLICE_X40Y73 FDCE r UPD_CLK_DIV/temp_reg[24]/C + ------------------------------------------------------------------- ------------------- + SLICE_X40Y73 FDCE (Prop_fdce_C_Q) 0.141 0.721 r UPD_CLK_DIV/temp_reg[24]/Q + net (fo=4, routed) 0.245 0.966 UPD_CLK_DIV/temp_reg[24] + SLICE_X42Y71 CARRY4 (Prop_carry4_S[0]_CO[0]) + 0.142 1.108 f UPD_CLK_DIV/temp_reg[0]_i_4/CO[0] + net (fo=1, routed) 0.219 1.328 UPD_CLK_DIV/temp_reg[0]_i_4_n_3 + SLICE_X43Y71 LUT2 (Prop_lut2_I0_O) 0.124 1.452 f UPD_CLK_DIV/temp[0]_i_2/O + net (fo=25, routed) 0.279 1.730 UPD_CLK_DIV/temp[0]_i_2_n_0 + SLICE_X40Y72 FDCE f UPD_CLK_DIV/temp_reg[20]/CLR + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_1 rise edge) + 0.000 0.000 r + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O + net (fo=60, routed) 0.847 0.849 UPD_CLK_DIV/clk_out1 + SLICE_X40Y72 FDCE r UPD_CLK_DIV/temp_reg[20]/C + clock pessimism -0.254 0.595 + SLICE_X40Y72 FDCE (Remov_fdce_C_CLR) -0.092 0.503 UPD_CLK_DIV/temp_reg[20] + ------------------------------------------------------------------- + required time -0.503 + arrival time 1.730 + ------------------------------------------------------------------- + slack 1.228 + +Slack (MET) : 1.228ns (arrival time - required time) + Source: UPD_CLK_DIV/temp_reg[24]/C + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: UPD_CLK_DIV/temp_reg[21]/CLR + (removal check against rising-edge clock clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) + Data Path Delay: 1.151ns (logic 0.407ns (35.369%) route 0.744ns (64.631%)) + Logic Levels: 2 (CARRY4=1 LUT2=1) + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.849ns + Source Clock Delay (SCD): 0.580ns + Clock Pessimism Removal (CPR): 0.254ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_1 rise edge) + 0.000 0.000 r + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.548 0.548 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.053 -0.506 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.482 -0.024 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.002 r U0/inst/clkout1_buf/O + net (fo=60, routed) 0.578 0.580 UPD_CLK_DIV/clk_out1 + SLICE_X40Y73 FDCE r UPD_CLK_DIV/temp_reg[24]/C + ------------------------------------------------------------------- ------------------- + SLICE_X40Y73 FDCE (Prop_fdce_C_Q) 0.141 0.721 r UPD_CLK_DIV/temp_reg[24]/Q + net (fo=4, routed) 0.245 0.966 UPD_CLK_DIV/temp_reg[24] + SLICE_X42Y71 CARRY4 (Prop_carry4_S[0]_CO[0]) + 0.142 1.108 f UPD_CLK_DIV/temp_reg[0]_i_4/CO[0] + net (fo=1, routed) 0.219 1.328 UPD_CLK_DIV/temp_reg[0]_i_4_n_3 + SLICE_X43Y71 LUT2 (Prop_lut2_I0_O) 0.124 1.452 f UPD_CLK_DIV/temp[0]_i_2/O + net (fo=25, routed) 0.279 1.730 UPD_CLK_DIV/temp[0]_i_2_n_0 + SLICE_X40Y72 FDCE f UPD_CLK_DIV/temp_reg[21]/CLR + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_1 rise edge) + 0.000 0.000 r + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O + net (fo=60, routed) 0.847 0.849 UPD_CLK_DIV/clk_out1 + SLICE_X40Y72 FDCE r UPD_CLK_DIV/temp_reg[21]/C + clock pessimism -0.254 0.595 + SLICE_X40Y72 FDCE (Remov_fdce_C_CLR) -0.092 0.503 UPD_CLK_DIV/temp_reg[21] + ------------------------------------------------------------------- + required time -0.503 + arrival time 1.730 + ------------------------------------------------------------------- + slack 1.228 + +Slack (MET) : 1.228ns (arrival time - required time) + Source: UPD_CLK_DIV/temp_reg[24]/C + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: UPD_CLK_DIV/temp_reg[22]/CLR + (removal check against rising-edge clock clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) + Data Path Delay: 1.151ns (logic 0.407ns (35.369%) route 0.744ns (64.631%)) + Logic Levels: 2 (CARRY4=1 LUT2=1) + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.849ns + Source Clock Delay (SCD): 0.580ns + Clock Pessimism Removal (CPR): 0.254ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_1 rise edge) + 0.000 0.000 r + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.548 0.548 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.053 -0.506 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.482 -0.024 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.002 r U0/inst/clkout1_buf/O + net (fo=60, routed) 0.578 0.580 UPD_CLK_DIV/clk_out1 + SLICE_X40Y73 FDCE r UPD_CLK_DIV/temp_reg[24]/C + ------------------------------------------------------------------- ------------------- + SLICE_X40Y73 FDCE (Prop_fdce_C_Q) 0.141 0.721 r UPD_CLK_DIV/temp_reg[24]/Q + net (fo=4, routed) 0.245 0.966 UPD_CLK_DIV/temp_reg[24] + SLICE_X42Y71 CARRY4 (Prop_carry4_S[0]_CO[0]) + 0.142 1.108 f UPD_CLK_DIV/temp_reg[0]_i_4/CO[0] + net (fo=1, routed) 0.219 1.328 UPD_CLK_DIV/temp_reg[0]_i_4_n_3 + SLICE_X43Y71 LUT2 (Prop_lut2_I0_O) 0.124 1.452 f UPD_CLK_DIV/temp[0]_i_2/O + net (fo=25, routed) 0.279 1.730 UPD_CLK_DIV/temp[0]_i_2_n_0 + SLICE_X40Y72 FDCE f UPD_CLK_DIV/temp_reg[22]/CLR + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_1 rise edge) + 0.000 0.000 r + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O + net (fo=60, routed) 0.847 0.849 UPD_CLK_DIV/clk_out1 + SLICE_X40Y72 FDCE r UPD_CLK_DIV/temp_reg[22]/C + clock pessimism -0.254 0.595 + SLICE_X40Y72 FDCE (Remov_fdce_C_CLR) -0.092 0.503 UPD_CLK_DIV/temp_reg[22] + ------------------------------------------------------------------- + required time -0.503 + arrival time 1.730 + ------------------------------------------------------------------- + slack 1.228 + +Slack (MET) : 1.228ns (arrival time - required time) + Source: UPD_CLK_DIV/temp_reg[24]/C + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: UPD_CLK_DIV/temp_reg[23]/CLR + (removal check against rising-edge clock clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) + Data Path Delay: 1.151ns (logic 0.407ns (35.369%) route 0.744ns (64.631%)) + Logic Levels: 2 (CARRY4=1 LUT2=1) + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.849ns + Source Clock Delay (SCD): 0.580ns + Clock Pessimism Removal (CPR): 0.254ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_1 rise edge) + 0.000 0.000 r + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.548 0.548 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.053 -0.506 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.482 -0.024 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.002 r U0/inst/clkout1_buf/O + net (fo=60, routed) 0.578 0.580 UPD_CLK_DIV/clk_out1 + SLICE_X40Y73 FDCE r UPD_CLK_DIV/temp_reg[24]/C + ------------------------------------------------------------------- ------------------- + SLICE_X40Y73 FDCE (Prop_fdce_C_Q) 0.141 0.721 r UPD_CLK_DIV/temp_reg[24]/Q + net (fo=4, routed) 0.245 0.966 UPD_CLK_DIV/temp_reg[24] + SLICE_X42Y71 CARRY4 (Prop_carry4_S[0]_CO[0]) + 0.142 1.108 f UPD_CLK_DIV/temp_reg[0]_i_4/CO[0] + net (fo=1, routed) 0.219 1.328 UPD_CLK_DIV/temp_reg[0]_i_4_n_3 + SLICE_X43Y71 LUT2 (Prop_lut2_I0_O) 0.124 1.452 f UPD_CLK_DIV/temp[0]_i_2/O + net (fo=25, routed) 0.279 1.730 UPD_CLK_DIV/temp[0]_i_2_n_0 + SLICE_X40Y72 FDCE f UPD_CLK_DIV/temp_reg[23]/CLR + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_1 rise edge) + 0.000 0.000 r + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O + net (fo=60, routed) 0.847 0.849 UPD_CLK_DIV/clk_out1 + SLICE_X40Y72 FDCE r UPD_CLK_DIV/temp_reg[23]/C + clock pessimism -0.254 0.595 + SLICE_X40Y72 FDCE (Remov_fdce_C_CLR) -0.092 0.503 UPD_CLK_DIV/temp_reg[23] + ------------------------------------------------------------------- + required time -0.503 + arrival time 1.730 + ------------------------------------------------------------------- + slack 1.228 + +Slack (MET) : 1.228ns (arrival time - required time) + Source: UPD_CLK_DIV/temp_reg[24]/C + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: UPD_CLK_DIV/temp_reg[12]/CLR + (removal check against rising-edge clock clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) + Data Path Delay: 1.153ns (logic 0.407ns (35.306%) route 0.746ns (64.694%)) + Logic Levels: 2 (CARRY4=1 LUT2=1) + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.851ns + Source Clock Delay (SCD): 0.580ns + Clock Pessimism Removal (CPR): 0.254ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_1 rise edge) + 0.000 0.000 r + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.548 0.548 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.053 -0.506 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.482 -0.024 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.002 r U0/inst/clkout1_buf/O + net (fo=60, routed) 0.578 0.580 UPD_CLK_DIV/clk_out1 + SLICE_X40Y73 FDCE r UPD_CLK_DIV/temp_reg[24]/C + ------------------------------------------------------------------- ------------------- + SLICE_X40Y73 FDCE (Prop_fdce_C_Q) 0.141 0.721 r UPD_CLK_DIV/temp_reg[24]/Q + net (fo=4, routed) 0.245 0.966 UPD_CLK_DIV/temp_reg[24] + SLICE_X42Y71 CARRY4 (Prop_carry4_S[0]_CO[0]) + 0.142 1.108 f UPD_CLK_DIV/temp_reg[0]_i_4/CO[0] + net (fo=1, routed) 0.219 1.328 UPD_CLK_DIV/temp_reg[0]_i_4_n_3 + SLICE_X43Y71 LUT2 (Prop_lut2_I0_O) 0.124 1.452 f UPD_CLK_DIV/temp[0]_i_2/O + net (fo=25, routed) 0.281 1.732 UPD_CLK_DIV/temp[0]_i_2_n_0 + SLICE_X40Y70 FDCE f UPD_CLK_DIV/temp_reg[12]/CLR + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_1 rise edge) + 0.000 0.000 r + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O + net (fo=60, routed) 0.849 0.851 UPD_CLK_DIV/clk_out1 + SLICE_X40Y70 FDCE r UPD_CLK_DIV/temp_reg[12]/C + clock pessimism -0.254 0.597 + SLICE_X40Y70 FDCE (Remov_fdce_C_CLR) -0.092 0.505 UPD_CLK_DIV/temp_reg[12] + ------------------------------------------------------------------- + required time -0.505 + arrival time 1.732 + ------------------------------------------------------------------- + slack 1.228 + +Slack (MET) : 1.228ns (arrival time - required time) + Source: UPD_CLK_DIV/temp_reg[24]/C + (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: UPD_CLK_DIV/temp_reg[13]/CLR + (removal check against rising-edge clock clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) + Data Path Delay: 1.153ns (logic 0.407ns (35.306%) route 0.746ns (64.694%)) + Logic Levels: 2 (CARRY4=1 LUT2=1) + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.851ns + Source Clock Delay (SCD): 0.580ns + Clock Pessimism Removal (CPR): 0.254ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_clk_wiz_1 rise edge) + 0.000 0.000 r + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.548 0.548 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.053 -0.506 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.482 -0.024 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.002 r U0/inst/clkout1_buf/O + net (fo=60, routed) 0.578 0.580 UPD_CLK_DIV/clk_out1 + SLICE_X40Y73 FDCE r UPD_CLK_DIV/temp_reg[24]/C + ------------------------------------------------------------------- ------------------- + SLICE_X40Y73 FDCE (Prop_fdce_C_Q) 0.141 0.721 r UPD_CLK_DIV/temp_reg[24]/Q + net (fo=4, routed) 0.245 0.966 UPD_CLK_DIV/temp_reg[24] + SLICE_X42Y71 CARRY4 (Prop_carry4_S[0]_CO[0]) + 0.142 1.108 f UPD_CLK_DIV/temp_reg[0]_i_4/CO[0] + net (fo=1, routed) 0.219 1.328 UPD_CLK_DIV/temp_reg[0]_i_4_n_3 + SLICE_X43Y71 LUT2 (Prop_lut2_I0_O) 0.124 1.452 f UPD_CLK_DIV/temp[0]_i_2/O + net (fo=25, routed) 0.281 1.732 UPD_CLK_DIV/temp[0]_i_2_n_0 + SLICE_X40Y70 FDCE f UPD_CLK_DIV/temp_reg[13]/CLR + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_1 rise edge) + 0.000 0.000 r + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O + net (fo=60, routed) 0.849 0.851 UPD_CLK_DIV/clk_out1 + SLICE_X40Y70 FDCE r UPD_CLK_DIV/temp_reg[13]/C + clock pessimism -0.254 0.597 + SLICE_X40Y70 FDCE (Remov_fdce_C_CLR) -0.092 0.505 UPD_CLK_DIV/temp_reg[13] + ------------------------------------------------------------------- + required time -0.505 + arrival time 1.732 + ------------------------------------------------------------------- + slack 1.228 + + + + + +--------------------------------------------------------------------------------------------------- +Path Group: **async_default** +From Clock: sys_clk_pin + To Clock: clk_out1_clk_wiz_1 + +Setup : 0 Failing Endpoints, Worst Slack 2.088ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.745ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 2.088ns (required time - arrival time) + Source: SNAKE/request_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: SNAKE/startUpdate_reg/CLR + (recovery check against rising-edge clock clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 8.000ns (clk_out1_clk_wiz_1 rise@40.000ns - sys_clk_pin rise@32.000ns) + Data Path Delay: 1.259ns (logic 0.580ns (46.066%) route 0.679ns (53.934%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: -3.842ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.498ns = ( 41.498 - 40.000 ) + Source Clock Delay (SCD): 5.340ns = ( 37.340 - 32.000 ) + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.313ns + Phase Error (PE): 0.246ns + Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 32.000 32.000 r + L16 0.000 32.000 r H125MHz (IN) + net (fo=0) 0.000 32.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.491 33.491 r H125MHz_IBUF_inst/O + net (fo=1, routed) 2.076 35.567 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 35.668 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.672 37.340 SNAKE/H125MHz + SLICE_X22Y44 FDRE r SNAKE/request_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X22Y44 FDRE (Prop_fdre_C_Q) 0.456 37.796 f SNAKE/request_reg/Q + net (fo=5, routed) 0.292 38.088 SNAKE/dataRequest + SLICE_X23Y44 LUT2 (Prop_lut2_I1_O) 0.124 38.212 f SNAKE/startUpdate_i_2/O + net (fo=1, routed) 0.387 38.599 SNAKE/startUpdate_i_2_n_0 + SLICE_X23Y44 FDCE f SNAKE/startUpdate_reg/CLR + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_1 rise edge) + 40.000 40.000 r + BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O + net (fo=60, routed) 1.495 41.498 SNAKE/clk_out1 + SLICE_X23Y44 FDCE r SNAKE/startUpdate_reg/C + clock pessimism 0.000 41.498 + clock uncertainty -0.406 41.092 + SLICE_X23Y44 FDCE (Recov_fdce_C_CLR) -0.405 40.687 SNAKE/startUpdate_reg + ------------------------------------------------------------------- + required time 40.687 + arrival time -38.599 + ------------------------------------------------------------------- + slack 2.088 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.745ns (arrival time - required time) + Source: SNAKE/request_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: SNAKE/startUpdate_reg/CLR + (removal check against rising-edge clock clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 0.415ns (logic 0.186ns (44.813%) route 0.229ns (55.187%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: -0.644ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.830ns + Source Clock Delay (SCD): 1.474ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.313ns + Phase Error (PE): 0.246ns + Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O + net (fo=1, routed) 0.627 0.886 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.562 1.474 SNAKE/H125MHz + SLICE_X22Y44 FDRE r SNAKE/request_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X22Y44 FDRE (Prop_fdre_C_Q) 0.141 1.615 f SNAKE/request_reg/Q + net (fo=5, routed) 0.110 1.725 SNAKE/dataRequest + SLICE_X23Y44 LUT2 (Prop_lut2_I1_O) 0.045 1.770 f SNAKE/startUpdate_i_2/O + net (fo=1, routed) 0.119 1.889 SNAKE/startUpdate_i_2_n_0 + SLICE_X23Y44 FDCE f SNAKE/startUpdate_reg/CLR + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_clk_wiz_1 rise edge) + 0.000 0.000 r + BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 + MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O + net (fo=60, routed) 0.828 0.830 SNAKE/clk_out1 + SLICE_X23Y44 FDCE r SNAKE/startUpdate_reg/C + clock pessimism 0.000 0.830 + clock uncertainty 0.406 1.236 + SLICE_X23Y44 FDCE (Remov_fdce_C_CLR) -0.092 1.144 SNAKE/startUpdate_reg + ------------------------------------------------------------------- + required time -1.144 + arrival time 1.889 + ------------------------------------------------------------------- + slack 0.745 + + + + + +--------------------------------------------------------------------------------------------------- +Path Group: **async_default** +From Clock: sys_clk_pin + To Clock: sys_clk_pin + +Setup : 0 Failing Endpoints, Worst Slack 4.029ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.841ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 4.029ns (required time - arrival time) + Source: UPD/update_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: UPD/dataOut_reg[13]/CLR + (recovery check against rising-edge clock sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 8.000ns (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 3.371ns (logic 0.773ns (22.929%) route 2.598ns (77.071%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.706ns - Source Clock Delay (SCD): -0.474ns - Clock Pessimism Removal (CPR): -0.232ns - Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: -0.160ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 4.895ns = ( 12.895 - 8.000 ) + Source Clock Delay (SCD): 5.345ns + Clock Pessimism Removal (CPR): 0.291ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.313ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns - Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1 rise edge) + (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.587 -0.474 U1/CLK - SLICE_X38Y51 FDRE r U1/comptY_reg[0]/C + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O + net (fo=1, routed) 2.076 3.567 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.677 5.345 UPD/H125MHz + SLICE_X8Y34 FDRE r UPD/update_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X38Y51 FDRE (Prop_fdre_C_Q) 0.164 -0.310 f U1/comptY_reg[0]/Q - net (fo=29, routed) 0.212 -0.098 U1/comptY_reg__0[0] - SLICE_X38Y51 LUT1 (Prop_lut1_I0_O) 0.045 -0.053 r U1/comptY[0]_i_1/O - net (fo=1, routed) 0.000 -0.053 U1/comptY[0]_i_1_n_0 - SLICE_X38Y51 FDRE r U1/comptY_reg[0]/D + SLICE_X8Y34 FDRE (Prop_fdre_C_Q) 0.478 5.823 r UPD/update_reg/Q + net (fo=46, routed) 0.804 6.627 UPD/update + SLICE_X9Y33 LUT1 (Prop_lut1_I0_O) 0.295 6.922 f UPD/currentSnake_reg[dirY][0]_i_2/O + net (fo=16, routed) 1.794 8.717 UPD/currentSnake_reg[dirY][0]_i_2_n_0 + SLICE_X26Y47 FDCE f UPD/dataOut_reg[13]/CLR ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) - 0.000 0.000 r - L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.857 -0.706 U1/CLK - SLICE_X38Y51 FDRE r U1/comptY_reg[0]/C - clock pessimism 0.232 -0.474 - clock uncertainty 0.160 -0.313 - SLICE_X38Y51 FDRE (Hold_fdre_C_D) 0.120 -0.193 U1/comptY_reg[0] + (clock sys_clk_pin rise edge) + 8.000 8.000 r + L16 0.000 8.000 r H125MHz (IN) + net (fo=0) 0.000 8.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O + net (fo=1, routed) 1.880 11.301 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.503 12.895 UPD/H125MHz + SLICE_X26Y47 FDCE r UPD/dataOut_reg[13]/C + clock pessimism 0.291 13.186 + clock uncertainty -0.035 13.150 + SLICE_X26Y47 FDCE (Recov_fdce_C_CLR) -0.405 12.745 UPD/dataOut_reg[13] ------------------------------------------------------------------- - required time 0.193 - arrival time -0.053 + required time 12.745 + arrival time -8.717 ------------------------------------------------------------------- - slack 0.140 + slack 4.029 -Slack (MET) : 0.140ns (arrival time - required time) - Source: U1/comptX_reg[0]/C - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: U1/comptX_reg[0]/D - (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: clk_out1_clk_wiz_1_1 - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) - Data Path Delay: 0.421ns (logic 0.209ns (49.671%) route 0.212ns (50.329%)) +Slack (MET) : 4.166ns (required time - arrival time) + Source: UPD/update_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: UPD/dataOut_reg[10]/CLR + (recovery check against rising-edge clock sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 8.000ns (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 3.233ns (logic 0.773ns (23.911%) route 2.460ns (76.089%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.705ns - Source Clock Delay (SCD): -0.473ns - Clock Pessimism Removal (CPR): -0.232ns - Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: -0.161ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 4.894ns = ( 12.894 - 8.000 ) + Source Clock Delay (SCD): 5.345ns + Clock Pessimism Removal (CPR): 0.291ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.313ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns - Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1 rise edge) + (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.588 -0.473 U1/CLK - SLICE_X42Y55 FDRE r U1/comptX_reg[0]/C + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O + net (fo=1, routed) 2.076 3.567 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.677 5.345 UPD/H125MHz + SLICE_X8Y34 FDRE r UPD/update_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X42Y55 FDRE (Prop_fdre_C_Q) 0.164 -0.309 f U1/comptX_reg[0]/Q - net (fo=25, routed) 0.212 -0.097 U1/comptX_reg__0[0] - SLICE_X42Y55 LUT1 (Prop_lut1_I0_O) 0.045 -0.052 r U1/comptX[0]_i_1/O - net (fo=1, routed) 0.000 -0.052 U1/plusOp[0] - SLICE_X42Y55 FDRE r U1/comptX_reg[0]/D + SLICE_X8Y34 FDRE (Prop_fdre_C_Q) 0.478 5.823 r UPD/update_reg/Q + net (fo=46, routed) 0.804 6.627 UPD/update + SLICE_X9Y33 LUT1 (Prop_lut1_I0_O) 0.295 6.922 f UPD/currentSnake_reg[dirY][0]_i_2/O + net (fo=16, routed) 1.656 8.578 UPD/currentSnake_reg[dirY][0]_i_2_n_0 + SLICE_X26Y46 FDCE f UPD/dataOut_reg[10]/CLR ------------------------------------------------------------------- ------------------- - (clock clk_out1_clk_wiz_1_1 rise edge) + (clock sys_clk_pin rise edge) + 8.000 8.000 r + L16 0.000 8.000 r H125MHz (IN) + net (fo=0) 0.000 8.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O + net (fo=1, routed) 1.880 11.301 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.502 12.894 UPD/H125MHz + SLICE_X26Y46 FDCE r UPD/dataOut_reg[10]/C + clock pessimism 0.291 13.185 + clock uncertainty -0.035 13.149 + SLICE_X26Y46 FDCE (Recov_fdce_C_CLR) -0.405 12.744 UPD/dataOut_reg[10] + ------------------------------------------------------------------- + required time 12.744 + arrival time -8.578 + ------------------------------------------------------------------- + slack 4.166 + +Slack (MET) : 4.166ns (required time - arrival time) + Source: UPD/update_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: UPD/dataOut_reg[11]/CLR + (recovery check against rising-edge clock sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 8.000ns (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 3.233ns (logic 0.773ns (23.911%) route 2.460ns (76.089%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.161ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 4.894ns = ( 12.894 - 8.000 ) + Source Clock Delay (SCD): 5.345ns + Clock Pessimism Removal (CPR): 0.291ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) - net (fo=0) 0.000 0.000 U0/inst/clk_in1 - L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O - net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 - MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) - -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 - net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O - net (fo=21, routed) 0.858 -0.705 U1/CLK - SLICE_X42Y55 FDRE r U1/comptX_reg[0]/C - clock pessimism 0.232 -0.473 - clock uncertainty 0.160 -0.312 - SLICE_X42Y55 FDRE (Hold_fdre_C_D) 0.120 -0.192 U1/comptX_reg[0] + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O + net (fo=1, routed) 2.076 3.567 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.677 5.345 UPD/H125MHz + SLICE_X8Y34 FDRE r UPD/update_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X8Y34 FDRE (Prop_fdre_C_Q) 0.478 5.823 r UPD/update_reg/Q + net (fo=46, routed) 0.804 6.627 UPD/update + SLICE_X9Y33 LUT1 (Prop_lut1_I0_O) 0.295 6.922 f UPD/currentSnake_reg[dirY][0]_i_2/O + net (fo=16, routed) 1.656 8.578 UPD/currentSnake_reg[dirY][0]_i_2_n_0 + SLICE_X26Y46 FDCE f UPD/dataOut_reg[11]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 8.000 8.000 r + L16 0.000 8.000 r H125MHz (IN) + net (fo=0) 0.000 8.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O + net (fo=1, routed) 1.880 11.301 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.502 12.894 UPD/H125MHz + SLICE_X26Y46 FDCE r UPD/dataOut_reg[11]/C + clock pessimism 0.291 13.185 + clock uncertainty -0.035 13.149 + SLICE_X26Y46 FDCE (Recov_fdce_C_CLR) -0.405 12.744 UPD/dataOut_reg[11] ------------------------------------------------------------------- - required time 0.192 - arrival time -0.052 + required time 12.744 + arrival time -8.578 ------------------------------------------------------------------- - slack 0.140 + slack 4.166 + +Slack (MET) : 4.166ns (required time - arrival time) + Source: UPD/update_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: UPD/dataOut_reg[12]/CLR + (recovery check against rising-edge clock sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 8.000ns (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 3.233ns (logic 0.773ns (23.911%) route 2.460ns (76.089%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.161ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 4.894ns = ( 12.894 - 8.000 ) + Source Clock Delay (SCD): 5.345ns + Clock Pessimism Removal (CPR): 0.291ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O + net (fo=1, routed) 2.076 3.567 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.677 5.345 UPD/H125MHz + SLICE_X8Y34 FDRE r UPD/update_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X8Y34 FDRE (Prop_fdre_C_Q) 0.478 5.823 r UPD/update_reg/Q + net (fo=46, routed) 0.804 6.627 UPD/update + SLICE_X9Y33 LUT1 (Prop_lut1_I0_O) 0.295 6.922 f UPD/currentSnake_reg[dirY][0]_i_2/O + net (fo=16, routed) 1.656 8.578 UPD/currentSnake_reg[dirY][0]_i_2_n_0 + SLICE_X26Y46 FDCE f UPD/dataOut_reg[12]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 8.000 8.000 r + L16 0.000 8.000 r H125MHz (IN) + net (fo=0) 0.000 8.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O + net (fo=1, routed) 1.880 11.301 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.502 12.894 UPD/H125MHz + SLICE_X26Y46 FDCE r UPD/dataOut_reg[12]/C + clock pessimism 0.291 13.185 + clock uncertainty -0.035 13.149 + SLICE_X26Y46 FDCE (Recov_fdce_C_CLR) -0.405 12.744 UPD/dataOut_reg[12] + ------------------------------------------------------------------- + required time 12.744 + arrival time -8.578 + ------------------------------------------------------------------- + slack 4.166 + +Slack (MET) : 4.166ns (required time - arrival time) + Source: UPD/update_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: UPD/dataOut_reg[9]/CLR + (recovery check against rising-edge clock sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 8.000ns (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 3.233ns (logic 0.773ns (23.911%) route 2.460ns (76.089%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.161ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 4.894ns = ( 12.894 - 8.000 ) + Source Clock Delay (SCD): 5.345ns + Clock Pessimism Removal (CPR): 0.291ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O + net (fo=1, routed) 2.076 3.567 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.677 5.345 UPD/H125MHz + SLICE_X8Y34 FDRE r UPD/update_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X8Y34 FDRE (Prop_fdre_C_Q) 0.478 5.823 r UPD/update_reg/Q + net (fo=46, routed) 0.804 6.627 UPD/update + SLICE_X9Y33 LUT1 (Prop_lut1_I0_O) 0.295 6.922 f UPD/currentSnake_reg[dirY][0]_i_2/O + net (fo=16, routed) 1.656 8.578 UPD/currentSnake_reg[dirY][0]_i_2_n_0 + SLICE_X26Y46 FDCE f UPD/dataOut_reg[9]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 8.000 8.000 r + L16 0.000 8.000 r H125MHz (IN) + net (fo=0) 0.000 8.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O + net (fo=1, routed) 1.880 11.301 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.502 12.894 UPD/H125MHz + SLICE_X26Y46 FDCE r UPD/dataOut_reg[9]/C + clock pessimism 0.291 13.185 + clock uncertainty -0.035 13.149 + SLICE_X26Y46 FDCE (Recov_fdce_C_CLR) -0.405 12.744 UPD/dataOut_reg[9] + ------------------------------------------------------------------- + required time 12.744 + arrival time -8.578 + ------------------------------------------------------------------- + slack 4.166 + +Slack (MET) : 4.315ns (required time - arrival time) + Source: UPD/update_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: UPD/dataOut_reg[5]/CLR + (recovery check against rising-edge clock sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 8.000ns (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 3.085ns (logic 0.773ns (25.061%) route 2.312ns (74.939%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.161ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 4.894ns = ( 12.894 - 8.000 ) + Source Clock Delay (SCD): 5.345ns + Clock Pessimism Removal (CPR): 0.291ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O + net (fo=1, routed) 2.076 3.567 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.677 5.345 UPD/H125MHz + SLICE_X8Y34 FDRE r UPD/update_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X8Y34 FDRE (Prop_fdre_C_Q) 0.478 5.823 r UPD/update_reg/Q + net (fo=46, routed) 0.804 6.627 UPD/update + SLICE_X9Y33 LUT1 (Prop_lut1_I0_O) 0.295 6.922 f UPD/currentSnake_reg[dirY][0]_i_2/O + net (fo=16, routed) 1.508 8.430 UPD/currentSnake_reg[dirY][0]_i_2_n_0 + SLICE_X26Y45 FDCE f UPD/dataOut_reg[5]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 8.000 8.000 r + L16 0.000 8.000 r H125MHz (IN) + net (fo=0) 0.000 8.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O + net (fo=1, routed) 1.880 11.301 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.502 12.894 UPD/H125MHz + SLICE_X26Y45 FDCE r UPD/dataOut_reg[5]/C + clock pessimism 0.291 13.185 + clock uncertainty -0.035 13.149 + SLICE_X26Y45 FDCE (Recov_fdce_C_CLR) -0.405 12.744 UPD/dataOut_reg[5] + ------------------------------------------------------------------- + required time 12.744 + arrival time -8.430 + ------------------------------------------------------------------- + slack 4.315 + +Slack (MET) : 4.315ns (required time - arrival time) + Source: UPD/update_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: UPD/dataOut_reg[6]/CLR + (recovery check against rising-edge clock sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 8.000ns (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 3.085ns (logic 0.773ns (25.061%) route 2.312ns (74.939%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.161ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 4.894ns = ( 12.894 - 8.000 ) + Source Clock Delay (SCD): 5.345ns + Clock Pessimism Removal (CPR): 0.291ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O + net (fo=1, routed) 2.076 3.567 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.677 5.345 UPD/H125MHz + SLICE_X8Y34 FDRE r UPD/update_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X8Y34 FDRE (Prop_fdre_C_Q) 0.478 5.823 r UPD/update_reg/Q + net (fo=46, routed) 0.804 6.627 UPD/update + SLICE_X9Y33 LUT1 (Prop_lut1_I0_O) 0.295 6.922 f UPD/currentSnake_reg[dirY][0]_i_2/O + net (fo=16, routed) 1.508 8.430 UPD/currentSnake_reg[dirY][0]_i_2_n_0 + SLICE_X26Y45 FDCE f UPD/dataOut_reg[6]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 8.000 8.000 r + L16 0.000 8.000 r H125MHz (IN) + net (fo=0) 0.000 8.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O + net (fo=1, routed) 1.880 11.301 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.502 12.894 UPD/H125MHz + SLICE_X26Y45 FDCE r UPD/dataOut_reg[6]/C + clock pessimism 0.291 13.185 + clock uncertainty -0.035 13.149 + SLICE_X26Y45 FDCE (Recov_fdce_C_CLR) -0.405 12.744 UPD/dataOut_reg[6] + ------------------------------------------------------------------- + required time 12.744 + arrival time -8.430 + ------------------------------------------------------------------- + slack 4.315 + +Slack (MET) : 4.315ns (required time - arrival time) + Source: UPD/update_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: UPD/dataOut_reg[7]/CLR + (recovery check against rising-edge clock sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 8.000ns (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 3.085ns (logic 0.773ns (25.061%) route 2.312ns (74.939%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.161ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 4.894ns = ( 12.894 - 8.000 ) + Source Clock Delay (SCD): 5.345ns + Clock Pessimism Removal (CPR): 0.291ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O + net (fo=1, routed) 2.076 3.567 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.677 5.345 UPD/H125MHz + SLICE_X8Y34 FDRE r UPD/update_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X8Y34 FDRE (Prop_fdre_C_Q) 0.478 5.823 r UPD/update_reg/Q + net (fo=46, routed) 0.804 6.627 UPD/update + SLICE_X9Y33 LUT1 (Prop_lut1_I0_O) 0.295 6.922 f UPD/currentSnake_reg[dirY][0]_i_2/O + net (fo=16, routed) 1.508 8.430 UPD/currentSnake_reg[dirY][0]_i_2_n_0 + SLICE_X26Y45 FDCE f UPD/dataOut_reg[7]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 8.000 8.000 r + L16 0.000 8.000 r H125MHz (IN) + net (fo=0) 0.000 8.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O + net (fo=1, routed) 1.880 11.301 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.502 12.894 UPD/H125MHz + SLICE_X26Y45 FDCE r UPD/dataOut_reg[7]/C + clock pessimism 0.291 13.185 + clock uncertainty -0.035 13.149 + SLICE_X26Y45 FDCE (Recov_fdce_C_CLR) -0.405 12.744 UPD/dataOut_reg[7] + ------------------------------------------------------------------- + required time 12.744 + arrival time -8.430 + ------------------------------------------------------------------- + slack 4.315 + +Slack (MET) : 4.319ns (required time - arrival time) + Source: UPD/update_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: UPD/dataOut_reg[2]/CLR + (recovery check against rising-edge clock sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 8.000ns (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 3.080ns (logic 0.773ns (25.096%) route 2.307ns (74.904%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.161ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 4.894ns = ( 12.894 - 8.000 ) + Source Clock Delay (SCD): 5.345ns + Clock Pessimism Removal (CPR): 0.291ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O + net (fo=1, routed) 2.076 3.567 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.677 5.345 UPD/H125MHz + SLICE_X8Y34 FDRE r UPD/update_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X8Y34 FDRE (Prop_fdre_C_Q) 0.478 5.823 r UPD/update_reg/Q + net (fo=46, routed) 0.804 6.627 UPD/update + SLICE_X9Y33 LUT1 (Prop_lut1_I0_O) 0.295 6.922 f UPD/currentSnake_reg[dirY][0]_i_2/O + net (fo=16, routed) 1.503 8.425 UPD/currentSnake_reg[dirY][0]_i_2_n_0 + SLICE_X27Y45 FDCE f UPD/dataOut_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 8.000 8.000 r + L16 0.000 8.000 r H125MHz (IN) + net (fo=0) 0.000 8.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O + net (fo=1, routed) 1.880 11.301 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.502 12.894 UPD/H125MHz + SLICE_X27Y45 FDCE r UPD/dataOut_reg[2]/C + clock pessimism 0.291 13.185 + clock uncertainty -0.035 13.149 + SLICE_X27Y45 FDCE (Recov_fdce_C_CLR) -0.405 12.744 UPD/dataOut_reg[2] + ------------------------------------------------------------------- + required time 12.744 + arrival time -8.425 + ------------------------------------------------------------------- + slack 4.319 + +Slack (MET) : 4.353ns (required time - arrival time) + Source: UPD/update_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: UPD/dataOut_reg[20]_P/PRE + (recovery check against rising-edge clock sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 8.000ns (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 3.188ns (logic 0.773ns (24.251%) route 2.415ns (75.749%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: -0.065ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 4.889ns = ( 12.889 - 8.000 ) + Source Clock Delay (SCD): 5.345ns + Clock Pessimism Removal (CPR): 0.391ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O + net (fo=1, routed) 2.076 3.567 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.677 5.345 UPD/H125MHz + SLICE_X8Y34 FDRE r UPD/update_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X8Y34 FDRE (Prop_fdre_C_Q) 0.478 5.823 r UPD/update_reg/Q + net (fo=46, routed) 1.437 7.260 UPD/update + SLICE_X6Y28 LUT2 (Prop_lut2_I1_O) 0.295 7.555 f UPD/dataOut_reg[20]_LDC_i_1/O + net (fo=2, routed) 0.977 8.533 UPD/dataOut_reg[20]_LDC_i_1_n_0 + SLICE_X7Y28 FDPE f UPD/dataOut_reg[20]_P/PRE + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 8.000 8.000 r + L16 0.000 8.000 r H125MHz (IN) + net (fo=0) 0.000 8.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O + net (fo=1, routed) 1.880 11.301 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 1.497 12.889 UPD/H125MHz + SLICE_X7Y28 FDPE r UPD/dataOut_reg[20]_P/C + clock pessimism 0.391 13.280 + clock uncertainty -0.035 13.245 + SLICE_X7Y28 FDPE (Recov_fdpe_C_PRE) -0.359 12.886 UPD/dataOut_reg[20]_P + ------------------------------------------------------------------- + required time 12.886 + arrival time -8.533 + ------------------------------------------------------------------- + slack 4.353 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.841ns (arrival time - required time) + Source: UPD/update_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: UPD/dataOut_reg[22]/CLR + (removal check against rising-edge clock sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 0.785ns (logic 0.246ns (31.332%) route 0.539ns (68.668%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.011ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.986ns + Source Clock Delay (SCD): 1.476ns + Clock Pessimism Removal (CPR): 0.499ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O + net (fo=1, routed) 0.627 0.886 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.564 1.476 UPD/H125MHz + SLICE_X8Y34 FDRE r UPD/update_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X8Y34 FDRE (Prop_fdre_C_Q) 0.148 1.624 r UPD/update_reg/Q + net (fo=46, routed) 0.357 1.981 UPD/update + SLICE_X9Y33 LUT1 (Prop_lut1_I0_O) 0.098 2.079 f UPD/currentSnake_reg[dirY][0]_i_2/O + net (fo=16, routed) 0.182 2.261 UPD/currentSnake_reg[dirY][0]_i_2_n_0 + SLICE_X8Y31 FDCE f UPD/dataOut_reg[22]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r H125MHz_IBUF_inst/O + net (fo=1, routed) 0.683 1.130 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.159 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.827 1.986 UPD/H125MHz + SLICE_X8Y31 FDCE r UPD/dataOut_reg[22]/C + clock pessimism -0.499 1.487 + SLICE_X8Y31 FDCE (Remov_fdce_C_CLR) -0.067 1.420 UPD/dataOut_reg[22] + ------------------------------------------------------------------- + required time -1.420 + arrival time 2.261 + ------------------------------------------------------------------- + slack 0.841 + +Slack (MET) : 0.841ns (arrival time - required time) + Source: UPD/update_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: UPD/dataOut_reg[23]/CLR + (removal check against rising-edge clock sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 0.785ns (logic 0.246ns (31.332%) route 0.539ns (68.668%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.011ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.986ns + Source Clock Delay (SCD): 1.476ns + Clock Pessimism Removal (CPR): 0.499ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O + net (fo=1, routed) 0.627 0.886 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.564 1.476 UPD/H125MHz + SLICE_X8Y34 FDRE r UPD/update_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X8Y34 FDRE (Prop_fdre_C_Q) 0.148 1.624 r UPD/update_reg/Q + net (fo=46, routed) 0.357 1.981 UPD/update + SLICE_X9Y33 LUT1 (Prop_lut1_I0_O) 0.098 2.079 f UPD/currentSnake_reg[dirY][0]_i_2/O + net (fo=16, routed) 0.182 2.261 UPD/currentSnake_reg[dirY][0]_i_2_n_0 + SLICE_X8Y31 FDCE f UPD/dataOut_reg[23]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r H125MHz_IBUF_inst/O + net (fo=1, routed) 0.683 1.130 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.159 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.827 1.986 UPD/H125MHz + SLICE_X8Y31 FDCE r UPD/dataOut_reg[23]/C + clock pessimism -0.499 1.487 + SLICE_X8Y31 FDCE (Remov_fdce_C_CLR) -0.067 1.420 UPD/dataOut_reg[23] + ------------------------------------------------------------------- + required time -1.420 + arrival time 2.261 + ------------------------------------------------------------------- + slack 0.841 + +Slack (MET) : 0.920ns (arrival time - required time) + Source: UPD/update_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: UPD/dataOut_reg[14]/CLR + (removal check against rising-edge clock sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 0.862ns (logic 0.246ns (28.546%) route 0.616ns (71.454%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.009ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.984ns + Source Clock Delay (SCD): 1.476ns + Clock Pessimism Removal (CPR): 0.499ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O + net (fo=1, routed) 0.627 0.886 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.564 1.476 UPD/H125MHz + SLICE_X8Y34 FDRE r UPD/update_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X8Y34 FDRE (Prop_fdre_C_Q) 0.148 1.624 r UPD/update_reg/Q + net (fo=46, routed) 0.357 1.981 UPD/update + SLICE_X9Y33 LUT1 (Prop_lut1_I0_O) 0.098 2.079 f UPD/currentSnake_reg[dirY][0]_i_2/O + net (fo=16, routed) 0.259 2.337 UPD/currentSnake_reg[dirY][0]_i_2_n_0 + SLICE_X8Y29 FDCE f UPD/dataOut_reg[14]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r H125MHz_IBUF_inst/O + net (fo=1, routed) 0.683 1.130 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.159 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.825 1.984 UPD/H125MHz + SLICE_X8Y29 FDCE r UPD/dataOut_reg[14]/C + clock pessimism -0.499 1.485 + SLICE_X8Y29 FDCE (Remov_fdce_C_CLR) -0.067 1.418 UPD/dataOut_reg[14] + ------------------------------------------------------------------- + required time -1.418 + arrival time 2.337 + ------------------------------------------------------------------- + slack 0.920 + +Slack (MET) : 0.920ns (arrival time - required time) + Source: UPD/update_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: UPD/dataOut_reg[15]/CLR + (removal check against rising-edge clock sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 0.862ns (logic 0.246ns (28.546%) route 0.616ns (71.454%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.009ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.984ns + Source Clock Delay (SCD): 1.476ns + Clock Pessimism Removal (CPR): 0.499ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O + net (fo=1, routed) 0.627 0.886 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.564 1.476 UPD/H125MHz + SLICE_X8Y34 FDRE r UPD/update_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X8Y34 FDRE (Prop_fdre_C_Q) 0.148 1.624 r UPD/update_reg/Q + net (fo=46, routed) 0.357 1.981 UPD/update + SLICE_X9Y33 LUT1 (Prop_lut1_I0_O) 0.098 2.079 f UPD/currentSnake_reg[dirY][0]_i_2/O + net (fo=16, routed) 0.259 2.337 UPD/currentSnake_reg[dirY][0]_i_2_n_0 + SLICE_X8Y29 FDCE f UPD/dataOut_reg[15]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r H125MHz_IBUF_inst/O + net (fo=1, routed) 0.683 1.130 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.159 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.825 1.984 UPD/H125MHz + SLICE_X8Y29 FDCE r UPD/dataOut_reg[15]/C + clock pessimism -0.499 1.485 + SLICE_X8Y29 FDCE (Remov_fdce_C_CLR) -0.067 1.418 UPD/dataOut_reg[15] + ------------------------------------------------------------------- + required time -1.418 + arrival time 2.337 + ------------------------------------------------------------------- + slack 0.920 + +Slack (MET) : 0.920ns (arrival time - required time) + Source: UPD/update_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: UPD/dataOut_reg[16]/CLR + (removal check against rising-edge clock sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 0.862ns (logic 0.246ns (28.546%) route 0.616ns (71.454%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.009ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.984ns + Source Clock Delay (SCD): 1.476ns + Clock Pessimism Removal (CPR): 0.499ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O + net (fo=1, routed) 0.627 0.886 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.564 1.476 UPD/H125MHz + SLICE_X8Y34 FDRE r UPD/update_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X8Y34 FDRE (Prop_fdre_C_Q) 0.148 1.624 r UPD/update_reg/Q + net (fo=46, routed) 0.357 1.981 UPD/update + SLICE_X9Y33 LUT1 (Prop_lut1_I0_O) 0.098 2.079 f UPD/currentSnake_reg[dirY][0]_i_2/O + net (fo=16, routed) 0.259 2.337 UPD/currentSnake_reg[dirY][0]_i_2_n_0 + SLICE_X8Y29 FDCE f UPD/dataOut_reg[16]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r H125MHz_IBUF_inst/O + net (fo=1, routed) 0.683 1.130 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.159 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.825 1.984 UPD/H125MHz + SLICE_X8Y29 FDCE r UPD/dataOut_reg[16]/C + clock pessimism -0.499 1.485 + SLICE_X8Y29 FDCE (Remov_fdce_C_CLR) -0.067 1.418 UPD/dataOut_reg[16] + ------------------------------------------------------------------- + required time -1.418 + arrival time 2.337 + ------------------------------------------------------------------- + slack 0.920 + +Slack (MET) : 0.924ns (arrival time - required time) + Source: UPD/update_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: UPD/dataOut_reg[17]/PRE + (removal check against rising-edge clock sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 0.862ns (logic 0.246ns (28.546%) route 0.616ns (71.454%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.009ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.984ns + Source Clock Delay (SCD): 1.476ns + Clock Pessimism Removal (CPR): 0.499ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O + net (fo=1, routed) 0.627 0.886 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.564 1.476 UPD/H125MHz + SLICE_X8Y34 FDRE r UPD/update_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X8Y34 FDRE (Prop_fdre_C_Q) 0.148 1.624 r UPD/update_reg/Q + net (fo=46, routed) 0.357 1.981 UPD/update + SLICE_X9Y33 LUT1 (Prop_lut1_I0_O) 0.098 2.079 f UPD/currentSnake_reg[dirY][0]_i_2/O + net (fo=16, routed) 0.259 2.337 UPD/currentSnake_reg[dirY][0]_i_2_n_0 + SLICE_X8Y29 FDPE f UPD/dataOut_reg[17]/PRE + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r H125MHz_IBUF_inst/O + net (fo=1, routed) 0.683 1.130 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.159 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.825 1.984 UPD/H125MHz + SLICE_X8Y29 FDPE r UPD/dataOut_reg[17]/C + clock pessimism -0.499 1.485 + SLICE_X8Y29 FDPE (Remov_fdpe_C_PRE) -0.071 1.414 UPD/dataOut_reg[17] + ------------------------------------------------------------------- + required time -1.414 + arrival time 2.337 + ------------------------------------------------------------------- + slack 0.924 + +Slack (MET) : 0.974ns (arrival time - required time) + Source: UPD/update_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: UPD/dataOut_reg[19]_P/PRE + (removal check against rising-edge clock sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 0.910ns (logic 0.246ns (27.026%) route 0.664ns (72.974%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: 0.031ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.987ns + Source Clock Delay (SCD): 1.476ns + Clock Pessimism Removal (CPR): 0.480ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O + net (fo=1, routed) 0.627 0.886 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.564 1.476 UPD/H125MHz + SLICE_X8Y34 FDRE r UPD/update_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X8Y34 FDRE (Prop_fdre_C_Q) 0.148 1.624 r UPD/update_reg/Q + net (fo=46, routed) 0.533 2.157 UPD/update + SLICE_X7Y32 LUT2 (Prop_lut2_I1_O) 0.098 2.255 f UPD/dataOut_reg[19]_LDC_i_1/O + net (fo=2, routed) 0.131 2.386 UPD/dataOut_reg[19]_LDC_i_1_n_0 + SLICE_X7Y32 FDPE f UPD/dataOut_reg[19]_P/PRE + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r H125MHz_IBUF_inst/O + net (fo=1, routed) 0.683 1.130 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.159 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.828 1.987 UPD/H125MHz + SLICE_X7Y32 FDPE r UPD/dataOut_reg[19]_P/C + clock pessimism -0.480 1.507 + SLICE_X7Y32 FDPE (Remov_fdpe_C_PRE) -0.095 1.412 UPD/dataOut_reg[19]_P + ------------------------------------------------------------------- + required time -1.412 + arrival time 2.386 + ------------------------------------------------------------------- + slack 0.974 + +Slack (MET) : 0.987ns (arrival time - required time) + Source: UPD/update_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: UPD/dataOut_reg[19]_C/CLR + (removal check against rising-edge clock sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 0.932ns (logic 0.246ns (26.401%) route 0.686ns (73.599%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.987ns + Source Clock Delay (SCD): 1.476ns + Clock Pessimism Removal (CPR): 0.499ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O + net (fo=1, routed) 0.627 0.886 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.564 1.476 UPD/H125MHz + SLICE_X8Y34 FDRE r UPD/update_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X8Y34 FDRE (Prop_fdre_C_Q) 0.148 1.624 r UPD/update_reg/Q + net (fo=46, routed) 0.502 2.126 UPD/update + SLICE_X7Y32 LUT2 (Prop_lut2_I1_O) 0.098 2.224 f UPD/dataOut_reg[19]_LDC_i_2/O + net (fo=2, routed) 0.184 2.408 UPD/dataOut_reg[19]_LDC_i_2_n_0 + SLICE_X8Y32 FDCE f UPD/dataOut_reg[19]_C/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r H125MHz_IBUF_inst/O + net (fo=1, routed) 0.683 1.130 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.159 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.828 1.987 UPD/H125MHz + SLICE_X8Y32 FDCE r UPD/dataOut_reg[19]_C/C + clock pessimism -0.499 1.488 + SLICE_X8Y32 FDCE (Remov_fdce_C_CLR) -0.067 1.421 UPD/dataOut_reg[19]_C + ------------------------------------------------------------------- + required time -1.421 + arrival time 2.408 + ------------------------------------------------------------------- + slack 0.987 + +Slack (MET) : 0.994ns (arrival time - required time) + Source: UPD/update_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: UPD/dataOut_reg[0]_C/CLR + (removal check against rising-edge clock sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 0.935ns (logic 0.246ns (26.298%) route 0.689ns (73.702%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: 0.008ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.983ns + Source Clock Delay (SCD): 1.476ns + Clock Pessimism Removal (CPR): 0.499ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O + net (fo=1, routed) 0.627 0.886 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.564 1.476 UPD/H125MHz + SLICE_X8Y34 FDRE r UPD/update_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X8Y34 FDRE (Prop_fdre_C_Q) 0.148 1.624 r UPD/update_reg/Q + net (fo=46, routed) 0.415 2.039 UPD/update + SLICE_X6Y27 LUT2 (Prop_lut2_I1_O) 0.098 2.137 f UPD/dataOut_reg[4]_LDC_i_2/O + net (fo=4, routed) 0.274 2.411 UPD/dataOut_reg[4]_LDC_i_2_n_0 + SLICE_X8Y28 FDCE f UPD/dataOut_reg[0]_C/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r H125MHz_IBUF_inst/O + net (fo=1, routed) 0.683 1.130 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.159 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.824 1.983 UPD/H125MHz + SLICE_X8Y28 FDCE r UPD/dataOut_reg[0]_C/C + clock pessimism -0.499 1.484 + SLICE_X8Y28 FDCE (Remov_fdce_C_CLR) -0.067 1.417 UPD/dataOut_reg[0]_C + ------------------------------------------------------------------- + required time -1.417 + arrival time 2.411 + ------------------------------------------------------------------- + slack 0.994 + +Slack (MET) : 0.994ns (arrival time - required time) + Source: UPD/update_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Destination: UPD/dataOut_reg[3]_C/CLR + (removal check against rising-edge clock sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) + Data Path Delay: 0.935ns (logic 0.246ns (26.298%) route 0.689ns (73.702%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: 0.008ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.983ns + Source Clock Delay (SCD): 1.476ns + Clock Pessimism Removal (CPR): 0.499ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O + net (fo=1, routed) 0.627 0.886 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.564 1.476 UPD/H125MHz + SLICE_X8Y34 FDRE r UPD/update_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X8Y34 FDRE (Prop_fdre_C_Q) 0.148 1.624 r UPD/update_reg/Q + net (fo=46, routed) 0.415 2.039 UPD/update + SLICE_X6Y27 LUT2 (Prop_lut2_I1_O) 0.098 2.137 f UPD/dataOut_reg[4]_LDC_i_2/O + net (fo=4, routed) 0.274 2.411 UPD/dataOut_reg[4]_LDC_i_2_n_0 + SLICE_X8Y28 FDCE f UPD/dataOut_reg[3]_C/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk_pin rise edge) + 0.000 0.000 r + L16 0.000 0.000 r H125MHz (IN) + net (fo=0) 0.000 0.000 H125MHz + L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r H125MHz_IBUF_inst/O + net (fo=1, routed) 0.683 1.130 H125MHz_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.159 r H125MHz_IBUF_BUFG_inst/O + net (fo=184, routed) 0.824 1.983 UPD/H125MHz + SLICE_X8Y28 FDCE r UPD/dataOut_reg[3]_C/C + clock pessimism -0.499 1.484 + SLICE_X8Y28 FDCE (Remov_fdce_C_CLR) -0.067 1.417 UPD/dataOut_reg[3]_C + ------------------------------------------------------------------- + required time -1.417 + arrival time 2.411 + ------------------------------------------------------------------- + slack 0.994 diff --git a/projet-vga.runs/impl_1/VGA_top_timing_summary_routed.rpx b/projet-vga.runs/impl_1/VGA_top_timing_summary_routed.rpx index 8926339..02e78a0 100644 Binary files a/projet-vga.runs/impl_1/VGA_top_timing_summary_routed.rpx and b/projet-vga.runs/impl_1/VGA_top_timing_summary_routed.rpx differ diff --git a/projet-vga.runs/impl_1/VGA_top_utilization_placed.pb b/projet-vga.runs/impl_1/VGA_top_utilization_placed.pb index a5a17f3..fd0779c 100644 Binary files a/projet-vga.runs/impl_1/VGA_top_utilization_placed.pb and b/projet-vga.runs/impl_1/VGA_top_utilization_placed.pb differ diff --git a/projet-vga.runs/impl_1/VGA_top_utilization_placed.rpt b/projet-vga.runs/impl_1/VGA_top_utilization_placed.rpt index 69aa6e0..0d1c939 100644 --- a/projet-vga.runs/impl_1/VGA_top_utilization_placed.rpt +++ b/projet-vga.runs/impl_1/VGA_top_utilization_placed.rpt @@ -1,8 +1,8 @@ Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. ----------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 -| Date : Tue Dec 7 12:43:23 2021 -| Host : irb121-02-w running 64-bit major release (build 9200) +| Date : Tue Jan 4 12:19:29 2022 +| Host : irb121-12-w running 64-bit major release (build 9200) | Command : report_utilization -file VGA_top_utilization_placed.rpt -pb VGA_top_utilization_placed.pb | Design : VGA_top | Device : 7z010clg400-1 @@ -31,14 +31,14 @@ Table of Contents +-------------------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +-------------------------+------+-------+-----------+-------+ -| Slice LUTs | 168 | 0 | 17600 | 0.95 | -| LUT as Logic | 168 | 0 | 17600 | 0.95 | +| Slice LUTs | 1491 | 0 | 17600 | 8.47 | +| LUT as Logic | 1491 | 0 | 17600 | 8.47 | | LUT as Memory | 0 | 0 | 6000 | 0.00 | -| Slice Registers | 21 | 0 | 35200 | 0.06 | -| Register as Flip Flop | 21 | 0 | 35200 | 0.06 | -| Register as Latch | 0 | 0 | 35200 | 0.00 | -| F7 Muxes | 0 | 0 | 8800 | 0.00 | -| F8 Muxes | 0 | 0 | 4400 | 0.00 | +| Slice Registers | 212 | 0 | 35200 | 0.60 | +| Register as Flip Flop | 189 | 0 | 35200 | 0.54 | +| Register as Latch | 23 | 0 | 35200 | 0.07 | +| F7 Muxes | 19 | 0 | 8800 | 0.22 | +| F8 Muxes | 1 | 0 | 4400 | 0.02 | +-------------------------+------+-------+-----------+-------+ @@ -54,10 +54,10 @@ Table of Contents | 0 | _ | Set | - | | 0 | _ | Reset | - | | 0 | Yes | - | - | -| 0 | Yes | - | Set | -| 0 | Yes | - | Reset | -| 0 | Yes | Set | - | -| 21 | Yes | Reset | - | +| 10 | Yes | - | Set | +| 87 | Yes | - | Reset | +| 1 | Yes | Set | - | +| 114 | Yes | Reset | - | +-------+--------------+-------------+--------------+ @@ -67,22 +67,22 @@ Table of Contents +--------------------------------------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +--------------------------------------------+------+-------+-----------+-------+ -| Slice | 61 | 0 | 4400 | 1.39 | -| SLICEL | 45 | 0 | | | -| SLICEM | 16 | 0 | | | -| LUT as Logic | 168 | 0 | 17600 | 0.95 | +| Slice | 541 | 0 | 4400 | 12.30 | +| SLICEL | 361 | 0 | | | +| SLICEM | 180 | 0 | | | +| LUT as Logic | 1491 | 0 | 17600 | 8.47 | | using O5 output only | 0 | | | | -| using O6 output only | 123 | | | | -| using O5 and O6 | 45 | | | | +| using O6 output only | 1193 | | | | +| using O5 and O6 | 298 | | | | | LUT as Memory | 0 | 0 | 6000 | 0.00 | | LUT as Distributed RAM | 0 | 0 | | | | LUT as Shift Register | 0 | 0 | | | -| Slice Registers | 21 | 0 | 35200 | 0.06 | -| Register driven from within the Slice | 20 | | | | -| Register driven from outside the Slice | 1 | | | | -| LUT in front of the register is unused | 0 | | | | -| LUT in front of the register is used | 1 | | | | -| Unique Control Sets | 2 | | 4400 | 0.05 | +| Slice Registers | 212 | 0 | 35200 | 0.60 | +| Register driven from within the Slice | 165 | | | | +| Register driven from outside the Slice | 47 | | | | +| LUT in front of the register is unused | 21 | | | | +| LUT in front of the register is used | 26 | | | | +| Unique Control Sets | 31 | | 4400 | 0.70 | +--------------------------------------------+------+-------+-----------+-------+ * Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets. @@ -90,13 +90,15 @@ Table of Contents 3. Memory --------- -+----------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+----------------+------+-------+-----------+-------+ -| Block RAM Tile | 0 | 0 | 60 | 0.00 | -| RAMB36/FIFO* | 0 | 0 | 60 | 0.00 | -| RAMB18 | 0 | 0 | 120 | 0.00 | -+----------------+------+-------+-----------+-------+ ++-------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------+------+-------+-----------+-------+ +| Block RAM Tile | 22.5 | 0 | 60 | 37.50 | +| RAMB36/FIFO* | 18 | 0 | 60 | 30.00 | +| RAMB36E1 only | 18 | | | | +| RAMB18 | 9 | 0 | 120 | 7.50 | +| RAMB18E1 only | 9 | | | | ++-------------------+------+-------+-----------+-------+ * Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 @@ -116,9 +118,9 @@ Table of Contents +-----------------------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +-----------------------------+------+-------+-----------+-------+ -| Bonded IOB | 19 | 19 | 100 | 19.00 | -| IOB Master Pads | 9 | | | | -| IOB Slave Pads | 9 | | | | +| Bonded IOB | 24 | 24 | 100 | 24.00 | +| IOB Master Pads | 10 | | | | +| IOB Slave Pads | 12 | | | | | Bonded IPADs | 0 | 0 | 2 | 0.00 | | Bonded IOPADs | 0 | 0 | 130 | 0.00 | | PHY_CONTROL | 0 | 0 | 2 | 0.00 | @@ -141,7 +143,7 @@ Table of Contents +------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +------------+------+-------+-----------+-------+ -| BUFGCTRL | 2 | 0 | 32 | 6.25 | +| BUFGCTRL | 3 | 0 | 32 | 9.38 | | BUFIO | 0 | 0 | 8 | 0.00 | | MMCME2_ADV | 1 | 0 | 2 | 50.00 | | PLLE2_ADV | 0 | 0 | 2 | 0.00 | @@ -174,18 +176,27 @@ Table of Contents +------------+------+---------------------+ | Ref Name | Used | Functional Category | +------------+------+---------------------+ -| LUT4 | 64 | LUT | -| LUT6 | 63 | LUT | -| LUT5 | 47 | LUT | -| CARRY4 | 34 | CarryLogic | -| LUT2 | 28 | LUT | -| FDRE | 21 | Flop & Latch | -| OBUF | 18 | IO | -| LUT3 | 7 | LUT | -| LUT1 | 4 | LUT | -| BUFG | 2 | Clock | +| LUT6 | 447 | LUT | +| LUT4 | 365 | LUT | +| LUT5 | 358 | LUT | +| LUT3 | 332 | LUT | +| LUT2 | 275 | LUT | +| CARRY4 | 266 | CarryLogic | +| FDRE | 114 | Flop & Latch | +| FDCE | 64 | Flop & Latch | +| LDCE | 23 | Flop & Latch | +| OBUF | 21 | IO | +| MUXF7 | 19 | MuxFx | +| RAMB36E1 | 18 | Block Memory | +| LUT1 | 12 | LUT | +| FDPE | 10 | Flop & Latch | +| RAMB18E1 | 9 | Block Memory | +| BUFG | 3 | Clock | +| IBUF | 2 | IO | +| OBUFT | 1 | IO | +| MUXF8 | 1 | MuxFx | | MMCME2_ADV | 1 | Clock | -| IBUF | 1 | IO | +| FDSE | 1 | Flop & Latch | +------------+------+---------------------+ diff --git a/projet-vga.runs/impl_1/gen_run.xml b/projet-vga.runs/impl_1/gen_run.xml index 6d4e04c..4a8ab30 100644 --- a/projet-vga.runs/impl_1/gen_run.xml +++ b/projet-vga.runs/impl_1/gen_run.xml @@ -1,5 +1,5 @@ - + @@ -71,52 +71,83 @@ - + - + - + + + + + + + + - + - + - + - + + + + + + + + + + + + + + + + + + + - + + + + + + + + - @@ -129,7 +160,7 @@ - + diff --git a/projet-vga.runs/impl_1/init_design.pb b/projet-vga.runs/impl_1/init_design.pb index bc39176..974d02d 100644 Binary files a/projet-vga.runs/impl_1/init_design.pb and b/projet-vga.runs/impl_1/init_design.pb differ diff --git a/projet-vga.runs/impl_1/opt_design.pb b/projet-vga.runs/impl_1/opt_design.pb index de5babb..54696cd 100644 Binary files a/projet-vga.runs/impl_1/opt_design.pb and b/projet-vga.runs/impl_1/opt_design.pb differ diff --git a/projet-vga.runs/impl_1/place_design.pb b/projet-vga.runs/impl_1/place_design.pb index b712d7f..8ea1b48 100644 Binary files a/projet-vga.runs/impl_1/place_design.pb and b/projet-vga.runs/impl_1/place_design.pb differ diff --git a/projet-vga.runs/impl_1/project.wdf b/projet-vga.runs/impl_1/project.wdf index 20c99f7..b3acc94 100644 --- a/projet-vga.runs/impl_1/project.wdf +++ b/projet-vga.runs/impl_1/project.wdf @@ -1,5 +1,5 @@ version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:38:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:3133:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 @@ -29,4 +29,4 @@ version:1 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:32:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:32:00:00 5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3535383763343761323538363466333061393431643931396134353838663432:506172656e742050412070726f6a656374204944:00 -eof:1227587853 +eof:2824691014 diff --git a/projet-vga.runs/impl_1/route_design.pb b/projet-vga.runs/impl_1/route_design.pb index c045f4e..9b07742 100644 Binary files a/projet-vga.runs/impl_1/route_design.pb and b/projet-vga.runs/impl_1/route_design.pb differ diff --git a/projet-vga.runs/impl_1/rundef.js b/projet-vga.runs/impl_1/rundef.js index e6878e5..b2810cb 100644 --- a/projet-vga.runs/impl_1/rundef.js +++ b/projet-vga.runs/impl_1/rundef.js @@ -23,7 +23,7 @@ eval( EAInclude(ISEJScriptLib) ); // pre-commands: -ISETouchFile( "write_bitstream", "begin" ); +ISETouchFile( "init_design", "begin" ); ISEStep( "vivado", "-log VGA_top.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace" ); diff --git a/projet-vga.runs/impl_1/runme.log b/projet-vga.runs/impl_1/runme.log index 1d1bb5f..94fb40f 100644 --- a/projet-vga.runs/impl_1/runme.log +++ b/projet-vga.runs/impl_1/runme.log @@ -12,29 +12,32 @@ source VGA_top.tcl -notrace Command: link_design -top VGA_top -part xc7z010clg400-1 Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 -INFO: [Project 1-454] Reading design checkpoint 'c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.dcp' for cell 'U0' -INFO: [Netlist 29-17] Analyzing 35 Unisim elements for replacement +INFO: [Project 1-454] Reading design checkpoint 'c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0.dcp' for cell 'U0' +INFO: [Netlist 29-17] Analyzing 314 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2018.3 INFO: [Device 21-403] Loading part xc7z010clg400-1 INFO: [Project 1-570] Preparing netlist for logic optimization -Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst' -Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] for cell 'U0/inst' -Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst' -INFO: [Timing 38-35] Done setting XDC timing constraints. [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57] -INFO: [Timing 38-2] Deriving generated clocks [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc:57] -get_clocks: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1248.586 ; gain = 558.375 -Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] for cell 'U0/inst' -Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc] -Finished Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc] +WARNING: [Opt 31-35] Removing redundant IBUF, U0/inst/clkin1_ibufg, from the path connected to top-level port: H125MHz +Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design. +WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'U0/clk_in1' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. +Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0_board.xdc] for cell 'U0/inst' +Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0_board.xdc] for cell 'U0/inst' +Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0.xdc] for cell 'U0/inst' +INFO: [Timing 38-35] Done setting XDC timing constraints. [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0.xdc:57] +INFO: [Timing 38-2] Deriving generated clocks [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0.xdc:57] +get_clocks: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1251.785 ; gain = 552.953 +Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0.xdc] for cell 'U0/inst' +Parsing XDC File [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/ZYBO_Master.xdc] +Finished Parsing XDC File [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/ZYBO_Master.xdc] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1248.586 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1251.785 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. -10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +10 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. link_design completed successfully -link_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:16 . Memory (MB): peak = 1248.586 ; gain = 885.598 +link_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:25 . Memory (MB): peak = 1251.785 ; gain = 888.395 Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' @@ -45,57 +48,58 @@ INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.499 . Memory (MB): peak = 1248.586 ; gain = 0.000 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.501 . Memory (MB): peak = 1251.785 ; gain = 0.000 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [Timing 38-2] Deriving generated clocks -Ending Cache Timing Information Task | Checksum: 20ae1d4cd +Ending Cache Timing Information Task | Checksum: 19f3e8d5f -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1265.152 ; gain = 16.566 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.092 . Memory (MB): peak = 1265.977 ; gain = 14.191 Starting Logic Optimization Task Phase 1 Retarget INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). -Phase 1 Retarget | Checksum: ddde5939 +Phase 1 Retarget | Checksum: c8a6b5ae -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 1351.098 ; gain = 0.000 -INFO: [Opt 31-389] Phase Retarget created 4 cells and removed 4 cells +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.096 . Memory (MB): peak = 1346.285 ; gain = 0.000 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 2 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Phase 2 Constant propagation | Checksum: ddde5939 +Phase 2 Constant propagation | Checksum: 1409f9166 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1351.098 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.123 . Memory (MB): peak = 1346.285 ; gain = 0.000 INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells Phase 3 Sweep -Phase 3 Sweep | Checksum: fec5e707 +Phase 3 Sweep | Checksum: 1b7440179 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 1351.098 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.178 . Memory (MB): peak = 1346.285 ; gain = 0.000 INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells +INFO: [Opt 31-1021] In phase Sweep, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 4 BUFG optimization INFO: [Opt 31-194] Inserted BUFG U0/inst/clk_out1_clk_wiz_1_BUFG_inst to drive 0 load(s) on clock net U0/inst/clk_out1_clk_wiz_1_BUFG -INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets -Phase 4 BUFG optimization | Checksum: 137e6b9d1 +INFO: [Opt 31-194] Inserted BUFG H125MHz_IBUF_BUFG_inst to drive 182 load(s) on clock net H125MHz_IBUF_BUFG +INFO: [Opt 31-193] Inserted 2 BUFG(s) on clock nets +Phase 4 BUFG optimization | Checksum: cecab300 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1351.098 ; gain = 0.000 -INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.259 . Memory (MB): peak = 1346.285 ; gain = 0.000 +INFO: [Opt 31-662] Phase BUFG optimization created 1 cells of which 1 are BUFGs and removed 0 cells. Phase 5 Shift Register Optimization -Phase 5 Shift Register Optimization | Checksum: 12c29fba6 +Phase 5 Shift Register Optimization | Checksum: 193828ea0 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.054 . Memory (MB): peak = 1351.098 ; gain = 0.000 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.412 . Memory (MB): peak = 1346.285 ; gain = 0.000 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 6 Post Processing Netlist -Phase 6 Post Processing Netlist | Checksum: 10c49128f +Phase 6 Post Processing Netlist | Checksum: 16ceef5f4 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.055 . Memory (MB): peak = 1351.098 ; gain = 0.000 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.421 . Memory (MB): peak = 1346.285 ; gain = 0.000 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells Opt_design Change Summary ========================= @@ -104,10 +108,10 @@ Opt_design Change Summary ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- -| Retarget | 4 | 4 | 1 | +| Retarget | 0 | 0 | 1 | | Constant propagation | 0 | 0 | 0 | -| Sweep | 0 | 0 | 0 | -| BUFG optimization | 0 | 0 | 0 | +| Sweep | 0 | 0 | 1 | +| BUFG optimization | 1 | 0 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 0 | 0 | ------------------------------------------------------------------------------------------------------------------------- @@ -116,44 +120,70 @@ Opt_design Change Summary Starting Connectivity Check Task -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1351.098 ; gain = 0.000 -Ending Logic Optimization Task | Checksum: e54fefee +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1346.285 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 20356351c -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.057 . Memory (MB): peak = 1351.098 ; gain = 0.000 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.429 . Memory (MB): peak = 1346.285 ; gain = 0.000 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. -Ending Power Optimization Task | Checksum: e54fefee +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-4.133 | TNS=-46.099 | +Running Vector-less Activity Propagation... -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1351.098 ; gain = 0.000 +Finished Running Vector-less Activity Propagation +INFO: [Pwropt 34-9] Applying IDT optimizations ... +INFO: [Pwropt 34-10] Applying ODC optimizations ... + + +Starting PowerOpt Patch Enables Task +INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 27 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. +INFO: [Pwropt 34-201] Structural ODC has moved 16 WE to EN ports +Number of BRAM Ports augmented: 0 newly gated: 25 Total Ports: 54 +Number of Flops added for Enable Generation: 2 + +Ending PowerOpt Patch Enables Task | Checksum: 215f1437d + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.085 . Memory (MB): peak = 1500.016 ; gain = 0.000 +Ending Power Optimization Task | Checksum: 215f1437d + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1500.016 ; gain = 153.730 Starting Final Cleanup Task -Ending Final Cleanup Task | Checksum: e54fefee -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000 +Starting Logic Optimization Task +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Opt 31-194] Inserted BUFG U0/inst/clk_out1_clk_wiz_1_BUFG_inst to drive 0 load(s) on clock net U0/inst/clk_out1_clk_wiz_1_BUFG +INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets +Ending Logic Optimization Task | Checksum: 2182f781c + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.228 . Memory (MB): peak = 1500.016 ; gain = 0.000 +Ending Final Cleanup Task | Checksum: 2182f781c + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.967 . Memory (MB): peak = 1500.016 ; gain = 0.000 Starting Netlist Obfuscation Task -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000 -Ending Netlist Obfuscation Task | Checksum: e54fefee +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1500.016 ; gain = 0.000 +Ending Netlist Obfuscation Task | Checksum: 2182f781c -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1500.016 ; gain = 0.000 INFO: [Common 17-83] Releasing license: Implementation -30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +40 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1500.016 ; gain = 0.000 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1351.098 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_opt.dcp' has been generated. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.035 . Memory (MB): peak = 1500.016 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1500.016 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/impl_1/VGA_top_opt.dcp' has been generated. INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx Command: report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_opted.rpt. +INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/impl_1/VGA_top_drc_opted.rpt. report_drc completed successfully Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' @@ -172,48 +202,56 @@ INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000 -Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 4ed236ad +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1500.016 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 131936915 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1351.098 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1500.016 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1500.016 ; gain = 0.000 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1a1c16c9c +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: d8624408 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.262 . Memory (MB): peak = 1351.098 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.459 . Memory (MB): peak = 1500.016 ; gain = 0.000 Phase 1.3 Build Placer Netlist Model -Phase 1.3 Build Placer Netlist Model | Checksum: 2939760d0 +Phase 1.3 Build Placer Netlist Model | Checksum: 1315496dd -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.351 . Memory (MB): peak = 1351.098 ; gain = 0.000 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.837 . Memory (MB): peak = 1500.016 ; gain = 0.000 Phase 1.4 Constrain Clocks/Macros -Phase 1.4 Constrain Clocks/Macros | Checksum: 2939760d0 +Phase 1.4 Constrain Clocks/Macros | Checksum: 1315496dd -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.353 . Memory (MB): peak = 1351.098 ; gain = 0.000 -Phase 1 Placer Initialization | Checksum: 2939760d0 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.840 . Memory (MB): peak = 1500.016 ; gain = 0.000 +Phase 1 Placer Initialization | Checksum: 1315496dd -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.353 . Memory (MB): peak = 1351.098 ; gain = 0.000 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.843 . Memory (MB): peak = 1500.016 ; gain = 0.000 Phase 2 Global Placement Phase 2.1 Floorplanning -Phase 2.1 Floorplanning | Checksum: 28231f14d +Phase 2.1 Floorplanning | Checksum: 1a8bfe1e0 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.397 . Memory (MB): peak = 1351.098 ; gain = 0.000 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.991 . Memory (MB): peak = 1500.016 ; gain = 0.000 Phase 2.2 Physical Synthesis In Placer INFO: [Physopt 32-65] No nets found for high-fanout optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell -INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed. -INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed. -INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed. +INFO: [Physopt 32-117] Net SNAKE/listRefs[8][0] could not be optimized because driver SNAKE/mem_reg_3_i_4 could not be replicated +INFO: [Physopt 32-117] Net SNAKE/listRefs[6][2] could not be optimized because driver SNAKE/mem_reg_1_i_4 could not be replicated +INFO: [Physopt 32-68] No nets found for critical-cell optimization. +INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. +INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-949] No candidate nets found for HD net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1351.098 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1500.016 ; gain = 0.000 Summary of Physical Synthesis Optimizations ============================================ @@ -223,60 +261,71 @@ Summary of Physical Synthesis Optimizations | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ---------------------------------------------------------------------------------------------------------------------------------------- | Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | +| Critical Cell | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| BRAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | HD Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| Total | 0 | 0 | 0 | 0 | 2 | 00:00:00 | +| Total | 0 | 0 | 0 | 0 | 6 | 00:00:00 | ---------------------------------------------------------------------------------------------------------------------------------------- -Phase 2.2 Physical Synthesis In Placer | Checksum: 22348ffd6 +Phase 2.2 Physical Synthesis In Placer | Checksum: aaf1c87e -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000 -Phase 2 Global Placement | Checksum: 2038a7242 +Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1500.016 ; gain = 0.000 +Phase 2 Global Placement | Checksum: 17a0bd3eb -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000 +Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1500.016 ; gain = 0.000 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros -Phase 3.1 Commit Multi Column Macros | Checksum: 2038a7242 +Phase 3.1 Commit Multi Column Macros | Checksum: 17a0bd3eb -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000 +Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 1500.016 ; gain = 0.000 Phase 3.2 Commit Most Macros & LUTRAMs -Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 2c58c3354 +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 18c86a722 -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000 +Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1500.016 ; gain = 0.000 Phase 3.3 Area Swap Optimization -Phase 3.3 Area Swap Optimization | Checksum: 279aeb7b4 +Phase 3.3 Area Swap Optimization | Checksum: 19f5ea993 -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000 +Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1500.016 ; gain = 0.000 Phase 3.4 Pipeline Register Optimization -Phase 3.4 Pipeline Register Optimization | Checksum: 279aeb7b4 +Phase 3.4 Pipeline Register Optimization | Checksum: 1bfb8a901 -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000 +Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1500.016 ; gain = 0.000 -Phase 3.5 Small Shape Detail Placement -Phase 3.5 Small Shape Detail Placement | Checksum: 1e0aaeea1 +Phase 3.5 Fast Optimization +Phase 3.5 Fast Optimization | Checksum: 108c906c7 -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 1500.016 ; gain = 0.000 -Phase 3.6 Re-assign LUT pins -Phase 3.6 Re-assign LUT pins | Checksum: 2d338840d +Phase 3.6 Small Shape Detail Placement +Phase 3.6 Small Shape Detail Placement | Checksum: 1f5ba145a -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000 +Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 1500.016 ; gain = 0.000 -Phase 3.7 Pipeline Register Optimization -Phase 3.7 Pipeline Register Optimization | Checksum: 2d338840d +Phase 3.7 Re-assign LUT pins +Phase 3.7 Re-assign LUT pins | Checksum: 1ca5326f1 -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000 -Phase 3 Detail Placement | Checksum: 2d338840d +Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 1500.016 ; gain = 0.000 -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1351.098 ; gain = 0.000 +Phase 3.8 Pipeline Register Optimization +Phase 3.8 Pipeline Register Optimization | Checksum: 1aa2d2687 + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 1500.016 ; gain = 0.000 + +Phase 3.9 Fast Optimization +Phase 3.9 Fast Optimization | Checksum: a4f5789a + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 1500.016 ; gain = 0.000 +Phase 3 Detail Placement | Checksum: a4f5789a + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 1500.016 ; gain = 0.000 Phase 4 Post Placement Optimization and Clean-Up @@ -284,59 +333,60 @@ Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization -Post Placement Optimization Initialization | Checksum: 15c68dcd4 +Post Placement Optimization Initialization | Checksum: 100368e26 Phase 4.1.1.1 BUFG Insertion INFO: [Place 46-46] BUFG insertion identified 0 candidate nets, 0 success, 0 bufg driver replicated, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason -Phase 4.1.1.1 BUFG Insertion | Checksum: 15c68dcd4 +Phase 4.1.1.1 BUFG Insertion | Checksum: 100368e26 -Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1351.098 ; gain = 0.000 -INFO: [Place 30-746] Post Placement Timing Summary WNS=35.245. For the most accurate timing information please run report_timing. -Phase 4.1.1 Post Placement Optimization | Checksum: 142e419cd +Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 1500.016 ; gain = 0.000 +INFO: [Place 30-746] Post Placement Timing Summary WNS=-3.374. For the most accurate timing information please run report_timing. +Phase 4.1.1 Post Placement Optimization | Checksum: be8bba9e -Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1351.098 ; gain = 0.000 -Phase 4.1 Post Commit Optimization | Checksum: 142e419cd +Time (s): cpu = 00:00:18 ; elapsed = 00:00:16 . Memory (MB): peak = 1500.016 ; gain = 0.000 +Phase 4.1 Post Commit Optimization | Checksum: be8bba9e -Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1351.098 ; gain = 0.000 +Time (s): cpu = 00:00:18 ; elapsed = 00:00:17 . Memory (MB): peak = 1500.016 ; gain = 0.000 Phase 4.2 Post Placement Cleanup -Phase 4.2 Post Placement Cleanup | Checksum: 142e419cd +Phase 4.2 Post Placement Cleanup | Checksum: be8bba9e -Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1351.098 ; gain = 0.000 +Time (s): cpu = 00:00:18 ; elapsed = 00:00:17 . Memory (MB): peak = 1500.016 ; gain = 0.000 Phase 4.3 Placer Reporting -Phase 4.3 Placer Reporting | Checksum: 142e419cd +Phase 4.3 Placer Reporting | Checksum: be8bba9e -Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1351.098 ; gain = 0.000 +Time (s): cpu = 00:00:18 ; elapsed = 00:00:17 . Memory (MB): peak = 1500.016 ; gain = 0.000 Phase 4.4 Final Placement Cleanup -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000 -Phase 4.4 Final Placement Cleanup | Checksum: 20695260e +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1500.016 ; gain = 0.000 +Phase 4.4 Final Placement Cleanup | Checksum: 540ff3bc -Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1351.098 ; gain = 0.000 -Phase 4 Post Placement Optimization and Clean-Up | Checksum: 20695260e +Time (s): cpu = 00:00:18 ; elapsed = 00:00:17 . Memory (MB): peak = 1500.016 ; gain = 0.000 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 540ff3bc -Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1351.098 ; gain = 0.000 -Ending Placer Task | Checksum: 1f2b3c1b8 +Time (s): cpu = 00:00:18 ; elapsed = 00:00:17 . Memory (MB): peak = 1500.016 ; gain = 0.000 +Ending Placer Task | Checksum: 531de2ac -Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1351.098 ; gain = 0.000 +Time (s): cpu = 00:00:18 ; elapsed = 00:00:17 . Memory (MB): peak = 1500.016 ; gain = 0.000 INFO: [Common 17-83] Releasing license: Implementation -57 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +75 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000 +place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:17 . Memory (MB): peak = 1500.016 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1500.016 ; gain = 0.000 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1500.016 ; gain = 0.000 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.050 . Memory (MB): peak = 1351.098 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1351.098 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_placed.dcp' has been generated. +Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.200 . Memory (MB): peak = 1500.016 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/impl_1/VGA_top_placed.dcp' has been generated. INFO: [runtcl-4] Executing : report_io -file VGA_top_io_placed.rpt -report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1351.098 ; gain = 0.000 +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.040 . Memory (MB): peak = 1500.016 ; gain = 0.000 INFO: [runtcl-4] Executing : report_utilization -file VGA_top_utilization_placed.rpt -pb VGA_top_utilization_placed.pb INFO: [runtcl-4] Executing : report_control_sets -verbose -file VGA_top_control_sets_placed.rpt -report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1351.098 ; gain = 0.000 +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1500.016 ; gain = 0.000 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' @@ -348,98 +398,150 @@ INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more in Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs -Checksum: PlaceDB: f9e7c0c6 ConstDB: 0 ShapeSum: f8cc00f2 RouteDB: 0 +Checksum: PlaceDB: 3ad47cdf ConstDB: 0 ShapeSum: 184965cd RouteDB: 0 Phase 1 Build RT Design -Phase 1 Build RT Design | Checksum: 9a64d846 +Phase 1 Build RT Design | Checksum: 13e412dc8 -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1417.348 ; gain = 66.250 -Post Restoration Checksum: NetGraph: 7c5b36de NumContArr: 1e09a168 Constraints: 0 Timing: 0 +Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1500.016 ; gain = 0.000 +Post Restoration Checksum: NetGraph: 58741a68 NumContArr: e5cd1360 Constraints: 0 Timing: 0 Phase 2 Router Initialization Phase 2.1 Create Timer -Phase 2.1 Create Timer | Checksum: 9a64d846 +Phase 2.1 Create Timer | Checksum: 13e412dc8 -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1449.676 ; gain = 98.578 +Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1500.016 ; gain = 0.000 Phase 2.2 Fix Topology Constraints -Phase 2.2 Fix Topology Constraints | Checksum: 9a64d846 +Phase 2.2 Fix Topology Constraints | Checksum: 13e412dc8 -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1455.699 ; gain = 104.602 +Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1500.016 ; gain = 0.000 Phase 2.3 Pre Route Cleanup -Phase 2.3 Pre Route Cleanup | Checksum: 9a64d846 +Phase 2.3 Pre Route Cleanup | Checksum: 13e412dc8 -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1455.699 ; gain = 104.602 +Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1500.016 ; gain = 0.000 Number of Nodes with overlaps = 0 Phase 2.4 Update Timing -Phase 2.4 Update Timing | Checksum: 82bae049 +Phase 2.4 Update Timing | Checksum: 1195a0f5b -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1460.445 ; gain = 109.348 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=35.391 | TNS=0.000 | WHS=-0.239 | THS=-2.915 | +Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1500.016 ; gain = 0.000 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=-3.513 | TNS=-50.092| WHS=-1.636 | THS=-51.724| -Phase 2 Router Initialization | Checksum: cf693307 +Phase 2 Router Initialization | Checksum: 12ae7c807 -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1460.445 ; gain = 109.348 +Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1500.016 ; gain = 0.000 Phase 3 Initial Routing -Phase 3 Initial Routing | Checksum: 16fee48da +Phase 3 Initial Routing | Checksum: 1b62d99da -Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348 +Time (s): cpu = 00:00:24 ; elapsed = 00:00:17 . Memory (MB): peak = 1546.250 ; gain = 46.234 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 - Number of Nodes with overlaps = 36 + Number of Nodes with overlaps = 954 + Number of Nodes with overlaps = 235 + Number of Nodes with overlaps = 66 + Number of Nodes with overlaps = 42 + Number of Nodes with overlaps = 19 + Number of Nodes with overlaps = 16 + Number of Nodes with overlaps = 15 + Number of Nodes with overlaps = 7 + Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=33.088 | TNS=0.000 | WHS=N/A | THS=N/A | +INFO: [Route 35-416] Intermediate Timing Summary | WNS=-5.639 | TNS=-90.744| WHS=N/A | THS=N/A | -Phase 4.1 Global Iteration 0 | Checksum: 1c93f85f6 +Phase 4.1 Global Iteration 0 | Checksum: 1a754acba -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348 -Phase 4 Rip-up And Reroute | Checksum: 1c93f85f6 +Time (s): cpu = 00:01:24 ; elapsed = 00:01:06 . Memory (MB): peak = 1596.598 ; gain = 96.582 -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348 +Phase 4.2 Global Iteration 1 + Number of Nodes with overlaps = 146 + Number of Nodes with overlaps = 24 + Number of Nodes with overlaps = 9 + Number of Nodes with overlaps = 8 + Number of Nodes with overlaps = 8 + Number of Nodes with overlaps = 5 + Number of Nodes with overlaps = 7 + Number of Nodes with overlaps = 5 + Number of Nodes with overlaps = 5 + Number of Nodes with overlaps = 2 + Number of Nodes with overlaps = 2 + Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 7 + Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 6 + Number of Nodes with overlaps = 0 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=-5.630 | TNS=-88.178| WHS=N/A | THS=N/A | + +Phase 4.2 Global Iteration 1 | Checksum: 13f25b21c + +Time (s): cpu = 00:02:20 ; elapsed = 00:01:46 . Memory (MB): peak = 1630.195 ; gain = 130.180 +Phase 4 Rip-up And Reroute | Checksum: 13f25b21c + +Time (s): cpu = 00:02:20 ; elapsed = 00:01:46 . Memory (MB): peak = 1630.195 ; gain = 130.180 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp -Phase 5.1 Delay CleanUp | Checksum: 1c93f85f6 -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348 +Phase 5.1.1 Update Timing +Phase 5.1.1 Update Timing | Checksum: 21c9bd585 + +Time (s): cpu = 00:02:20 ; elapsed = 00:01:46 . Memory (MB): peak = 1630.195 ; gain = 130.180 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=-5.617 | TNS=-86.848| WHS=N/A | THS=N/A | + + Number of Nodes with overlaps = 0 +Phase 5.1 Delay CleanUp | Checksum: e7e5e811 + +Time (s): cpu = 00:02:20 ; elapsed = 00:01:46 . Memory (MB): peak = 1630.195 ; gain = 130.180 Phase 5.2 Clock Skew Optimization -Phase 5.2 Clock Skew Optimization | Checksum: 1c93f85f6 +Phase 5.2 Clock Skew Optimization | Checksum: e7e5e811 -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348 -Phase 5 Delay and Skew Optimization | Checksum: 1c93f85f6 +Time (s): cpu = 00:02:20 ; elapsed = 00:01:46 . Memory (MB): peak = 1630.195 ; gain = 130.180 +Phase 5 Delay and Skew Optimization | Checksum: e7e5e811 -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348 +Time (s): cpu = 00:02:20 ; elapsed = 00:01:46 . Memory (MB): peak = 1630.195 ; gain = 130.180 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing -Phase 6.1.1 Update Timing | Checksum: 144941f51 +Phase 6.1.1 Update Timing | Checksum: ef9abc12 -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=33.241 | TNS=0.000 | WHS=0.083 | THS=0.000 | +Time (s): cpu = 00:02:21 ; elapsed = 00:01:47 . Memory (MB): peak = 1630.195 ; gain = 130.180 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=-5.617 | TNS=-86.439| WHS=-0.443 | THS=-0.849 | -Phase 6.1 Hold Fix Iter | Checksum: 144941f51 +Phase 6.1 Hold Fix Iter | Checksum: 151f6c881 -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348 -Phase 6 Post Hold Fix | Checksum: 144941f51 +Time (s): cpu = 00:02:22 ; elapsed = 00:01:48 . Memory (MB): peak = 1630.195 ; gain = 130.180 +WARNING: [Route 35-468] The router encountered 388 pins that are both setup-critical and hold-critical and tried to fix hold violations at the expense of setup slack. Such pins are: + RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_302/I0 + SYNC/ROMAddress_reg[3]_i_146/DI[3] + SYNC/ROMAddress_reg[9]_i_237/DI[3] + SYNC/ROMAddress[9]_i_588/I0 + SYNC/ROMAddress[9]_i_595/I0 + RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_589/I1 + RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_624/I1 + SYNC/ROMAddress_reg[9]_i_237/DI[2] + SYNC/ROMAddress_reg[9]_i_266/DI[2] + SYNC/ROMAddress[3]_i_103/I5 + .. and 378 more pins. -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348 +Phase 6 Post Hold Fix | Checksum: 197295544 + +Time (s): cpu = 00:02:22 ; elapsed = 00:01:48 . Memory (MB): peak = 1630.195 ; gain = 130.180 Phase 7 Route finalize Router Utilization Summary - Global Vertical Routing Utilization = 0.0881194 % - Global Horizontal Routing Utilization = 0.100414 % + Global Vertical Routing Utilization = 2.83094 % + Global Horizontal Routing Utilization = 3.41935 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. @@ -448,58 +550,90 @@ Router Utilization Summary Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 -Phase 7 Route finalize | Checksum: 19cea99c1 +Congestion Report +North Dir 1x1 Area, Max Cong = 54.0541%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 79.2793%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 60.2941%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 75%, No Congested Regions. -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1460.445 ; gain = 109.348 +------------------------------ +Reporting congestion hotspots +------------------------------ +Direction: North +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: South +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: East +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: West +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 + +Phase 7 Route finalize | Checksum: 1f1dffd6a + +Time (s): cpu = 00:02:22 ; elapsed = 00:01:48 . Memory (MB): peak = 1630.195 ; gain = 130.180 Phase 8 Verifying routed nets Verification completed successfully -Phase 8 Verifying routed nets | Checksum: 19cea99c1 +Phase 8 Verifying routed nets | Checksum: 1f1dffd6a -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1461.477 ; gain = 110.379 +Time (s): cpu = 00:02:22 ; elapsed = 00:01:48 . Memory (MB): peak = 1630.195 ; gain = 130.180 Phase 9 Depositing Routes -Phase 9 Depositing Routes | Checksum: 17f26a4e0 +Phase 9 Depositing Routes | Checksum: 238ddaa41 -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1461.477 ; gain = 110.379 +Time (s): cpu = 00:02:23 ; elapsed = 00:01:49 . Memory (MB): peak = 1630.195 ; gain = 130.180 Phase 10 Post Router Timing -INFO: [Route 35-57] Estimated Timing Summary | WNS=33.241 | TNS=0.000 | WHS=0.083 | THS=0.000 | -INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. -Phase 10 Post Router Timing | Checksum: 17f26a4e0 +Phase 10.1 Update Timing +Phase 10.1 Update Timing | Checksum: 1f42f7dac -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1461.477 ; gain = 110.379 +Time (s): cpu = 00:02:23 ; elapsed = 00:01:49 . Memory (MB): peak = 1630.195 ; gain = 130.180 +INFO: [Route 35-57] Estimated Timing Summary | WNS=-5.617 | TNS=-86.439| WHS=-0.027 | THS=-0.027 | + +WARNING: [Route 35-328] Router estimated timing not met. +Resolution: For a complete and accurate timing signoff, report_timing_summary must be run after route_design. Alternatively, route_design can be run with the -timing_summary option to enable a complete timing signoff at the end of route_design. +Phase 10 Post Router Timing | Checksum: 1f42f7dac + +Time (s): cpu = 00:02:23 ; elapsed = 00:01:49 . Memory (MB): peak = 1630.195 ; gain = 130.180 INFO: [Route 35-16] Router Completed Successfully -Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 1461.477 ; gain = 110.379 +Time (s): cpu = 00:02:23 ; elapsed = 00:01:49 . Memory (MB): peak = 1630.195 ; gain = 130.180 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation -74 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +93 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully -route_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:22 . Memory (MB): peak = 1461.477 ; gain = 110.379 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1461.477 ; gain = 0.000 +route_design: Time (s): cpu = 00:02:25 ; elapsed = 00:01:52 . Memory (MB): peak = 1630.195 ; gain = 130.180 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1630.195 ; gain = 0.000 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1630.195 ; gain = 0.000 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.054 . Memory (MB): peak = 1461.910 ; gain = 0.434 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1461.910 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_routed.dcp' has been generated. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.257 . Memory (MB): peak = 1630.195 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/impl_1/VGA_top_routed.dcp' has been generated. INFO: [runtcl-4] Executing : report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx Command: report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_drc_routed.rpt. +INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/impl_1/VGA_top_drc_routed.rpt. report_drc completed successfully INFO: [runtcl-4] Executing : report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx Command: report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [DRC 23-133] Running Methodology with 2 threads -INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top_methodology_drc_routed.rpt. +INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/impl_1/VGA_top_methodology_drc_routed.rpt. report_methodology completed successfully INFO: [runtcl-4] Executing : report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx Command: report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx @@ -507,66 +641,33 @@ INFO: [Timing 38-35] Done setting XDC timing constraints. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation -86 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +105 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. report_power completed successfully INFO: [runtcl-4] Executing : report_route_status -file VGA_top_route_status.rpt -pb VGA_top_route_status.pb INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file VGA_top_timing_summary_routed.rpt -pb VGA_top_timing_summary_routed.pb -rpx VGA_top_timing_summary_routed.rpx -warn_on_violation INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +CRITICAL WARNING: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations. INFO: [runtcl-4] Executing : report_incremental_reuse -file VGA_top_incremental_reuse_routed.rpt INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. INFO: [runtcl-4] Executing : report_clock_utilization -file VGA_top_clock_utilization_routed.rpt INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file VGA_top_bus_skew_routed.rpt -pb VGA_top_bus_skew_routed.pb -rpx VGA_top_bus_skew_routed.rpx INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs -INFO: [Common 17-206] Exiting Vivado at Tue Dec 7 12:43:48 2021... - -*** Running vivado - with args -log VGA_top.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace - - -****** Vivado v2018.3 (64-bit) - **** SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 - **** IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 - ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. - -source VGA_top.tcl -notrace -Command: open_checkpoint VGA_top_routed.dcp - -Starting open_checkpoint Task - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 250.652 ; gain = 0.000 -INFO: [Netlist 29-17] Analyzing 35 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-479] Netlist was created with Vivado 2018.3 -INFO: [Device 21-403] Loading part xc7z010clg400-1 -INFO: [Project 1-570] Preparing netlist for logic optimization -INFO: [Timing 38-478] Restoring timing data from binary archive. -INFO: [Timing 38-479] Binary timing data restore complete. -INFO: [Project 1-856] Restoring constraints from binary archive. -INFO: [Project 1-853] Binary constraint restore complete. -Reading XDEF placement. -Reading placer database... -Reading XDEF routing. -Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.095 . Memory (MB): peak = 1208.145 ; gain = 0.000 -Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB | -Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.095 . Memory (MB): peak = 1208.145 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1208.145 ; gain = 0.000 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -INFO: [Project 1-604] Checkpoint was created with Vivado v2018.3 (64-bit) build 2405991 -open_checkpoint: Time (s): cpu = 00:00:12 ; elapsed = 00:00:17 . Memory (MB): peak = 1208.145 ; gain = 957.492 Command: write_bitstream -force VGA_top.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' Running DRC as a precondition to command write_bitstream -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1704] No user IP repositories specified -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2018.3/data/ip'. +INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [DRC 23-27] Running DRC with 2 threads +WARNING: [DRC PDRC-153] Gated clock check: Net UPD/dataOut_reg[18]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin UPD/dataOut_reg[18]_LDC_i_1/O, cell UPD/dataOut_reg[18]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net UPD/dataOut_reg[19]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin UPD/dataOut_reg[19]_LDC_i_1/O, cell UPD/dataOut_reg[19]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net UPD/dataOut_reg[1]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin UPD/dataOut_reg[1]_LDC_i_1/O, cell UPD/dataOut_reg[1]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net UPD/dataOut_reg[20]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin UPD/dataOut_reg[20]_LDC_i_1/O, cell UPD/dataOut_reg[20]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net UPD/dataOut_reg[21]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin UPD/dataOut_reg[21]_LDC_i_1/O, cell UPD/dataOut_reg[21]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net UPD/dataOut_reg[4]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin UPD/dataOut_reg[4]_LDC_i_1/O, cell UPD/dataOut_reg[4]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. -INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings +INFO: [Vivado 12-3199] DRC finished with 0 Errors, 7 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Designutils 20-2272] Running write_bitstream with 2 threads. Loading data files... @@ -577,9 +678,9 @@ Creating bitmap... Creating bitstream... Writing bitstream ./VGA_top.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. -INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. +INFO: [Project 1-118] WebTalk data collection is enabled (User setting is ON. Install Setting is ON.). INFO: [Common 17-83] Releasing license: Implementation -22 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +124 Infos, 11 Warnings, 1 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully -write_bitstream: Time (s): cpu = 00:00:10 ; elapsed = 00:00:28 . Memory (MB): peak = 1679.344 ; gain = 471.199 -INFO: [Common 17-206] Exiting Vivado at Tue Dec 7 12:44:53 2021... +write_bitstream: Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1942.887 ; gain = 312.691 +INFO: [Common 17-206] Exiting Vivado at Tue Jan 4 12:21:36 2022... diff --git a/projet-vga.runs/impl_1/runme.sh b/projet-vga.runs/impl_1/runme.sh index 4922688..affdd4c 100644 --- a/projet-vga.runs/impl_1/runme.sh +++ b/projet-vga.runs/impl_1/runme.sh @@ -24,7 +24,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1' +HD_PWD='C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/impl_1' cd "$HD_PWD" HD_LOG=runme.log @@ -41,7 +41,7 @@ EAStep() } # pre-commands: -/bin/touch .write_bitstream.begin.rst +/bin/touch .init_design.begin.rst EAStep vivado -log VGA_top.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace diff --git a/projet-vga.runs/impl_1/usage_statistics_webtalk.html b/projet-vga.runs/impl_1/usage_statistics_webtalk.html index db64368..4cf1c5e 100644 --- a/projet-vga.runs/impl_1/usage_statistics_webtalk.html +++ b/projet-vga.runs/impl_1/usage_statistics_webtalk.html @@ -4,13 +4,13 @@ software_version_and_target_device betaFALSE build_version2405991 - date_generatedTue Dec 7 12:44:52 2021 + date_generatedTue Jan 4 12:21:35 2022 os_platformWIN64 product_versionVivado v2018.3 (64-bit) project_id5587c47a25864f30a941d919a4588f42 - project_iteration43 + project_iteration49 random_id5c5083d208095dd793a4532428ca92e6 - registration_id5c5083d208095dd793a4532428ca92e6 + registration_id174121763_1777493939_210660961_260 route_designTRUE target_devicexc7z010 target_familyzynq @@ -34,101 +34,122 @@ abstractcombinedpanel_add_element=9 abstractcombinedpanel_remove_selected_elements=2 abstractfileview_close=1 - basedialog_cancel=45 - basedialog_close=1 - basedialog_no=1 - basedialog_ok=396 - basedialog_yes=2 - constraintschooserpanel_add_files=1 - coretreetablepanel_core_tree_table=18 + abstractfileview_reload=2 + addsrcwizard_specify_or_create_constraint_files=1 + basedialog_cancel=59 + basedialog_close=1 + basedialog_no=3 + basedialog_ok=474 + basedialog_yes=4 + cmdmsgdialog_ok=2 + confirmsavetexteditsdialog_no=1 + constraintschooserpanel_add_files=2 + coretreetablepanel_core_tree_table=24 + createnewdiagramdialog_design_name=1 createsrcfiledialog_file_name=5 - definemodulesdialog_define_modules_and_specify_io_ports=95 - filesetpanel_file_set_panel_tree=157 - flownavigatortreepanel_flow_navigator_tree=206 + definemodulesdialog_define_modules_and_specify_io_ports=95 + filesetpanel_file_set_panel_tree=209 + flownavigatortreepanel_flow_navigator_tree=261 fpgachooser_fpga_table=1 - gettingstartedview_create_new_project=1 - hcodeeditor_blank_operations=17 - hcodeeditor_close=1 - hcodeeditor_commands_to_fold_text=2 + gettingstartedview_create_new_project=2 + gettingstartedview_open_project=1 + hcodeeditor_blank_operations=17 + hcodeeditor_close=3 + hcodeeditor_commands_to_fold_text=2 hcodeeditor_diff_with=8 - hcodeeditor_search_text_combo_box=15 + hcodeeditor_search_text_combo_box=20 hinputhandler_indent_selection=1 - hinputhandler_toggle_line_comments=37 + hinputhandler_toggle_line_comments=40 hinputhandler_unindent_selection=2 - hpopuptitle_close=1 + hpopuptitle_close=1 logmonitor_monitor=3 - msgtreepanel_manage_suppression=1 - msgtreepanel_message_view_tree=79 - msgview_clear_messages_resulting_from_user_executed=1 + msgtreepanel_manage_suppression=1 + msgtreepanel_message_view_tree=137 + msgview_clear_messages_resulting_from_user_executed=4 msgview_critical_warnings=2 - msgview_error_messages=4 + msgview_error_messages=4 msgview_information_messages=3 - msgview_warning_messages=9 - numjobschooser_number_of_jobs=2 - pacommandnames_auto_connect_target=16 - pacommandnames_auto_update_hier=11 - pacommandnames_goto_implemented_design=1 - pacommandnames_goto_netlist_design=1 + msgview_warning_messages=11 + netlisttreeview_netlist_tree=4 + numjobschooser_number_of_jobs=3 + pacommandnames_auto_connect_target=18 + pacommandnames_auto_update_hier=15 + pacommandnames_goto_implemented_design=2 + pacommandnames_goto_netlist_design=1 pacommandnames_log_window=1 + pacommandnames_message_window=2 pacommandnames_open_hardware_manager=2 pacommandnames_recustomize_core=1 - pacommandnames_run_bitgen=42 + pacommandnames_run_bitgen=45 pacommandnames_run_implementation=8 - paviews_code=5 - paviews_device=3 - paviews_ip_catalog=1 - paviews_project_summary=21 - paviews_schematic=9 - programdebugtab_refresh_device=1 - programfpgadialog_program=45 - progressdialog_background=4 + pacommandnames_src_disable=1 + paviews_code=7 + paviews_device=3 + paviews_ip_catalog=2 + paviews_project_summary=26 + paviews_schematic=10 + programdebugtab_program_device=1 + programdebugtab_refresh_device=2 + programfpgadialog_program=51 + progressdialog_background=5 progressdialog_cancel=5 - projectnamechooser_project_name=1 - projecttab_reload=6 - rdicommands_delete=4 + projectnamechooser_project_name=1 + projecttab_reload=9 + rdicommands_copy=1 + rdicommands_delete=8 + removesourcesdialog_also_delete=2 rungadget_show_warning_and_error_messages_in_messages=2 saveprojectutils_dont_save=8 - saveprojectutils_save=5 + saveprojectutils_save=6 schematicview_previous=10 - simpleoutputproductdialog_generate_output_products_immediately=3 - srcchooserpanel_add_hdl_and_netlist_files_to_your_project=1 + simpleoutputproductdialog_generate_output_products_immediately=4 + specifylibrarydialog_library_name=1 + srcchooserpanel_add_directories=2 + srcchooserpanel_add_hdl_and_netlist_files_to_your_project=3 srcchooserpanel_add_or_create_source_file=1 - srcchooserpanel_create_file=6 - srcmenu_ip_documentation=5 - srcmenu_ip_hierarchy=8 + srcchooserpanel_create_file=6 + srcfileproppanels_type=4 + srcfiletypecombobox_source_file_type=4 + srcmenu_ip_documentation=6 + srcmenu_ip_hierarchy=10 + srcmenu_set_library=1 stalerundialog_no=1 syntheticagettingstartedview_recent_projects=4 - syntheticastatemonitor_cancel=5 - taskbanner_close=16 + syntheticastatemonitor_cancel=7 + taskbanner_close=19 - - - - - - + + + + + + + - - - - - - - - + + + + + + + + + + - - - + + + + - +
java_command_handlers
addsources=6autoconnecttarget=16coreview=3customizecore=4
editdelete=4editpaste=2
addsources=11autoconnecttarget=18coreview=4createblockdesign=3
customizecore=5editdelete=9editpaste=3 editundo=1launchprogramfpga=45
newproject=1openhardwaremanager=67openrecenttarget=21programdevice=45
recustomizecore=3runbitgen=45runimplementation=59
fliptoviewtaskrtlanalysis=1launchprogramfpga=51newproject=2openhardwaremanager=74
openproject=1openrecenttarget=24programdevice=50recustomizecore=3
runbitgen=54runimplementation=68 runschematic=7
runsynthesis=92savefileproxyhandler=3showview=24runsynthesis=114
savefileproxyhandler=3setsourceenabled=1showview=35 viewtaskimplementation=8
viewtaskrtlanalysis=3
viewtaskrtlanalysis=7 viewtasksynthesis=2
- +
other_data
guimode=5
guimode=6
@@ -154,7 +175,7 @@ - + @@ -168,38 +189,83 @@
project_data
launch_simulation_vcs=0
launch_simulation_xsim=0 simulator_language=VHDLsrcsetcount=8srcsetcount=13 synthesisstrategy=Vivado Synthesis Defaults
target_language=VHDL target_simulator=XSim
- - - - - - - - - - + + + + + + + + + + + + + + - - + + + + + + +
post_unisim_transformation
bufg=2carry4=34fdre=21gnd=2
ibuf=1lut1=4lut2=28lut3=7
lut4=62lut5=47lut6=65carry4=266fdce=62fdpe=10
fdre=114fdse=1gnd=11ibuf=2
ldce=23lut1=12lut2=275lut3=323
lut4=365lut5=358lut6=447 mmcme2_adv=1
obuf=18vcc=2
muxf7=19muxf8=1obuf=21obuft=1
ramb18e1=9ramb36e1=18vcc=11
- - - - - - - - - - + + + + + + + + + + + + + + - - + + + + + + + +
pre_unisim_transformation
bufg=2carry4=34fdre=21gnd=2
ibuf=1lut1=4lut2=28lut3=7
lut4=62lut5=47lut6=65carry4=266fdce=62fdpe=10
fdre=114fdse=1gnd=11ibuf=3
ldce=23lut1=12lut2=275lut3=323
lut4=365lut5=358lut6=447 mmcme2_adv=1
obuf=18vcc=2
muxf7=19muxf8=1obuf=21obuft=1
ramb18e1=9ramb36e1=18vcc=11
+ +
+ + + +
power_opt_design
+ + + + + + +
command_line_options_spo
-cell_types=default::all-clocks=default::[not_specified]-exclude_cells=default::[not_specified]-include_cells=default::[not_specified]
+
+ + + + + + + + + + + +
usage
bram_ports_augmented=0bram_ports_newly_gated=25bram_ports_total=54flow_state=default
slice_registers_augmented=0slice_registers_newly_gated=0slice_registers_total=187srls_augmented=0
srls_newly_gated=0srls_total=0

@@ -257,7 +323,208 @@ - + + +
results
zps7-1=1
pdrc-153=6zps7-1=1
+ +
+ + + + +
report_methodology
+ + + + + + + + + + + + +
command_line_options
-append=default::[not_specified]-checks=default::[not_specified]-fail_on=default::[not_specified]-force=default::[not_specified]
-format=default::[not_specified]-messages=default::[not_specified]-name=default::[not_specified]-return_string=default::[not_specified]
-slack_lesser_than=default::[not_specified]-waived=default::[not_specified]
+
+ + + + + + + + + + + +
results
lutar-1=14synth-6=26timing-16=21timing-18=5
timing-20=23timing-27=1timing-4=1timing-6=2
timing-7=2
+

+ + + +
report_power
+ + + + + + + + + + + + + + + + +
command_line_options
-advisory=default::[not_specified]-append=default::[not_specified]-file=[specified]-format=default::text
-hier=default::power-hierarchical_depth=default::4-l=default::[not_specified]-name=default::[not_specified]
-no_propagation=default::[not_specified]-return_string=default::[not_specified]-rpx=[specified]-verbose=default::[not_specified]
-vid=default::[not_specified]-xpe=default::[not_specified]
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
usage
airflow=250 (LFM)ambient_temp=25.0 (C)bi-dir_toggle=12.500000bidir_output_enable=1.000000
board_layers=8to11 (8 to 11 Layers)board_selection=medium (10"x10")bram=0.074844clocks=0.003860
confidence_level_clock_activity=Mediumconfidence_level_design_state=Highconfidence_level_device_models=Highconfidence_level_internal_activity=Medium
confidence_level_io_activity=Mediumconfidence_level_overall=Mediumcustomer=TBDcustomer_class=TBD
devstatic=0.096510die=xc7z010clg400-1dsp_output_toggle=12.500000dynamic=0.201475
effective_thetaja=11.5enable_probability=0.990000family=zynqff_toggle=12.500000
flow_state=routedheatsink=nonei/o=0.001879input_toggle=12.500000
junction_temp=28.4 (C)logic=0.002055mgtavcc_dynamic_current=0.000000mgtavcc_static_current=0.000000
mgtavcc_total_current=0.000000mgtavcc_voltage=1.000000mgtavtt_dynamic_current=0.000000mgtavtt_static_current=0.000000
mgtavtt_total_current=0.000000mgtavtt_voltage=1.200000mgtvccaux_dynamic_current=0.000000mgtvccaux_static_current=0.000000
mgtvccaux_total_current=0.000000mgtvccaux_voltage=1.800000mmcm=0.115225netlist_net_matched=NA
off-chip_power=0.000000on-chip_power=0.297985output_enable=1.000000output_load=5.000000
output_toggle=12.500000package=clg400pct_clock_constrained=1.000000pct_inputs_defined=50
platform=nt64process=typicalram_enable=50.000000ram_write=50.000000
read_saif=Falseset/reset_probability=0.000000signal_rate=Falsesignals=0.003612
simulation_file=Nonespeedgrade=-1static_prob=Falsetemp_grade=commercial
thetajb=9.3 (C/W)thetasa=0.0 (C/W)toggle_rate=Falseuser_board_temp=25.0 (C)
user_effective_thetaja=11.5user_junc_temp=28.4 (C)user_thetajb=9.3 (C/W)user_thetasa=0.0 (C/W)
vccadc_dynamic_current=0.000000vccadc_static_current=0.020000vccadc_total_current=0.020000vccadc_voltage=1.800000
vccaux_dynamic_current=0.064022vccaux_io_dynamic_current=0.000000vccaux_io_static_current=0.000000vccaux_io_total_current=0.000000
vccaux_io_voltage=1.800000vccaux_static_current=0.005617vccaux_total_current=0.069639vccaux_voltage=1.800000
vccbram_dynamic_current=0.006550vccbram_static_current=0.001052vccbram_total_current=0.007602vccbram_voltage=1.000000
vccint_dynamic_current=0.078006vccint_static_current=0.004501vccint_total_current=0.082507vccint_voltage=1.000000
vcco12_dynamic_current=0.000000vcco12_static_current=0.000000vcco12_total_current=0.000000vcco12_voltage=1.200000
vcco135_dynamic_current=0.000000vcco135_static_current=0.000000vcco135_total_current=0.000000vcco135_voltage=1.350000
vcco15_dynamic_current=0.000000vcco15_static_current=0.000000vcco15_total_current=0.000000vcco15_voltage=1.500000
vcco18_dynamic_current=0.000000vcco18_static_current=0.000000vcco18_total_current=0.000000vcco18_voltage=1.800000
vcco25_dynamic_current=0.000000vcco25_static_current=0.000000vcco25_total_current=0.000000vcco25_voltage=2.500000
vcco33_dynamic_current=0.000509vcco33_static_current=0.001000vcco33_total_current=0.001509vcco33_voltage=3.300000
vcco_ddr_dynamic_current=0.000000vcco_ddr_static_current=0.000000vcco_ddr_total_current=0.000000vcco_ddr_voltage=1.500000
vcco_mio0_dynamic_current=0.000000vcco_mio0_static_current=0.000000vcco_mio0_total_current=0.000000vcco_mio0_voltage=1.800000
vcco_mio1_dynamic_current=0.000000vcco_mio1_static_current=0.000000vcco_mio1_total_current=0.000000vcco_mio1_voltage=1.800000
vccpaux_dynamic_current=0.000000vccpaux_static_current=0.010330vccpaux_total_current=0.010330vccpaux_voltage=1.800000
vccpint_dynamic_current=0.000000vccpint_static_current=0.017552vccpint_total_current=0.017552vccpint_voltage=1.000000
vccpll_dynamic_current=0.000000vccpll_static_current=0.003000vccpll_total_current=0.003000vccpll_voltage=1.800000
version=2018.3

@@ -268,8 +535,8 @@ clocking bufgctrl_available=32 bufgctrl_fixed=0 - bufgctrl_used=2 - bufgctrl_util_percentage=6.25 + bufgctrl_used=3 + bufgctrl_util_percentage=9.38 bufhce_available=48 bufhce_fixed=0 bufhce_used=0 @@ -352,45 +619,65 @@ memory block_ram_tile_available=60 block_ram_tile_fixed=0 - block_ram_tile_used=0 - block_ram_tile_util_percentage=0.00 + block_ram_tile_used=22.5 + block_ram_tile_util_percentage=37.50 ramb18_available=120 ramb18_fixed=0 - ramb18_used=0 - ramb18_util_percentage=0.00 - ramb36_fifo_available=60 + ramb18_used=9 + ramb18_util_percentage=7.50 + ramb18e1_only_used=9 + ramb36_fifo_available=60 ramb36_fifo_fixed=0 - ramb36_fifo_used=0 - ramb36_fifo_util_percentage=0.00 + ramb36_fifo_used=18 + ramb36_fifo_util_percentage=30.00 + ramb36e1_only_used=18 - + - + + + + + - - - + + + + + + + - + - + - + - + - + - + + + + + - + + + + + + +
primitives
bufg_functional_category=Clockbufg_used=2bufg_used=3 carry4_functional_category=CarryLogiccarry4_used=34carry4_used=266
fdce_functional_category=Flop & Latchfdce_used=64fdpe_functional_category=Flop & Latchfdpe_used=10
fdre_functional_category=Flop & Latchfdre_used=21ibuf_functional_category=IOibuf_used=1fdre_used=114fdse_functional_category=Flop & Latchfdse_used=1
ibuf_functional_category=IOibuf_used=2ldce_functional_category=Flop & Latchldce_used=23
lut1_functional_category=LUTlut1_used=4lut1_used=12 lut2_functional_category=LUTlut2_used=28lut2_used=275
lut3_functional_category=LUTlut3_used=7lut3_used=332 lut4_functional_category=LUTlut4_used=64lut4_used=365
lut5_functional_category=LUTlut5_used=47lut5_used=358 lut6_functional_category=LUTlut6_used=63lut6_used=447
mmcme2_adv_functional_category=Clock mmcme2_adv_used=1muxf7_functional_category=MuxFxmuxf7_used=19
muxf8_functional_category=MuxFxmuxf8_used=1 obuf_functional_category=IOobuf_used=18obuf_used=21
obuft_functional_category=IOobuft_used=1ramb18e1_functional_category=Block Memoryramb18e1_used=9
ramb36e1_functional_category=Block Memoryramb36e1_used=18
@@ -398,42 +685,42 @@ slice_logic f7_muxes_available=8800 f7_muxes_fixed=0 - f7_muxes_used=0 - f7_muxes_util_percentage=0.00 + f7_muxes_used=19 + f7_muxes_util_percentage=0.22 f8_muxes_available=4400 f8_muxes_fixed=0 - f8_muxes_used=0 - f8_muxes_util_percentage=0.00 + f8_muxes_used=1 + f8_muxes_util_percentage=0.02 lut_as_logic_available=17600 lut_as_logic_fixed=0 - lut_as_logic_used=168 - lut_as_logic_util_percentage=0.95 + lut_as_logic_used=1491 + lut_as_logic_util_percentage=8.47 lut_as_memory_available=6000 lut_as_memory_fixed=0 lut_as_memory_used=0 lut_as_memory_util_percentage=0.00 register_as_flip_flop_available=35200 register_as_flip_flop_fixed=0 - register_as_flip_flop_used=21 - register_as_flip_flop_util_percentage=0.06 + register_as_flip_flop_used=189 + register_as_flip_flop_util_percentage=0.54 register_as_latch_available=35200 register_as_latch_fixed=0 - register_as_latch_used=0 - register_as_latch_util_percentage=0.00 + register_as_latch_used=23 + register_as_latch_util_percentage=0.07 slice_luts_available=17600 slice_luts_fixed=0 - slice_luts_used=168 - slice_luts_util_percentage=0.95 + slice_luts_used=1491 + slice_luts_util_percentage=8.47 slice_registers_available=35200 slice_registers_fixed=0 - slice_registers_used=21 - slice_registers_util_percentage=0.06 + slice_registers_used=212 + slice_registers_util_percentage=0.60 lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=0 lut_as_logic_available=17600 lut_as_logic_fixed=0 - lut_as_logic_used=168 - lut_as_logic_util_percentage=0.95 + lut_as_logic_used=1491 + lut_as_logic_util_percentage=8.47 lut_as_memory_available=6000 lut_as_memory_fixed=0 lut_as_memory_used=0 @@ -441,35 +728,35 @@ lut_as_shift_register_fixed=0 lut_as_shift_register_used=0 lut_in_front_of_the_register_is_unused_fixed=0 - lut_in_front_of_the_register_is_unused_used=0 - lut_in_front_of_the_register_is_used_fixed=0 - lut_in_front_of_the_register_is_used_used=1 - register_driven_from_outside_the_slice_fixed=1 - register_driven_from_outside_the_slice_used=1 - register_driven_from_within_the_slice_fixed=1 - register_driven_from_within_the_slice_used=20 + lut_in_front_of_the_register_is_unused_used=21 + lut_in_front_of_the_register_is_used_fixed=21 + lut_in_front_of_the_register_is_used_used=26 + register_driven_from_outside_the_slice_fixed=26 + register_driven_from_outside_the_slice_used=47 + register_driven_from_within_the_slice_fixed=47 + register_driven_from_within_the_slice_used=165 slice_available=4400 slice_fixed=0 slice_registers_available=35200 slice_registers_fixed=0 - slice_registers_used=21 - slice_registers_util_percentage=0.06 - slice_used=61 - slice_util_percentage=1.39 + slice_registers_used=212 + slice_registers_util_percentage=0.60 + slice_used=541 + slice_util_percentage=12.30 slicel_fixed=0 - slicel_used=45 + slicel_used=361 slicem_fixed=0 - slicem_used=16 + slicem_used=180 unique_control_sets_available=4400 unique_control_sets_fixed=4400 - unique_control_sets_used=2 - unique_control_sets_util_percentage=0.05 - using_o5_and_o6_fixed=0.05 - using_o5_and_o6_used=45 - using_o5_output_only_fixed=45 + unique_control_sets_used=31 + unique_control_sets_util_percentage=0.70 + using_o5_and_o6_fixed=0.70 + using_o5_and_o6_used=298 + using_o5_output_only_fixed=298 using_o5_output_only_used=0 using_o6_output_only_fixed=0 - using_o6_output_only_used=123 + using_o6_output_only_used=1193 @@ -554,10 +841,10 @@ - + - - + +
usage
elapsed=00:01:36s
elapsed=00:00:46s hls_ip=0memory_gain=948.426MBmemory_peak=1310.512MBmemory_gain=613.590MBmemory_peak=976.145MB

diff --git a/projet-vga.runs/impl_1/usage_statistics_webtalk.xml b/projet-vga.runs/impl_1/usage_statistics_webtalk.xml index 2f1a4f7..e322fae 100644 --- a/projet-vga.runs/impl_1/usage_statistics_webtalk.xml +++ b/projet-vga.runs/impl_1/usage_statistics_webtalk.xml @@ -1,16 +1,16 @@ - +
- + - + - + @@ -52,7 +52,27 @@
-
+
+
+ + + + +
+
+ + + + + + + + + + +
+
+
@@ -70,15 +90,202 @@
+
-
+
+
+ + + + + + + + + + +
+
+ + + + + + + + + +
+
+
+
+ + + + + + + + + + + + + + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
- - + + @@ -152,62 +359,82 @@
- - + + - - + + + - - + + +
- + - + + + + + - + + + - + + + - + - + - + - + - + - + + + + + - + + + + + + +
- - + + - - + + - - - - + + + + @@ -219,51 +446,51 @@ - - - + + + - - + + - - - - - - + + + + + + - - + + - - - - - - + + + + + + - + - + - - - - - + + + + + - +
@@ -300,7 +527,7 @@
-
+
@@ -338,144 +565,183 @@
- + - - + +
-
+
- - - - - - - - - - + + + + + + + + + + + + + + - - + + + + + + +
- - - - - - - - - - + + + + + + + + + + + + + + - - + + + + + + +
-
+
- + + + - - - - - + + + + + + + + - - + + - + + - + - + - + - - + + - - - - - + + + + + + + - + - + + - - - - - - + + + + + + + - - + + + + - + - - + + + + - - + + + + + - - + +
- - - - - - + + + + + + + - - - - - + + + + + + + - - + + - + - + + - +
- +
@@ -500,7 +766,7 @@ - + diff --git a/projet-vga.runs/impl_1/vivado.jou b/projet-vga.runs/impl_1/vivado.jou index e6dcfde..ffbf857 100644 --- a/projet-vga.runs/impl_1/vivado.jou +++ b/projet-vga.runs/impl_1/vivado.jou @@ -2,11 +2,11 @@ # Vivado v2018.3 (64-bit) # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Tue Dec 7 12:44:06 2021 -# Process ID: 5252 -# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1 +# Start of session at: Tue Jan 4 12:18:37 2022 +# Process ID: 13232 +# Current directory: C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/impl_1 # Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace -# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi -# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou +# Log file: C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/impl_1/VGA_top.vdi +# Journal file: C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/impl_1\vivado.jou #----------------------------------------------------------- source VGA_top.tcl -notrace diff --git a/projet-vga.runs/impl_1/vivado.pb b/projet-vga.runs/impl_1/vivado.pb index 24aecc3..a15f7da 100644 Binary files a/projet-vga.runs/impl_1/vivado.pb and b/projet-vga.runs/impl_1/vivado.pb differ diff --git a/projet-vga.runs/impl_1/vivado_11872.backup.jou b/projet-vga.runs/impl_1/vivado_11872.backup.jou deleted file mode 100644 index 7c67724..0000000 --- a/projet-vga.runs/impl_1/vivado_11872.backup.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Tue Nov 23 09:55:17 2021 -# Process ID: 11872 -# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1 -# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace -# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi -# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou -#----------------------------------------------------------- -source VGA_top.tcl -notrace diff --git a/projet-vga.runs/impl_1/vivado_12280.backup.jou b/projet-vga.runs/impl_1/vivado_12280.backup.jou deleted file mode 100644 index 02dea48..0000000 --- a/projet-vga.runs/impl_1/vivado_12280.backup.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Tue Nov 30 12:02:04 2021 -# Process ID: 12280 -# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1 -# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace -# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi -# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou -#----------------------------------------------------------- -source VGA_top.tcl -notrace diff --git a/projet-vga.runs/impl_1/vivado_12864.backup.jou b/projet-vga.runs/impl_1/vivado_12864.backup.jou deleted file mode 100644 index a02e7c1..0000000 --- a/projet-vga.runs/impl_1/vivado_12864.backup.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Tue Dec 7 12:19:39 2021 -# Process ID: 12864 -# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1 -# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace -# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi -# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou -#----------------------------------------------------------- -source VGA_top.tcl -notrace diff --git a/projet-vga.runs/impl_1/vivado_12968.backup.jou b/projet-vga.runs/impl_1/vivado_12968.backup.jou deleted file mode 100644 index 5691576..0000000 --- a/projet-vga.runs/impl_1/vivado_12968.backup.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Tue Nov 30 12:20:41 2021 -# Process ID: 12968 -# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1 -# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace -# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi -# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou -#----------------------------------------------------------- -source VGA_top.tcl -notrace diff --git a/projet-vga.runs/impl_1/vivado_13936.backup.jou b/projet-vga.runs/impl_1/vivado_13936.backup.jou deleted file mode 100644 index e278f66..0000000 --- a/projet-vga.runs/impl_1/vivado_13936.backup.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Tue Nov 30 12:26:23 2021 -# Process ID: 13936 -# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1 -# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace -# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi -# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou -#----------------------------------------------------------- -source VGA_top.tcl -notrace diff --git a/projet-vga.runs/impl_1/vivado_14844.backup.jou b/projet-vga.runs/impl_1/vivado_14844.backup.jou deleted file mode 100644 index 54cdd1d..0000000 --- a/projet-vga.runs/impl_1/vivado_14844.backup.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Tue Nov 23 10:29:07 2021 -# Process ID: 14844 -# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1 -# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace -# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi -# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou -#----------------------------------------------------------- -source VGA_top.tcl -notrace diff --git a/projet-vga.runs/impl_1/vivado_15112.backup.jou b/projet-vga.runs/impl_1/vivado_15112.backup.jou deleted file mode 100644 index 738c3fe..0000000 --- a/projet-vga.runs/impl_1/vivado_15112.backup.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Tue Nov 30 12:16:55 2021 -# Process ID: 15112 -# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1 -# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace -# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi -# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou -#----------------------------------------------------------- -source VGA_top.tcl -notrace diff --git a/projet-vga.runs/impl_1/vivado_1568.backup.jou b/projet-vga.runs/impl_1/vivado_1568.backup.jou deleted file mode 100644 index 332f28e..0000000 --- a/projet-vga.runs/impl_1/vivado_1568.backup.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Tue Nov 30 12:43:37 2021 -# Process ID: 1568 -# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1 -# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace -# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi -# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou -#----------------------------------------------------------- -source VGA_top.tcl -notrace diff --git a/projet-vga.runs/impl_1/vivado_4688.backup.jou b/projet-vga.runs/impl_1/vivado_4688.backup.jou deleted file mode 100644 index 68aec63..0000000 --- a/projet-vga.runs/impl_1/vivado_4688.backup.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Tue Nov 23 10:08:25 2021 -# Process ID: 4688 -# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1 -# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace -# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi -# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou -#----------------------------------------------------------- -source VGA_top.tcl -notrace diff --git a/projet-vga.runs/impl_1/vivado_4708.backup.jou b/projet-vga.runs/impl_1/vivado_4708.backup.jou deleted file mode 100644 index 913ae24..0000000 --- a/projet-vga.runs/impl_1/vivado_4708.backup.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Tue Dec 7 12:30:30 2021 -# Process ID: 4708 -# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1 -# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace -# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi -# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou -#----------------------------------------------------------- -source VGA_top.tcl -notrace diff --git a/projet-vga.runs/impl_1/vivado_4856.backup.jou b/projet-vga.runs/impl_1/vivado_4856.backup.jou deleted file mode 100644 index b70ecb7..0000000 --- a/projet-vga.runs/impl_1/vivado_4856.backup.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Tue Dec 7 12:42:58 2021 -# Process ID: 4856 -# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1 -# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace -# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi -# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou -#----------------------------------------------------------- -source VGA_top.tcl -notrace diff --git a/projet-vga.runs/impl_1/vivado_6484.backup.jou b/projet-vga.runs/impl_1/vivado_6484.backup.jou deleted file mode 100644 index c7753f9..0000000 --- a/projet-vga.runs/impl_1/vivado_6484.backup.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Tue Dec 7 12:35:58 2021 -# Process ID: 6484 -# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1 -# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace -# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi -# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou -#----------------------------------------------------------- -source VGA_top.tcl -notrace diff --git a/projet-vga.runs/impl_1/vivado_8972.backup.jou b/projet-vga.runs/impl_1/vivado_8972.backup.jou deleted file mode 100644 index 05859bc..0000000 --- a/projet-vga.runs/impl_1/vivado_8972.backup.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Tue Nov 23 10:20:49 2021 -# Process ID: 8972 -# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1 -# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace -# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi -# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou -#----------------------------------------------------------- -source VGA_top.tcl -notrace diff --git a/projet-vga.runs/impl_1/vivado_9384.backup.jou b/projet-vga.runs/impl_1/vivado_9384.backup.jou deleted file mode 100644 index 543681e..0000000 --- a/projet-vga.runs/impl_1/vivado_9384.backup.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Tue Dec 7 12:26:40 2021 -# Process ID: 9384 -# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1 -# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace -# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi -# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou -#----------------------------------------------------------- -source VGA_top.tcl -notrace diff --git a/projet-vga.runs/impl_1/vivado_9960.backup.jou b/projet-vga.runs/impl_1/vivado_9960.backup.jou deleted file mode 100644 index 3365a82..0000000 --- a/projet-vga.runs/impl_1/vivado_9960.backup.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Tue Nov 23 10:14:24 2021 -# Process ID: 9960 -# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1 -# Command line: vivado.exe -log VGA_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VGA_top.tcl -notrace -# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1/VGA_top.vdi -# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/impl_1\vivado.jou -#----------------------------------------------------------- -source VGA_top.tcl -notrace diff --git a/projet-vga.runs/impl_1/write_bitstream.pb b/projet-vga.runs/impl_1/write_bitstream.pb index 737fff4..e8784e0 100644 Binary files a/projet-vga.runs/impl_1/write_bitstream.pb and b/projet-vga.runs/impl_1/write_bitstream.pb differ diff --git a/projet-vga.runs/synth_1/.Xil/VGA_top_propImpl.xdc b/projet-vga.runs/synth_1/.Xil/VGA_top_propImpl.xdc index 635737f..7ee4730 100644 --- a/projet-vga.runs/synth_1/.Xil/VGA_top_propImpl.xdc +++ b/projet-vga.runs/synth_1/.Xil/VGA_top_propImpl.xdc @@ -1,49 +1,49 @@ -set_property SRC_FILE_INFO {cfile:{C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc} rfile:{../../../../../../../../../e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc} id:1} [current_design] +set_property SRC_FILE_INFO {cfile:C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/ZYBO_Master.xdc rfile:../../../sources_snake/ZYBO_Master.xdc id:1} [current_design] set_property src_info {type:XDC file:1 line:8 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN L16 [get_ports H125MHz] -set_property src_info {type:XDC file:1 line:17 export:INPUT save:INPUT read:READ} [current_design] +set_property src_info {type:XDC file:1 line:14 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN G15 [get_ports resetGeneral] -set_property src_info {type:XDC file:1 line:34 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN R18 [get_ports bouton_up] -set_property src_info {type:XDC file:1 line:38 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN P16 [get_ports bouton_down] -set_property src_info {type:XDC file:1 line:42 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN V16 [get_ports bouton_left] -set_property src_info {type:XDC file:1 line:46 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN Y16 [get_ports bouton_right] -set_property src_info {type:XDC file:1 line:341 export:INPUT save:INPUT read:READ} [current_design] +set_property src_info {type:XDC file:1 line:48 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN M14 [get_ports {led[0]}] +set_property src_info {type:XDC file:1 line:52 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN M15 [get_ports {led[1]}] +set_property src_info {type:XDC file:1 line:56 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN G14 [get_ports {led[2]}] +set_property src_info {type:XDC file:1 line:60 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN D18 [get_ports {led[3]}] +set_property src_info {type:XDC file:1 line:337 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN M19 [get_ports {vga_r[0]}] -set_property src_info {type:XDC file:1 line:345 export:INPUT save:INPUT read:READ} [current_design] +set_property src_info {type:XDC file:1 line:341 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN L20 [get_ports {vga_r[1]}] -set_property src_info {type:XDC file:1 line:349 export:INPUT save:INPUT read:READ} [current_design] +set_property src_info {type:XDC file:1 line:345 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN J20 [get_ports {vga_r[2]}] -set_property src_info {type:XDC file:1 line:353 export:INPUT save:INPUT read:READ} [current_design] +set_property src_info {type:XDC file:1 line:349 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN G20 [get_ports {vga_r[3]}] -set_property src_info {type:XDC file:1 line:357 export:INPUT save:INPUT read:READ} [current_design] +set_property src_info {type:XDC file:1 line:353 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN F19 [get_ports {vga_r[4]}] -set_property src_info {type:XDC file:1 line:361 export:INPUT save:INPUT read:READ} [current_design] +set_property src_info {type:XDC file:1 line:357 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN H18 [get_ports {vga_g[0]}] -set_property src_info {type:XDC file:1 line:365 export:INPUT save:INPUT read:READ} [current_design] +set_property src_info {type:XDC file:1 line:361 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN N20 [get_ports {vga_g[1]}] -set_property src_info {type:XDC file:1 line:369 export:INPUT save:INPUT read:READ} [current_design] +set_property src_info {type:XDC file:1 line:365 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN L19 [get_ports {vga_g[2]}] -set_property src_info {type:XDC file:1 line:373 export:INPUT save:INPUT read:READ} [current_design] +set_property src_info {type:XDC file:1 line:369 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN J19 [get_ports {vga_g[3]}] -set_property src_info {type:XDC file:1 line:377 export:INPUT save:INPUT read:READ} [current_design] +set_property src_info {type:XDC file:1 line:373 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN H20 [get_ports {vga_g[4]}] -set_property src_info {type:XDC file:1 line:381 export:INPUT save:INPUT read:READ} [current_design] +set_property src_info {type:XDC file:1 line:377 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN F20 [get_ports {vga_g[5]}] -set_property src_info {type:XDC file:1 line:385 export:INPUT save:INPUT read:READ} [current_design] +set_property src_info {type:XDC file:1 line:381 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN P20 [get_ports {vga_b[0]}] -set_property src_info {type:XDC file:1 line:389 export:INPUT save:INPUT read:READ} [current_design] +set_property src_info {type:XDC file:1 line:385 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN M20 [get_ports {vga_b[1]}] -set_property src_info {type:XDC file:1 line:393 export:INPUT save:INPUT read:READ} [current_design] +set_property src_info {type:XDC file:1 line:389 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN K19 [get_ports {vga_b[2]}] -set_property src_info {type:XDC file:1 line:397 export:INPUT save:INPUT read:READ} [current_design] +set_property src_info {type:XDC file:1 line:393 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN J18 [get_ports {vga_b[3]}] -set_property src_info {type:XDC file:1 line:401 export:INPUT save:INPUT read:READ} [current_design] +set_property src_info {type:XDC file:1 line:397 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN G19 [get_ports {vga_b[4]}] -set_property src_info {type:XDC file:1 line:405 export:INPUT save:INPUT read:READ} [current_design] +set_property src_info {type:XDC file:1 line:401 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN P19 [get_ports vga_hs] -set_property src_info {type:XDC file:1 line:409 export:INPUT save:INPUT read:READ} [current_design] +set_property src_info {type:XDC file:1 line:405 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN R19 [get_ports vga_vs] diff --git a/projet-vga.runs/synth_1/.vivado.begin.rst b/projet-vga.runs/synth_1/.vivado.begin.rst index e96f067..8ea98f1 100644 --- a/projet-vga.runs/synth_1/.vivado.begin.rst +++ b/projet-vga.runs/synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/projet-vga.runs/synth_1/VGA_top.dcp b/projet-vga.runs/synth_1/VGA_top.dcp index 9fd8122..29cdfc8 100644 Binary files a/projet-vga.runs/synth_1/VGA_top.dcp and b/projet-vga.runs/synth_1/VGA_top.dcp differ diff --git a/projet-vga.runs/synth_1/VGA_top.tcl b/projet-vga.runs/synth_1/VGA_top.tcl index 3b6fd28..878d246 100644 --- a/projet-vga.runs/synth_1/VGA_top.tcl +++ b/projet-vga.runs/synth_1/VGA_top.tcl @@ -17,9 +17,7 @@ proc create_report { reportName command } { send_msg_id runtcl-5 warning "$msg" } } -set_param synth.incrementalSynthesisCache C:/Users/E209098F/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-12508-irb121-02-w/incrSyn set_param xicom.use_bs_reader 1 -set_msg_config -id {Common 17-41} -limit 10000000 set_msg_config -id {Synth 8-256} -limit 10000 set_msg_config -id {Synth 8-638} -limit 10000 create_project -in_memory -part xc7z010clg400-1 @@ -28,25 +26,32 @@ set_param project.singleFileAddWarning.threshold 0 set_param project.compositeFile.enableAutoGeneration 0 set_param synth.vivado.isSynthRun true set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info -set_property webtalk.parent_dir C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.cache/wt [current_project] -set_property parent.project_path C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.xpr [current_project] +set_property webtalk.parent_dir C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.cache/wt [current_project] +set_property parent.project_path C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.xpr [current_project] set_property XPM_LIBRARIES XPM_CDC [current_project] set_property default_lib xil_defaultlib [current_project] set_property target_language VHDL [current_project] -set_property ip_output_repo c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.cache/ip [current_project] +set_property ip_output_repo c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.cache/ip [current_project] set_property ip_cache_permissions {read write} [current_project] +read_mem C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sprites/sprites.mem read_vhdl -library xil_defaultlib { - C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Diviseur.vhd - {C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/GeneRGB_V1.vhd} - {C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/GeneSync.vhd} - C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Position.vhd - C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd - {C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/VGA_top.vhd} + C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Diviseur.vhd + C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/GeneRGB_V1.vhd + C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/GeneSync.vhd + C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd + C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd + C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/VGA_top.vhd } -read_ip -quiet C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xci -set_property used_in_implementation false [get_files -all c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_board.xdc] -set_property used_in_implementation false [get_files -all c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0.xdc] -set_property used_in_implementation false [get_files -all c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0_ooc.xdc] +read_vhdl -library ourTypes C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/types.vhd +read_vhdl -vhdl2008 -library xil_defaultlib { + C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/RAMController.vhd + C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/snakeRam.vhd + C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/spritesRom.vhd +} +read_ip -quiet c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0.xci +set_property used_in_implementation false [get_files -all c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0_board.xdc] +set_property used_in_implementation false [get_files -all c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0.xdc] +set_property used_in_implementation false [get_files -all c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0_ooc.xdc] # Mark all dcp files as not used in implementation to prevent them from being # stitched into the results of this synthesis run. Any black boxes in the @@ -56,8 +61,8 @@ set_property used_in_implementation false [get_files -all c:/Users/e209098F/Docu foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { set_property used_in_implementation false $dcp } -read_xdc {{C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc}} -set_property used_in_implementation false [get_files {{C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc}}] +read_xdc C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/ZYBO_Master.xdc +set_property used_in_implementation false [get_files C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/ZYBO_Master.xdc] read_xdc dont_touch.xdc set_property used_in_implementation false [get_files dont_touch.xdc] diff --git a/projet-vga.runs/synth_1/VGA_top.vds b/projet-vga.runs/synth_1/VGA_top.vds index 1145096..74136b7 100644 --- a/projet-vga.runs/synth_1/VGA_top.vds +++ b/projet-vga.runs/synth_1/VGA_top.vds @@ -2,12 +2,12 @@ # Vivado v2018.3 (64-bit) # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Tue Dec 7 12:41:01 2021 -# Process ID: 5952 -# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/synth_1 +# Start of session at: Tue Jan 4 12:17:37 2022 +# Process ID: 5272 +# Current directory: C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/synth_1 # Command line: vivado.exe -log VGA_top.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source VGA_top.tcl -# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/synth_1/VGA_top.vds -# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/synth_1\vivado.jou +# Log file: C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/synth_1/VGA_top.vds +# Journal file: C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/synth_1\vivado.jou #----------------------------------------------------------- source VGA_top.tcl -notrace Command: synth_design -top VGA_top -part xc7z010clg400-1 @@ -15,38 +15,102 @@ Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010' INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 12208 +INFO: Helper process launched with PID 8152 --------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 467.680 ; gain = 94.113 +Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 467.723 ; gain = 93.676 --------------------------------------------------------------------------------- -INFO: [Synth 8-638] synthesizing module 'VGA_top' [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/VGA_top.vhd:48] -INFO: [Synth 8-637] synthesizing blackbox instance 'U0' of component 'clk_wiz_0' [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/VGA_top.vhd:148] -INFO: [Synth 8-3491] module 'GeneSync' declared at 'C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/GeneSync.vhd:7' bound to instance 'U1' of component 'GeneSync' [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/VGA_top.vhd:156] -INFO: [Synth 8-638] synthesizing module 'GeneSync' [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/GeneSync.vhd:16] -INFO: [Synth 8-256] done synthesizing module 'GeneSync' (1#1) [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/GeneSync.vhd:16] -INFO: [Synth 8-3491] module 'GeneRGB_V1' declared at 'C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/GeneRGB_V1.vhd:36' bound to instance 'U2' of component 'GeneRGB_V1' [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/VGA_top.vhd:165] -INFO: [Synth 8-638] synthesizing module 'GeneRGB_V1' [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/GeneRGB_V1.vhd:47] -INFO: [Synth 8-256] done synthesizing module 'GeneRGB_V1' (2#1) [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/GeneRGB_V1.vhd:47] -INFO: [Synth 8-3491] module 'Gene_Position' declared at 'C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Position.vhd:34' bound to instance 'U4' of component 'Gene_Position' [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/VGA_top.vhd:183] -INFO: [Synth 8-638] synthesizing module 'Gene_Position' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Position.vhd:45] -INFO: [Synth 8-256] done synthesizing module 'Gene_Position' (3#1) [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Position.vhd:45] - Parameter nbBits bound to: 18 - type: integer -INFO: [Synth 8-3491] module 'Diviseur' declared at 'C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Diviseur.vhd:34' bound to instance 'U5' of component 'Diviseur' [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/VGA_top.vhd:194] -INFO: [Synth 8-638] synthesizing module 'Diviseur' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Diviseur.vhd:42] - Parameter nbBits bound to: 18 - type: integer -INFO: [Synth 8-256] done synthesizing module 'Diviseur' (4#1) [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Diviseur.vhd:42] -INFO: [Synth 8-3491] module 'Gene_Snake' declared at 'C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:36' bound to instance 'U6' of component 'Gene_Snake' [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/VGA_top.vhd:202] -INFO: [Synth 8-638] synthesizing module 'Gene_Snake' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:49] -WARNING: [Synth 8-614] signal 'snakeHere' is read in the process but is not in the sensitivity list [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:70] -WARNING: [Synth 8-5858] RAM snake_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers -INFO: [Synth 8-256] done synthesizing module 'Gene_Snake' (5#1) [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:49] -INFO: [Synth 8-256] done synthesizing module 'VGA_top' (6#1) [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/VGA_top.vhd:48] -WARNING: [Synth 8-3331] design Gene_Snake has unconnected port up -WARNING: [Synth 8-3331] design Gene_Snake has unconnected port down -WARNING: [Synth 8-3331] design Gene_Snake has unconnected port left -WARNING: [Synth 8-3331] design Gene_Snake has unconnected port right -WARNING: [Synth 8-3331] design Gene_Snake has unconnected port clk_rapide -WARNING: [Synth 8-3331] design Gene_Snake has unconnected port clk_lente +INFO: [Synth 8-638] synthesizing module 'VGA_top' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/VGA_top.vhd:48] +INFO: [Synth 8-637] synthesizing blackbox instance 'U0' of component 'clk_wiz_0' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/VGA_top.vhd:217] +INFO: [Synth 8-3491] module 'GeneSync' declared at 'C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/GeneSync.vhd:8' bound to instance 'SYNC' of component 'GeneSync' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/VGA_top.vhd:235] +INFO: [Synth 8-638] synthesizing module 'GeneSync' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/GeneSync.vhd:17] +WARNING: [Synth 8-312] ignoring unsynthesizable construct: non-synthesizable procedure call [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/GeneSync.vhd:45] +INFO: [Synth 8-256] done synthesizing module 'GeneSync' (1#1) [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/GeneSync.vhd:17] +INFO: [Synth 8-3491] module 'GeneRGB_V1' declared at 'C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/GeneRGB_V1.vhd:37' bound to instance 'RGB' of component 'GeneRGB_V1' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/VGA_top.vhd:244] +INFO: [Synth 8-638] synthesizing module 'GeneRGB_V1' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/GeneRGB_V1.vhd:47] +INFO: [Synth 8-256] done synthesizing module 'GeneRGB_V1' (2#1) [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/GeneRGB_V1.vhd:47] + Parameter nbBits bound to: 25 - type: integer +INFO: [Synth 8-3491] module 'Diviseur' declared at 'C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Diviseur.vhd:34' bound to instance 'UPD_CLK_DIV' of component 'Diviseur' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/VGA_top.vhd:254] +INFO: [Synth 8-638] synthesizing module 'Diviseur' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Diviseur.vhd:42] + Parameter nbBits bound to: 25 - type: integer +INFO: [Synth 8-256] done synthesizing module 'Diviseur' (3#1) [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Diviseur.vhd:42] + Parameter addressSize bound to: 11 - type: integer +INFO: [Synth 8-3491] module 'Gene_Snake' declared at 'C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:39' bound to instance 'SNAKE' of component 'Gene_Snake' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/VGA_top.vhd:265] +INFO: [Synth 8-638] synthesizing module 'Gene_Snake' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:63] + Parameter addressSize bound to: 11 - type: integer +INFO: [Synth 8-226] default block is never used [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109] +INFO: [Synth 8-226] default block is never used [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109] +INFO: [Synth 8-226] default block is never used [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109] +INFO: [Synth 8-226] default block is never used [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109] +INFO: [Synth 8-226] default block is never used [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109] +INFO: [Synth 8-226] default block is never used [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109] +INFO: [Synth 8-226] default block is never used [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109] +INFO: [Synth 8-226] default block is never used [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109] +INFO: [Synth 8-226] default block is never used [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109] +WARNING: [Synth 8-6014] Unused sequential element iterInd_reg was removed. [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:97] +WARNING: [Synth 8-6014] Unused sequential element sX_reg was removed. [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:100] +WARNING: [Synth 8-6014] Unused sequential element sY_reg was removed. [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:101] +WARNING: [Synth 8-6014] Unused sequential element sOff_reg was removed. [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:103] +INFO: [Synth 8-256] done synthesizing module 'Gene_Snake' (4#1) [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:63] + Parameter snakeDataSize bound to: 24 - type: integer +INFO: [Synth 8-3491] module 'RAMController' declared at 'C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/RAMController.vhd:9' bound to instance 'RAMCTRL' of component 'RAMController' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/VGA_top.vhd:284] +INFO: [Synth 8-638] synthesizing module 'RAMController' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/RAMController.vhd:37] + Parameter snakeDataSize bound to: 24 - type: integer + Parameter length bound to: 1200 - type: integer + Parameter addressSize bound to: 11 - type: integer + Parameter dataSize bound to: 24 - type: integer +INFO: [Synth 8-3491] module 'snakeRam' declared at 'C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/snakeRam.vhd:37' bound to instance 'SNAKE_RAM' of component 'snakeRam' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/RAMController.vhd:61] +INFO: [Synth 8-638] synthesizing module 'snakeRam' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/snakeRam.vhd:54] + Parameter length bound to: 1200 - type: integer + Parameter addressSize bound to: 11 - type: integer + Parameter dataSize bound to: 24 - type: integer +INFO: [Synth 8-256] done synthesizing module 'snakeRam' (5#1) [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/snakeRam.vhd:54] + Parameter length bound to: 1200 - type: integer + Parameter addressSize bound to: 11 - type: integer + Parameter dataSize bound to: 11 - type: integer +INFO: [Synth 8-3491] module 'snakeRam' declared at 'C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/snakeRam.vhd:37' bound to instance 'MAT_RAM' of component 'snakeRam' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/RAMController.vhd:79] +INFO: [Synth 8-638] synthesizing module 'snakeRam__parameterized1' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/snakeRam.vhd:54] + Parameter length bound to: 1200 - type: integer + Parameter addressSize bound to: 11 - type: integer + Parameter dataSize bound to: 11 - type: integer +INFO: [Synth 8-256] done synthesizing module 'snakeRam__parameterized1' (5#1) [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/snakeRam.vhd:54] +INFO: [Synth 8-256] done synthesizing module 'RAMController' (6#1) [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/RAMController.vhd:37] + Parameter dataSize bound to: 24 - type: integer +INFO: [Synth 8-3491] module 'updateSnake' declared at 'C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd:37' bound to instance 'UPD' of component 'updateSnake' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/VGA_top.vhd:309] +INFO: [Synth 8-638] synthesizing module 'updateSnake' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd:56] + Parameter dataSize bound to: 24 - type: integer +WARNING: [Synth 8-5825] expecting unsigned expression [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd:112] +WARNING: [Synth 8-6014] Unused sequential element cSnake_reg[X] was removed. [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd:93] +WARNING: [Synth 8-6014] Unused sequential element cSnake_reg[Y] was removed. [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd:93] +WARNING: [Synth 8-6014] Unused sequential element cSnake_reg[dirX] was removed. [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd:93] +WARNING: [Synth 8-6014] Unused sequential element cSnake_reg[dirY] was removed. [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd:93] +WARNING: [Synth 8-6014] Unused sequential element cSnake_reg[isDefined] was removed. [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd:93] +WARNING: [Synth 8-6014] Unused sequential element isUpdating_reg was removed. [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd:69] +WARNING: [Synth 8-6014] Unused sequential element updateIndex_reg was removed. [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd:70] +INFO: [Synth 8-256] done synthesizing module 'updateSnake' (7#1) [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd:56] + Parameter addressSize bound to: 10 - type: integer + Parameter length bound to: 768 - type: integer + Parameter dataSize bound to: 24 - type: integer + Parameter fileName bound to: C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sprites/sprites.mem - type: string +INFO: [Synth 8-3491] module 'spritesRom' declared at 'C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/spritesRom.vhd:36' bound to instance 'ROM' of component 'spritesRom' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/VGA_top.vhd:326] +INFO: [Synth 8-638] synthesizing module 'spritesRom' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/spritesRom.vhd:47] + Parameter addressSize bound to: 10 - type: integer + Parameter length bound to: 768 - type: integer + Parameter dataSize bound to: 24 - type: integer + Parameter fileName bound to: C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sprites/sprites.mem - type: string +INFO: [Synth 8-256] done synthesizing module 'spritesRom' (8#1) [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/spritesRom.vhd:47] +INFO: [Synth 8-256] done synthesizing module 'VGA_top' (9#1) [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/VGA_top.vhd:48] +WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[10] +WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[9] +WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[8] +WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[7] +WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[6] +WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[5] +WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[4] +WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[3] +WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[2] +WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[1] +WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[0] +WARNING: [Synth 8-3331] design updateSnake has unconnected port clk_lente WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port X[9] WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port X[8] WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port X[7] @@ -66,8 +130,9 @@ WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port Y[3] WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port Y[2] WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port Y[1] WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port Y[0] +WARNING: [Synth 8-3331] design VGA_top has unconnected port led[3] --------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 780.012 ; gain = 406.445 +Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 528.090 ; gain = 154.043 --------------------------------------------------------------------------------- Report Check Netlist: @@ -80,191 +145,163 @@ Report Check Netlist: Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 780.012 ; gain = 406.445 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 528.090 ; gain = 154.043 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 780.012 ; gain = 406.445 +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 528.090 ; gain = 154.043 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z010clg400-1 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine -Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0/clk_wiz_1_in_context.xdc] for cell 'U0' -Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0/clk_wiz_1_in_context.xdc] for cell 'U0' -Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc] -Finished Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc] -INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/VGA_top_propImpl.xdc]. +Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0/clk_wiz_1_in_context.xdc] for cell 'U0' +Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0/clk_wiz_1_in_context.xdc] for cell 'U0' +Parsing XDC File [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/ZYBO_Master.xdc] +Finished Parsing XDC File [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/ZYBO_Master.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/ZYBO_Master.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/VGA_top_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/VGA_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. -Parsing XDC File [C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/synth_1/dont_touch.xdc] -Finished Parsing XDC File [C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/synth_1/dont_touch.xdc] -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1102.379 ; gain = 0.000 +Parsing XDC File [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/synth_1/dont_touch.xdc] +Finished Parsing XDC File [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/synth_1/dont_touch.xdc] +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 876.688 ; gain = 0.000 Completed Processing XDC Constraints -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1102.379 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 876.688 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1102.379 ; gain = 0.000 -Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1102.379 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 876.688 ; gain = 0.000 +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 876.688 ; gain = 0.000 --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 1102.379 ; gain = 728.812 +Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:22 . Memory (MB): peak = 876.688 ; gain = 502.641 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z010clg400-1 --------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 1102.379 ; gain = 728.812 +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:22 . Memory (MB): peak = 876.688 ; gain = 502.641 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- -Applied set_property IO_BUFFER_TYPE = NONE for H125MHz. (constraint file c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0/clk_wiz_1_in_context.xdc, line 3). -Applied set_property CLOCK_BUFFER_TYPE = NONE for H125MHz. (constraint file c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0/clk_wiz_1_in_context.xdc, line 4). +Applied set_property IO_BUFFER_TYPE = NONE for H125MHz. (constraint file c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0/clk_wiz_1_in_context.xdc, line 3). +Applied set_property CLOCK_BUFFER_TYPE = NONE for H125MHz. (constraint file c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0/clk_wiz_1_in_context.xdc, line 4). Applied set_property DONT_TOUCH = true for U0. (constraint file auto generated constraint, line ). --------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 1102.379 ; gain = 728.812 +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:09 ; elapsed = 00:00:22 . Memory (MB): peak = 876.688 ; gain = 502.641 --------------------------------------------------------------------------------- -INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Position.vhd:58] -INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Position.vhd:58] -WARNING: [Synth 8-327] inferring latch for variable 'snake_reg[0][X]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:80] -WARNING: [Synth 8-327] inferring latch for variable 'snake_reg[101][X]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:80] -WARNING: [Synth 8-327] inferring latch for variable 'snake_reg[102][X]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:80] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[0,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[1,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[2,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[3,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[4,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[5,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[6,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[7,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[8,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[9,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[10,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[11,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[12,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[13,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[14,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[15,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[16,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[17,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[18,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[19,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[20,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[21,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[22,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[23,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[24,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[25,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[26,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[27,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[28,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[29,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[30,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[31,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[32,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[33,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[34,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[35,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[36,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[37,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[38,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[39,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[0,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[1,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[2,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[3,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[4,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[5,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[6,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[7,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[8,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[9,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[10,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[11,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[12,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[13,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[14,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[15,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[16,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[17,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[18,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[19,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[20,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[21,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[22,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[23,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[24,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[25,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[26,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[27,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[28,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[29,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[30,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[31,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[32,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[33,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[34,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[35,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[36,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[37,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[38,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[39,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[0,2]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[1,2]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[2,2]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[3,2]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[4,2]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[5,2]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[6,2]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[7,2]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[8,2]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[9,2]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[10,2]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[11,2]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[12,2]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[13,2]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[14,2]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[15,2]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[16,2]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -INFO: [Common 17-14] Message 'Synth 8-327' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:98] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:98] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:98] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:98] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:98] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:98] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:98] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:98] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:98] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:98] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:98] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:98] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:98] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:98] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:98] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:98] +INFO: [Synth 8-5544] ROM "sOff" won't be mapped to Block RAM because address size (1) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "sOff" won't be mapped to Block RAM because address size (1) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "sOff" won't be mapped to Block RAM because address size (1) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "sOff" won't be mapped to Block RAM because address size (1) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "sOff" won't be mapped to Block RAM because address size (1) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "sOff" won't be mapped to Block RAM because address size (1) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "sOff" won't be mapped to Block RAM because address size (1) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "sOff" won't be mapped to Block RAM because address size (1) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "sOff" won't be mapped to Block RAM because address size (1) smaller than threshold (5) +INFO: [Synth 8-5545] ROM "running" won't be mapped to RAM because address size (32) is larger than maximum supported(25) +INFO: [Synth 8-5545] ROM "dataReady" won't be mapped to RAM because address size (32) is larger than maximum supported(25) +INFO: [Synth 8-5545] ROM "clkCount" won't be mapped to RAM because address size (32) is larger than maximum supported(25) +INFO: [Synth 8-5546] ROM "writeEnable" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5544] ROM "writeEnable" won't be mapped to Block RAM because address size (4) smaller than threshold (5) +INFO: [Synth 8-5546] ROM "mem" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-3971] The signal mem_reg was recognized as a true dual port RAM template. +INFO: [Synth 8-3971] The signal mem_reg was recognized as a true dual port RAM template. +WARNING: [Synth 8-327] inferring latch for variable 'currentSnake_reg[isDefined]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd:108] +WARNING: [Synth 8-327] inferring latch for variable 'currentSnake_reg[dirY]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd:108] +WARNING: [Synth 8-327] inferring latch for variable 'currentSnake_reg[dirX]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd:108] +WARNING: [Synth 8-327] inferring latch for variable 'currentSnake_reg[Y]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd:108] +WARNING: [Synth 8-327] inferring latch for variable 'currentSnake_reg[X]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd:108] +WARNING: [Synth 8-327] inferring latch for variable 'matAddress_reg' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd:122] --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:44 ; elapsed = 00:00:50 . Memory (MB): peak = 1272.715 ; gain = 899.148 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:23 . Memory (MB): peak = 876.688 ; gain = 502.641 --------------------------------------------------------------------------------- Report RTL Partitions: -+------+----------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+------+----------------+------------+----------+ -|1 |Gene_Snake__GB0 | 1| 55621| -|2 |Gene_Snake__GB1 | 1| 2622| -|3 |Gene_Snake__GB2 | 1| 11799| -|4 |Gene_Snake__GB3 | 1| 15734| -|5 |VGA_top__GC0 | 1| 947| -+------+----------------+------------+----------+ ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : - 2 Input 11 Bit Adders := 1 - 2 Input 10 Bit Adders := 11 - 2 Input 9 Bit Adders := 10 + 2 Input 32 Bit Adders := 1 + 2 Input 11 Bit Adders := 2 + 3 Input 11 Bit Adders := 9 + 2 Input 10 Bit Adders := 21 + 3 Input 10 Bit Adders := 18 + 2 Input 9 Bit Adders := 20 + 2 Input 8 Bit Adders := 1 + 2 Input 7 Bit Adders := 2 + 2 Input 6 Bit Adders := 1 + 2 Input 4 Bit Adders := 1 +---Registers : - 11 Bit Registers := 1 - 10 Bit Registers := 2 - 9 Bit Registers := 1 - 1 Bit Registers := 1 + 32 Bit Registers := 1 + 24 Bit Registers := 12 + 11 Bit Registers := 13 + 10 Bit Registers := 1 + 8 Bit Registers := 1 + 6 Bit Registers := 2 + 5 Bit Registers := 3 + 4 Bit Registers := 1 + 1 Bit Registers := 8 ++---RAMs : + 28K Bit RAMs := 1 + 12K Bit RAMs := 1 +---Muxes : - 3 Input 10 Bit Muxes := 4 - 2 Input 10 Bit Muxes := 3 - 2 Input 9 Bit Muxes := 3 - 2 Input 6 Bit Muxes := 1 - 1201 Input 2 Bit Muxes := 4 - 2 Input 2 Bit Muxes := 1 - 2 Input 1 Bit Muxes := 8 - 1201 Input 1 Bit Muxes := 3 + 2 Input 32 Bit Muxes := 1 + 2 Input 24 Bit Muxes := 2 + 769 Input 24 Bit Muxes := 1 + 2 Input 12 Bit Muxes := 9 + 2 Input 11 Bit Muxes := 12 + 2 Input 10 Bit Muxes := 45 + 2 Input 9 Bit Muxes := 4 + 2 Input 8 Bit Muxes := 5 + 2 Input 7 Bit Muxes := 1 + 2 Input 6 Bit Muxes := 2 + 2 Input 5 Bit Muxes := 4 + 2 Input 4 Bit Muxes := 1 + 4 Input 4 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 14 + 9 Input 1 Bit Muxes := 2 + 3 Input 1 Bit Muxes := 2 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- @@ -272,16 +309,6 @@ Finished RTL Component Statistics Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report -Module Gene_Snake -Detailed RTL Component Info : -+---Adders : - 2 Input 10 Bit Adders := 8 - 2 Input 9 Bit Adders := 8 -+---Muxes : - 3 Input 10 Bit Muxes := 4 - 1201 Input 2 Bit Muxes := 4 - 2 Input 1 Bit Muxes := 6 - 1201 Input 1 Bit Muxes := 3 Module GeneSync Detailed RTL Component Info : +---Adders : @@ -298,21 +325,83 @@ Module GeneRGB_V1 Detailed RTL Component Info : +---Muxes : 2 Input 6 Bit Muxes := 1 -Module Gene_Position + 2 Input 5 Bit Muxes := 2 +Module Gene_Snake Detailed RTL Component Info : +---Adders : - 2 Input 10 Bit Adders := 1 - 2 Input 9 Bit Adders := 1 + 3 Input 11 Bit Adders := 9 + 2 Input 10 Bit Adders := 18 + 3 Input 10 Bit Adders := 18 + 2 Input 9 Bit Adders := 18 +---Registers : - 10 Bit Registers := 1 - 9 Bit Registers := 1 + 8 Bit Registers := 1 + 6 Bit Registers := 2 + 5 Bit Registers := 3 + 1 Bit Registers := 3 +---Muxes : - 2 Input 2 Bit Muxes := 1 + 2 Input 12 Bit Muxes := 9 + 2 Input 11 Bit Muxes := 9 + 2 Input 10 Bit Muxes := 42 + 2 Input 8 Bit Muxes := 1 + 2 Input 6 Bit Muxes := 1 + 2 Input 5 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 -Module Diviseur + 9 Input 1 Bit Muxes := 2 +Module snakeRam Detailed RTL Component Info : +---Registers : - 1 Bit Registers := 1 + 24 Bit Registers := 10 ++---RAMs : + 28K Bit RAMs := 1 +Module snakeRam__parameterized1 +Detailed RTL Component Info : ++---Registers : + 11 Bit Registers := 10 ++---RAMs : + 12K Bit RAMs := 1 +Module RAMController +Detailed RTL Component Info : ++---Adders : + 2 Input 32 Bit Adders := 1 + 2 Input 8 Bit Adders := 1 + 2 Input 7 Bit Adders := 2 + 2 Input 6 Bit Adders := 1 ++---Registers : + 32 Bit Registers := 1 + 1 Bit Registers := 2 ++---Muxes : + 2 Input 32 Bit Muxes := 1 + 2 Input 11 Bit Muxes := 2 + 2 Input 9 Bit Muxes := 1 + 2 Input 8 Bit Muxes := 3 + 2 Input 7 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 3 +Module updateSnake +Detailed RTL Component Info : ++---Adders : + 2 Input 11 Bit Adders := 1 + 2 Input 10 Bit Adders := 1 + 2 Input 9 Bit Adders := 1 + 2 Input 4 Bit Adders := 1 ++---Registers : + 24 Bit Registers := 1 + 11 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 24 Bit Muxes := 2 + 2 Input 11 Bit Muxes := 1 + 2 Input 8 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 1 + 4 Input 4 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 9 + 3 Input 1 Bit Muxes := 2 +Module spritesRom +Detailed RTL Component Info : ++---Registers : + 24 Bit Registers := 1 ++---Muxes : + 769 Input 24 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- @@ -329,250 +418,205 @@ Finished Part Resource Summary Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Warning: Parallel synthesis criteria is not met -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[101][Y][0] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][Y][0] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[101][Y][1] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][Y][1] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][X][0] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[101][X][0] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[102][X][0] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][X][1] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[101][X][1] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[102][X][1] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[101][Y][2] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][Y][2] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[101][Y][3] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][Y][3] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[101][Y][4] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][Y][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[101][Y][5] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][Y][5] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[101][Y][6] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][Y][6] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[101][Y][7] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][Y][7] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[101][Y][8] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][Y][8] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][X][2] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[101][X][2] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[102][X][2] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][X][8] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[101][X][8] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[102][X][8] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][X][7] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[101][X][7] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[102][X][7] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][X][6] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[101][X][6] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[102][X][6] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][X][5] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[101][X][5] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[102][X][5] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][X][4] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[101][X][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[102][X][4] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][X][3] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[101][X][3] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[102][X][3] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][X][9] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[101][X][9] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[102][X][9] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[101][isDefined] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[39,21][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[38,21][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[37,21][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[36,21][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[35,21][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[34,21][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[33,21][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[32,21][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[31,21][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[30,21][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[29,21][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[28,21][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[27,21][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[26,21][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[25,21][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[24,21][4] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\mat_reg[23,21][4] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\mat_reg[22,21][4] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\mat_reg[21,21][4] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\mat_reg[20,21][4] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\mat_reg[19,21][4] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\mat_reg[18,21][4] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\mat_reg[17,21][4] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\mat_reg[16,21][4] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\mat_reg[15,21][4] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\mat_reg[14,21][4] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\mat_reg[13,21][4] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\mat_reg[12,21][4] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\mat_reg[11,21][4] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\mat_reg[10,21][4] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\mat_reg[9,21][4] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\mat_reg[8,21][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[7,21][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[6,21][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[5,21][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[4,21][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[3,21][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[2,21][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[1,21][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[0,21][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[39,13][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[38,13][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[37,13][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[36,13][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[35,13][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[34,13][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[33,13][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[32,13][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[31,13][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[30,13][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[29,13][4] ) -INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[39,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[38,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[37,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[36,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[35,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[34,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[33,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[32,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[31,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[30,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[29,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[28,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[27,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[26,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[25,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[24,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[23,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[22,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[21,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[20,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[19,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[18,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[17,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[16,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[15,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[14,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[13,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[12,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[11,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[10,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[9,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[8,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[7,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[6,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[5,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[4,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[3,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[2,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[1,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[0,22][0]' (LD) to 'U6i_2/mat_reg[0,22][1]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[39,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[38,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[37,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[36,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[35,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[34,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[33,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[32,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[31,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[30,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[29,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[28,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[27,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[26,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[25,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[24,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[23,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[22,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[21,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[20,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[19,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[18,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[17,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[16,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[15,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[14,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[13,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[12,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[11,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[10,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[9,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[8,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[7,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[6,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[5,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[4,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[3,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[2,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[1,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[0,22][1]' (LD) to 'U6i_2/mat_reg[0,22][2]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[39,22][2]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[38,22][2]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[37,22][2]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[36,22][2]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[35,22][2]' (LD) to 'U6i_2/mat_reg[0,22][2]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[34,22][2]' (LD) to 'U6i_2/mat_reg[0,22][2]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[33,22][2]' (LD) to 'U6i_2/mat_reg[0,22][2]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[32,22][2]' (LD) to 'U6i_2/mat_reg[0,22][2]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[31,22][2]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[30,22][2]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[29,22][2]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[28,22][2]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[27,22][2]' (LD) to 'U6i_2/mat_reg[0,22][2]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[26,22][2]' (LD) to 'U6i_2/mat_reg[0,22][2]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[25,22][2]' (LD) to 'U6i_2/mat_reg[0,22][2]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[24,22][2]' (LD) to 'U6i_2/mat_reg[0,22][2]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[23,22][2]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[22,22][2]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[21,22][2]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[20,22][2]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-5545] ROM "clkCount" won't be mapped to RAM because address size (32) is larger than maximum supported(25) +INFO: [Synth 8-5545] ROM "running" won't be mapped to RAM because address size (32) is larger than maximum supported(25) +INFO: [Synth 8-5545] ROM "dataReady" won't be mapped to RAM because address size (32) is larger than maximum supported(25) +INFO: [Synth 8-4471] merging register 'index_reg[10:0]' into 'index_reg[10:0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd:74] +INFO: [Synth 8-5544] ROM "writeEnable" won't be mapped to Block RAM because address size (4) smaller than threshold (5) +INFO: [Synth 8-5546] ROM "writeEnable" won't be mapped to RAM because it is too sparse +WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[10] +WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[9] +WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[8] +WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[7] +WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[6] +WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[5] +WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[4] +WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[3] +WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[2] +WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[1] +WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[0] +WARNING: [Synth 8-3331] design updateSnake has unconnected port clk_lente +WARNING: [Synth 8-3331] design Gene_Snake has unconnected port currentSnakes[0][dirX][0] +WARNING: [Synth 8-3331] design Gene_Snake has unconnected port currentSnakes[1][dirX][0] +WARNING: [Synth 8-3331] design Gene_Snake has unconnected port currentSnakes[2][dirX][0] +WARNING: [Synth 8-3331] design Gene_Snake has unconnected port currentSnakes[3][dirX][0] +WARNING: [Synth 8-3331] design Gene_Snake has unconnected port currentSnakes[4][dirX][0] +WARNING: [Synth 8-3331] design Gene_Snake has unconnected port currentSnakes[5][dirX][0] +WARNING: [Synth 8-3331] design Gene_Snake has unconnected port currentSnakes[6][dirX][0] +WARNING: [Synth 8-3331] design Gene_Snake has unconnected port currentSnakes[7][dirX][0] +WARNING: [Synth 8-3331] design Gene_Snake has unconnected port currentSnakes[8][dirX][0] +WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port X[9] +WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port X[8] +WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port X[7] +WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port X[6] +WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port X[5] +WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port X[4] +WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port X[3] +WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port X[2] +WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port X[1] +WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port X[0] +WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port Y[8] +WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port Y[7] +WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port Y[6] +WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port Y[5] +WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port Y[4] +WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port Y[3] +WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port Y[2] +WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port Y[1] +WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port Y[0] +WARNING: [Synth 8-3331] design VGA_top has unconnected port led[3] +INFO: [Synth 8-3971] The signal SNAKE_RAM/mem_reg was recognized as a true dual port RAM template. +INFO: [Synth 8-4652] Swapped enable and write-enable on 16 RAM instances of RAM SNAKE_RAM/mem_reg to conserve power +INFO: [Synth 8-3971] The signal MAT_RAM/mem_reg was recognized as a true dual port RAM template. +INFO: [Synth 8-4652] Swapped enable and write-enable on 8 RAM instances of RAM MAT_RAM/mem_reg to conserve power +INFO: [Synth 8-3886] merging instance 'UPD/currentSnake_reg[X][2]' (LD) to 'UPD/currentSnake_reg[X][9]' +INFO: [Synth 8-3886] merging instance 'UPD/currentSnake_reg[X][3]' (LD) to 'UPD/currentSnake_reg[Y][3]' +INFO: [Synth 8-3886] merging instance 'UPD/currentSnake_reg[isDefined]' (LD) to 'UPD/currentSnake_reg[dirX][0]' +INFO: [Synth 8-3886] merging instance 'UPD/currentSnake_reg[dirX][0]' (LD) to 'UPD/currentSnake_reg[dirX][1]' +INFO: [Synth 8-3886] merging instance 'UPD/currentSnake_reg[Y][0]' (LD) to 'UPD/currentSnake_reg[X][9]' +INFO: [Synth 8-3886] merging instance 'UPD/currentSnake_reg[Y][1]' (LD) to 'UPD/currentSnake_reg[X][9]' +INFO: [Synth 8-3886] merging instance 'UPD/currentSnake_reg[Y][2]' (LD) to 'UPD/currentSnake_reg[X][9]' +INFO: [Synth 8-3333] propagating constant 1 across sequential element (UPD/\currentSnake_reg[Y][3] ) +INFO: [Synth 8-3886] merging instance 'UPD/currentSnake_reg[Y][4]' (LD) to 'UPD/currentSnake_reg[X][9]' +INFO: [Synth 8-3886] merging instance 'UPD/currentSnake_reg[Y][5]' (LD) to 'UPD/currentSnake_reg[X][9]' +INFO: [Synth 8-3886] merging instance 'UPD/currentSnake_reg[Y][6]' (LD) to 'UPD/currentSnake_reg[X][9]' +INFO: [Synth 8-3886] merging instance 'UPD/currentSnake_reg[Y][7]' (LD) to 'UPD/currentSnake_reg[X][9]' +INFO: [Synth 8-3886] merging instance 'UPD/currentSnake_reg[Y][8]' (LD) to 'UPD/currentSnake_reg[X][9]' +INFO: [Synth 8-3886] merging instance 'UPD/currentSnake_reg[X][0]' (LD) to 'UPD/currentSnake_reg[X][9]' +INFO: [Synth 8-3886] merging instance 'UPD/currentSnake_reg[X][1]' (LD) to 'UPD/currentSnake_reg[X][9]' +INFO: [Synth 8-3886] merging instance 'UPD/currentSnake_reg[X][8]' (LD) to 'UPD/currentSnake_reg[X][9]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (UPD/\currentSnake_reg[X][9] ) +INFO: [Synth 8-3886] merging instance 'ROM/data_reg[8]' (FD) to 'ROM/data_reg[9]' +INFO: [Synth 8-3886] merging instance 'ROM/data_reg[11]' (FD) to 'ROM/data_reg[12]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (ROM/\data_reg[12] ) +INFO: [Synth 8-3886] merging instance 'ROM/data_reg[2]' (FD) to 'ROM/data_reg[3]' +INFO: [Synth 8-3886] merging instance 'ROM/data_reg[19]' (FD) to 'ROM/data_reg[20]' +INFO: [Synth 8-3886] merging instance 'ROM/data_reg[3]' (FD) to 'ROM/data_reg[4]' +INFO: [Synth 8-3886] merging instance 'ROM/data_reg[4]' (FD) to 'ROM/data_reg[5]' +INFO: [Synth 8-3886] merging instance 'ROM/data_reg[5]' (FD) to 'ROM/data_reg[6]' +INFO: [Synth 8-3886] merging instance 'ROM/data_reg[6]' (FD) to 'ROM/data_reg[7]' +INFO: [Synth 8-3886] merging instance 'SNAKE/snakeColor_reg[B][0]' (FDC) to 'SNAKE/snakeColor_reg[B][1]' +INFO: [Synth 8-3886] merging instance 'SNAKE/snakeColor_reg[A][2]' (FDC) to 'SNAKE/snakeColor_reg[A][3]' +INFO: [Synth 8-3886] merging instance 'SNAKE/snakeColor_reg[R][0]' (FDC) to 'SNAKE/snakeColor_reg[R][1]' +INFO: [Synth 8-3886] merging instance 'SNAKE/snakeColor_reg[A][3]' (FDC) to 'SNAKE/snakeColor_reg[A][4]' +INFO: [Synth 8-3886] merging instance 'SNAKE/snakeColor_reg[A][4]' (FDC) to 'SNAKE/snakeColor_reg[A][5]' +INFO: [Synth 8-3886] merging instance 'SNAKE/snakeColor_reg[A][5]' (FDC) to 'SNAKE/snakeColor_reg[A][6]' +INFO: [Synth 8-3886] merging instance 'SNAKE/snakeColor_reg[A][6]' (FDC) to 'SNAKE/snakeColor_reg[A][7]' +WARNING: [Synth 8-3332] Sequential element (currentSnake_reg[Y][3]) is unused and will be removed from module updateSnake. +WARNING: [Synth 8-3332] Sequential element (currentSnake_reg[X][9]) is unused and will be removed from module updateSnake. --------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:22 ; elapsed = 00:01:28 . Memory (MB): peak = 1310.512 ; gain = 936.945 +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:33 . Memory (MB): peak = 876.688 ; gain = 502.641 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- +Block RAM: Preliminary Mapping Report (see note below) +-------NONE------- +Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once. +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_2_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_2_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_3_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_3_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_4_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_4_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_5_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_5_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_6_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_6_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_7_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_7_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_8_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_8_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_9_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_9_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-4652] Swapped enable and write-enable on 1 RAM instances of RAM MAT_RAM/mem_reg to conserve power +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_2/MAT_RAM/mem_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_2/MAT_RAM/mem_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_2/MAT_RAM/mem_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_2/MAT_RAM/mem_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_2/MAT_RAM/mem_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_2/MAT_RAM/mem_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_2/MAT_RAM/mem_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_2/MAT_RAM/mem_reg_8 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_2/MAT_RAM/mem_reg_9 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. + Report RTL Partitions: -+------+----------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+------+----------------+------------+----------+ -|1 |Gene_Snake__GB0 | 1| 504| -|2 |Gene_Snake__GB2 | 1| 80| -|3 |Gene_Snake__GB3 | 1| 58| -|4 |VGA_top__GC0 | 1| 179| -+------+----------------+------------+----------+ ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- INFO: [Synth 8-5578] Moved timing constraint from pin 'U0/clk_out1' to pin 'U0/bbstub_clk_out1/O' INFO: [Synth 8-5819] Moved 1 constraints on hierarchical pins to their respective driving/loading pins --------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:28 ; elapsed = 00:01:34 . Memory (MB): peak = 1310.512 ; gain = 936.945 +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:26 ; elapsed = 00:00:39 . Memory (MB): peak = 876.688 ; gain = 502.641 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- +INFO: [Synth 8-3971] The signal SNAKE_RAM/mem_reg was recognized as a true dual port RAM template. --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:01:28 ; elapsed = 00:01:34 . Memory (MB): peak = 1310.512 ; gain = 936.945 +Finished Timing Optimization : Time (s): cpu = 00:00:30 ; elapsed = 00:00:43 . Memory (MB): peak = 976.145 ; gain = 602.098 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- + +Block RAM: Final Mapping Report +-------NONE------- +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Report RTL Partitions: -+------+----------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+------+----------------+------------+----------+ -|1 |Gene_Snake__GB0 | 1| 504| -|2 |Gene_Snake__GB2 | 1| 80| -|3 |Gene_Snake__GB3 | 1| 58| -|4 |VGA_top__GC0 | 1| 179| -+------+----------------+------------+----------+ ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_2_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_2_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_3_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_3_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_4_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_4_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_5_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_5_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_6_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_6_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_7_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_7_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_8_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_8_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_9_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_9_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/MAT_RAM/mem_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/MAT_RAM/mem_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/MAT_RAM/mem_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/MAT_RAM/mem_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/MAT_RAM/mem_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/MAT_RAM/mem_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/MAT_RAM/mem_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/MAT_RAM/mem_reg_8 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/MAT_RAM/mem_reg_9 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:01:28 ; elapsed = 00:01:34 . Memory (MB): peak = 1310.512 ; gain = 936.945 +Finished Technology Mapping : Time (s): cpu = 00:00:31 ; elapsed = 00:00:44 . Memory (MB): peak = 976.145 ; gain = 602.098 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -592,11 +636,12 @@ Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- +INFO: [Synth 8-6064] Net led[1] is driving 54 big block pins (URAM, BRAM and DSP loads). Created 6 replicas of its driver. --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:01:29 ; elapsed = 00:01:35 . Memory (MB): peak = 1310.512 ; gain = 936.945 +Finished IO Insertion : Time (s): cpu = 00:00:32 ; elapsed = 00:00:45 . Memory (MB): peak = 976.145 ; gain = 602.098 --------------------------------------------------------------------------------- Report Check Netlist: @@ -609,7 +654,7 @@ Report Check Netlist: Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:01:29 ; elapsed = 00:01:35 . Memory (MB): peak = 1310.512 ; gain = 936.945 +Finished Renaming Generated Instances : Time (s): cpu = 00:00:32 ; elapsed = 00:00:45 . Memory (MB): peak = 976.145 ; gain = 602.098 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -621,25 +666,25 @@ Report RTL Partitions: Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:29 ; elapsed = 00:01:35 . Memory (MB): peak = 1310.512 ; gain = 936.945 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:32 ; elapsed = 00:00:45 . Memory (MB): peak = 976.145 ; gain = 602.098 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:01:29 ; elapsed = 00:01:35 . Memory (MB): peak = 1310.512 ; gain = 936.945 +Finished Renaming Generated Ports : Time (s): cpu = 00:00:32 ; elapsed = 00:00:45 . Memory (MB): peak = 976.145 ; gain = 602.098 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:01:29 ; elapsed = 00:01:35 . Memory (MB): peak = 1310.512 ; gain = 936.945 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:32 ; elapsed = 00:00:45 . Memory (MB): peak = 976.145 ; gain = 602.098 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:01:29 ; elapsed = 00:01:35 . Memory (MB): peak = 1310.512 ; gain = 936.945 +Finished Renaming Generated Nets : Time (s): cpu = 00:00:32 ; elapsed = 00:00:45 . Memory (MB): peak = 976.145 ; gain = 602.098 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report @@ -657,46 +702,68 @@ Report Cell Usage: | |Cell |Count | +------+-----------------+------+ |1 |clk_wiz_0_bbox_0 | 1| -|2 |CARRY4 | 34| -|3 |LUT1 | 4| -|4 |LUT2 | 28| -|5 |LUT3 | 7| -|6 |LUT4 | 62| -|7 |LUT5 | 47| -|8 |LUT6 | 65| -|9 |FDRE | 21| -|10 |OBUF | 18| +|2 |CARRY4 | 266| +|3 |LUT1 | 12| +|4 |LUT2 | 275| +|5 |LUT3 | 323| +|6 |LUT4 | 365| +|7 |LUT5 | 358| +|8 |LUT6 | 447| +|9 |MUXF7 | 19| +|10 |MUXF8 | 1| +|11 |RAMB18E1_1 | 9| +|12 |RAMB36E1 | 9| +|13 |RAMB36E1_1 | 9| +|14 |FDCE | 62| +|15 |FDPE | 10| +|16 |FDRE | 114| +|17 |FDSE | 1| +|18 |LD | 17| +|19 |LDC | 6| +|20 |IBUF | 1| +|21 |OBUF | 21| +|22 |OBUFT | 1| +------+-----------------+------+ Report Instance Areas: -+------+---------+---------+------+ -| |Instance |Module |Cells | -+------+---------+---------+------+ -|1 |top | | 287| -|2 | U1 |GeneSync | 267| -+------+---------+---------+------+ ++------+--------------+-------------------------+------+ +| |Instance |Module |Cells | ++------+--------------+-------------------------+------+ +|1 |top | | 2327| +|2 | ROM |spritesRom | 13| +|3 | RAMCTRL |RAMController | 1346| +|4 | MAT_RAM |snakeRam__parameterized1 | 9| +|5 | SNAKE_RAM |snakeRam | 1282| +|6 | SNAKE |Gene_Snake | 375| +|7 | SYNC |GeneSync | 344| +|8 | UPD |updateSnake | 155| +|9 | UPD_CLK_DIV |Diviseur | 70| ++------+--------------+-------------------------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:01:29 ; elapsed = 00:01:35 . Memory (MB): peak = 1310.512 ; gain = 936.945 +Finished Writing Synthesis Report : Time (s): cpu = 00:00:32 ; elapsed = 00:00:45 . Memory (MB): peak = 976.145 ; gain = 602.098 --------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 1207 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:01:03 ; elapsed = 00:01:23 . Memory (MB): peak = 1310.512 ; gain = 614.578 -Synthesis Optimization Complete : Time (s): cpu = 00:01:29 ; elapsed = 00:01:35 . Memory (MB): peak = 1310.512 ; gain = 936.945 +Synthesis finished with 0 errors, 0 critical warnings and 49 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:25 ; elapsed = 00:00:28 . Memory (MB): peak = 976.145 ; gain = 253.500 +Synthesis Optimization Complete : Time (s): cpu = 00:00:32 ; elapsed = 00:00:45 . Memory (MB): peak = 976.145 ; gain = 602.098 INFO: [Project 1-571] Translating synthesized netlist -INFO: [Netlist 29-17] Analyzing 34 Unisim elements for replacement +INFO: [Netlist 29-17] Analyzing 336 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1310.512 ; gain = 0.000 +INFO: [Opt 31-140] Inserted 1 IBUFs to IO ports without IO buffers. +INFO: [Opt 31-138] Pushed 1 inverter(s) to 17 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 976.145 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. + A total of 23 instances were transformed. + LD => LDCE (inverted pins: G): 17 instances + LDC => LDCE: 6 instances INFO: [Common 17-83] Releasing license: Synthesis -237 Infos, 127 Warnings, 0 Critical Warnings and 0 Errors encountered. +209 Infos, 94 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:01:30 ; elapsed = 00:01:37 . Memory (MB): peak = 1310.512 ; gain = 948.426 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1310.512 ; gain = 0.000 +synth_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:48 . Memory (MB): peak = 976.145 ; gain = 613.590 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 976.145 ; gain = 0.000 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/synth_1/VGA_top.dcp' has been generated. +INFO: [Common 17-1381] The checkpoint 'C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/synth_1/VGA_top.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file VGA_top_utilization_synth.rpt -pb VGA_top_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Tue Dec 7 12:42:42 2021... +INFO: [Common 17-206] Exiting Vivado at Tue Jan 4 12:18:30 2022... diff --git a/projet-vga.runs/synth_1/VGA_top_utilization_synth.pb b/projet-vga.runs/synth_1/VGA_top_utilization_synth.pb index 4046529..f9fb6e9 100644 Binary files a/projet-vga.runs/synth_1/VGA_top_utilization_synth.pb and b/projet-vga.runs/synth_1/VGA_top_utilization_synth.pb differ diff --git a/projet-vga.runs/synth_1/VGA_top_utilization_synth.rpt b/projet-vga.runs/synth_1/VGA_top_utilization_synth.rpt index b2823e7..bfe416e 100644 --- a/projet-vga.runs/synth_1/VGA_top_utilization_synth.rpt +++ b/projet-vga.runs/synth_1/VGA_top_utilization_synth.rpt @@ -1,8 +1,8 @@ Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 -| Date : Tue Dec 7 12:42:42 2021 -| Host : irb121-02-w running 64-bit major release (build 9200) +| Date : Tue Jan 4 12:18:30 2022 +| Host : irb121-12-w running 64-bit major release (build 9200) | Command : report_utilization -file VGA_top_utilization_synth.rpt -pb VGA_top_utilization_synth.pb | Design : VGA_top | Device : 7z010clg400-1 @@ -30,14 +30,14 @@ Table of Contents +-------------------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +-------------------------+------+-------+-----------+-------+ -| Slice LUTs* | 170 | 0 | 17600 | 0.97 | -| LUT as Logic | 170 | 0 | 17600 | 0.97 | +| Slice LUTs* | 1481 | 0 | 17600 | 8.41 | +| LUT as Logic | 1481 | 0 | 17600 | 8.41 | | LUT as Memory | 0 | 0 | 6000 | 0.00 | -| Slice Registers | 21 | 0 | 35200 | 0.06 | -| Register as Flip Flop | 21 | 0 | 35200 | 0.06 | -| Register as Latch | 0 | 0 | 35200 | 0.00 | -| F7 Muxes | 0 | 0 | 8800 | 0.00 | -| F8 Muxes | 0 | 0 | 4400 | 0.00 | +| Slice Registers | 210 | 0 | 35200 | 0.60 | +| Register as Flip Flop | 187 | 0 | 35200 | 0.53 | +| Register as Latch | 23 | 0 | 35200 | 0.07 | +| F7 Muxes | 19 | 0 | 8800 | 0.22 | +| F8 Muxes | 1 | 0 | 4400 | 0.02 | +-------------------------+------+-------+-----------+-------+ * Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. @@ -54,23 +54,25 @@ Table of Contents | 0 | _ | Set | - | | 0 | _ | Reset | - | | 0 | Yes | - | - | -| 0 | Yes | - | Set | -| 0 | Yes | - | Reset | -| 0 | Yes | Set | - | -| 21 | Yes | Reset | - | +| 10 | Yes | - | Set | +| 85 | Yes | - | Reset | +| 1 | Yes | Set | - | +| 114 | Yes | Reset | - | +-------+--------------+-------------+--------------+ 2. Memory --------- -+----------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+----------------+------+-------+-----------+-------+ -| Block RAM Tile | 0 | 0 | 60 | 0.00 | -| RAMB36/FIFO* | 0 | 0 | 60 | 0.00 | -| RAMB18 | 0 | 0 | 120 | 0.00 | -+----------------+------+-------+-----------+-------+ ++-------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------+------+-------+-----------+-------+ +| Block RAM Tile | 22.5 | 0 | 60 | 37.50 | +| RAMB36/FIFO* | 18 | 0 | 60 | 30.00 | +| RAMB36E1 only | 18 | | | | +| RAMB18 | 9 | 0 | 120 | 7.50 | +| RAMB18E1 only | 9 | | | | ++-------------------+------+-------+-----------+-------+ * Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 @@ -90,7 +92,7 @@ Table of Contents +-----------------------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +-----------------------------+------+-------+-----------+-------+ -| Bonded IOB | 18 | 0 | 100 | 18.00 | +| Bonded IOB | 24 | 0 | 100 | 24.00 | | Bonded IPADs | 0 | 0 | 2 | 0.00 | | Bonded IOPADs | 0 | 0 | 130 | 0.00 | | PHY_CONTROL | 0 | 0 | 2 | 0.00 | @@ -146,15 +148,25 @@ Table of Contents +----------+------+---------------------+ | Ref Name | Used | Functional Category | +----------+------+---------------------+ -| LUT6 | 65 | LUT | -| LUT4 | 62 | LUT | -| LUT5 | 47 | LUT | -| CARRY4 | 34 | CarryLogic | -| LUT2 | 28 | LUT | -| FDRE | 21 | Flop & Latch | -| OBUF | 18 | IO | -| LUT3 | 7 | LUT | -| LUT1 | 4 | LUT | +| LUT6 | 447 | LUT | +| LUT4 | 365 | LUT | +| LUT5 | 358 | LUT | +| LUT3 | 323 | LUT | +| LUT2 | 275 | LUT | +| CARRY4 | 266 | CarryLogic | +| FDRE | 114 | Flop & Latch | +| FDCE | 62 | Flop & Latch | +| LDCE | 23 | Flop & Latch | +| OBUF | 21 | IO | +| MUXF7 | 19 | MuxFx | +| RAMB36E1 | 18 | Block Memory | +| LUT1 | 12 | LUT | +| FDPE | 10 | Flop & Latch | +| RAMB18E1 | 9 | Block Memory | +| IBUF | 2 | IO | +| OBUFT | 1 | IO | +| MUXF8 | 1 | MuxFx | +| FDSE | 1 | Flop & Latch | +----------+------+---------------------+ diff --git a/projet-vga.runs/synth_1/dont_touch.xdc b/projet-vga.runs/synth_1/dont_touch.xdc index d4ce590..420cc0e 100644 --- a/projet-vga.runs/synth_1/dont_touch.xdc +++ b/projet-vga.runs/synth_1/dont_touch.xdc @@ -1,7 +1,7 @@ # This file is automatically generated. # It contains project source information necessary for synthesis and implementation. -# XDC: C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc +# XDC: C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/ZYBO_Master.xdc -# IP: ip/clk_wiz_0_1/clk_wiz_0.xci +# IP: ip/clk_wiz_0_2/clk_wiz_0.xci set_property DONT_TOUCH TRUE [get_cells -hier -filter {REF_NAME==clk_wiz_0 || ORIG_REF_NAME==clk_wiz_0} -quiet] -quiet diff --git a/projet-vga.runs/synth_1/gen_run.xml b/projet-vga.runs/synth_1/gen_run.xml index 714b46b..7025f6a 100644 --- a/projet-vga.runs/synth_1/gen_run.xml +++ b/projet-vga.runs/synth_1/gen_run.xml @@ -1,5 +1,5 @@ - + @@ -11,52 +11,83 @@ - + - + - + + + + + + + + - + - + - + - + + + + + + + + + + + + + + + + + + + - + + + + + + + + - @@ -69,7 +100,7 @@ - + diff --git a/projet-vga.runs/synth_1/project.wdf b/projet-vga.runs/synth_1/project.wdf deleted file mode 100644 index 20c99f7..0000000 --- a/projet-vga.runs/synth_1/project.wdf +++ /dev/null @@ -1,32 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:38:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:5648444c:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:5648444c:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00 -70726f6a656374:69705f636f72655f636f6e7461696e65725c636c6b5f77697a5f76365f305f325c636c6b5f77697a5f30:636f72655f636f6e7461696e6572:66616c7365:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:32:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:32:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:32:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:32:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:32:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:32:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:32:00:00 -5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3535383763343761323538363466333061393431643931396134353838663432:506172656e742050412070726f6a656374204944:00 -eof:1227587853 diff --git a/projet-vga.runs/synth_1/runme.log b/projet-vga.runs/synth_1/runme.log index 0924cce..c5ac1d6 100644 --- a/projet-vga.runs/synth_1/runme.log +++ b/projet-vga.runs/synth_1/runme.log @@ -14,38 +14,102 @@ Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010' INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 12208 +INFO: Helper process launched with PID 8152 --------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 467.680 ; gain = 94.113 +Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 467.723 ; gain = 93.676 --------------------------------------------------------------------------------- -INFO: [Synth 8-638] synthesizing module 'VGA_top' [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/VGA_top.vhd:48] -INFO: [Synth 8-637] synthesizing blackbox instance 'U0' of component 'clk_wiz_0' [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/VGA_top.vhd:148] -INFO: [Synth 8-3491] module 'GeneSync' declared at 'C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/GeneSync.vhd:7' bound to instance 'U1' of component 'GeneSync' [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/VGA_top.vhd:156] -INFO: [Synth 8-638] synthesizing module 'GeneSync' [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/GeneSync.vhd:16] -INFO: [Synth 8-256] done synthesizing module 'GeneSync' (1#1) [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/GeneSync.vhd:16] -INFO: [Synth 8-3491] module 'GeneRGB_V1' declared at 'C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/GeneRGB_V1.vhd:36' bound to instance 'U2' of component 'GeneRGB_V1' [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/VGA_top.vhd:165] -INFO: [Synth 8-638] synthesizing module 'GeneRGB_V1' [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/GeneRGB_V1.vhd:47] -INFO: [Synth 8-256] done synthesizing module 'GeneRGB_V1' (2#1) [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/GeneRGB_V1.vhd:47] -INFO: [Synth 8-3491] module 'Gene_Position' declared at 'C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Position.vhd:34' bound to instance 'U4' of component 'Gene_Position' [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/VGA_top.vhd:183] -INFO: [Synth 8-638] synthesizing module 'Gene_Position' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Position.vhd:45] -INFO: [Synth 8-256] done synthesizing module 'Gene_Position' (3#1) [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Position.vhd:45] - Parameter nbBits bound to: 18 - type: integer -INFO: [Synth 8-3491] module 'Diviseur' declared at 'C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Diviseur.vhd:34' bound to instance 'U5' of component 'Diviseur' [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/VGA_top.vhd:194] -INFO: [Synth 8-638] synthesizing module 'Diviseur' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Diviseur.vhd:42] - Parameter nbBits bound to: 18 - type: integer -INFO: [Synth 8-256] done synthesizing module 'Diviseur' (4#1) [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Diviseur.vhd:42] -INFO: [Synth 8-3491] module 'Gene_Snake' declared at 'C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:36' bound to instance 'U6' of component 'Gene_Snake' [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/VGA_top.vhd:202] -INFO: [Synth 8-638] synthesizing module 'Gene_Snake' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:49] -WARNING: [Synth 8-614] signal 'snakeHere' is read in the process but is not in the sensitivity list [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:70] -WARNING: [Synth 8-5858] RAM snake_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers -INFO: [Synth 8-256] done synthesizing module 'Gene_Snake' (5#1) [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:49] -INFO: [Synth 8-256] done synthesizing module 'VGA_top' (6#1) [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/VGA_top.vhd:48] -WARNING: [Synth 8-3331] design Gene_Snake has unconnected port up -WARNING: [Synth 8-3331] design Gene_Snake has unconnected port down -WARNING: [Synth 8-3331] design Gene_Snake has unconnected port left -WARNING: [Synth 8-3331] design Gene_Snake has unconnected port right -WARNING: [Synth 8-3331] design Gene_Snake has unconnected port clk_rapide -WARNING: [Synth 8-3331] design Gene_Snake has unconnected port clk_lente +INFO: [Synth 8-638] synthesizing module 'VGA_top' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/VGA_top.vhd:48] +INFO: [Synth 8-637] synthesizing blackbox instance 'U0' of component 'clk_wiz_0' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/VGA_top.vhd:217] +INFO: [Synth 8-3491] module 'GeneSync' declared at 'C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/GeneSync.vhd:8' bound to instance 'SYNC' of component 'GeneSync' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/VGA_top.vhd:235] +INFO: [Synth 8-638] synthesizing module 'GeneSync' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/GeneSync.vhd:17] +WARNING: [Synth 8-312] ignoring unsynthesizable construct: non-synthesizable procedure call [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/GeneSync.vhd:45] +INFO: [Synth 8-256] done synthesizing module 'GeneSync' (1#1) [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/GeneSync.vhd:17] +INFO: [Synth 8-3491] module 'GeneRGB_V1' declared at 'C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/GeneRGB_V1.vhd:37' bound to instance 'RGB' of component 'GeneRGB_V1' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/VGA_top.vhd:244] +INFO: [Synth 8-638] synthesizing module 'GeneRGB_V1' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/GeneRGB_V1.vhd:47] +INFO: [Synth 8-256] done synthesizing module 'GeneRGB_V1' (2#1) [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/GeneRGB_V1.vhd:47] + Parameter nbBits bound to: 25 - type: integer +INFO: [Synth 8-3491] module 'Diviseur' declared at 'C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Diviseur.vhd:34' bound to instance 'UPD_CLK_DIV' of component 'Diviseur' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/VGA_top.vhd:254] +INFO: [Synth 8-638] synthesizing module 'Diviseur' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Diviseur.vhd:42] + Parameter nbBits bound to: 25 - type: integer +INFO: [Synth 8-256] done synthesizing module 'Diviseur' (3#1) [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Diviseur.vhd:42] + Parameter addressSize bound to: 11 - type: integer +INFO: [Synth 8-3491] module 'Gene_Snake' declared at 'C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:39' bound to instance 'SNAKE' of component 'Gene_Snake' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/VGA_top.vhd:265] +INFO: [Synth 8-638] synthesizing module 'Gene_Snake' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:63] + Parameter addressSize bound to: 11 - type: integer +INFO: [Synth 8-226] default block is never used [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109] +INFO: [Synth 8-226] default block is never used [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109] +INFO: [Synth 8-226] default block is never used [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109] +INFO: [Synth 8-226] default block is never used [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109] +INFO: [Synth 8-226] default block is never used [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109] +INFO: [Synth 8-226] default block is never used [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109] +INFO: [Synth 8-226] default block is never used [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109] +INFO: [Synth 8-226] default block is never used [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109] +INFO: [Synth 8-226] default block is never used [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109] +WARNING: [Synth 8-6014] Unused sequential element iterInd_reg was removed. [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:97] +WARNING: [Synth 8-6014] Unused sequential element sX_reg was removed. [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:100] +WARNING: [Synth 8-6014] Unused sequential element sY_reg was removed. [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:101] +WARNING: [Synth 8-6014] Unused sequential element sOff_reg was removed. [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:103] +INFO: [Synth 8-256] done synthesizing module 'Gene_Snake' (4#1) [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:63] + Parameter snakeDataSize bound to: 24 - type: integer +INFO: [Synth 8-3491] module 'RAMController' declared at 'C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/RAMController.vhd:9' bound to instance 'RAMCTRL' of component 'RAMController' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/VGA_top.vhd:284] +INFO: [Synth 8-638] synthesizing module 'RAMController' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/RAMController.vhd:37] + Parameter snakeDataSize bound to: 24 - type: integer + Parameter length bound to: 1200 - type: integer + Parameter addressSize bound to: 11 - type: integer + Parameter dataSize bound to: 24 - type: integer +INFO: [Synth 8-3491] module 'snakeRam' declared at 'C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/snakeRam.vhd:37' bound to instance 'SNAKE_RAM' of component 'snakeRam' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/RAMController.vhd:61] +INFO: [Synth 8-638] synthesizing module 'snakeRam' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/snakeRam.vhd:54] + Parameter length bound to: 1200 - type: integer + Parameter addressSize bound to: 11 - type: integer + Parameter dataSize bound to: 24 - type: integer +INFO: [Synth 8-256] done synthesizing module 'snakeRam' (5#1) [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/snakeRam.vhd:54] + Parameter length bound to: 1200 - type: integer + Parameter addressSize bound to: 11 - type: integer + Parameter dataSize bound to: 11 - type: integer +INFO: [Synth 8-3491] module 'snakeRam' declared at 'C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/snakeRam.vhd:37' bound to instance 'MAT_RAM' of component 'snakeRam' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/RAMController.vhd:79] +INFO: [Synth 8-638] synthesizing module 'snakeRam__parameterized1' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/snakeRam.vhd:54] + Parameter length bound to: 1200 - type: integer + Parameter addressSize bound to: 11 - type: integer + Parameter dataSize bound to: 11 - type: integer +INFO: [Synth 8-256] done synthesizing module 'snakeRam__parameterized1' (5#1) [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/snakeRam.vhd:54] +INFO: [Synth 8-256] done synthesizing module 'RAMController' (6#1) [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/RAMController.vhd:37] + Parameter dataSize bound to: 24 - type: integer +INFO: [Synth 8-3491] module 'updateSnake' declared at 'C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd:37' bound to instance 'UPD' of component 'updateSnake' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/VGA_top.vhd:309] +INFO: [Synth 8-638] synthesizing module 'updateSnake' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd:56] + Parameter dataSize bound to: 24 - type: integer +WARNING: [Synth 8-5825] expecting unsigned expression [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd:112] +WARNING: [Synth 8-6014] Unused sequential element cSnake_reg[X] was removed. [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd:93] +WARNING: [Synth 8-6014] Unused sequential element cSnake_reg[Y] was removed. [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd:93] +WARNING: [Synth 8-6014] Unused sequential element cSnake_reg[dirX] was removed. [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd:93] +WARNING: [Synth 8-6014] Unused sequential element cSnake_reg[dirY] was removed. [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd:93] +WARNING: [Synth 8-6014] Unused sequential element cSnake_reg[isDefined] was removed. [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd:93] +WARNING: [Synth 8-6014] Unused sequential element isUpdating_reg was removed. [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd:69] +WARNING: [Synth 8-6014] Unused sequential element updateIndex_reg was removed. [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd:70] +INFO: [Synth 8-256] done synthesizing module 'updateSnake' (7#1) [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd:56] + Parameter addressSize bound to: 10 - type: integer + Parameter length bound to: 768 - type: integer + Parameter dataSize bound to: 24 - type: integer + Parameter fileName bound to: C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sprites/sprites.mem - type: string +INFO: [Synth 8-3491] module 'spritesRom' declared at 'C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/spritesRom.vhd:36' bound to instance 'ROM' of component 'spritesRom' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/VGA_top.vhd:326] +INFO: [Synth 8-638] synthesizing module 'spritesRom' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/spritesRom.vhd:47] + Parameter addressSize bound to: 10 - type: integer + Parameter length bound to: 768 - type: integer + Parameter dataSize bound to: 24 - type: integer + Parameter fileName bound to: C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sprites/sprites.mem - type: string +INFO: [Synth 8-256] done synthesizing module 'spritesRom' (8#1) [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/spritesRom.vhd:47] +INFO: [Synth 8-256] done synthesizing module 'VGA_top' (9#1) [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/VGA_top.vhd:48] +WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[10] +WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[9] +WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[8] +WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[7] +WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[6] +WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[5] +WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[4] +WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[3] +WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[2] +WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[1] +WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[0] +WARNING: [Synth 8-3331] design updateSnake has unconnected port clk_lente WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port X[9] WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port X[8] WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port X[7] @@ -65,8 +129,9 @@ WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port Y[3] WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port Y[2] WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port Y[1] WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port Y[0] +WARNING: [Synth 8-3331] design VGA_top has unconnected port led[3] --------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 780.012 ; gain = 406.445 +Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 528.090 ; gain = 154.043 --------------------------------------------------------------------------------- Report Check Netlist: @@ -79,191 +144,163 @@ Report Check Netlist: Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 780.012 ; gain = 406.445 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 528.090 ; gain = 154.043 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 780.012 ; gain = 406.445 +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 528.090 ; gain = 154.043 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z010clg400-1 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine -Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0/clk_wiz_1_in_context.xdc] for cell 'U0' -Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0/clk_wiz_1_in_context.xdc] for cell 'U0' -Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc] -Finished Parsing XDC File [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc] -INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Users/e209098F/Downloads/VGA Game 2017 V1-20211109/ZYBO_Master.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/VGA_top_propImpl.xdc]. +Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0/clk_wiz_1_in_context.xdc] for cell 'U0' +Finished Parsing XDC File [c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0/clk_wiz_1_in_context.xdc] for cell 'U0' +Parsing XDC File [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/ZYBO_Master.xdc] +Finished Parsing XDC File [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/ZYBO_Master.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/ZYBO_Master.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/VGA_top_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/VGA_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. -Parsing XDC File [C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/synth_1/dont_touch.xdc] -Finished Parsing XDC File [C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/synth_1/dont_touch.xdc] -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1102.379 ; gain = 0.000 +Parsing XDC File [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/synth_1/dont_touch.xdc] +Finished Parsing XDC File [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/synth_1/dont_touch.xdc] +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 876.688 ; gain = 0.000 Completed Processing XDC Constraints -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1102.379 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 876.688 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1102.379 ; gain = 0.000 -Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1102.379 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 876.688 ; gain = 0.000 +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 876.688 ; gain = 0.000 --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 1102.379 ; gain = 728.812 +Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:22 . Memory (MB): peak = 876.688 ; gain = 502.641 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z010clg400-1 --------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 1102.379 ; gain = 728.812 +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:22 . Memory (MB): peak = 876.688 ; gain = 502.641 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- -Applied set_property IO_BUFFER_TYPE = NONE for H125MHz. (constraint file c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0/clk_wiz_1_in_context.xdc, line 3). -Applied set_property CLOCK_BUFFER_TYPE = NONE for H125MHz. (constraint file c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/ip/clk_wiz_0_1/clk_wiz_0/clk_wiz_1_in_context.xdc, line 4). +Applied set_property IO_BUFFER_TYPE = NONE for H125MHz. (constraint file c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0/clk_wiz_1_in_context.xdc, line 3). +Applied set_property CLOCK_BUFFER_TYPE = NONE for H125MHz. (constraint file c:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.srcs/sources_1/ip/clk_wiz_0_2/clk_wiz_0/clk_wiz_1_in_context.xdc, line 4). Applied set_property DONT_TOUCH = true for U0. (constraint file auto generated constraint, line ). --------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 1102.379 ; gain = 728.812 +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:09 ; elapsed = 00:00:22 . Memory (MB): peak = 876.688 ; gain = 502.641 --------------------------------------------------------------------------------- -INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Position.vhd:58] -INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Position.vhd:58] -WARNING: [Synth 8-327] inferring latch for variable 'snake_reg[0][X]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:80] -WARNING: [Synth 8-327] inferring latch for variable 'snake_reg[101][X]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:80] -WARNING: [Synth 8-327] inferring latch for variable 'snake_reg[102][X]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:80] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[0,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[1,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[2,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[3,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[4,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[5,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[6,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[7,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[8,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[9,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[10,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[11,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[12,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[13,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[14,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[15,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[16,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[17,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[18,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[19,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[20,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[21,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[22,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[23,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[24,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[25,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[26,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[27,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[28,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[29,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[30,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[31,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[32,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[33,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[34,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[35,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[36,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[37,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[38,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[39,0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[0,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[1,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[2,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[3,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[4,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[5,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[6,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[7,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[8,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[9,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[10,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[11,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[12,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[13,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[14,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[15,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[16,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[17,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[18,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[19,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[20,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[21,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[22,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[23,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[24,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[25,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[26,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[27,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[28,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[29,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[30,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[31,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[32,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[33,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[34,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[35,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[36,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[37,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[38,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[39,1]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[0,2]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[1,2]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[2,2]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[3,2]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[4,2]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[5,2]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[6,2]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[7,2]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[8,2]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[9,2]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[10,2]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[11,2]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[12,2]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[13,2]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[14,2]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[15,2]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -WARNING: [Synth 8-327] inferring latch for variable 'mat_reg[16,2]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.srcs/sources_1/new/Gene_Snake.vhd:93] -INFO: [Common 17-14] Message 'Synth 8-327' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:98] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:98] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:98] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:98] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:98] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:98] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:98] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:98] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:98] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:98] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:98] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:98] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:98] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:98] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:109] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:98] +INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/Gene_Snake.vhd:98] +INFO: [Synth 8-5544] ROM "sOff" won't be mapped to Block RAM because address size (1) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "sOff" won't be mapped to Block RAM because address size (1) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "sOff" won't be mapped to Block RAM because address size (1) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "sOff" won't be mapped to Block RAM because address size (1) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "sOff" won't be mapped to Block RAM because address size (1) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "sOff" won't be mapped to Block RAM because address size (1) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "sOff" won't be mapped to Block RAM because address size (1) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "sOff" won't be mapped to Block RAM because address size (1) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "sOff" won't be mapped to Block RAM because address size (1) smaller than threshold (5) +INFO: [Synth 8-5545] ROM "running" won't be mapped to RAM because address size (32) is larger than maximum supported(25) +INFO: [Synth 8-5545] ROM "dataReady" won't be mapped to RAM because address size (32) is larger than maximum supported(25) +INFO: [Synth 8-5545] ROM "clkCount" won't be mapped to RAM because address size (32) is larger than maximum supported(25) +INFO: [Synth 8-5546] ROM "writeEnable" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5544] ROM "writeEnable" won't be mapped to Block RAM because address size (4) smaller than threshold (5) +INFO: [Synth 8-5546] ROM "mem" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-3971] The signal mem_reg was recognized as a true dual port RAM template. +INFO: [Synth 8-3971] The signal mem_reg was recognized as a true dual port RAM template. +WARNING: [Synth 8-327] inferring latch for variable 'currentSnake_reg[isDefined]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd:108] +WARNING: [Synth 8-327] inferring latch for variable 'currentSnake_reg[dirY]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd:108] +WARNING: [Synth 8-327] inferring latch for variable 'currentSnake_reg[dirX]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd:108] +WARNING: [Synth 8-327] inferring latch for variable 'currentSnake_reg[Y]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd:108] +WARNING: [Synth 8-327] inferring latch for variable 'currentSnake_reg[X]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd:108] +WARNING: [Synth 8-327] inferring latch for variable 'matAddress_reg' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd:122] --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:44 ; elapsed = 00:00:50 . Memory (MB): peak = 1272.715 ; gain = 899.148 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:23 . Memory (MB): peak = 876.688 ; gain = 502.641 --------------------------------------------------------------------------------- Report RTL Partitions: -+------+----------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+------+----------------+------------+----------+ -|1 |Gene_Snake__GB0 | 1| 55621| -|2 |Gene_Snake__GB1 | 1| 2622| -|3 |Gene_Snake__GB2 | 1| 11799| -|4 |Gene_Snake__GB3 | 1| 15734| -|5 |VGA_top__GC0 | 1| 947| -+------+----------------+------------+----------+ ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : - 2 Input 11 Bit Adders := 1 - 2 Input 10 Bit Adders := 11 - 2 Input 9 Bit Adders := 10 + 2 Input 32 Bit Adders := 1 + 2 Input 11 Bit Adders := 2 + 3 Input 11 Bit Adders := 9 + 2 Input 10 Bit Adders := 21 + 3 Input 10 Bit Adders := 18 + 2 Input 9 Bit Adders := 20 + 2 Input 8 Bit Adders := 1 + 2 Input 7 Bit Adders := 2 + 2 Input 6 Bit Adders := 1 + 2 Input 4 Bit Adders := 1 +---Registers : - 11 Bit Registers := 1 - 10 Bit Registers := 2 - 9 Bit Registers := 1 - 1 Bit Registers := 1 + 32 Bit Registers := 1 + 24 Bit Registers := 12 + 11 Bit Registers := 13 + 10 Bit Registers := 1 + 8 Bit Registers := 1 + 6 Bit Registers := 2 + 5 Bit Registers := 3 + 4 Bit Registers := 1 + 1 Bit Registers := 8 ++---RAMs : + 28K Bit RAMs := 1 + 12K Bit RAMs := 1 +---Muxes : - 3 Input 10 Bit Muxes := 4 - 2 Input 10 Bit Muxes := 3 - 2 Input 9 Bit Muxes := 3 - 2 Input 6 Bit Muxes := 1 - 1201 Input 2 Bit Muxes := 4 - 2 Input 2 Bit Muxes := 1 - 2 Input 1 Bit Muxes := 8 - 1201 Input 1 Bit Muxes := 3 + 2 Input 32 Bit Muxes := 1 + 2 Input 24 Bit Muxes := 2 + 769 Input 24 Bit Muxes := 1 + 2 Input 12 Bit Muxes := 9 + 2 Input 11 Bit Muxes := 12 + 2 Input 10 Bit Muxes := 45 + 2 Input 9 Bit Muxes := 4 + 2 Input 8 Bit Muxes := 5 + 2 Input 7 Bit Muxes := 1 + 2 Input 6 Bit Muxes := 2 + 2 Input 5 Bit Muxes := 4 + 2 Input 4 Bit Muxes := 1 + 4 Input 4 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 14 + 9 Input 1 Bit Muxes := 2 + 3 Input 1 Bit Muxes := 2 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- @@ -271,16 +308,6 @@ Finished RTL Component Statistics Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report -Module Gene_Snake -Detailed RTL Component Info : -+---Adders : - 2 Input 10 Bit Adders := 8 - 2 Input 9 Bit Adders := 8 -+---Muxes : - 3 Input 10 Bit Muxes := 4 - 1201 Input 2 Bit Muxes := 4 - 2 Input 1 Bit Muxes := 6 - 1201 Input 1 Bit Muxes := 3 Module GeneSync Detailed RTL Component Info : +---Adders : @@ -297,21 +324,83 @@ Module GeneRGB_V1 Detailed RTL Component Info : +---Muxes : 2 Input 6 Bit Muxes := 1 -Module Gene_Position + 2 Input 5 Bit Muxes := 2 +Module Gene_Snake Detailed RTL Component Info : +---Adders : - 2 Input 10 Bit Adders := 1 - 2 Input 9 Bit Adders := 1 + 3 Input 11 Bit Adders := 9 + 2 Input 10 Bit Adders := 18 + 3 Input 10 Bit Adders := 18 + 2 Input 9 Bit Adders := 18 +---Registers : - 10 Bit Registers := 1 - 9 Bit Registers := 1 + 8 Bit Registers := 1 + 6 Bit Registers := 2 + 5 Bit Registers := 3 + 1 Bit Registers := 3 +---Muxes : - 2 Input 2 Bit Muxes := 1 + 2 Input 12 Bit Muxes := 9 + 2 Input 11 Bit Muxes := 9 + 2 Input 10 Bit Muxes := 42 + 2 Input 8 Bit Muxes := 1 + 2 Input 6 Bit Muxes := 1 + 2 Input 5 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 -Module Diviseur + 9 Input 1 Bit Muxes := 2 +Module snakeRam Detailed RTL Component Info : +---Registers : - 1 Bit Registers := 1 + 24 Bit Registers := 10 ++---RAMs : + 28K Bit RAMs := 1 +Module snakeRam__parameterized1 +Detailed RTL Component Info : ++---Registers : + 11 Bit Registers := 10 ++---RAMs : + 12K Bit RAMs := 1 +Module RAMController +Detailed RTL Component Info : ++---Adders : + 2 Input 32 Bit Adders := 1 + 2 Input 8 Bit Adders := 1 + 2 Input 7 Bit Adders := 2 + 2 Input 6 Bit Adders := 1 ++---Registers : + 32 Bit Registers := 1 + 1 Bit Registers := 2 ++---Muxes : + 2 Input 32 Bit Muxes := 1 + 2 Input 11 Bit Muxes := 2 + 2 Input 9 Bit Muxes := 1 + 2 Input 8 Bit Muxes := 3 + 2 Input 7 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 3 +Module updateSnake +Detailed RTL Component Info : ++---Adders : + 2 Input 11 Bit Adders := 1 + 2 Input 10 Bit Adders := 1 + 2 Input 9 Bit Adders := 1 + 2 Input 4 Bit Adders := 1 ++---Registers : + 24 Bit Registers := 1 + 11 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 24 Bit Muxes := 2 + 2 Input 11 Bit Muxes := 1 + 2 Input 8 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 1 + 4 Input 4 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 9 + 3 Input 1 Bit Muxes := 2 +Module spritesRom +Detailed RTL Component Info : ++---Registers : + 24 Bit Registers := 1 ++---Muxes : + 769 Input 24 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- @@ -328,250 +417,205 @@ Finished Part Resource Summary Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Warning: Parallel synthesis criteria is not met -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[101][Y][0] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][Y][0] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[101][Y][1] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][Y][1] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][X][0] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[101][X][0] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[102][X][0] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][X][1] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[101][X][1] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[102][X][1] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[101][Y][2] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][Y][2] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[101][Y][3] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][Y][3] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[101][Y][4] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][Y][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[101][Y][5] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][Y][5] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[101][Y][6] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][Y][6] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[101][Y][7] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][Y][7] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[101][Y][8] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][Y][8] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][X][2] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[101][X][2] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[102][X][2] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][X][8] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[101][X][8] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[102][X][8] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][X][7] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[101][X][7] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[102][X][7] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][X][6] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[101][X][6] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[102][X][6] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][X][5] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[101][X][5] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[102][X][5] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][X][4] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[101][X][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[102][X][4] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][X][3] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[101][X][3] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[102][X][3] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[0][X][9] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[101][X][9] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\snake_reg[102][X][9] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\snake_reg[101][isDefined] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[39,21][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[38,21][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[37,21][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[36,21][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[35,21][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[34,21][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[33,21][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[32,21][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[31,21][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[30,21][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[29,21][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[28,21][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[27,21][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[26,21][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[25,21][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[24,21][4] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\mat_reg[23,21][4] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\mat_reg[22,21][4] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\mat_reg[21,21][4] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\mat_reg[20,21][4] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\mat_reg[19,21][4] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\mat_reg[18,21][4] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\mat_reg[17,21][4] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\mat_reg[16,21][4] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\mat_reg[15,21][4] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\mat_reg[14,21][4] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\mat_reg[13,21][4] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\mat_reg[12,21][4] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\mat_reg[11,21][4] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\mat_reg[10,21][4] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\mat_reg[9,21][4] ) -INFO: [Synth 8-3333] propagating constant 1 across sequential element (U6i_1/\mat_reg[8,21][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[7,21][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[6,21][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[5,21][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[4,21][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[3,21][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[2,21][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[1,21][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[0,21][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[39,13][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[38,13][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[37,13][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[36,13][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[35,13][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[34,13][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[33,13][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[32,13][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[31,13][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[30,13][4] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (U6i_1/\mat_reg[29,13][4] ) -INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[39,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[38,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[37,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[36,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[35,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[34,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[33,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[32,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[31,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[30,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[29,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[28,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[27,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[26,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[25,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[24,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[23,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[22,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[21,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[20,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[19,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[18,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[17,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[16,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[15,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[14,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[13,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[12,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[11,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[10,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[9,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[8,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[7,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[6,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[5,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[4,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[3,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[2,22][0]' (LD) to 'U6i_2/mat_reg[0,22][0]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[1,22][0]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[0,22][0]' (LD) to 'U6i_2/mat_reg[0,22][1]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[39,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[38,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[37,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[36,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[35,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[34,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[33,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[32,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[31,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[30,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[29,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[28,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[27,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[26,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[25,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[24,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[23,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[22,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[21,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[20,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[19,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[18,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[17,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[16,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[15,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[14,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[13,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[12,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[11,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[10,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[9,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[8,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[7,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[6,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[5,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[4,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[3,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[2,22][1]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[1,22][1]' (LD) to 'U6i_2/mat_reg[0,22][1]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[0,22][1]' (LD) to 'U6i_2/mat_reg[0,22][2]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[39,22][2]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[38,22][2]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[37,22][2]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[36,22][2]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[35,22][2]' (LD) to 'U6i_2/mat_reg[0,22][2]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[34,22][2]' (LD) to 'U6i_2/mat_reg[0,22][2]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[33,22][2]' (LD) to 'U6i_2/mat_reg[0,22][2]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[32,22][2]' (LD) to 'U6i_2/mat_reg[0,22][2]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[31,22][2]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[30,22][2]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[29,22][2]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[28,22][2]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[27,22][2]' (LD) to 'U6i_2/mat_reg[0,22][2]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[26,22][2]' (LD) to 'U6i_2/mat_reg[0,22][2]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[25,22][2]' (LD) to 'U6i_2/mat_reg[0,22][2]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[24,22][2]' (LD) to 'U6i_2/mat_reg[0,22][2]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[23,22][2]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[22,22][2]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[21,22][2]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Synth 8-3886] merging instance 'U6i_2/mat_reg[20,22][2]' (LD) to 'U6i_2/mat_reg[0,22][4]' -INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-5545] ROM "clkCount" won't be mapped to RAM because address size (32) is larger than maximum supported(25) +INFO: [Synth 8-5545] ROM "running" won't be mapped to RAM because address size (32) is larger than maximum supported(25) +INFO: [Synth 8-5545] ROM "dataReady" won't be mapped to RAM because address size (32) is larger than maximum supported(25) +INFO: [Synth 8-4471] merging register 'index_reg[10:0]' into 'index_reg[10:0]' [C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/sources_snake/updateSnake.vhd:74] +INFO: [Synth 8-5544] ROM "writeEnable" won't be mapped to Block RAM because address size (4) smaller than threshold (5) +INFO: [Synth 8-5546] ROM "writeEnable" won't be mapped to RAM because it is too sparse +WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[10] +WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[9] +WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[8] +WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[7] +WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[6] +WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[5] +WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[4] +WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[3] +WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[2] +WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[1] +WARNING: [Synth 8-3331] design updateSnake has unconnected port matDataIn[0] +WARNING: [Synth 8-3331] design updateSnake has unconnected port clk_lente +WARNING: [Synth 8-3331] design Gene_Snake has unconnected port currentSnakes[0][dirX][0] +WARNING: [Synth 8-3331] design Gene_Snake has unconnected port currentSnakes[1][dirX][0] +WARNING: [Synth 8-3331] design Gene_Snake has unconnected port currentSnakes[2][dirX][0] +WARNING: [Synth 8-3331] design Gene_Snake has unconnected port currentSnakes[3][dirX][0] +WARNING: [Synth 8-3331] design Gene_Snake has unconnected port currentSnakes[4][dirX][0] +WARNING: [Synth 8-3331] design Gene_Snake has unconnected port currentSnakes[5][dirX][0] +WARNING: [Synth 8-3331] design Gene_Snake has unconnected port currentSnakes[6][dirX][0] +WARNING: [Synth 8-3331] design Gene_Snake has unconnected port currentSnakes[7][dirX][0] +WARNING: [Synth 8-3331] design Gene_Snake has unconnected port currentSnakes[8][dirX][0] +WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port X[9] +WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port X[8] +WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port X[7] +WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port X[6] +WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port X[5] +WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port X[4] +WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port X[3] +WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port X[2] +WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port X[1] +WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port X[0] +WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port Y[8] +WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port Y[7] +WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port Y[6] +WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port Y[5] +WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port Y[4] +WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port Y[3] +WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port Y[2] +WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port Y[1] +WARNING: [Synth 8-3331] design GeneRGB_V1 has unconnected port Y[0] +WARNING: [Synth 8-3331] design VGA_top has unconnected port led[3] +INFO: [Synth 8-3971] The signal SNAKE_RAM/mem_reg was recognized as a true dual port RAM template. +INFO: [Synth 8-4652] Swapped enable and write-enable on 16 RAM instances of RAM SNAKE_RAM/mem_reg to conserve power +INFO: [Synth 8-3971] The signal MAT_RAM/mem_reg was recognized as a true dual port RAM template. +INFO: [Synth 8-4652] Swapped enable and write-enable on 8 RAM instances of RAM MAT_RAM/mem_reg to conserve power +INFO: [Synth 8-3886] merging instance 'UPD/currentSnake_reg[X][2]' (LD) to 'UPD/currentSnake_reg[X][9]' +INFO: [Synth 8-3886] merging instance 'UPD/currentSnake_reg[X][3]' (LD) to 'UPD/currentSnake_reg[Y][3]' +INFO: [Synth 8-3886] merging instance 'UPD/currentSnake_reg[isDefined]' (LD) to 'UPD/currentSnake_reg[dirX][0]' +INFO: [Synth 8-3886] merging instance 'UPD/currentSnake_reg[dirX][0]' (LD) to 'UPD/currentSnake_reg[dirX][1]' +INFO: [Synth 8-3886] merging instance 'UPD/currentSnake_reg[Y][0]' (LD) to 'UPD/currentSnake_reg[X][9]' +INFO: [Synth 8-3886] merging instance 'UPD/currentSnake_reg[Y][1]' (LD) to 'UPD/currentSnake_reg[X][9]' +INFO: [Synth 8-3886] merging instance 'UPD/currentSnake_reg[Y][2]' (LD) to 'UPD/currentSnake_reg[X][9]' +INFO: [Synth 8-3333] propagating constant 1 across sequential element (UPD/\currentSnake_reg[Y][3] ) +INFO: [Synth 8-3886] merging instance 'UPD/currentSnake_reg[Y][4]' (LD) to 'UPD/currentSnake_reg[X][9]' +INFO: [Synth 8-3886] merging instance 'UPD/currentSnake_reg[Y][5]' (LD) to 'UPD/currentSnake_reg[X][9]' +INFO: [Synth 8-3886] merging instance 'UPD/currentSnake_reg[Y][6]' (LD) to 'UPD/currentSnake_reg[X][9]' +INFO: [Synth 8-3886] merging instance 'UPD/currentSnake_reg[Y][7]' (LD) to 'UPD/currentSnake_reg[X][9]' +INFO: [Synth 8-3886] merging instance 'UPD/currentSnake_reg[Y][8]' (LD) to 'UPD/currentSnake_reg[X][9]' +INFO: [Synth 8-3886] merging instance 'UPD/currentSnake_reg[X][0]' (LD) to 'UPD/currentSnake_reg[X][9]' +INFO: [Synth 8-3886] merging instance 'UPD/currentSnake_reg[X][1]' (LD) to 'UPD/currentSnake_reg[X][9]' +INFO: [Synth 8-3886] merging instance 'UPD/currentSnake_reg[X][8]' (LD) to 'UPD/currentSnake_reg[X][9]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (UPD/\currentSnake_reg[X][9] ) +INFO: [Synth 8-3886] merging instance 'ROM/data_reg[8]' (FD) to 'ROM/data_reg[9]' +INFO: [Synth 8-3886] merging instance 'ROM/data_reg[11]' (FD) to 'ROM/data_reg[12]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (ROM/\data_reg[12] ) +INFO: [Synth 8-3886] merging instance 'ROM/data_reg[2]' (FD) to 'ROM/data_reg[3]' +INFO: [Synth 8-3886] merging instance 'ROM/data_reg[19]' (FD) to 'ROM/data_reg[20]' +INFO: [Synth 8-3886] merging instance 'ROM/data_reg[3]' (FD) to 'ROM/data_reg[4]' +INFO: [Synth 8-3886] merging instance 'ROM/data_reg[4]' (FD) to 'ROM/data_reg[5]' +INFO: [Synth 8-3886] merging instance 'ROM/data_reg[5]' (FD) to 'ROM/data_reg[6]' +INFO: [Synth 8-3886] merging instance 'ROM/data_reg[6]' (FD) to 'ROM/data_reg[7]' +INFO: [Synth 8-3886] merging instance 'SNAKE/snakeColor_reg[B][0]' (FDC) to 'SNAKE/snakeColor_reg[B][1]' +INFO: [Synth 8-3886] merging instance 'SNAKE/snakeColor_reg[A][2]' (FDC) to 'SNAKE/snakeColor_reg[A][3]' +INFO: [Synth 8-3886] merging instance 'SNAKE/snakeColor_reg[R][0]' (FDC) to 'SNAKE/snakeColor_reg[R][1]' +INFO: [Synth 8-3886] merging instance 'SNAKE/snakeColor_reg[A][3]' (FDC) to 'SNAKE/snakeColor_reg[A][4]' +INFO: [Synth 8-3886] merging instance 'SNAKE/snakeColor_reg[A][4]' (FDC) to 'SNAKE/snakeColor_reg[A][5]' +INFO: [Synth 8-3886] merging instance 'SNAKE/snakeColor_reg[A][5]' (FDC) to 'SNAKE/snakeColor_reg[A][6]' +INFO: [Synth 8-3886] merging instance 'SNAKE/snakeColor_reg[A][6]' (FDC) to 'SNAKE/snakeColor_reg[A][7]' +WARNING: [Synth 8-3332] Sequential element (currentSnake_reg[Y][3]) is unused and will be removed from module updateSnake. +WARNING: [Synth 8-3332] Sequential element (currentSnake_reg[X][9]) is unused and will be removed from module updateSnake. --------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:22 ; elapsed = 00:01:28 . Memory (MB): peak = 1310.512 ; gain = 936.945 +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:33 . Memory (MB): peak = 876.688 ; gain = 502.641 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- +Block RAM: Preliminary Mapping Report (see note below) +-------NONE------- +Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once. +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_2_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_2_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_3_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_3_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_4_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_4_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_5_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_5_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_6_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_6_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_7_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_7_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_8_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_8_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_9_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_1/SNAKE_RAM/mem_reg_9_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-4652] Swapped enable and write-enable on 1 RAM instances of RAM MAT_RAM/mem_reg to conserve power +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_2/MAT_RAM/mem_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_2/MAT_RAM/mem_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_2/MAT_RAM/mem_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_2/MAT_RAM/mem_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_2/MAT_RAM/mem_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_2/MAT_RAM/mem_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_2/MAT_RAM/mem_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_2/MAT_RAM/mem_reg_8 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/i_2/MAT_RAM/mem_reg_9 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. + Report RTL Partitions: -+------+----------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+------+----------------+------------+----------+ -|1 |Gene_Snake__GB0 | 1| 504| -|2 |Gene_Snake__GB2 | 1| 80| -|3 |Gene_Snake__GB3 | 1| 58| -|4 |VGA_top__GC0 | 1| 179| -+------+----------------+------------+----------+ ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- INFO: [Synth 8-5578] Moved timing constraint from pin 'U0/clk_out1' to pin 'U0/bbstub_clk_out1/O' INFO: [Synth 8-5819] Moved 1 constraints on hierarchical pins to their respective driving/loading pins --------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:28 ; elapsed = 00:01:34 . Memory (MB): peak = 1310.512 ; gain = 936.945 +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:26 ; elapsed = 00:00:39 . Memory (MB): peak = 876.688 ; gain = 502.641 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- +INFO: [Synth 8-3971] The signal SNAKE_RAM/mem_reg was recognized as a true dual port RAM template. --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:01:28 ; elapsed = 00:01:34 . Memory (MB): peak = 1310.512 ; gain = 936.945 +Finished Timing Optimization : Time (s): cpu = 00:00:30 ; elapsed = 00:00:43 . Memory (MB): peak = 976.145 ; gain = 602.098 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- + +Block RAM: Final Mapping Report +-------NONE------- +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Report RTL Partitions: -+------+----------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+------+----------------+------------+----------+ -|1 |Gene_Snake__GB0 | 1| 504| -|2 |Gene_Snake__GB2 | 1| 80| -|3 |Gene_Snake__GB3 | 1| 58| -|4 |VGA_top__GC0 | 1| 179| -+------+----------------+------------+----------+ ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_2_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_2_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_3_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_3_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_4_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_4_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_5_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_5_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_6_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_6_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_7_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_7_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_8_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_8_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_9_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/SNAKE_RAM/mem_reg_9_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/MAT_RAM/mem_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/MAT_RAM/mem_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/MAT_RAM/mem_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/MAT_RAM/mem_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/MAT_RAM/mem_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/MAT_RAM/mem_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/MAT_RAM/mem_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/MAT_RAM/mem_reg_8 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance RAMCTRL/MAT_RAM/mem_reg_9 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:01:28 ; elapsed = 00:01:34 . Memory (MB): peak = 1310.512 ; gain = 936.945 +Finished Technology Mapping : Time (s): cpu = 00:00:31 ; elapsed = 00:00:44 . Memory (MB): peak = 976.145 ; gain = 602.098 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -591,11 +635,12 @@ Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- +INFO: [Synth 8-6064] Net led[1] is driving 54 big block pins (URAM, BRAM and DSP loads). Created 6 replicas of its driver. --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:01:29 ; elapsed = 00:01:35 . Memory (MB): peak = 1310.512 ; gain = 936.945 +Finished IO Insertion : Time (s): cpu = 00:00:32 ; elapsed = 00:00:45 . Memory (MB): peak = 976.145 ; gain = 602.098 --------------------------------------------------------------------------------- Report Check Netlist: @@ -608,7 +653,7 @@ Report Check Netlist: Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:01:29 ; elapsed = 00:01:35 . Memory (MB): peak = 1310.512 ; gain = 936.945 +Finished Renaming Generated Instances : Time (s): cpu = 00:00:32 ; elapsed = 00:00:45 . Memory (MB): peak = 976.145 ; gain = 602.098 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -620,25 +665,25 @@ Report RTL Partitions: Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:29 ; elapsed = 00:01:35 . Memory (MB): peak = 1310.512 ; gain = 936.945 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:32 ; elapsed = 00:00:45 . Memory (MB): peak = 976.145 ; gain = 602.098 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:01:29 ; elapsed = 00:01:35 . Memory (MB): peak = 1310.512 ; gain = 936.945 +Finished Renaming Generated Ports : Time (s): cpu = 00:00:32 ; elapsed = 00:00:45 . Memory (MB): peak = 976.145 ; gain = 602.098 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:01:29 ; elapsed = 00:01:35 . Memory (MB): peak = 1310.512 ; gain = 936.945 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:32 ; elapsed = 00:00:45 . Memory (MB): peak = 976.145 ; gain = 602.098 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:01:29 ; elapsed = 00:01:35 . Memory (MB): peak = 1310.512 ; gain = 936.945 +Finished Renaming Generated Nets : Time (s): cpu = 00:00:32 ; elapsed = 00:00:45 . Memory (MB): peak = 976.145 ; gain = 602.098 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report @@ -656,46 +701,68 @@ Report Cell Usage: | |Cell |Count | +------+-----------------+------+ |1 |clk_wiz_0_bbox_0 | 1| -|2 |CARRY4 | 34| -|3 |LUT1 | 4| -|4 |LUT2 | 28| -|5 |LUT3 | 7| -|6 |LUT4 | 62| -|7 |LUT5 | 47| -|8 |LUT6 | 65| -|9 |FDRE | 21| -|10 |OBUF | 18| +|2 |CARRY4 | 266| +|3 |LUT1 | 12| +|4 |LUT2 | 275| +|5 |LUT3 | 323| +|6 |LUT4 | 365| +|7 |LUT5 | 358| +|8 |LUT6 | 447| +|9 |MUXF7 | 19| +|10 |MUXF8 | 1| +|11 |RAMB18E1_1 | 9| +|12 |RAMB36E1 | 9| +|13 |RAMB36E1_1 | 9| +|14 |FDCE | 62| +|15 |FDPE | 10| +|16 |FDRE | 114| +|17 |FDSE | 1| +|18 |LD | 17| +|19 |LDC | 6| +|20 |IBUF | 1| +|21 |OBUF | 21| +|22 |OBUFT | 1| +------+-----------------+------+ Report Instance Areas: -+------+---------+---------+------+ -| |Instance |Module |Cells | -+------+---------+---------+------+ -|1 |top | | 287| -|2 | U1 |GeneSync | 267| -+------+---------+---------+------+ ++------+--------------+-------------------------+------+ +| |Instance |Module |Cells | ++------+--------------+-------------------------+------+ +|1 |top | | 2327| +|2 | ROM |spritesRom | 13| +|3 | RAMCTRL |RAMController | 1346| +|4 | MAT_RAM |snakeRam__parameterized1 | 9| +|5 | SNAKE_RAM |snakeRam | 1282| +|6 | SNAKE |Gene_Snake | 375| +|7 | SYNC |GeneSync | 344| +|8 | UPD |updateSnake | 155| +|9 | UPD_CLK_DIV |Diviseur | 70| ++------+--------------+-------------------------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:01:29 ; elapsed = 00:01:35 . Memory (MB): peak = 1310.512 ; gain = 936.945 +Finished Writing Synthesis Report : Time (s): cpu = 00:00:32 ; elapsed = 00:00:45 . Memory (MB): peak = 976.145 ; gain = 602.098 --------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 1207 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:01:03 ; elapsed = 00:01:23 . Memory (MB): peak = 1310.512 ; gain = 614.578 -Synthesis Optimization Complete : Time (s): cpu = 00:01:29 ; elapsed = 00:01:35 . Memory (MB): peak = 1310.512 ; gain = 936.945 +Synthesis finished with 0 errors, 0 critical warnings and 49 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:25 ; elapsed = 00:00:28 . Memory (MB): peak = 976.145 ; gain = 253.500 +Synthesis Optimization Complete : Time (s): cpu = 00:00:32 ; elapsed = 00:00:45 . Memory (MB): peak = 976.145 ; gain = 602.098 INFO: [Project 1-571] Translating synthesized netlist -INFO: [Netlist 29-17] Analyzing 34 Unisim elements for replacement +INFO: [Netlist 29-17] Analyzing 336 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1310.512 ; gain = 0.000 +INFO: [Opt 31-140] Inserted 1 IBUFs to IO ports without IO buffers. +INFO: [Opt 31-138] Pushed 1 inverter(s) to 17 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 976.145 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. + A total of 23 instances were transformed. + LD => LDCE (inverted pins: G): 17 instances + LDC => LDCE: 6 instances INFO: [Common 17-83] Releasing license: Synthesis -237 Infos, 127 Warnings, 0 Critical Warnings and 0 Errors encountered. +209 Infos, 94 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:01:30 ; elapsed = 00:01:37 . Memory (MB): peak = 1310.512 ; gain = 948.426 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1310.512 ; gain = 0.000 +synth_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:48 . Memory (MB): peak = 976.145 ; gain = 613.590 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 976.145 ; gain = 0.000 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint 'C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/synth_1/VGA_top.dcp' has been generated. +INFO: [Common 17-1381] The checkpoint 'C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/synth_1/VGA_top.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file VGA_top_utilization_synth.rpt -pb VGA_top_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Tue Dec 7 12:42:42 2021... +INFO: [Common 17-206] Exiting Vivado at Tue Jan 4 12:18:30 2022... diff --git a/projet-vga.runs/synth_1/runme.sh b/projet-vga.runs/synth_1/runme.sh index b4e39eb..0262a94 100644 --- a/projet-vga.runs/synth_1/runme.sh +++ b/projet-vga.runs/synth_1/runme.sh @@ -24,7 +24,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/synth_1' +HD_PWD='C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/synth_1' cd "$HD_PWD" HD_LOG=runme.log diff --git a/projet-vga.runs/synth_1/vivado.jou b/projet-vga.runs/synth_1/vivado.jou index f5441e4..0389c60 100644 --- a/projet-vga.runs/synth_1/vivado.jou +++ b/projet-vga.runs/synth_1/vivado.jou @@ -2,11 +2,11 @@ # Vivado v2018.3 (64-bit) # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Tue Dec 7 12:41:01 2021 -# Process ID: 5952 -# Current directory: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/synth_1 +# Start of session at: Tue Jan 4 12:17:37 2022 +# Process ID: 5272 +# Current directory: C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/synth_1 # Command line: vivado.exe -log VGA_top.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source VGA_top.tcl -# Log file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/synth_1/VGA_top.vds -# Journal file: C:/Users/E209098F/Documents/uec-electronique/td4/projet/projet-vga/projet-vga.runs/synth_1\vivado.jou +# Log file: C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/synth_1/VGA_top.vds +# Journal file: C:/Users/e209098F/Documents/uec-electronique/td4/projet/projet-electronique/projet-vga.runs/synth_1\vivado.jou #----------------------------------------------------------- source VGA_top.tcl -notrace diff --git a/projet-vga.runs/synth_1/vivado.pb b/projet-vga.runs/synth_1/vivado.pb index fefd241..ebfcd77 100644 Binary files a/projet-vga.runs/synth_1/vivado.pb and b/projet-vga.runs/synth_1/vivado.pb differ diff --git a/projet-vga.srcs/sources_1/new/Diviseur.vhd b/projet-vga.srcs/sources_1/new/Diviseur.vhd index 8f4fca4..51deab7 100644 --- a/projet-vga.srcs/sources_1/new/Diviseur.vhd +++ b/projet-vga.srcs/sources_1/new/Diviseur.vhd @@ -1,21 +1,21 @@ ---------------------------------------------------------------------------------- --- Company: --- Engineer: --- +-- Company: +-- Engineer: +-- -- Create Date: 23.11.2021 11:56:55 --- Design Name: +-- Design Name: -- Module Name: Diviseur - Behavioral --- Project Name: --- Target Devices: --- Tool Versions: --- Description: --- --- Dependencies: --- +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: --- +-- ---------------------------------------------------------------------------------- @@ -40,23 +40,25 @@ entity Diviseur is end Diviseur; architecture Behavioral of Diviseur is -signal temp : unsigned (nbBits-1 downto 0); +signal temp : unsigned (nbBits-1 downto 0) := (others => '0'); begin -process(clk_in,reset) +process(clk_in,reset,temp,max) begin if reset='0' then - temp<=(others=>'0'); + temp<=(others=>'0'); elsif (clk_in'event and clk_in='1') then - temp <=temp+1; - if temp=max then - clk_out <= '1'; - temp <= (others => '0'); - else + temp <= temp+1; + end if; + + if(temp>max/2) then clk_out <= '0'; - end if; + else + clk_out <= '1'; + end if; + if(temp=max) then + temp <= to_unsigned(0,nbBits); end if; end process; - end Behavioral; diff --git a/projet-vga.srcs/sources_1/new/Gene_Snake.vhd b/projet-vga.srcs/sources_1/new/Gene_Snake.vhd index 8f95c6e..7b03333 100644 --- a/projet-vga.srcs/sources_1/new/Gene_Snake.vhd +++ b/projet-vga.srcs/sources_1/new/Gene_Snake.vhd @@ -28,124 +28,107 @@ use IEEE.STD_LOGIC_1164.ALL; -- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL; +library ourTypes; +use ourTypes.types.all; + -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Gene_Snake is +generic( addressSize : integer:=10); Port ( X : in unsigned (9 downto 0); Y : in unsigned (8 downto 0); - up : in std_logic; - down : in std_logic; - left : in std_logic; - right : in std_logic; - clk_rapide: in std_logic; - clk_lente : in std_logic; + clk: in std_logic; reset: in std_logic; - snakePresent : out std_logic); + + currentSnakes : in nSnakes; + listRefs : in addresses; + tailIndex : in unsigned(SNAKE_ADDRESS_SIZE-1 downto 0); + updateOrder : in std_logic; + dataReady : in std_logic; + + cCaseX : out unsigned(5 downto 0); + cCaseY : out unsigned(4 downto 0); + dataRequest : out std_logic := '0'; + + colorOut : out color; + + ROMAddress : out unsigned(SPRITES_ADDRESS_SIZE-1 downto 0) := (others => '0'); + ROMData : in std_logic_vector(SPRITES_DATA_SIZE-1 downto 0) + ); end Gene_Snake; architecture Behavioral of Gene_Snake is --- Déclaration des types de données -type coord is array(0 to 39, 0 to 29) of unsigned(10 downto 0); -type direction is (haut, bas, gauche, droite); -type pos is record - X: unsigned(9 downto 0); - Y: unsigned(8 downto 0); - dir: direction; - isDefined: std_logic; -end record; -type listSnake is array(0 to 1200) of pos; --- Déclaration des signaux -signal mat: coord; -signal snake: listSnake; -signal snakeHere: std_logic; -signal update: std_logic; -signal current_index: unsigned(10 downto 0); -signal lastSnake: pos; +-- D???claration des signaux +signal snakeHere: std_logic := '0'; --1 si on doit afficher le pixel 0 sinon +signal startUpdate : std_logic := '0'; +signal request :std_logic := '0'; +signal snakeColor : color := (others => (others => '0')); + begin -process(X,Y,mat,reset, snake) -variable ref : unsigned(10 downto 0); -variable position : pos; +process(reset,updateOrder,clk) +variable sX,sY,sOff,iterInd : integer; begin - if(reset='0') - then --- snake <= (others=>(to_unsigned(1023,10),to_unsigned(511,10))); - for i in 0 to snake'length-1 loop - if(i>100 and i<103) - then - snake(i).X <= to_unsigned((22+i-101)*16 - 8,10); - snake(i).Y <= to_unsigned(32-8,9); - snake(i).dir <= gauche; - snake(i).isDefined <= '1'; - else - snake(i).X <= to_unsigned(1023,10); - snake(i).Y <= to_unsigned(511,9); - snake(i).dir <= gauche; - snake(i).isDefined <= '0'; - end if; - end loop; - for x in 0 to 39 loop - for y in 0 to 29 loop - mat(x,y) <= to_unsigned(y*40+x,11); - end loop; - end loop; + if(reset = '0') then + snakeHere <= '0'; + snakeColor <= (others => (others => '0')); + else + + + if(updateOrder'event and updateOrder = '1') then + if(snakeHere = '1') then + --snakeColor <= (others => (others => '1')); + snakeColor <= to_color(ROMData); + else + snakeColor <= (others => (others => '0')); + end if; + startUpdate <= '1'; end if; - snakeHere <= '0'; - for dx in -1 to 0 loop - for dy in -1 to 0 loop - ref := mat(to_integer(X/16)+dx,to_integer(Y/16)+dy); - position := snake(to_integer(ref)); - if(position.isDefined= '1') then - if(X>=position.X-8 and X<=position.X+8 and Y>=position.Y-8 and Y<=position.Y+8) then - snakeHere <= snakeHere or '1'; + + if(clk'event and clk = '1') then + if(dataReady = '1') then + request <= '0'; + for j in currentSnakes'LOW to currentSnakes'HIGH loop + iterInd := (j + 5) rem 9; + if(currentSnakes(iterInd).isDefined = '1' and X>=currentSnakes(iterInd).X-8 and X=currentSnakes(iterInd).Y-8 and Y ROMAddress <= to_unsigned(sX*16+sY+sOff,SPRITES_ADDRESS_SIZE); + when '0' => ROMAddress <= to_unsigned(sY*16+sX+sOff,SPRITES_ADDRESS_SIZE); + when others => NULL; + end case; end if; - end if; - end loop; - end loop; + end loop; + end if; + + if(startUpdate = '1') then + snakeHere <= '0'; + cCaseX <= X(9 downto 4); + cCaseY <= Y(8 downto 4); + request <= '1'; + end if; + end if; + + if(request = '1') then + startUpdate <= '0'; + end if; + end if; end process; --- On change la position (X et Y) d'une case du snake à chaque coup --- d'horloge de clk_rapide. ---process(snake, clk_lente, clk_rapide, update, current_index) ---variable current_dir : direction; ---begin ---current_dir := snake(to_integer(current_index)).dir; ---if (clk_lente'event and clk_lente = '1') then --- update <= '1'; ---end if; - ---if (update ='1' and clk_rapide'event and clk_rapide = '1') then --- lastSnake <= snake(to_integer(current_index)); --- if (current_dir = haut) then --- snake(to_integer(current_index)).Y <= snake(to_integer(current_index)).Y - 1; --- end if; --- if (current_dir = bas) then --- snake(to_integer(current_index)).Y <= snake(to_integer(current_index)).Y + 1; --- end if; --- if (current_dir = droite) then --- snake(to_integer(current_index)).X <= snake(to_integer(current_index)).X + 1; --- end if; --- if (current_dir = gauche) then --- snake(to_integer(current_index)).X <= snake(to_integer(current_index)).X - 1; --- end if; - --- if ((snake(to_integer(current_index)).X/16 /= lastSnake.X/16) or (snake(to_integer(current_index)).Y/16 /= lastSnake.Y/16)) then --- mat(to_integer(lastSnake.X/16),to_integer(lastSnake.Y/16)) <= to_unsigned(1200,11); --- mat(to_integer(snake(to_integer(current_index)).X/16),to_integer(snake(to_integer(current_index)).Y/16))<=current_index; --- end if; --- current_index <= current_index + 1; ---end if; - ---if (to_integer(current_index) = snake'length) then --- current_index <= (others => '0'); --- update <= '0'; ---end if; ---end process; - -snakePresent <= snakeHere; +dataRequest <= request; +colorOut <= snakeColor; end Behavioral; diff --git a/projet-vga.xpr b/projet-vga.xpr index 6116a01..2bdacb0 100644 --- a/projet-vga.xpr +++ b/projet-vga.xpr @@ -3,7 +3,7 @@ - +