j'avais oublié les fichiers RAM et ROM

sources_snake/VGA_top.vhd

@@ -141,7 +141,7 @@ component spritesRom
 generic( addressSize : integer := SPRITES_ADDRESS_SIZE;
          length : integer := SPRITES_DATA_LENGTH;
          dataSize : integer := SPRITES_DATA_SIZE;
-         fileName : string := "/home/leo/projet-electronique/sprites/sprites.mem"
+         fileName : string := "../projet-electronique/sprites/sprites.mem"
 );
 Port ( address : in unsigned (addressSize-1 downto 0);
        data : out STD_LOGIC_VECTOR (dataSize-1 downto 0);

sources_snake/snakeRam.vhd

@@ -0,0 +1,78 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 12/16/2021 09:57:33 PM
+-- Design Name: 
+-- Module Name: snakeRam - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+library ourTypes;
+use ourTypes.types.all;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity snakeRam is
+    generic (
+        length : integer;
+        addressSize : integer;
+        dataSize : integer
+    );
+    Port ( address1 : in unsigned(addressSize-1 downto 0);
+           data1 : out std_logic_vector(dataSize-1 downto 0);
+           writeEnable1 : in STD_LOGIC;
+           clk1 : in STD_LOGIC;
+           
+           address2 : in unsigned(addressSize-1 downto 0);
+           data2 : in std_logic_vector(dataSize-1 downto 0);
+           writeEnable2 : in STD_LOGIC;
+           clk2 : in STD_LOGIC);
+end snakeRam;
+
+architecture Behavioral of snakeRam is
+type listData is array(0 to length-1) of std_logic_vector(dataSize-1 downto 0);
+signal mem : listData;
+begin
+
+process(clk1,address1)
+begin
+    if(clk1'event and clk1 = '1') then
+        data1 <= mem(to_integer(address1));
+--        if(writeEnable1 = '1') then
+--            mem(to_integer(address1)) <= data1;
+--        end if;
+    end if;
+end process;
+
+process(clk2,address2,data2)
+begin
+    if(clk2'event and clk2 = '1') then
+--        data2 <= mem(to_integer(address2));
+        if(writeEnable2 = '1') then
+            mem(to_integer(address2)) <= data2;
+        end if;
+    end if;
+end process;
+end Behavioral;

sources_snake/spritesRom.vhd

@@ -0,0 +1,72 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 12/21/2021 03:36:18 PM
+-- Design Name: 
+-- Module Name: spritesRom - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+	
+use std.textio.all;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity spritesRom is
+    generic( addressSize : integer;
+             length : integer;
+             dataSize : integer;
+             fileName : string
+    );
+    Port ( address : in unsigned (addressSize-1 downto 0);
+           data : out STD_LOGIC_VECTOR (dataSize-1 downto 0);
+           clk : in STD_LOGIC);
+end spritesRom;
+
+architecture Behavioral of spritesRom is
+type listData is array(0 to length-1) of std_logic_vector(dataSize-1 downto 0);
+
+--code "emprunté" ici : https://vhdlwhiz.com/initialize-ram-from-file/
+impure function init_ram_hex return listData is
+  file text_file : text open read_mode is fileName;
+  variable text_line : line;
+  variable ram_content : listData;
+begin
+  for i in 0 to length-1 loop
+    readline(text_file, text_line);
+    hread(text_line, ram_content(i));
+  end loop;
+ 
+  return ram_content;
+end function;
+
+signal mem : listData := init_ram_hex;
+begin
+process(clk,address)
+begin
+    if(clk'event and clk = '1') then
+        data <= mem(TO_INTEGER(address));
+    end if;
+end process;
+end Behavioral;