# compile vhdl design source files
vhdl xil_defaultlib  \
"../../../../../projet_vga_etn_sources/Diviseur.vhd" \
"../../../../../projet_vga_etn_sources/GeneRGB_V1.vhd" \
"../../../../../projet_vga_etn_sources/GeneSync.vhd" \

vhdl ourTypes  \
"../../../../../projet_vga_etn_sources/types.vhd" \

vhdl xil_defaultlib  \
"../../../../../projet_vga_etn_sources/Gene_Snake.vhd" \
"../../../../ETN_snake.srcs/sources_1/new/snakeRam.vhd" \
"../../../../../projet_vga_etn_sources/updateSnake.vhd" \
"../../../../../projet_vga_etn_sources/VGA_top.vhd" \

# Do not sort compile order
nosort