----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 16.11.2021 11:35:27
-- Design Name: 
-- Module Name: Gene_Balle - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Gene_Balle is
    Port ( X : in unsigned (9 downto 0);
           Y : in unsigned (8 downto 0);
           ballePresente : out std_logic;
           PosX : in unsigned (9 downto 0);
           PosY : in unsigned (8 downto 0));
end Gene_Balle;

architecture Behavioral of Gene_Balle is

begin

process(X,Y,PosX, PosY)
begin
if (PosX - 10 <=X and X<=PosX + 10 and  PosY - 10<=Y and Y<=PosY + 10) then
    ballePresente <= '1';
else 
    ballePresente <= '0';
end if;
end process;


end Behavioral;