----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 19.10.2017 08:16:09
-- Design Name: 
-- Module Name: GeneRGB_V1 - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

library ourTypes;
use ourTypes.types.all;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity GeneRGB_V1 is
    Port ( X : in unsigned (9 downto 0);
           Y : in unsigned (8 downto 0);
           IMG : in STD_LOGIC;
           R : out STD_LOGIC_VECTOR (4 downto 0);
           G : out STD_LOGIC_VECTOR (5 downto 0);
           B : out STD_LOGIC_VECTOR (4 downto 0);
           snakeIn : in color;
           pommeIn : in color
           );
end GeneRGB_V1;

architecture Behavioral of GeneRGB_V1 is

begin

process(X,Y,IMG,snakeIn,pommeIn)
variable snakeCol,pommeCol : color;
begin
    if (IMG='0') then
        R<=(others=>'0');
        B<=(others=>'0');
        G<=(others=>'0');
    else
        snakeCol := pValue(snakeIn);
        pommeCol := pValue(pommeIn);
        R<=std_logic_vector(to_unsigned(min_int(to_integer(snakeCol.R) + to_integer(pommeCol.R),31),5));
        G<=std_logic_vector(to_unsigned(min_int(to_integer(snakeCol.G) + to_integer(pommeCol.G),63),6));
        B<=std_logic_vector(to_unsigned(min_int(to_integer(snakeCol.B) + to_integer(pommeCol.B),31),5));
    end if;
end process;
end Behavioral;