Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 | Date : Tue Nov 30 12:44:26 2021 | Host : irb121-02-w running 64-bit major release (build 9200) | Command : report_timing_summary -max_paths 10 -file VGA_top_timing_summary_routed.rpt -pb VGA_top_timing_summary_routed.pb -rpx VGA_top_timing_summary_routed.rpx -warn_on_violation | Design : VGA_top | Device : 7z010-clg400 | Speed File : -1 PRODUCTION 1.11 2014-09-11 -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Timing Summary Report ------------------------------------------------------------------------------------------------ | Timer Settings | -------------- ------------------------------------------------------------------------------------------------ Enable Multi Corner Analysis : Yes Enable Pessimism Removal : Yes Pessimism Removal Resolution : Nearest Common Node Enable Input Delay Default Clock : No Enable Preset / Clear Arcs : No Disable Flight Delays : No Ignore I/O Paths : No Timing Early Launch at Borrowing Latches : false Corner Analyze Analyze Name Max Paths Min Paths ------ --------- --------- Slow Yes Yes Fast Yes Yes check_timing report Table of Contents ----------------- 1. checking no_clock 2. checking constant_clock 3. checking pulse_width_clock 4. checking unconstrained_internal_endpoints 5. checking no_input_delay 6. checking no_output_delay 7. checking multiple_clock 8. checking generated_clocks 9. checking loops 10. checking partial_input_delay 11. checking partial_output_delay 12. checking latch_loops 1. checking no_clock -------------------- There are 0 register/latch pins with no clock. 2. checking constant_clock -------------------------- There are 0 register/latch pins with constant_clock. 3. checking pulse_width_clock ----------------------------- There are 0 register/latch pins which need pulse_width check 4. checking unconstrained_internal_endpoints -------------------------------------------- There are 0 pins that are not constrained for maximum delay. There are 0 pins that are not constrained for maximum delay due to constant clock. 5. checking no_input_delay -------------------------- There are 0 input ports with no input delay specified. There are 0 input ports with no input delay but user has a false path constraint. 6. checking no_output_delay --------------------------- There are 18 ports with no output delay specified. (HIGH) There are 0 ports with no output delay but user has a false path constraint There are 0 ports with no output delay but with a timing clock defined on it or propagating through it 7. checking multiple_clock -------------------------- There are 21 register/latch pins with multiple clocks. (HIGH) 8. checking generated_clocks ---------------------------- There are 0 generated clocks that are not connected to a clock source. 9. checking loops ----------------- There are 0 combinational loops in the design. 10. checking partial_input_delay -------------------------------- There are 0 input ports with partial input delay specified. 11. checking partial_output_delay --------------------------------- There are 0 ports with partial output delay specified. 12. checking latch_loops ------------------------ There are 0 combinational latch loops in the design through latch input ------------------------------------------------------------------------------------------------ | Design Timing Summary | --------------------- ------------------------------------------------------------------------------------------------ WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- 35.149 0.000 0 52 0.063 0.000 0 52 2.000 0.000 0 27 All user specified timing constraints are met. ------------------------------------------------------------------------------------------------ | Clock Summary | ------------- ------------------------------------------------------------------------------------------------ Clock Waveform(ns) Period(ns) Frequency(MHz) ----- ------------ ---------- -------------- H125MHz {0.000 4.000} 8.000 125.000 clk_out1_clk_wiz_1 {0.000 20.000} 40.000 25.000 clkfbout_clk_wiz_1 {0.000 20.000} 40.000 25.000 sys_clk_pin {0.000 4.000} 8.000 125.000 clk_out1_clk_wiz_1_1 {0.000 20.000} 40.000 25.000 clkfbout_clk_wiz_1_1 {0.000 20.000} 40.000 25.000 ------------------------------------------------------------------------------------------------ | Intra Clock Table | ----------------- ------------------------------------------------------------------------------------------------ Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- H125MHz 2.000 0.000 0 1 clk_out1_clk_wiz_1 35.149 0.000 0 52 0.223 0.000 0 52 19.500 0.000 0 23 clkfbout_clk_wiz_1 37.845 0.000 0 3 sys_clk_pin 2.000 0.000 0 1 clk_out1_clk_wiz_1_1 35.162 0.000 0 52 0.223 0.000 0 52 19.500 0.000 0 23 clkfbout_clk_wiz_1_1 37.845 0.000 0 3 ------------------------------------------------------------------------------------------------ | Inter Clock Table | ----------------- ------------------------------------------------------------------------------------------------ From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- clk_out1_clk_wiz_1_1 clk_out1_clk_wiz_1 35.149 0.000 0 52 0.063 0.000 0 52 clk_out1_clk_wiz_1 clk_out1_clk_wiz_1_1 35.149 0.000 0 52 0.063 0.000 0 52 ------------------------------------------------------------------------------------------------ | Other Path Groups Table | ----------------------- ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- ------------------------------------------------------------------------------------------------ | Timing Details | -------------- ------------------------------------------------------------------------------------------------ --------------------------------------------------------------------------------------------------- From Clock: H125MHz To Clock: H125MHz Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 2.000ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: H125MHz Waveform(ns): { 0.000 4.000 } Period(ns): 8.000 Sources: { H125MHz } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a MMCME2_ADV/CLKIN1 n/a 1.249 8.000 6.751 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKIN1 Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 8.000 92.000 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKIN1 Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 4.000 2.000 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKIN1 Low Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 2.000 4.000 2.000 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKIN1 High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 4.000 2.000 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKIN1 High Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 2.000 4.000 2.000 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKIN1 --------------------------------------------------------------------------------------------------- From Clock: clk_out1_clk_wiz_1 To Clock: clk_out1_clk_wiz_1 Setup : 0 Failing Endpoints, Worst Slack 35.149ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.223ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 19.500ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 35.149ns (required time - arrival time) Source: U1/comptY_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[0]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 4.145ns (logic 0.952ns (22.969%) route 3.193ns (77.031%)) Logic Levels: 4 (LUT4=1 LUT6=3) Clock Path Skew: -0.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.261ns = ( 38.739 - 40.000 ) Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.626ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.746 -0.613 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y31 FDRE (Prop_fdre_C_Q) 0.456 -0.157 r U1/comptY_reg[7]/Q net (fo=10, routed) 1.014 0.857 U1/comptY_reg__0[7] SLICE_X43Y31 LUT4 (Prop_lut4_I1_O) 0.124 0.981 r U1/vga_vs_OBUF_inst_i_2/O net (fo=3, routed) 0.540 1.521 U1/vga_vs_OBUF_inst_i_2_n_0 SLICE_X42Y31 LUT6 (Prop_lut6_I5_O) 0.124 1.645 r U1/comptY[9]_i_8/O net (fo=1, routed) 0.304 1.949 U1/comptY[9]_i_8_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.073 r U1/comptY[9]_i_5/O net (fo=1, routed) 0.650 2.723 U1/comptY[9]_i_5_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.847 r U1/comptY[9]_i_1/O net (fo=10, routed) 0.685 3.532 U1/comptY SLICE_X42Y32 FDRE r U1/comptY_reg[0]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r L16 0.000 40.000 r H125MHz (IN) net (fo=0) 0.000 40.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.571 38.739 U1/CLK SLICE_X42Y32 FDRE r U1/comptY_reg[0]/C clock pessimism 0.626 39.365 clock uncertainty -0.160 39.205 SLICE_X42Y32 FDRE (Setup_fdre_C_R) -0.524 38.681 U1/comptY_reg[0] ------------------------------------------------------------------- required time 38.681 arrival time -3.532 ------------------------------------------------------------------- slack 35.149 Slack (MET) : 35.149ns (required time - arrival time) Source: U1/comptY_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[1]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 4.145ns (logic 0.952ns (22.969%) route 3.193ns (77.031%)) Logic Levels: 4 (LUT4=1 LUT6=3) Clock Path Skew: -0.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.261ns = ( 38.739 - 40.000 ) Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.626ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.746 -0.613 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y31 FDRE (Prop_fdre_C_Q) 0.456 -0.157 r U1/comptY_reg[7]/Q net (fo=10, routed) 1.014 0.857 U1/comptY_reg__0[7] SLICE_X43Y31 LUT4 (Prop_lut4_I1_O) 0.124 0.981 r U1/vga_vs_OBUF_inst_i_2/O net (fo=3, routed) 0.540 1.521 U1/vga_vs_OBUF_inst_i_2_n_0 SLICE_X42Y31 LUT6 (Prop_lut6_I5_O) 0.124 1.645 r U1/comptY[9]_i_8/O net (fo=1, routed) 0.304 1.949 U1/comptY[9]_i_8_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.073 r U1/comptY[9]_i_5/O net (fo=1, routed) 0.650 2.723 U1/comptY[9]_i_5_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.847 r U1/comptY[9]_i_1/O net (fo=10, routed) 0.685 3.532 U1/comptY SLICE_X42Y32 FDRE r U1/comptY_reg[1]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r L16 0.000 40.000 r H125MHz (IN) net (fo=0) 0.000 40.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.571 38.739 U1/CLK SLICE_X42Y32 FDRE r U1/comptY_reg[1]/C clock pessimism 0.626 39.365 clock uncertainty -0.160 39.205 SLICE_X42Y32 FDRE (Setup_fdre_C_R) -0.524 38.681 U1/comptY_reg[1] ------------------------------------------------------------------- required time 38.681 arrival time -3.532 ------------------------------------------------------------------- slack 35.149 Slack (MET) : 35.149ns (required time - arrival time) Source: U1/comptY_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[2]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 4.145ns (logic 0.952ns (22.969%) route 3.193ns (77.031%)) Logic Levels: 4 (LUT4=1 LUT6=3) Clock Path Skew: -0.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.261ns = ( 38.739 - 40.000 ) Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.626ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.746 -0.613 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y31 FDRE (Prop_fdre_C_Q) 0.456 -0.157 r U1/comptY_reg[7]/Q net (fo=10, routed) 1.014 0.857 U1/comptY_reg__0[7] SLICE_X43Y31 LUT4 (Prop_lut4_I1_O) 0.124 0.981 r U1/vga_vs_OBUF_inst_i_2/O net (fo=3, routed) 0.540 1.521 U1/vga_vs_OBUF_inst_i_2_n_0 SLICE_X42Y31 LUT6 (Prop_lut6_I5_O) 0.124 1.645 r U1/comptY[9]_i_8/O net (fo=1, routed) 0.304 1.949 U1/comptY[9]_i_8_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.073 r U1/comptY[9]_i_5/O net (fo=1, routed) 0.650 2.723 U1/comptY[9]_i_5_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.847 r U1/comptY[9]_i_1/O net (fo=10, routed) 0.685 3.532 U1/comptY SLICE_X42Y32 FDRE r U1/comptY_reg[2]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r L16 0.000 40.000 r H125MHz (IN) net (fo=0) 0.000 40.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.571 38.739 U1/CLK SLICE_X42Y32 FDRE r U1/comptY_reg[2]/C clock pessimism 0.626 39.365 clock uncertainty -0.160 39.205 SLICE_X42Y32 FDRE (Setup_fdre_C_R) -0.524 38.681 U1/comptY_reg[2] ------------------------------------------------------------------- required time 38.681 arrival time -3.532 ------------------------------------------------------------------- slack 35.149 Slack (MET) : 35.149ns (required time - arrival time) Source: U1/comptY_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[3]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 4.145ns (logic 0.952ns (22.969%) route 3.193ns (77.031%)) Logic Levels: 4 (LUT4=1 LUT6=3) Clock Path Skew: -0.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.261ns = ( 38.739 - 40.000 ) Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.626ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.746 -0.613 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y31 FDRE (Prop_fdre_C_Q) 0.456 -0.157 r U1/comptY_reg[7]/Q net (fo=10, routed) 1.014 0.857 U1/comptY_reg__0[7] SLICE_X43Y31 LUT4 (Prop_lut4_I1_O) 0.124 0.981 r U1/vga_vs_OBUF_inst_i_2/O net (fo=3, routed) 0.540 1.521 U1/vga_vs_OBUF_inst_i_2_n_0 SLICE_X42Y31 LUT6 (Prop_lut6_I5_O) 0.124 1.645 r U1/comptY[9]_i_8/O net (fo=1, routed) 0.304 1.949 U1/comptY[9]_i_8_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.073 r U1/comptY[9]_i_5/O net (fo=1, routed) 0.650 2.723 U1/comptY[9]_i_5_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.847 r U1/comptY[9]_i_1/O net (fo=10, routed) 0.685 3.532 U1/comptY SLICE_X42Y32 FDRE r U1/comptY_reg[3]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r L16 0.000 40.000 r H125MHz (IN) net (fo=0) 0.000 40.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.571 38.739 U1/CLK SLICE_X42Y32 FDRE r U1/comptY_reg[3]/C clock pessimism 0.626 39.365 clock uncertainty -0.160 39.205 SLICE_X42Y32 FDRE (Setup_fdre_C_R) -0.524 38.681 U1/comptY_reg[3] ------------------------------------------------------------------- required time 38.681 arrival time -3.532 ------------------------------------------------------------------- slack 35.149 Slack (MET) : 35.149ns (required time - arrival time) Source: U1/comptY_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[5]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 4.145ns (logic 0.952ns (22.969%) route 3.193ns (77.031%)) Logic Levels: 4 (LUT4=1 LUT6=3) Clock Path Skew: -0.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.261ns = ( 38.739 - 40.000 ) Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.626ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.746 -0.613 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y31 FDRE (Prop_fdre_C_Q) 0.456 -0.157 r U1/comptY_reg[7]/Q net (fo=10, routed) 1.014 0.857 U1/comptY_reg__0[7] SLICE_X43Y31 LUT4 (Prop_lut4_I1_O) 0.124 0.981 r U1/vga_vs_OBUF_inst_i_2/O net (fo=3, routed) 0.540 1.521 U1/vga_vs_OBUF_inst_i_2_n_0 SLICE_X42Y31 LUT6 (Prop_lut6_I5_O) 0.124 1.645 r U1/comptY[9]_i_8/O net (fo=1, routed) 0.304 1.949 U1/comptY[9]_i_8_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.073 r U1/comptY[9]_i_5/O net (fo=1, routed) 0.650 2.723 U1/comptY[9]_i_5_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.847 r U1/comptY[9]_i_1/O net (fo=10, routed) 0.685 3.532 U1/comptY SLICE_X42Y32 FDRE r U1/comptY_reg[5]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r L16 0.000 40.000 r H125MHz (IN) net (fo=0) 0.000 40.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.571 38.739 U1/CLK SLICE_X42Y32 FDRE r U1/comptY_reg[5]/C clock pessimism 0.626 39.365 clock uncertainty -0.160 39.205 SLICE_X42Y32 FDRE (Setup_fdre_C_R) -0.524 38.681 U1/comptY_reg[5] ------------------------------------------------------------------- required time 38.681 arrival time -3.532 ------------------------------------------------------------------- slack 35.149 Slack (MET) : 35.281ns (required time - arrival time) Source: U1/comptY_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[4]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 4.011ns (logic 0.952ns (23.735%) route 3.059ns (76.265%)) Logic Levels: 4 (LUT4=1 LUT6=3) Clock Path Skew: -0.024ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.263ns = ( 38.737 - 40.000 ) Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.626ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.746 -0.613 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y31 FDRE (Prop_fdre_C_Q) 0.456 -0.157 r U1/comptY_reg[7]/Q net (fo=10, routed) 1.014 0.857 U1/comptY_reg__0[7] SLICE_X43Y31 LUT4 (Prop_lut4_I1_O) 0.124 0.981 r U1/vga_vs_OBUF_inst_i_2/O net (fo=3, routed) 0.540 1.521 U1/vga_vs_OBUF_inst_i_2_n_0 SLICE_X42Y31 LUT6 (Prop_lut6_I5_O) 0.124 1.645 r U1/comptY[9]_i_8/O net (fo=1, routed) 0.304 1.949 U1/comptY[9]_i_8_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.073 r U1/comptY[9]_i_5/O net (fo=1, routed) 0.650 2.723 U1/comptY[9]_i_5_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.847 r U1/comptY[9]_i_1/O net (fo=10, routed) 0.552 3.398 U1/comptY SLICE_X42Y31 FDRE r U1/comptY_reg[4]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r L16 0.000 40.000 r H125MHz (IN) net (fo=0) 0.000 40.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.569 38.737 U1/CLK SLICE_X42Y31 FDRE r U1/comptY_reg[4]/C clock pessimism 0.626 39.363 clock uncertainty -0.160 39.203 SLICE_X42Y31 FDRE (Setup_fdre_C_R) -0.524 38.679 U1/comptY_reg[4] ------------------------------------------------------------------- required time 38.679 arrival time -3.398 ------------------------------------------------------------------- slack 35.281 Slack (MET) : 35.427ns (required time - arrival time) Source: U1/comptY_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[6]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 3.961ns (logic 0.952ns (24.032%) route 3.009ns (75.968%)) Logic Levels: 4 (LUT4=1 LUT6=3) Clock Path Skew: -0.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.263ns = ( 38.737 - 40.000 ) Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.628ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.746 -0.613 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y31 FDRE (Prop_fdre_C_Q) 0.456 -0.157 r U1/comptY_reg[7]/Q net (fo=10, routed) 1.014 0.857 U1/comptY_reg__0[7] SLICE_X43Y31 LUT4 (Prop_lut4_I1_O) 0.124 0.981 r U1/vga_vs_OBUF_inst_i_2/O net (fo=3, routed) 0.540 1.521 U1/vga_vs_OBUF_inst_i_2_n_0 SLICE_X42Y31 LUT6 (Prop_lut6_I5_O) 0.124 1.645 r U1/comptY[9]_i_8/O net (fo=1, routed) 0.304 1.949 U1/comptY[9]_i_8_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.073 r U1/comptY[9]_i_5/O net (fo=1, routed) 0.650 2.723 U1/comptY[9]_i_5_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.847 r U1/comptY[9]_i_1/O net (fo=10, routed) 0.502 3.349 U1/comptY SLICE_X41Y31 FDRE r U1/comptY_reg[6]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r L16 0.000 40.000 r H125MHz (IN) net (fo=0) 0.000 40.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.569 38.737 U1/CLK SLICE_X41Y31 FDRE r U1/comptY_reg[6]/C clock pessimism 0.628 39.365 clock uncertainty -0.160 39.205 SLICE_X41Y31 FDRE (Setup_fdre_C_R) -0.429 38.776 U1/comptY_reg[6] ------------------------------------------------------------------- required time 38.776 arrival time -3.349 ------------------------------------------------------------------- slack 35.427 Slack (MET) : 35.445ns (required time - arrival time) Source: U1/comptY_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[7]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 3.966ns (logic 0.952ns (24.006%) route 3.014ns (75.994%)) Logic Levels: 4 (LUT4=1 LUT6=3) Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.263ns = ( 38.737 - 40.000 ) Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.650ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.746 -0.613 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y31 FDRE (Prop_fdre_C_Q) 0.456 -0.157 r U1/comptY_reg[7]/Q net (fo=10, routed) 1.014 0.857 U1/comptY_reg__0[7] SLICE_X43Y31 LUT4 (Prop_lut4_I1_O) 0.124 0.981 r U1/vga_vs_OBUF_inst_i_2/O net (fo=3, routed) 0.540 1.521 U1/vga_vs_OBUF_inst_i_2_n_0 SLICE_X42Y31 LUT6 (Prop_lut6_I5_O) 0.124 1.645 r U1/comptY[9]_i_8/O net (fo=1, routed) 0.304 1.949 U1/comptY[9]_i_8_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.073 r U1/comptY[9]_i_5/O net (fo=1, routed) 0.650 2.723 U1/comptY[9]_i_5_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.847 r U1/comptY[9]_i_1/O net (fo=10, routed) 0.506 3.353 U1/comptY SLICE_X40Y31 FDRE r U1/comptY_reg[7]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r L16 0.000 40.000 r H125MHz (IN) net (fo=0) 0.000 40.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.569 38.737 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[7]/C clock pessimism 0.650 39.387 clock uncertainty -0.160 39.227 SLICE_X40Y31 FDRE (Setup_fdre_C_R) -0.429 38.798 U1/comptY_reg[7] ------------------------------------------------------------------- required time 38.798 arrival time -3.353 ------------------------------------------------------------------- slack 35.445 Slack (MET) : 35.445ns (required time - arrival time) Source: U1/comptY_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[8]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 3.966ns (logic 0.952ns (24.006%) route 3.014ns (75.994%)) Logic Levels: 4 (LUT4=1 LUT6=3) Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.263ns = ( 38.737 - 40.000 ) Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.650ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.746 -0.613 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y31 FDRE (Prop_fdre_C_Q) 0.456 -0.157 r U1/comptY_reg[7]/Q net (fo=10, routed) 1.014 0.857 U1/comptY_reg__0[7] SLICE_X43Y31 LUT4 (Prop_lut4_I1_O) 0.124 0.981 r U1/vga_vs_OBUF_inst_i_2/O net (fo=3, routed) 0.540 1.521 U1/vga_vs_OBUF_inst_i_2_n_0 SLICE_X42Y31 LUT6 (Prop_lut6_I5_O) 0.124 1.645 r U1/comptY[9]_i_8/O net (fo=1, routed) 0.304 1.949 U1/comptY[9]_i_8_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.073 r U1/comptY[9]_i_5/O net (fo=1, routed) 0.650 2.723 U1/comptY[9]_i_5_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.847 r U1/comptY[9]_i_1/O net (fo=10, routed) 0.506 3.353 U1/comptY SLICE_X40Y31 FDRE r U1/comptY_reg[8]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r L16 0.000 40.000 r H125MHz (IN) net (fo=0) 0.000 40.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.569 38.737 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[8]/C clock pessimism 0.650 39.387 clock uncertainty -0.160 39.227 SLICE_X40Y31 FDRE (Setup_fdre_C_R) -0.429 38.798 U1/comptY_reg[8] ------------------------------------------------------------------- required time 38.798 arrival time -3.353 ------------------------------------------------------------------- slack 35.445 Slack (MET) : 35.445ns (required time - arrival time) Source: U1/comptY_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[9]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 3.966ns (logic 0.952ns (24.006%) route 3.014ns (75.994%)) Logic Levels: 4 (LUT4=1 LUT6=3) Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.263ns = ( 38.737 - 40.000 ) Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.650ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.746 -0.613 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y31 FDRE (Prop_fdre_C_Q) 0.456 -0.157 r U1/comptY_reg[7]/Q net (fo=10, routed) 1.014 0.857 U1/comptY_reg__0[7] SLICE_X43Y31 LUT4 (Prop_lut4_I1_O) 0.124 0.981 r U1/vga_vs_OBUF_inst_i_2/O net (fo=3, routed) 0.540 1.521 U1/vga_vs_OBUF_inst_i_2_n_0 SLICE_X42Y31 LUT6 (Prop_lut6_I5_O) 0.124 1.645 r U1/comptY[9]_i_8/O net (fo=1, routed) 0.304 1.949 U1/comptY[9]_i_8_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.073 r U1/comptY[9]_i_5/O net (fo=1, routed) 0.650 2.723 U1/comptY[9]_i_5_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.847 r U1/comptY[9]_i_1/O net (fo=10, routed) 0.506 3.353 U1/comptY SLICE_X40Y31 FDRE r U1/comptY_reg[9]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r L16 0.000 40.000 r H125MHz (IN) net (fo=0) 0.000 40.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.569 38.737 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[9]/C clock pessimism 0.650 39.387 clock uncertainty -0.160 39.227 SLICE_X40Y31 FDRE (Setup_fdre_C_R) -0.429 38.798 U1/comptY_reg[9] ------------------------------------------------------------------- required time 38.798 arrival time -3.353 ------------------------------------------------------------------- slack 35.445 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.223ns (arrival time - required time) Source: U1/comptY_reg[6]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[8]/D (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 0.343ns (logic 0.189ns (55.030%) route 0.154ns (44.970%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.709ns Source Clock Delay (SCD): -0.474ns Clock Pessimism Removal (CPR): -0.248ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.587 -0.474 U1/CLK SLICE_X41Y31 FDRE r U1/comptY_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X41Y31 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptY_reg[6]/Q net (fo=11, routed) 0.154 -0.178 U1/comptY_reg__0[6] SLICE_X40Y31 LUT5 (Prop_lut5_I1_O) 0.048 -0.130 r U1/comptY[8]_i_1/O net (fo=1, routed) 0.000 -0.130 U1/plusOp__0[8] SLICE_X40Y31 FDRE r U1/comptY_reg[8]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.854 -0.709 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[8]/C clock pessimism 0.248 -0.461 SLICE_X40Y31 FDRE (Hold_fdre_C_D) 0.107 -0.354 U1/comptY_reg[8] ------------------------------------------------------------------- required time 0.354 arrival time -0.130 ------------------------------------------------------------------- slack 0.223 Slack (MET) : 0.236ns (arrival time - required time) Source: U1/comptY_reg[6]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[9]/D (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 0.341ns (logic 0.186ns (54.474%) route 0.155ns (45.526%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.709ns Source Clock Delay (SCD): -0.474ns Clock Pessimism Removal (CPR): -0.248ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.587 -0.474 U1/CLK SLICE_X41Y31 FDRE r U1/comptY_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X41Y31 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptY_reg[6]/Q net (fo=11, routed) 0.155 -0.177 U1/comptY_reg__0[6] SLICE_X40Y31 LUT6 (Prop_lut6_I1_O) 0.045 -0.132 r U1/comptY[9]_i_3/O net (fo=1, routed) 0.000 -0.132 U1/plusOp__0[9] SLICE_X40Y31 FDRE r U1/comptY_reg[9]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.854 -0.709 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[9]/C clock pessimism 0.248 -0.461 SLICE_X40Y31 FDRE (Hold_fdre_C_D) 0.092 -0.369 U1/comptY_reg[9] ------------------------------------------------------------------- required time 0.369 arrival time -0.132 ------------------------------------------------------------------- slack 0.236 Slack (MET) : 0.236ns (arrival time - required time) Source: U1/comptY_reg[6]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[7]/D (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 0.340ns (logic 0.186ns (54.634%) route 0.154ns (45.366%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.709ns Source Clock Delay (SCD): -0.474ns Clock Pessimism Removal (CPR): -0.248ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.587 -0.474 U1/CLK SLICE_X41Y31 FDRE r U1/comptY_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X41Y31 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptY_reg[6]/Q net (fo=11, routed) 0.154 -0.178 U1/comptY_reg__0[6] SLICE_X40Y31 LUT4 (Prop_lut4_I2_O) 0.045 -0.133 r U1/comptY[7]_i_1/O net (fo=1, routed) 0.000 -0.133 U1/plusOp__0[7] SLICE_X40Y31 FDRE r U1/comptY_reg[7]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.854 -0.709 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[7]/C clock pessimism 0.248 -0.461 SLICE_X40Y31 FDRE (Hold_fdre_C_D) 0.091 -0.370 U1/comptY_reg[7] ------------------------------------------------------------------- required time 0.370 arrival time -0.133 ------------------------------------------------------------------- slack 0.236 Slack (MET) : 0.251ns (arrival time - required time) Source: U1/comptX_reg[8]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptX_reg[9]/D (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 0.382ns (logic 0.207ns (54.146%) route 0.175ns (45.854%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.714ns Source Clock Delay (SCD): -0.479ns Clock Pessimism Removal (CPR): -0.235ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.582 -0.479 U1/CLK SLICE_X38Y28 FDRE r U1/comptX_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X38Y28 FDRE (Prop_fdre_C_Q) 0.164 -0.315 r U1/comptX_reg[8]/Q net (fo=12, routed) 0.175 -0.140 U1/comptX_reg__0[8] SLICE_X38Y28 LUT5 (Prop_lut5_I0_O) 0.043 -0.097 r U1/comptX[9]_i_1/O net (fo=1, routed) 0.000 -0.097 U1/plusOp[9] SLICE_X38Y28 FDRE r U1/comptX_reg[9]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.849 -0.714 U1/CLK SLICE_X38Y28 FDRE r U1/comptX_reg[9]/C clock pessimism 0.235 -0.479 SLICE_X38Y28 FDRE (Hold_fdre_C_D) 0.131 -0.348 U1/comptX_reg[9] ------------------------------------------------------------------- required time 0.348 arrival time -0.097 ------------------------------------------------------------------- slack 0.251 Slack (MET) : 0.253ns (arrival time - required time) Source: U1/comptY_reg[4]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[5]/D (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 0.389ns (logic 0.209ns (53.754%) route 0.180ns (46.246%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.708ns Source Clock Delay (SCD): -0.474ns Clock Pessimism Removal (CPR): -0.249ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.587 -0.474 U1/CLK SLICE_X42Y31 FDRE r U1/comptY_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X42Y31 FDRE (Prop_fdre_C_Q) 0.164 -0.310 r U1/comptY_reg[4]/Q net (fo=5, routed) 0.180 -0.130 U1/comptY_reg__0[4] SLICE_X42Y32 LUT6 (Prop_lut6_I0_O) 0.045 -0.085 r U1/comptY[5]_i_1/O net (fo=1, routed) 0.000 -0.085 U1/comptY[5]_i_1_n_0 SLICE_X42Y32 FDRE r U1/comptY_reg[5]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.855 -0.708 U1/CLK SLICE_X42Y32 FDRE r U1/comptY_reg[5]/C clock pessimism 0.249 -0.459 SLICE_X42Y32 FDRE (Hold_fdre_C_D) 0.121 -0.338 U1/comptY_reg[5] ------------------------------------------------------------------- required time 0.338 arrival time -0.085 ------------------------------------------------------------------- slack 0.253 Slack (MET) : 0.254ns (arrival time - required time) Source: U1/comptX_reg[3]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptX_reg[5]/D (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 0.381ns (logic 0.186ns (48.823%) route 0.195ns (51.177%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.710ns Source Clock Delay (SCD): -0.477ns Clock Pessimism Removal (CPR): -0.269ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.584 -0.477 U1/CLK SLICE_X39Y30 FDRE r U1/comptX_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X39Y30 FDRE (Prop_fdre_C_Q) 0.141 -0.336 r U1/comptX_reg[3]/Q net (fo=6, routed) 0.195 -0.141 U1/comptX_reg__0[3] SLICE_X40Y30 LUT6 (Prop_lut6_I4_O) 0.045 -0.096 r U1/comptX[5]_i_1/O net (fo=1, routed) 0.000 -0.096 U1/plusOp[5] SLICE_X40Y30 FDRE r U1/comptX_reg[5]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.853 -0.710 U1/CLK SLICE_X40Y30 FDRE r U1/comptX_reg[5]/C clock pessimism 0.269 -0.441 SLICE_X40Y30 FDRE (Hold_fdre_C_D) 0.091 -0.350 U1/comptX_reg[5] ------------------------------------------------------------------- required time 0.350 arrival time -0.096 ------------------------------------------------------------------- slack 0.254 Slack (MET) : 0.256ns (arrival time - required time) Source: U1/comptX_reg[6]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptX_reg[7]/D (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 0.363ns (logic 0.183ns (50.353%) route 0.180ns (49.647%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.714ns Source Clock Delay (SCD): -0.479ns Clock Pessimism Removal (CPR): -0.235ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.582 -0.479 U1/CLK SLICE_X39Y28 FDRE r U1/comptX_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X39Y28 FDRE (Prop_fdre_C_Q) 0.141 -0.338 r U1/comptX_reg[6]/Q net (fo=10, routed) 0.180 -0.157 U1/comptX_reg__0[6] SLICE_X39Y28 LUT3 (Prop_lut3_I0_O) 0.042 -0.115 r U1/comptX[7]_i_1/O net (fo=1, routed) 0.000 -0.115 U1/plusOp[7] SLICE_X39Y28 FDRE r U1/comptX_reg[7]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.849 -0.714 U1/CLK SLICE_X39Y28 FDRE r U1/comptX_reg[7]/C clock pessimism 0.235 -0.479 SLICE_X39Y28 FDRE (Hold_fdre_C_D) 0.107 -0.372 U1/comptX_reg[7] ------------------------------------------------------------------- required time 0.372 arrival time -0.115 ------------------------------------------------------------------- slack 0.256 Slack (MET) : 0.259ns (arrival time - required time) Source: U1/comptY_reg[4]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[4]/D (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 0.382ns (logic 0.207ns (54.146%) route 0.175ns (45.854%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.709ns Source Clock Delay (SCD): -0.474ns Clock Pessimism Removal (CPR): -0.235ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.587 -0.474 U1/CLK SLICE_X42Y31 FDRE r U1/comptY_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X42Y31 FDRE (Prop_fdre_C_Q) 0.164 -0.310 r U1/comptY_reg[4]/Q net (fo=5, routed) 0.175 -0.135 U1/comptY_reg__0[4] SLICE_X42Y31 LUT5 (Prop_lut5_I4_O) 0.043 -0.092 r U1/comptY[4]_i_1/O net (fo=2, routed) 0.000 -0.092 U1/comptY[4]_i_1_n_0 SLICE_X42Y31 FDRE r U1/comptY_reg[4]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.854 -0.709 U1/CLK SLICE_X42Y31 FDRE r U1/comptY_reg[4]/C clock pessimism 0.235 -0.474 SLICE_X42Y31 FDRE (Hold_fdre_C_D) 0.123 -0.351 U1/comptY_reg[4] ------------------------------------------------------------------- required time 0.351 arrival time -0.092 ------------------------------------------------------------------- slack 0.259 Slack (MET) : 0.264ns (arrival time - required time) Source: U1/comptX_reg[8]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptX_reg[8]/D (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 0.384ns (logic 0.209ns (54.384%) route 0.175ns (45.616%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.714ns Source Clock Delay (SCD): -0.479ns Clock Pessimism Removal (CPR): -0.235ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.582 -0.479 U1/CLK SLICE_X38Y28 FDRE r U1/comptX_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X38Y28 FDRE (Prop_fdre_C_Q) 0.164 -0.315 r U1/comptX_reg[8]/Q net (fo=12, routed) 0.175 -0.140 U1/comptX_reg__0[8] SLICE_X38Y28 LUT4 (Prop_lut4_I3_O) 0.045 -0.095 r U1/comptX[8]_i_1/O net (fo=1, routed) 0.000 -0.095 U1/plusOp[8] SLICE_X38Y28 FDRE r U1/comptX_reg[8]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.849 -0.714 U1/CLK SLICE_X38Y28 FDRE r U1/comptX_reg[8]/C clock pessimism 0.235 -0.479 SLICE_X38Y28 FDRE (Hold_fdre_C_D) 0.120 -0.359 U1/comptX_reg[8] ------------------------------------------------------------------- required time 0.359 arrival time -0.095 ------------------------------------------------------------------- slack 0.264 Slack (MET) : 0.267ns (arrival time - required time) Source: U1/comptX_reg[1]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptX_reg[2]/D (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 0.374ns (logic 0.183ns (48.868%) route 0.191ns (51.132%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.712ns Source Clock Delay (SCD): -0.477ns Clock Pessimism Removal (CPR): -0.235ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.584 -0.477 U1/CLK SLICE_X39Y30 FDRE r U1/comptX_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X39Y30 FDRE (Prop_fdre_C_Q) 0.141 -0.336 r U1/comptX_reg[1]/Q net (fo=8, routed) 0.191 -0.144 U1/comptX_reg__0[1] SLICE_X39Y30 LUT3 (Prop_lut3_I0_O) 0.042 -0.102 r U1/comptX[2]_i_1/O net (fo=1, routed) 0.000 -0.102 U1/plusOp[2] SLICE_X39Y30 FDRE r U1/comptX_reg[2]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.851 -0.712 U1/CLK SLICE_X39Y30 FDRE r U1/comptX_reg[2]/C clock pessimism 0.235 -0.477 SLICE_X39Y30 FDRE (Hold_fdre_C_D) 0.107 -0.370 U1/comptX_reg[2] ------------------------------------------------------------------- required time 0.370 arrival time -0.102 ------------------------------------------------------------------- slack 0.267 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk_out1_clk_wiz_1 Waveform(ns): { 0.000 20.000 } Period(ns): 40.000 Sources: { U0/inst/mmcm_adv_inst/CLKOUT0 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFG/I n/a 2.155 40.000 37.845 BUFGCTRL_X0Y16 U0/inst/clkout1_buf/I Min Period n/a MMCME2_ADV/CLKOUT0 n/a 1.249 40.000 38.751 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKOUT0 Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X39Y30 U1/comptX_reg[0]/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X40Y29 U1/comptX_reg[10]/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X39Y30 U1/comptX_reg[1]/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X39Y30 U1/comptX_reg[2]/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X39Y30 U1/comptX_reg[3]/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X39Y30 U1/comptX_reg[4]/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X40Y30 U1/comptX_reg[5]/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X39Y28 U1/comptX_reg[6]/C Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 40.000 173.360 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKOUT0 Low Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X39Y30 U1/comptX_reg[0]/C Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X39Y30 U1/comptX_reg[0]/C Low Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X39Y30 U1/comptX_reg[1]/C Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X39Y30 U1/comptX_reg[1]/C Low Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X39Y30 U1/comptX_reg[2]/C Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X39Y30 U1/comptX_reg[2]/C Low Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X39Y30 U1/comptX_reg[3]/C Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X39Y30 U1/comptX_reg[3]/C Low Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X39Y30 U1/comptX_reg[4]/C Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X39Y30 U1/comptX_reg[4]/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X39Y30 U1/comptX_reg[0]/C High Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X39Y30 U1/comptX_reg[0]/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X40Y29 U1/comptX_reg[10]/C High Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X40Y29 U1/comptX_reg[10]/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X39Y30 U1/comptX_reg[1]/C High Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X39Y30 U1/comptX_reg[1]/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X39Y30 U1/comptX_reg[2]/C High Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X39Y30 U1/comptX_reg[2]/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X39Y30 U1/comptX_reg[3]/C High Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X39Y30 U1/comptX_reg[3]/C --------------------------------------------------------------------------------------------------- From Clock: clkfbout_clk_wiz_1 To Clock: clkfbout_clk_wiz_1 Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 37.845ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clkfbout_clk_wiz_1 Waveform(ns): { 0.000 20.000 } Period(ns): 40.000 Sources: { U0/inst/mmcm_adv_inst/CLKFBOUT } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFG/I n/a 2.155 40.000 37.845 BUFGCTRL_X0Y17 U0/inst/clkf_buf/I Min Period n/a MMCME2_ADV/CLKFBOUT n/a 1.249 40.000 38.751 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKFBOUT Min Period n/a MMCME2_ADV/CLKFBIN n/a 1.249 40.000 38.751 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKFBIN Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 40.000 60.000 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKFBIN Max Period n/a MMCME2_ADV/CLKFBOUT n/a 213.360 40.000 173.360 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKFBOUT --------------------------------------------------------------------------------------------------- From Clock: sys_clk_pin To Clock: sys_clk_pin Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 2.000ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: sys_clk_pin Waveform(ns): { 0.000 4.000 } Period(ns): 8.000 Sources: { H125MHz } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a MMCME2_ADV/CLKIN1 n/a 1.249 8.000 6.751 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKIN1 Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 8.000 92.000 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKIN1 Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 4.000 2.000 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKIN1 Low Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 2.000 4.000 2.000 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKIN1 High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 4.000 2.000 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKIN1 High Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 2.000 4.000 2.000 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKIN1 --------------------------------------------------------------------------------------------------- From Clock: clk_out1_clk_wiz_1_1 To Clock: clk_out1_clk_wiz_1_1 Setup : 0 Failing Endpoints, Worst Slack 35.162ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.223ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 19.500ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 35.162ns (required time - arrival time) Source: U1/comptY_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[0]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) Data Path Delay: 4.145ns (logic 0.952ns (22.969%) route 3.193ns (77.031%)) Logic Levels: 4 (LUT4=1 LUT6=3) Clock Path Skew: -0.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.261ns = ( 38.739 - 40.000 ) Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.626ns Clock Uncertainty: 0.147ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.286ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.746 -0.613 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y31 FDRE (Prop_fdre_C_Q) 0.456 -0.157 r U1/comptY_reg[7]/Q net (fo=10, routed) 1.014 0.857 U1/comptY_reg__0[7] SLICE_X43Y31 LUT4 (Prop_lut4_I1_O) 0.124 0.981 r U1/vga_vs_OBUF_inst_i_2/O net (fo=3, routed) 0.540 1.521 U1/vga_vs_OBUF_inst_i_2_n_0 SLICE_X42Y31 LUT6 (Prop_lut6_I5_O) 0.124 1.645 r U1/comptY[9]_i_8/O net (fo=1, routed) 0.304 1.949 U1/comptY[9]_i_8_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.073 r U1/comptY[9]_i_5/O net (fo=1, routed) 0.650 2.723 U1/comptY[9]_i_5_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.847 r U1/comptY[9]_i_1/O net (fo=10, routed) 0.685 3.532 U1/comptY SLICE_X42Y32 FDRE r U1/comptY_reg[0]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 40.000 40.000 r L16 0.000 40.000 r H125MHz (IN) net (fo=0) 0.000 40.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.571 38.739 U1/CLK SLICE_X42Y32 FDRE r U1/comptY_reg[0]/C clock pessimism 0.626 39.365 clock uncertainty -0.147 39.218 SLICE_X42Y32 FDRE (Setup_fdre_C_R) -0.524 38.694 U1/comptY_reg[0] ------------------------------------------------------------------- required time 38.694 arrival time -3.532 ------------------------------------------------------------------- slack 35.162 Slack (MET) : 35.162ns (required time - arrival time) Source: U1/comptY_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[1]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) Data Path Delay: 4.145ns (logic 0.952ns (22.969%) route 3.193ns (77.031%)) Logic Levels: 4 (LUT4=1 LUT6=3) Clock Path Skew: -0.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.261ns = ( 38.739 - 40.000 ) Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.626ns Clock Uncertainty: 0.147ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.286ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.746 -0.613 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y31 FDRE (Prop_fdre_C_Q) 0.456 -0.157 r U1/comptY_reg[7]/Q net (fo=10, routed) 1.014 0.857 U1/comptY_reg__0[7] SLICE_X43Y31 LUT4 (Prop_lut4_I1_O) 0.124 0.981 r U1/vga_vs_OBUF_inst_i_2/O net (fo=3, routed) 0.540 1.521 U1/vga_vs_OBUF_inst_i_2_n_0 SLICE_X42Y31 LUT6 (Prop_lut6_I5_O) 0.124 1.645 r U1/comptY[9]_i_8/O net (fo=1, routed) 0.304 1.949 U1/comptY[9]_i_8_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.073 r U1/comptY[9]_i_5/O net (fo=1, routed) 0.650 2.723 U1/comptY[9]_i_5_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.847 r U1/comptY[9]_i_1/O net (fo=10, routed) 0.685 3.532 U1/comptY SLICE_X42Y32 FDRE r U1/comptY_reg[1]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 40.000 40.000 r L16 0.000 40.000 r H125MHz (IN) net (fo=0) 0.000 40.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.571 38.739 U1/CLK SLICE_X42Y32 FDRE r U1/comptY_reg[1]/C clock pessimism 0.626 39.365 clock uncertainty -0.147 39.218 SLICE_X42Y32 FDRE (Setup_fdre_C_R) -0.524 38.694 U1/comptY_reg[1] ------------------------------------------------------------------- required time 38.694 arrival time -3.532 ------------------------------------------------------------------- slack 35.162 Slack (MET) : 35.162ns (required time - arrival time) Source: U1/comptY_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[2]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) Data Path Delay: 4.145ns (logic 0.952ns (22.969%) route 3.193ns (77.031%)) Logic Levels: 4 (LUT4=1 LUT6=3) Clock Path Skew: -0.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.261ns = ( 38.739 - 40.000 ) Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.626ns Clock Uncertainty: 0.147ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.286ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.746 -0.613 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y31 FDRE (Prop_fdre_C_Q) 0.456 -0.157 r U1/comptY_reg[7]/Q net (fo=10, routed) 1.014 0.857 U1/comptY_reg__0[7] SLICE_X43Y31 LUT4 (Prop_lut4_I1_O) 0.124 0.981 r U1/vga_vs_OBUF_inst_i_2/O net (fo=3, routed) 0.540 1.521 U1/vga_vs_OBUF_inst_i_2_n_0 SLICE_X42Y31 LUT6 (Prop_lut6_I5_O) 0.124 1.645 r U1/comptY[9]_i_8/O net (fo=1, routed) 0.304 1.949 U1/comptY[9]_i_8_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.073 r U1/comptY[9]_i_5/O net (fo=1, routed) 0.650 2.723 U1/comptY[9]_i_5_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.847 r U1/comptY[9]_i_1/O net (fo=10, routed) 0.685 3.532 U1/comptY SLICE_X42Y32 FDRE r U1/comptY_reg[2]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 40.000 40.000 r L16 0.000 40.000 r H125MHz (IN) net (fo=0) 0.000 40.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.571 38.739 U1/CLK SLICE_X42Y32 FDRE r U1/comptY_reg[2]/C clock pessimism 0.626 39.365 clock uncertainty -0.147 39.218 SLICE_X42Y32 FDRE (Setup_fdre_C_R) -0.524 38.694 U1/comptY_reg[2] ------------------------------------------------------------------- required time 38.694 arrival time -3.532 ------------------------------------------------------------------- slack 35.162 Slack (MET) : 35.162ns (required time - arrival time) Source: U1/comptY_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[3]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) Data Path Delay: 4.145ns (logic 0.952ns (22.969%) route 3.193ns (77.031%)) Logic Levels: 4 (LUT4=1 LUT6=3) Clock Path Skew: -0.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.261ns = ( 38.739 - 40.000 ) Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.626ns Clock Uncertainty: 0.147ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.286ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.746 -0.613 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y31 FDRE (Prop_fdre_C_Q) 0.456 -0.157 r U1/comptY_reg[7]/Q net (fo=10, routed) 1.014 0.857 U1/comptY_reg__0[7] SLICE_X43Y31 LUT4 (Prop_lut4_I1_O) 0.124 0.981 r U1/vga_vs_OBUF_inst_i_2/O net (fo=3, routed) 0.540 1.521 U1/vga_vs_OBUF_inst_i_2_n_0 SLICE_X42Y31 LUT6 (Prop_lut6_I5_O) 0.124 1.645 r U1/comptY[9]_i_8/O net (fo=1, routed) 0.304 1.949 U1/comptY[9]_i_8_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.073 r U1/comptY[9]_i_5/O net (fo=1, routed) 0.650 2.723 U1/comptY[9]_i_5_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.847 r U1/comptY[9]_i_1/O net (fo=10, routed) 0.685 3.532 U1/comptY SLICE_X42Y32 FDRE r U1/comptY_reg[3]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 40.000 40.000 r L16 0.000 40.000 r H125MHz (IN) net (fo=0) 0.000 40.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.571 38.739 U1/CLK SLICE_X42Y32 FDRE r U1/comptY_reg[3]/C clock pessimism 0.626 39.365 clock uncertainty -0.147 39.218 SLICE_X42Y32 FDRE (Setup_fdre_C_R) -0.524 38.694 U1/comptY_reg[3] ------------------------------------------------------------------- required time 38.694 arrival time -3.532 ------------------------------------------------------------------- slack 35.162 Slack (MET) : 35.162ns (required time - arrival time) Source: U1/comptY_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[5]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) Data Path Delay: 4.145ns (logic 0.952ns (22.969%) route 3.193ns (77.031%)) Logic Levels: 4 (LUT4=1 LUT6=3) Clock Path Skew: -0.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.261ns = ( 38.739 - 40.000 ) Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.626ns Clock Uncertainty: 0.147ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.286ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.746 -0.613 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y31 FDRE (Prop_fdre_C_Q) 0.456 -0.157 r U1/comptY_reg[7]/Q net (fo=10, routed) 1.014 0.857 U1/comptY_reg__0[7] SLICE_X43Y31 LUT4 (Prop_lut4_I1_O) 0.124 0.981 r U1/vga_vs_OBUF_inst_i_2/O net (fo=3, routed) 0.540 1.521 U1/vga_vs_OBUF_inst_i_2_n_0 SLICE_X42Y31 LUT6 (Prop_lut6_I5_O) 0.124 1.645 r U1/comptY[9]_i_8/O net (fo=1, routed) 0.304 1.949 U1/comptY[9]_i_8_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.073 r U1/comptY[9]_i_5/O net (fo=1, routed) 0.650 2.723 U1/comptY[9]_i_5_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.847 r U1/comptY[9]_i_1/O net (fo=10, routed) 0.685 3.532 U1/comptY SLICE_X42Y32 FDRE r U1/comptY_reg[5]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 40.000 40.000 r L16 0.000 40.000 r H125MHz (IN) net (fo=0) 0.000 40.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.571 38.739 U1/CLK SLICE_X42Y32 FDRE r U1/comptY_reg[5]/C clock pessimism 0.626 39.365 clock uncertainty -0.147 39.218 SLICE_X42Y32 FDRE (Setup_fdre_C_R) -0.524 38.694 U1/comptY_reg[5] ------------------------------------------------------------------- required time 38.694 arrival time -3.532 ------------------------------------------------------------------- slack 35.162 Slack (MET) : 35.294ns (required time - arrival time) Source: U1/comptY_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[4]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) Data Path Delay: 4.011ns (logic 0.952ns (23.735%) route 3.059ns (76.265%)) Logic Levels: 4 (LUT4=1 LUT6=3) Clock Path Skew: -0.024ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.263ns = ( 38.737 - 40.000 ) Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.626ns Clock Uncertainty: 0.147ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.286ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.746 -0.613 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y31 FDRE (Prop_fdre_C_Q) 0.456 -0.157 r U1/comptY_reg[7]/Q net (fo=10, routed) 1.014 0.857 U1/comptY_reg__0[7] SLICE_X43Y31 LUT4 (Prop_lut4_I1_O) 0.124 0.981 r U1/vga_vs_OBUF_inst_i_2/O net (fo=3, routed) 0.540 1.521 U1/vga_vs_OBUF_inst_i_2_n_0 SLICE_X42Y31 LUT6 (Prop_lut6_I5_O) 0.124 1.645 r U1/comptY[9]_i_8/O net (fo=1, routed) 0.304 1.949 U1/comptY[9]_i_8_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.073 r U1/comptY[9]_i_5/O net (fo=1, routed) 0.650 2.723 U1/comptY[9]_i_5_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.847 r U1/comptY[9]_i_1/O net (fo=10, routed) 0.552 3.398 U1/comptY SLICE_X42Y31 FDRE r U1/comptY_reg[4]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 40.000 40.000 r L16 0.000 40.000 r H125MHz (IN) net (fo=0) 0.000 40.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.569 38.737 U1/CLK SLICE_X42Y31 FDRE r U1/comptY_reg[4]/C clock pessimism 0.626 39.363 clock uncertainty -0.147 39.216 SLICE_X42Y31 FDRE (Setup_fdre_C_R) -0.524 38.692 U1/comptY_reg[4] ------------------------------------------------------------------- required time 38.692 arrival time -3.398 ------------------------------------------------------------------- slack 35.294 Slack (MET) : 35.440ns (required time - arrival time) Source: U1/comptY_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[6]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) Data Path Delay: 3.961ns (logic 0.952ns (24.032%) route 3.009ns (75.968%)) Logic Levels: 4 (LUT4=1 LUT6=3) Clock Path Skew: -0.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.263ns = ( 38.737 - 40.000 ) Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.628ns Clock Uncertainty: 0.147ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.286ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.746 -0.613 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y31 FDRE (Prop_fdre_C_Q) 0.456 -0.157 r U1/comptY_reg[7]/Q net (fo=10, routed) 1.014 0.857 U1/comptY_reg__0[7] SLICE_X43Y31 LUT4 (Prop_lut4_I1_O) 0.124 0.981 r U1/vga_vs_OBUF_inst_i_2/O net (fo=3, routed) 0.540 1.521 U1/vga_vs_OBUF_inst_i_2_n_0 SLICE_X42Y31 LUT6 (Prop_lut6_I5_O) 0.124 1.645 r U1/comptY[9]_i_8/O net (fo=1, routed) 0.304 1.949 U1/comptY[9]_i_8_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.073 r U1/comptY[9]_i_5/O net (fo=1, routed) 0.650 2.723 U1/comptY[9]_i_5_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.847 r U1/comptY[9]_i_1/O net (fo=10, routed) 0.502 3.349 U1/comptY SLICE_X41Y31 FDRE r U1/comptY_reg[6]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 40.000 40.000 r L16 0.000 40.000 r H125MHz (IN) net (fo=0) 0.000 40.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.569 38.737 U1/CLK SLICE_X41Y31 FDRE r U1/comptY_reg[6]/C clock pessimism 0.628 39.365 clock uncertainty -0.147 39.218 SLICE_X41Y31 FDRE (Setup_fdre_C_R) -0.429 38.789 U1/comptY_reg[6] ------------------------------------------------------------------- required time 38.789 arrival time -3.349 ------------------------------------------------------------------- slack 35.440 Slack (MET) : 35.458ns (required time - arrival time) Source: U1/comptY_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[7]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) Data Path Delay: 3.966ns (logic 0.952ns (24.006%) route 3.014ns (75.994%)) Logic Levels: 4 (LUT4=1 LUT6=3) Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.263ns = ( 38.737 - 40.000 ) Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.650ns Clock Uncertainty: 0.147ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.286ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.746 -0.613 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y31 FDRE (Prop_fdre_C_Q) 0.456 -0.157 r U1/comptY_reg[7]/Q net (fo=10, routed) 1.014 0.857 U1/comptY_reg__0[7] SLICE_X43Y31 LUT4 (Prop_lut4_I1_O) 0.124 0.981 r U1/vga_vs_OBUF_inst_i_2/O net (fo=3, routed) 0.540 1.521 U1/vga_vs_OBUF_inst_i_2_n_0 SLICE_X42Y31 LUT6 (Prop_lut6_I5_O) 0.124 1.645 r U1/comptY[9]_i_8/O net (fo=1, routed) 0.304 1.949 U1/comptY[9]_i_8_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.073 r U1/comptY[9]_i_5/O net (fo=1, routed) 0.650 2.723 U1/comptY[9]_i_5_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.847 r U1/comptY[9]_i_1/O net (fo=10, routed) 0.506 3.353 U1/comptY SLICE_X40Y31 FDRE r U1/comptY_reg[7]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 40.000 40.000 r L16 0.000 40.000 r H125MHz (IN) net (fo=0) 0.000 40.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.569 38.737 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[7]/C clock pessimism 0.650 39.387 clock uncertainty -0.147 39.240 SLICE_X40Y31 FDRE (Setup_fdre_C_R) -0.429 38.811 U1/comptY_reg[7] ------------------------------------------------------------------- required time 38.811 arrival time -3.353 ------------------------------------------------------------------- slack 35.458 Slack (MET) : 35.458ns (required time - arrival time) Source: U1/comptY_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[8]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) Data Path Delay: 3.966ns (logic 0.952ns (24.006%) route 3.014ns (75.994%)) Logic Levels: 4 (LUT4=1 LUT6=3) Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.263ns = ( 38.737 - 40.000 ) Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.650ns Clock Uncertainty: 0.147ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.286ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.746 -0.613 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y31 FDRE (Prop_fdre_C_Q) 0.456 -0.157 r U1/comptY_reg[7]/Q net (fo=10, routed) 1.014 0.857 U1/comptY_reg__0[7] SLICE_X43Y31 LUT4 (Prop_lut4_I1_O) 0.124 0.981 r U1/vga_vs_OBUF_inst_i_2/O net (fo=3, routed) 0.540 1.521 U1/vga_vs_OBUF_inst_i_2_n_0 SLICE_X42Y31 LUT6 (Prop_lut6_I5_O) 0.124 1.645 r U1/comptY[9]_i_8/O net (fo=1, routed) 0.304 1.949 U1/comptY[9]_i_8_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.073 r U1/comptY[9]_i_5/O net (fo=1, routed) 0.650 2.723 U1/comptY[9]_i_5_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.847 r U1/comptY[9]_i_1/O net (fo=10, routed) 0.506 3.353 U1/comptY SLICE_X40Y31 FDRE r U1/comptY_reg[8]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 40.000 40.000 r L16 0.000 40.000 r H125MHz (IN) net (fo=0) 0.000 40.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.569 38.737 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[8]/C clock pessimism 0.650 39.387 clock uncertainty -0.147 39.240 SLICE_X40Y31 FDRE (Setup_fdre_C_R) -0.429 38.811 U1/comptY_reg[8] ------------------------------------------------------------------- required time 38.811 arrival time -3.353 ------------------------------------------------------------------- slack 35.458 Slack (MET) : 35.458ns (required time - arrival time) Source: U1/comptY_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[9]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) Data Path Delay: 3.966ns (logic 0.952ns (24.006%) route 3.014ns (75.994%)) Logic Levels: 4 (LUT4=1 LUT6=3) Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.263ns = ( 38.737 - 40.000 ) Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.650ns Clock Uncertainty: 0.147ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.286ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.746 -0.613 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y31 FDRE (Prop_fdre_C_Q) 0.456 -0.157 r U1/comptY_reg[7]/Q net (fo=10, routed) 1.014 0.857 U1/comptY_reg__0[7] SLICE_X43Y31 LUT4 (Prop_lut4_I1_O) 0.124 0.981 r U1/vga_vs_OBUF_inst_i_2/O net (fo=3, routed) 0.540 1.521 U1/vga_vs_OBUF_inst_i_2_n_0 SLICE_X42Y31 LUT6 (Prop_lut6_I5_O) 0.124 1.645 r U1/comptY[9]_i_8/O net (fo=1, routed) 0.304 1.949 U1/comptY[9]_i_8_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.073 r U1/comptY[9]_i_5/O net (fo=1, routed) 0.650 2.723 U1/comptY[9]_i_5_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.847 r U1/comptY[9]_i_1/O net (fo=10, routed) 0.506 3.353 U1/comptY SLICE_X40Y31 FDRE r U1/comptY_reg[9]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 40.000 40.000 r L16 0.000 40.000 r H125MHz (IN) net (fo=0) 0.000 40.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.569 38.737 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[9]/C clock pessimism 0.650 39.387 clock uncertainty -0.147 39.240 SLICE_X40Y31 FDRE (Setup_fdre_C_R) -0.429 38.811 U1/comptY_reg[9] ------------------------------------------------------------------- required time 38.811 arrival time -3.353 ------------------------------------------------------------------- slack 35.458 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.223ns (arrival time - required time) Source: U1/comptY_reg[6]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[8]/D (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) Data Path Delay: 0.343ns (logic 0.189ns (55.030%) route 0.154ns (44.970%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.709ns Source Clock Delay (SCD): -0.474ns Clock Pessimism Removal (CPR): -0.248ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.587 -0.474 U1/CLK SLICE_X41Y31 FDRE r U1/comptY_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X41Y31 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptY_reg[6]/Q net (fo=11, routed) 0.154 -0.178 U1/comptY_reg__0[6] SLICE_X40Y31 LUT5 (Prop_lut5_I1_O) 0.048 -0.130 r U1/comptY[8]_i_1/O net (fo=1, routed) 0.000 -0.130 U1/plusOp__0[8] SLICE_X40Y31 FDRE r U1/comptY_reg[8]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.854 -0.709 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[8]/C clock pessimism 0.248 -0.461 SLICE_X40Y31 FDRE (Hold_fdre_C_D) 0.107 -0.354 U1/comptY_reg[8] ------------------------------------------------------------------- required time 0.354 arrival time -0.130 ------------------------------------------------------------------- slack 0.223 Slack (MET) : 0.236ns (arrival time - required time) Source: U1/comptY_reg[6]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[9]/D (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) Data Path Delay: 0.341ns (logic 0.186ns (54.474%) route 0.155ns (45.526%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.709ns Source Clock Delay (SCD): -0.474ns Clock Pessimism Removal (CPR): -0.248ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.587 -0.474 U1/CLK SLICE_X41Y31 FDRE r U1/comptY_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X41Y31 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptY_reg[6]/Q net (fo=11, routed) 0.155 -0.177 U1/comptY_reg__0[6] SLICE_X40Y31 LUT6 (Prop_lut6_I1_O) 0.045 -0.132 r U1/comptY[9]_i_3/O net (fo=1, routed) 0.000 -0.132 U1/plusOp__0[9] SLICE_X40Y31 FDRE r U1/comptY_reg[9]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.854 -0.709 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[9]/C clock pessimism 0.248 -0.461 SLICE_X40Y31 FDRE (Hold_fdre_C_D) 0.092 -0.369 U1/comptY_reg[9] ------------------------------------------------------------------- required time 0.369 arrival time -0.132 ------------------------------------------------------------------- slack 0.236 Slack (MET) : 0.236ns (arrival time - required time) Source: U1/comptY_reg[6]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[7]/D (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) Data Path Delay: 0.340ns (logic 0.186ns (54.634%) route 0.154ns (45.366%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.709ns Source Clock Delay (SCD): -0.474ns Clock Pessimism Removal (CPR): -0.248ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.587 -0.474 U1/CLK SLICE_X41Y31 FDRE r U1/comptY_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X41Y31 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptY_reg[6]/Q net (fo=11, routed) 0.154 -0.178 U1/comptY_reg__0[6] SLICE_X40Y31 LUT4 (Prop_lut4_I2_O) 0.045 -0.133 r U1/comptY[7]_i_1/O net (fo=1, routed) 0.000 -0.133 U1/plusOp__0[7] SLICE_X40Y31 FDRE r U1/comptY_reg[7]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.854 -0.709 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[7]/C clock pessimism 0.248 -0.461 SLICE_X40Y31 FDRE (Hold_fdre_C_D) 0.091 -0.370 U1/comptY_reg[7] ------------------------------------------------------------------- required time 0.370 arrival time -0.133 ------------------------------------------------------------------- slack 0.236 Slack (MET) : 0.251ns (arrival time - required time) Source: U1/comptX_reg[8]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptX_reg[9]/D (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) Data Path Delay: 0.382ns (logic 0.207ns (54.146%) route 0.175ns (45.854%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.714ns Source Clock Delay (SCD): -0.479ns Clock Pessimism Removal (CPR): -0.235ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.582 -0.479 U1/CLK SLICE_X38Y28 FDRE r U1/comptX_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X38Y28 FDRE (Prop_fdre_C_Q) 0.164 -0.315 r U1/comptX_reg[8]/Q net (fo=12, routed) 0.175 -0.140 U1/comptX_reg__0[8] SLICE_X38Y28 LUT5 (Prop_lut5_I0_O) 0.043 -0.097 r U1/comptX[9]_i_1/O net (fo=1, routed) 0.000 -0.097 U1/plusOp[9] SLICE_X38Y28 FDRE r U1/comptX_reg[9]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.849 -0.714 U1/CLK SLICE_X38Y28 FDRE r U1/comptX_reg[9]/C clock pessimism 0.235 -0.479 SLICE_X38Y28 FDRE (Hold_fdre_C_D) 0.131 -0.348 U1/comptX_reg[9] ------------------------------------------------------------------- required time 0.348 arrival time -0.097 ------------------------------------------------------------------- slack 0.251 Slack (MET) : 0.253ns (arrival time - required time) Source: U1/comptY_reg[4]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[5]/D (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) Data Path Delay: 0.389ns (logic 0.209ns (53.754%) route 0.180ns (46.246%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.708ns Source Clock Delay (SCD): -0.474ns Clock Pessimism Removal (CPR): -0.249ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.587 -0.474 U1/CLK SLICE_X42Y31 FDRE r U1/comptY_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X42Y31 FDRE (Prop_fdre_C_Q) 0.164 -0.310 r U1/comptY_reg[4]/Q net (fo=5, routed) 0.180 -0.130 U1/comptY_reg__0[4] SLICE_X42Y32 LUT6 (Prop_lut6_I0_O) 0.045 -0.085 r U1/comptY[5]_i_1/O net (fo=1, routed) 0.000 -0.085 U1/comptY[5]_i_1_n_0 SLICE_X42Y32 FDRE r U1/comptY_reg[5]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.855 -0.708 U1/CLK SLICE_X42Y32 FDRE r U1/comptY_reg[5]/C clock pessimism 0.249 -0.459 SLICE_X42Y32 FDRE (Hold_fdre_C_D) 0.121 -0.338 U1/comptY_reg[5] ------------------------------------------------------------------- required time 0.338 arrival time -0.085 ------------------------------------------------------------------- slack 0.253 Slack (MET) : 0.254ns (arrival time - required time) Source: U1/comptX_reg[3]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptX_reg[5]/D (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) Data Path Delay: 0.381ns (logic 0.186ns (48.823%) route 0.195ns (51.177%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.710ns Source Clock Delay (SCD): -0.477ns Clock Pessimism Removal (CPR): -0.269ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.584 -0.477 U1/CLK SLICE_X39Y30 FDRE r U1/comptX_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X39Y30 FDRE (Prop_fdre_C_Q) 0.141 -0.336 r U1/comptX_reg[3]/Q net (fo=6, routed) 0.195 -0.141 U1/comptX_reg__0[3] SLICE_X40Y30 LUT6 (Prop_lut6_I4_O) 0.045 -0.096 r U1/comptX[5]_i_1/O net (fo=1, routed) 0.000 -0.096 U1/plusOp[5] SLICE_X40Y30 FDRE r U1/comptX_reg[5]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.853 -0.710 U1/CLK SLICE_X40Y30 FDRE r U1/comptX_reg[5]/C clock pessimism 0.269 -0.441 SLICE_X40Y30 FDRE (Hold_fdre_C_D) 0.091 -0.350 U1/comptX_reg[5] ------------------------------------------------------------------- required time 0.350 arrival time -0.096 ------------------------------------------------------------------- slack 0.254 Slack (MET) : 0.256ns (arrival time - required time) Source: U1/comptX_reg[6]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptX_reg[7]/D (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) Data Path Delay: 0.363ns (logic 0.183ns (50.353%) route 0.180ns (49.647%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.714ns Source Clock Delay (SCD): -0.479ns Clock Pessimism Removal (CPR): -0.235ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.582 -0.479 U1/CLK SLICE_X39Y28 FDRE r U1/comptX_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X39Y28 FDRE (Prop_fdre_C_Q) 0.141 -0.338 r U1/comptX_reg[6]/Q net (fo=10, routed) 0.180 -0.157 U1/comptX_reg__0[6] SLICE_X39Y28 LUT3 (Prop_lut3_I0_O) 0.042 -0.115 r U1/comptX[7]_i_1/O net (fo=1, routed) 0.000 -0.115 U1/plusOp[7] SLICE_X39Y28 FDRE r U1/comptX_reg[7]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.849 -0.714 U1/CLK SLICE_X39Y28 FDRE r U1/comptX_reg[7]/C clock pessimism 0.235 -0.479 SLICE_X39Y28 FDRE (Hold_fdre_C_D) 0.107 -0.372 U1/comptX_reg[7] ------------------------------------------------------------------- required time 0.372 arrival time -0.115 ------------------------------------------------------------------- slack 0.256 Slack (MET) : 0.259ns (arrival time - required time) Source: U1/comptY_reg[4]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[4]/D (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) Data Path Delay: 0.382ns (logic 0.207ns (54.146%) route 0.175ns (45.854%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.709ns Source Clock Delay (SCD): -0.474ns Clock Pessimism Removal (CPR): -0.235ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.587 -0.474 U1/CLK SLICE_X42Y31 FDRE r U1/comptY_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X42Y31 FDRE (Prop_fdre_C_Q) 0.164 -0.310 r U1/comptY_reg[4]/Q net (fo=5, routed) 0.175 -0.135 U1/comptY_reg__0[4] SLICE_X42Y31 LUT5 (Prop_lut5_I4_O) 0.043 -0.092 r U1/comptY[4]_i_1/O net (fo=2, routed) 0.000 -0.092 U1/comptY[4]_i_1_n_0 SLICE_X42Y31 FDRE r U1/comptY_reg[4]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.854 -0.709 U1/CLK SLICE_X42Y31 FDRE r U1/comptY_reg[4]/C clock pessimism 0.235 -0.474 SLICE_X42Y31 FDRE (Hold_fdre_C_D) 0.123 -0.351 U1/comptY_reg[4] ------------------------------------------------------------------- required time 0.351 arrival time -0.092 ------------------------------------------------------------------- slack 0.259 Slack (MET) : 0.264ns (arrival time - required time) Source: U1/comptX_reg[8]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptX_reg[8]/D (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) Data Path Delay: 0.384ns (logic 0.209ns (54.384%) route 0.175ns (45.616%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.714ns Source Clock Delay (SCD): -0.479ns Clock Pessimism Removal (CPR): -0.235ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.582 -0.479 U1/CLK SLICE_X38Y28 FDRE r U1/comptX_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X38Y28 FDRE (Prop_fdre_C_Q) 0.164 -0.315 r U1/comptX_reg[8]/Q net (fo=12, routed) 0.175 -0.140 U1/comptX_reg__0[8] SLICE_X38Y28 LUT4 (Prop_lut4_I3_O) 0.045 -0.095 r U1/comptX[8]_i_1/O net (fo=1, routed) 0.000 -0.095 U1/plusOp[8] SLICE_X38Y28 FDRE r U1/comptX_reg[8]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.849 -0.714 U1/CLK SLICE_X38Y28 FDRE r U1/comptX_reg[8]/C clock pessimism 0.235 -0.479 SLICE_X38Y28 FDRE (Hold_fdre_C_D) 0.120 -0.359 U1/comptX_reg[8] ------------------------------------------------------------------- required time 0.359 arrival time -0.095 ------------------------------------------------------------------- slack 0.264 Slack (MET) : 0.267ns (arrival time - required time) Source: U1/comptX_reg[1]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptX_reg[2]/D (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) Data Path Delay: 0.374ns (logic 0.183ns (48.868%) route 0.191ns (51.132%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.712ns Source Clock Delay (SCD): -0.477ns Clock Pessimism Removal (CPR): -0.235ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.584 -0.477 U1/CLK SLICE_X39Y30 FDRE r U1/comptX_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X39Y30 FDRE (Prop_fdre_C_Q) 0.141 -0.336 r U1/comptX_reg[1]/Q net (fo=8, routed) 0.191 -0.144 U1/comptX_reg__0[1] SLICE_X39Y30 LUT3 (Prop_lut3_I0_O) 0.042 -0.102 r U1/comptX[2]_i_1/O net (fo=1, routed) 0.000 -0.102 U1/plusOp[2] SLICE_X39Y30 FDRE r U1/comptX_reg[2]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.851 -0.712 U1/CLK SLICE_X39Y30 FDRE r U1/comptX_reg[2]/C clock pessimism 0.235 -0.477 SLICE_X39Y30 FDRE (Hold_fdre_C_D) 0.107 -0.370 U1/comptX_reg[2] ------------------------------------------------------------------- required time 0.370 arrival time -0.102 ------------------------------------------------------------------- slack 0.267 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk_out1_clk_wiz_1_1 Waveform(ns): { 0.000 20.000 } Period(ns): 40.000 Sources: { U0/inst/mmcm_adv_inst/CLKOUT0 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFG/I n/a 2.155 40.000 37.845 BUFGCTRL_X0Y16 U0/inst/clkout1_buf/I Min Period n/a MMCME2_ADV/CLKOUT0 n/a 1.249 40.000 38.751 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKOUT0 Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X39Y30 U1/comptX_reg[0]/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X40Y29 U1/comptX_reg[10]/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X39Y30 U1/comptX_reg[1]/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X39Y30 U1/comptX_reg[2]/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X39Y30 U1/comptX_reg[3]/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X39Y30 U1/comptX_reg[4]/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X40Y30 U1/comptX_reg[5]/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X39Y28 U1/comptX_reg[6]/C Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 40.000 173.360 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKOUT0 Low Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X39Y30 U1/comptX_reg[0]/C Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X39Y30 U1/comptX_reg[0]/C Low Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X39Y30 U1/comptX_reg[1]/C Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X39Y30 U1/comptX_reg[1]/C Low Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X39Y30 U1/comptX_reg[2]/C Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X39Y30 U1/comptX_reg[2]/C Low Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X39Y30 U1/comptX_reg[3]/C Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X39Y30 U1/comptX_reg[3]/C Low Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X39Y30 U1/comptX_reg[4]/C Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X39Y30 U1/comptX_reg[4]/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X39Y30 U1/comptX_reg[0]/C High Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X39Y30 U1/comptX_reg[0]/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X40Y29 U1/comptX_reg[10]/C High Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X40Y29 U1/comptX_reg[10]/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X39Y30 U1/comptX_reg[1]/C High Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X39Y30 U1/comptX_reg[1]/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X39Y30 U1/comptX_reg[2]/C High Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X39Y30 U1/comptX_reg[2]/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X39Y30 U1/comptX_reg[3]/C High Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X39Y30 U1/comptX_reg[3]/C --------------------------------------------------------------------------------------------------- From Clock: clkfbout_clk_wiz_1_1 To Clock: clkfbout_clk_wiz_1_1 Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 37.845ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clkfbout_clk_wiz_1_1 Waveform(ns): { 0.000 20.000 } Period(ns): 40.000 Sources: { U0/inst/mmcm_adv_inst/CLKFBOUT } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFG/I n/a 2.155 40.000 37.845 BUFGCTRL_X0Y17 U0/inst/clkf_buf/I Min Period n/a MMCME2_ADV/CLKFBOUT n/a 1.249 40.000 38.751 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKFBOUT Min Period n/a MMCME2_ADV/CLKFBIN n/a 1.249 40.000 38.751 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKFBIN Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 40.000 60.000 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKFBIN Max Period n/a MMCME2_ADV/CLKFBOUT n/a 213.360 40.000 173.360 MMCME2_ADV_X0Y1 U0/inst/mmcm_adv_inst/CLKFBOUT --------------------------------------------------------------------------------------------------- From Clock: clk_out1_clk_wiz_1_1 To Clock: clk_out1_clk_wiz_1 Setup : 0 Failing Endpoints, Worst Slack 35.149ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.063ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 35.149ns (required time - arrival time) Source: U1/comptY_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[0]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) Data Path Delay: 4.145ns (logic 0.952ns (22.969%) route 3.193ns (77.031%)) Logic Levels: 4 (LUT4=1 LUT6=3) Clock Path Skew: -0.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.261ns = ( 38.739 - 40.000 ) Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.626ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.746 -0.613 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y31 FDRE (Prop_fdre_C_Q) 0.456 -0.157 r U1/comptY_reg[7]/Q net (fo=10, routed) 1.014 0.857 U1/comptY_reg__0[7] SLICE_X43Y31 LUT4 (Prop_lut4_I1_O) 0.124 0.981 r U1/vga_vs_OBUF_inst_i_2/O net (fo=3, routed) 0.540 1.521 U1/vga_vs_OBUF_inst_i_2_n_0 SLICE_X42Y31 LUT6 (Prop_lut6_I5_O) 0.124 1.645 r U1/comptY[9]_i_8/O net (fo=1, routed) 0.304 1.949 U1/comptY[9]_i_8_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.073 r U1/comptY[9]_i_5/O net (fo=1, routed) 0.650 2.723 U1/comptY[9]_i_5_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.847 r U1/comptY[9]_i_1/O net (fo=10, routed) 0.685 3.532 U1/comptY SLICE_X42Y32 FDRE r U1/comptY_reg[0]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r L16 0.000 40.000 r H125MHz (IN) net (fo=0) 0.000 40.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.571 38.739 U1/CLK SLICE_X42Y32 FDRE r U1/comptY_reg[0]/C clock pessimism 0.626 39.365 clock uncertainty -0.160 39.205 SLICE_X42Y32 FDRE (Setup_fdre_C_R) -0.524 38.681 U1/comptY_reg[0] ------------------------------------------------------------------- required time 38.681 arrival time -3.532 ------------------------------------------------------------------- slack 35.149 Slack (MET) : 35.149ns (required time - arrival time) Source: U1/comptY_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[1]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) Data Path Delay: 4.145ns (logic 0.952ns (22.969%) route 3.193ns (77.031%)) Logic Levels: 4 (LUT4=1 LUT6=3) Clock Path Skew: -0.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.261ns = ( 38.739 - 40.000 ) Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.626ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.746 -0.613 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y31 FDRE (Prop_fdre_C_Q) 0.456 -0.157 r U1/comptY_reg[7]/Q net (fo=10, routed) 1.014 0.857 U1/comptY_reg__0[7] SLICE_X43Y31 LUT4 (Prop_lut4_I1_O) 0.124 0.981 r U1/vga_vs_OBUF_inst_i_2/O net (fo=3, routed) 0.540 1.521 U1/vga_vs_OBUF_inst_i_2_n_0 SLICE_X42Y31 LUT6 (Prop_lut6_I5_O) 0.124 1.645 r U1/comptY[9]_i_8/O net (fo=1, routed) 0.304 1.949 U1/comptY[9]_i_8_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.073 r U1/comptY[9]_i_5/O net (fo=1, routed) 0.650 2.723 U1/comptY[9]_i_5_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.847 r U1/comptY[9]_i_1/O net (fo=10, routed) 0.685 3.532 U1/comptY SLICE_X42Y32 FDRE r U1/comptY_reg[1]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r L16 0.000 40.000 r H125MHz (IN) net (fo=0) 0.000 40.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.571 38.739 U1/CLK SLICE_X42Y32 FDRE r U1/comptY_reg[1]/C clock pessimism 0.626 39.365 clock uncertainty -0.160 39.205 SLICE_X42Y32 FDRE (Setup_fdre_C_R) -0.524 38.681 U1/comptY_reg[1] ------------------------------------------------------------------- required time 38.681 arrival time -3.532 ------------------------------------------------------------------- slack 35.149 Slack (MET) : 35.149ns (required time - arrival time) Source: U1/comptY_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[2]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) Data Path Delay: 4.145ns (logic 0.952ns (22.969%) route 3.193ns (77.031%)) Logic Levels: 4 (LUT4=1 LUT6=3) Clock Path Skew: -0.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.261ns = ( 38.739 - 40.000 ) Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.626ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.746 -0.613 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y31 FDRE (Prop_fdre_C_Q) 0.456 -0.157 r U1/comptY_reg[7]/Q net (fo=10, routed) 1.014 0.857 U1/comptY_reg__0[7] SLICE_X43Y31 LUT4 (Prop_lut4_I1_O) 0.124 0.981 r U1/vga_vs_OBUF_inst_i_2/O net (fo=3, routed) 0.540 1.521 U1/vga_vs_OBUF_inst_i_2_n_0 SLICE_X42Y31 LUT6 (Prop_lut6_I5_O) 0.124 1.645 r U1/comptY[9]_i_8/O net (fo=1, routed) 0.304 1.949 U1/comptY[9]_i_8_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.073 r U1/comptY[9]_i_5/O net (fo=1, routed) 0.650 2.723 U1/comptY[9]_i_5_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.847 r U1/comptY[9]_i_1/O net (fo=10, routed) 0.685 3.532 U1/comptY SLICE_X42Y32 FDRE r U1/comptY_reg[2]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r L16 0.000 40.000 r H125MHz (IN) net (fo=0) 0.000 40.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.571 38.739 U1/CLK SLICE_X42Y32 FDRE r U1/comptY_reg[2]/C clock pessimism 0.626 39.365 clock uncertainty -0.160 39.205 SLICE_X42Y32 FDRE (Setup_fdre_C_R) -0.524 38.681 U1/comptY_reg[2] ------------------------------------------------------------------- required time 38.681 arrival time -3.532 ------------------------------------------------------------------- slack 35.149 Slack (MET) : 35.149ns (required time - arrival time) Source: U1/comptY_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[3]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) Data Path Delay: 4.145ns (logic 0.952ns (22.969%) route 3.193ns (77.031%)) Logic Levels: 4 (LUT4=1 LUT6=3) Clock Path Skew: -0.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.261ns = ( 38.739 - 40.000 ) Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.626ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.746 -0.613 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y31 FDRE (Prop_fdre_C_Q) 0.456 -0.157 r U1/comptY_reg[7]/Q net (fo=10, routed) 1.014 0.857 U1/comptY_reg__0[7] SLICE_X43Y31 LUT4 (Prop_lut4_I1_O) 0.124 0.981 r U1/vga_vs_OBUF_inst_i_2/O net (fo=3, routed) 0.540 1.521 U1/vga_vs_OBUF_inst_i_2_n_0 SLICE_X42Y31 LUT6 (Prop_lut6_I5_O) 0.124 1.645 r U1/comptY[9]_i_8/O net (fo=1, routed) 0.304 1.949 U1/comptY[9]_i_8_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.073 r U1/comptY[9]_i_5/O net (fo=1, routed) 0.650 2.723 U1/comptY[9]_i_5_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.847 r U1/comptY[9]_i_1/O net (fo=10, routed) 0.685 3.532 U1/comptY SLICE_X42Y32 FDRE r U1/comptY_reg[3]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r L16 0.000 40.000 r H125MHz (IN) net (fo=0) 0.000 40.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.571 38.739 U1/CLK SLICE_X42Y32 FDRE r U1/comptY_reg[3]/C clock pessimism 0.626 39.365 clock uncertainty -0.160 39.205 SLICE_X42Y32 FDRE (Setup_fdre_C_R) -0.524 38.681 U1/comptY_reg[3] ------------------------------------------------------------------- required time 38.681 arrival time -3.532 ------------------------------------------------------------------- slack 35.149 Slack (MET) : 35.149ns (required time - arrival time) Source: U1/comptY_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[5]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) Data Path Delay: 4.145ns (logic 0.952ns (22.969%) route 3.193ns (77.031%)) Logic Levels: 4 (LUT4=1 LUT6=3) Clock Path Skew: -0.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.261ns = ( 38.739 - 40.000 ) Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.626ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.746 -0.613 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y31 FDRE (Prop_fdre_C_Q) 0.456 -0.157 r U1/comptY_reg[7]/Q net (fo=10, routed) 1.014 0.857 U1/comptY_reg__0[7] SLICE_X43Y31 LUT4 (Prop_lut4_I1_O) 0.124 0.981 r U1/vga_vs_OBUF_inst_i_2/O net (fo=3, routed) 0.540 1.521 U1/vga_vs_OBUF_inst_i_2_n_0 SLICE_X42Y31 LUT6 (Prop_lut6_I5_O) 0.124 1.645 r U1/comptY[9]_i_8/O net (fo=1, routed) 0.304 1.949 U1/comptY[9]_i_8_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.073 r U1/comptY[9]_i_5/O net (fo=1, routed) 0.650 2.723 U1/comptY[9]_i_5_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.847 r U1/comptY[9]_i_1/O net (fo=10, routed) 0.685 3.532 U1/comptY SLICE_X42Y32 FDRE r U1/comptY_reg[5]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r L16 0.000 40.000 r H125MHz (IN) net (fo=0) 0.000 40.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.571 38.739 U1/CLK SLICE_X42Y32 FDRE r U1/comptY_reg[5]/C clock pessimism 0.626 39.365 clock uncertainty -0.160 39.205 SLICE_X42Y32 FDRE (Setup_fdre_C_R) -0.524 38.681 U1/comptY_reg[5] ------------------------------------------------------------------- required time 38.681 arrival time -3.532 ------------------------------------------------------------------- slack 35.149 Slack (MET) : 35.281ns (required time - arrival time) Source: U1/comptY_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[4]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) Data Path Delay: 4.011ns (logic 0.952ns (23.735%) route 3.059ns (76.265%)) Logic Levels: 4 (LUT4=1 LUT6=3) Clock Path Skew: -0.024ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.263ns = ( 38.737 - 40.000 ) Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.626ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.746 -0.613 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y31 FDRE (Prop_fdre_C_Q) 0.456 -0.157 r U1/comptY_reg[7]/Q net (fo=10, routed) 1.014 0.857 U1/comptY_reg__0[7] SLICE_X43Y31 LUT4 (Prop_lut4_I1_O) 0.124 0.981 r U1/vga_vs_OBUF_inst_i_2/O net (fo=3, routed) 0.540 1.521 U1/vga_vs_OBUF_inst_i_2_n_0 SLICE_X42Y31 LUT6 (Prop_lut6_I5_O) 0.124 1.645 r U1/comptY[9]_i_8/O net (fo=1, routed) 0.304 1.949 U1/comptY[9]_i_8_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.073 r U1/comptY[9]_i_5/O net (fo=1, routed) 0.650 2.723 U1/comptY[9]_i_5_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.847 r U1/comptY[9]_i_1/O net (fo=10, routed) 0.552 3.398 U1/comptY SLICE_X42Y31 FDRE r U1/comptY_reg[4]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r L16 0.000 40.000 r H125MHz (IN) net (fo=0) 0.000 40.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.569 38.737 U1/CLK SLICE_X42Y31 FDRE r U1/comptY_reg[4]/C clock pessimism 0.626 39.363 clock uncertainty -0.160 39.203 SLICE_X42Y31 FDRE (Setup_fdre_C_R) -0.524 38.679 U1/comptY_reg[4] ------------------------------------------------------------------- required time 38.679 arrival time -3.398 ------------------------------------------------------------------- slack 35.281 Slack (MET) : 35.427ns (required time - arrival time) Source: U1/comptY_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[6]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) Data Path Delay: 3.961ns (logic 0.952ns (24.032%) route 3.009ns (75.968%)) Logic Levels: 4 (LUT4=1 LUT6=3) Clock Path Skew: -0.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.263ns = ( 38.737 - 40.000 ) Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.628ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.746 -0.613 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y31 FDRE (Prop_fdre_C_Q) 0.456 -0.157 r U1/comptY_reg[7]/Q net (fo=10, routed) 1.014 0.857 U1/comptY_reg__0[7] SLICE_X43Y31 LUT4 (Prop_lut4_I1_O) 0.124 0.981 r U1/vga_vs_OBUF_inst_i_2/O net (fo=3, routed) 0.540 1.521 U1/vga_vs_OBUF_inst_i_2_n_0 SLICE_X42Y31 LUT6 (Prop_lut6_I5_O) 0.124 1.645 r U1/comptY[9]_i_8/O net (fo=1, routed) 0.304 1.949 U1/comptY[9]_i_8_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.073 r U1/comptY[9]_i_5/O net (fo=1, routed) 0.650 2.723 U1/comptY[9]_i_5_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.847 r U1/comptY[9]_i_1/O net (fo=10, routed) 0.502 3.349 U1/comptY SLICE_X41Y31 FDRE r U1/comptY_reg[6]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r L16 0.000 40.000 r H125MHz (IN) net (fo=0) 0.000 40.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.569 38.737 U1/CLK SLICE_X41Y31 FDRE r U1/comptY_reg[6]/C clock pessimism 0.628 39.365 clock uncertainty -0.160 39.205 SLICE_X41Y31 FDRE (Setup_fdre_C_R) -0.429 38.776 U1/comptY_reg[6] ------------------------------------------------------------------- required time 38.776 arrival time -3.349 ------------------------------------------------------------------- slack 35.427 Slack (MET) : 35.445ns (required time - arrival time) Source: U1/comptY_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[7]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) Data Path Delay: 3.966ns (logic 0.952ns (24.006%) route 3.014ns (75.994%)) Logic Levels: 4 (LUT4=1 LUT6=3) Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.263ns = ( 38.737 - 40.000 ) Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.650ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.746 -0.613 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y31 FDRE (Prop_fdre_C_Q) 0.456 -0.157 r U1/comptY_reg[7]/Q net (fo=10, routed) 1.014 0.857 U1/comptY_reg__0[7] SLICE_X43Y31 LUT4 (Prop_lut4_I1_O) 0.124 0.981 r U1/vga_vs_OBUF_inst_i_2/O net (fo=3, routed) 0.540 1.521 U1/vga_vs_OBUF_inst_i_2_n_0 SLICE_X42Y31 LUT6 (Prop_lut6_I5_O) 0.124 1.645 r U1/comptY[9]_i_8/O net (fo=1, routed) 0.304 1.949 U1/comptY[9]_i_8_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.073 r U1/comptY[9]_i_5/O net (fo=1, routed) 0.650 2.723 U1/comptY[9]_i_5_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.847 r U1/comptY[9]_i_1/O net (fo=10, routed) 0.506 3.353 U1/comptY SLICE_X40Y31 FDRE r U1/comptY_reg[7]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r L16 0.000 40.000 r H125MHz (IN) net (fo=0) 0.000 40.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.569 38.737 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[7]/C clock pessimism 0.650 39.387 clock uncertainty -0.160 39.227 SLICE_X40Y31 FDRE (Setup_fdre_C_R) -0.429 38.798 U1/comptY_reg[7] ------------------------------------------------------------------- required time 38.798 arrival time -3.353 ------------------------------------------------------------------- slack 35.445 Slack (MET) : 35.445ns (required time - arrival time) Source: U1/comptY_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[8]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) Data Path Delay: 3.966ns (logic 0.952ns (24.006%) route 3.014ns (75.994%)) Logic Levels: 4 (LUT4=1 LUT6=3) Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.263ns = ( 38.737 - 40.000 ) Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.650ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.746 -0.613 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y31 FDRE (Prop_fdre_C_Q) 0.456 -0.157 r U1/comptY_reg[7]/Q net (fo=10, routed) 1.014 0.857 U1/comptY_reg__0[7] SLICE_X43Y31 LUT4 (Prop_lut4_I1_O) 0.124 0.981 r U1/vga_vs_OBUF_inst_i_2/O net (fo=3, routed) 0.540 1.521 U1/vga_vs_OBUF_inst_i_2_n_0 SLICE_X42Y31 LUT6 (Prop_lut6_I5_O) 0.124 1.645 r U1/comptY[9]_i_8/O net (fo=1, routed) 0.304 1.949 U1/comptY[9]_i_8_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.073 r U1/comptY[9]_i_5/O net (fo=1, routed) 0.650 2.723 U1/comptY[9]_i_5_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.847 r U1/comptY[9]_i_1/O net (fo=10, routed) 0.506 3.353 U1/comptY SLICE_X40Y31 FDRE r U1/comptY_reg[8]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r L16 0.000 40.000 r H125MHz (IN) net (fo=0) 0.000 40.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.569 38.737 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[8]/C clock pessimism 0.650 39.387 clock uncertainty -0.160 39.227 SLICE_X40Y31 FDRE (Setup_fdre_C_R) -0.429 38.798 U1/comptY_reg[8] ------------------------------------------------------------------- required time 38.798 arrival time -3.353 ------------------------------------------------------------------- slack 35.445 Slack (MET) : 35.445ns (required time - arrival time) Source: U1/comptY_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[9]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) Data Path Delay: 3.966ns (logic 0.952ns (24.006%) route 3.014ns (75.994%)) Logic Levels: 4 (LUT4=1 LUT6=3) Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.263ns = ( 38.737 - 40.000 ) Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.650ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.746 -0.613 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y31 FDRE (Prop_fdre_C_Q) 0.456 -0.157 r U1/comptY_reg[7]/Q net (fo=10, routed) 1.014 0.857 U1/comptY_reg__0[7] SLICE_X43Y31 LUT4 (Prop_lut4_I1_O) 0.124 0.981 r U1/vga_vs_OBUF_inst_i_2/O net (fo=3, routed) 0.540 1.521 U1/vga_vs_OBUF_inst_i_2_n_0 SLICE_X42Y31 LUT6 (Prop_lut6_I5_O) 0.124 1.645 r U1/comptY[9]_i_8/O net (fo=1, routed) 0.304 1.949 U1/comptY[9]_i_8_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.073 r U1/comptY[9]_i_5/O net (fo=1, routed) 0.650 2.723 U1/comptY[9]_i_5_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.847 r U1/comptY[9]_i_1/O net (fo=10, routed) 0.506 3.353 U1/comptY SLICE_X40Y31 FDRE r U1/comptY_reg[9]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r L16 0.000 40.000 r H125MHz (IN) net (fo=0) 0.000 40.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.569 38.737 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[9]/C clock pessimism 0.650 39.387 clock uncertainty -0.160 39.227 SLICE_X40Y31 FDRE (Setup_fdre_C_R) -0.429 38.798 U1/comptY_reg[9] ------------------------------------------------------------------- required time 38.798 arrival time -3.353 ------------------------------------------------------------------- slack 35.445 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.063ns (arrival time - required time) Source: U1/comptY_reg[6]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[8]/D (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) Data Path Delay: 0.343ns (logic 0.189ns (55.030%) route 0.154ns (44.970%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.709ns Source Clock Delay (SCD): -0.474ns Clock Pessimism Removal (CPR): -0.248ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.587 -0.474 U1/CLK SLICE_X41Y31 FDRE r U1/comptY_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X41Y31 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptY_reg[6]/Q net (fo=11, routed) 0.154 -0.178 U1/comptY_reg__0[6] SLICE_X40Y31 LUT5 (Prop_lut5_I1_O) 0.048 -0.130 r U1/comptY[8]_i_1/O net (fo=1, routed) 0.000 -0.130 U1/plusOp__0[8] SLICE_X40Y31 FDRE r U1/comptY_reg[8]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.854 -0.709 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[8]/C clock pessimism 0.248 -0.461 clock uncertainty 0.160 -0.301 SLICE_X40Y31 FDRE (Hold_fdre_C_D) 0.107 -0.194 U1/comptY_reg[8] ------------------------------------------------------------------- required time 0.194 arrival time -0.130 ------------------------------------------------------------------- slack 0.063 Slack (MET) : 0.076ns (arrival time - required time) Source: U1/comptY_reg[6]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[9]/D (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) Data Path Delay: 0.341ns (logic 0.186ns (54.474%) route 0.155ns (45.526%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.709ns Source Clock Delay (SCD): -0.474ns Clock Pessimism Removal (CPR): -0.248ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.587 -0.474 U1/CLK SLICE_X41Y31 FDRE r U1/comptY_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X41Y31 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptY_reg[6]/Q net (fo=11, routed) 0.155 -0.177 U1/comptY_reg__0[6] SLICE_X40Y31 LUT6 (Prop_lut6_I1_O) 0.045 -0.132 r U1/comptY[9]_i_3/O net (fo=1, routed) 0.000 -0.132 U1/plusOp__0[9] SLICE_X40Y31 FDRE r U1/comptY_reg[9]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.854 -0.709 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[9]/C clock pessimism 0.248 -0.461 clock uncertainty 0.160 -0.301 SLICE_X40Y31 FDRE (Hold_fdre_C_D) 0.092 -0.209 U1/comptY_reg[9] ------------------------------------------------------------------- required time 0.209 arrival time -0.132 ------------------------------------------------------------------- slack 0.076 Slack (MET) : 0.076ns (arrival time - required time) Source: U1/comptY_reg[6]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[7]/D (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) Data Path Delay: 0.340ns (logic 0.186ns (54.634%) route 0.154ns (45.366%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.709ns Source Clock Delay (SCD): -0.474ns Clock Pessimism Removal (CPR): -0.248ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.587 -0.474 U1/CLK SLICE_X41Y31 FDRE r U1/comptY_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X41Y31 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptY_reg[6]/Q net (fo=11, routed) 0.154 -0.178 U1/comptY_reg__0[6] SLICE_X40Y31 LUT4 (Prop_lut4_I2_O) 0.045 -0.133 r U1/comptY[7]_i_1/O net (fo=1, routed) 0.000 -0.133 U1/plusOp__0[7] SLICE_X40Y31 FDRE r U1/comptY_reg[7]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.854 -0.709 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[7]/C clock pessimism 0.248 -0.461 clock uncertainty 0.160 -0.301 SLICE_X40Y31 FDRE (Hold_fdre_C_D) 0.091 -0.210 U1/comptY_reg[7] ------------------------------------------------------------------- required time 0.210 arrival time -0.133 ------------------------------------------------------------------- slack 0.076 Slack (MET) : 0.091ns (arrival time - required time) Source: U1/comptX_reg[8]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptX_reg[9]/D (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) Data Path Delay: 0.382ns (logic 0.207ns (54.146%) route 0.175ns (45.854%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.714ns Source Clock Delay (SCD): -0.479ns Clock Pessimism Removal (CPR): -0.235ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.582 -0.479 U1/CLK SLICE_X38Y28 FDRE r U1/comptX_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X38Y28 FDRE (Prop_fdre_C_Q) 0.164 -0.315 r U1/comptX_reg[8]/Q net (fo=12, routed) 0.175 -0.140 U1/comptX_reg__0[8] SLICE_X38Y28 LUT5 (Prop_lut5_I0_O) 0.043 -0.097 r U1/comptX[9]_i_1/O net (fo=1, routed) 0.000 -0.097 U1/plusOp[9] SLICE_X38Y28 FDRE r U1/comptX_reg[9]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.849 -0.714 U1/CLK SLICE_X38Y28 FDRE r U1/comptX_reg[9]/C clock pessimism 0.235 -0.479 clock uncertainty 0.160 -0.319 SLICE_X38Y28 FDRE (Hold_fdre_C_D) 0.131 -0.188 U1/comptX_reg[9] ------------------------------------------------------------------- required time 0.188 arrival time -0.097 ------------------------------------------------------------------- slack 0.091 Slack (MET) : 0.093ns (arrival time - required time) Source: U1/comptY_reg[4]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[5]/D (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) Data Path Delay: 0.389ns (logic 0.209ns (53.754%) route 0.180ns (46.246%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.708ns Source Clock Delay (SCD): -0.474ns Clock Pessimism Removal (CPR): -0.249ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.587 -0.474 U1/CLK SLICE_X42Y31 FDRE r U1/comptY_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X42Y31 FDRE (Prop_fdre_C_Q) 0.164 -0.310 r U1/comptY_reg[4]/Q net (fo=5, routed) 0.180 -0.130 U1/comptY_reg__0[4] SLICE_X42Y32 LUT6 (Prop_lut6_I0_O) 0.045 -0.085 r U1/comptY[5]_i_1/O net (fo=1, routed) 0.000 -0.085 U1/comptY[5]_i_1_n_0 SLICE_X42Y32 FDRE r U1/comptY_reg[5]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.855 -0.708 U1/CLK SLICE_X42Y32 FDRE r U1/comptY_reg[5]/C clock pessimism 0.249 -0.459 clock uncertainty 0.160 -0.299 SLICE_X42Y32 FDRE (Hold_fdre_C_D) 0.121 -0.178 U1/comptY_reg[5] ------------------------------------------------------------------- required time 0.178 arrival time -0.085 ------------------------------------------------------------------- slack 0.093 Slack (MET) : 0.094ns (arrival time - required time) Source: U1/comptX_reg[3]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptX_reg[5]/D (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) Data Path Delay: 0.381ns (logic 0.186ns (48.823%) route 0.195ns (51.177%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.710ns Source Clock Delay (SCD): -0.477ns Clock Pessimism Removal (CPR): -0.269ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.584 -0.477 U1/CLK SLICE_X39Y30 FDRE r U1/comptX_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X39Y30 FDRE (Prop_fdre_C_Q) 0.141 -0.336 r U1/comptX_reg[3]/Q net (fo=6, routed) 0.195 -0.141 U1/comptX_reg__0[3] SLICE_X40Y30 LUT6 (Prop_lut6_I4_O) 0.045 -0.096 r U1/comptX[5]_i_1/O net (fo=1, routed) 0.000 -0.096 U1/plusOp[5] SLICE_X40Y30 FDRE r U1/comptX_reg[5]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.853 -0.710 U1/CLK SLICE_X40Y30 FDRE r U1/comptX_reg[5]/C clock pessimism 0.269 -0.441 clock uncertainty 0.160 -0.281 SLICE_X40Y30 FDRE (Hold_fdre_C_D) 0.091 -0.190 U1/comptX_reg[5] ------------------------------------------------------------------- required time 0.190 arrival time -0.096 ------------------------------------------------------------------- slack 0.094 Slack (MET) : 0.096ns (arrival time - required time) Source: U1/comptX_reg[6]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptX_reg[7]/D (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) Data Path Delay: 0.363ns (logic 0.183ns (50.353%) route 0.180ns (49.647%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.714ns Source Clock Delay (SCD): -0.479ns Clock Pessimism Removal (CPR): -0.235ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.582 -0.479 U1/CLK SLICE_X39Y28 FDRE r U1/comptX_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X39Y28 FDRE (Prop_fdre_C_Q) 0.141 -0.338 r U1/comptX_reg[6]/Q net (fo=10, routed) 0.180 -0.157 U1/comptX_reg__0[6] SLICE_X39Y28 LUT3 (Prop_lut3_I0_O) 0.042 -0.115 r U1/comptX[7]_i_1/O net (fo=1, routed) 0.000 -0.115 U1/plusOp[7] SLICE_X39Y28 FDRE r U1/comptX_reg[7]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.849 -0.714 U1/CLK SLICE_X39Y28 FDRE r U1/comptX_reg[7]/C clock pessimism 0.235 -0.479 clock uncertainty 0.160 -0.319 SLICE_X39Y28 FDRE (Hold_fdre_C_D) 0.107 -0.212 U1/comptX_reg[7] ------------------------------------------------------------------- required time 0.212 arrival time -0.115 ------------------------------------------------------------------- slack 0.096 Slack (MET) : 0.099ns (arrival time - required time) Source: U1/comptY_reg[4]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[4]/D (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) Data Path Delay: 0.382ns (logic 0.207ns (54.146%) route 0.175ns (45.854%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.709ns Source Clock Delay (SCD): -0.474ns Clock Pessimism Removal (CPR): -0.235ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.587 -0.474 U1/CLK SLICE_X42Y31 FDRE r U1/comptY_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X42Y31 FDRE (Prop_fdre_C_Q) 0.164 -0.310 r U1/comptY_reg[4]/Q net (fo=5, routed) 0.175 -0.135 U1/comptY_reg__0[4] SLICE_X42Y31 LUT5 (Prop_lut5_I4_O) 0.043 -0.092 r U1/comptY[4]_i_1/O net (fo=2, routed) 0.000 -0.092 U1/comptY[4]_i_1_n_0 SLICE_X42Y31 FDRE r U1/comptY_reg[4]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.854 -0.709 U1/CLK SLICE_X42Y31 FDRE r U1/comptY_reg[4]/C clock pessimism 0.235 -0.474 clock uncertainty 0.160 -0.314 SLICE_X42Y31 FDRE (Hold_fdre_C_D) 0.123 -0.191 U1/comptY_reg[4] ------------------------------------------------------------------- required time 0.191 arrival time -0.092 ------------------------------------------------------------------- slack 0.099 Slack (MET) : 0.104ns (arrival time - required time) Source: U1/comptX_reg[8]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptX_reg[8]/D (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) Data Path Delay: 0.384ns (logic 0.209ns (54.384%) route 0.175ns (45.616%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.714ns Source Clock Delay (SCD): -0.479ns Clock Pessimism Removal (CPR): -0.235ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.582 -0.479 U1/CLK SLICE_X38Y28 FDRE r U1/comptX_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X38Y28 FDRE (Prop_fdre_C_Q) 0.164 -0.315 r U1/comptX_reg[8]/Q net (fo=12, routed) 0.175 -0.140 U1/comptX_reg__0[8] SLICE_X38Y28 LUT4 (Prop_lut4_I3_O) 0.045 -0.095 r U1/comptX[8]_i_1/O net (fo=1, routed) 0.000 -0.095 U1/plusOp[8] SLICE_X38Y28 FDRE r U1/comptX_reg[8]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.849 -0.714 U1/CLK SLICE_X38Y28 FDRE r U1/comptX_reg[8]/C clock pessimism 0.235 -0.479 clock uncertainty 0.160 -0.319 SLICE_X38Y28 FDRE (Hold_fdre_C_D) 0.120 -0.199 U1/comptX_reg[8] ------------------------------------------------------------------- required time 0.199 arrival time -0.095 ------------------------------------------------------------------- slack 0.104 Slack (MET) : 0.107ns (arrival time - required time) Source: U1/comptX_reg[1]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptX_reg[2]/D (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1_1 rise@0.000ns) Data Path Delay: 0.374ns (logic 0.183ns (48.868%) route 0.191ns (51.132%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.712ns Source Clock Delay (SCD): -0.477ns Clock Pessimism Removal (CPR): -0.235ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.584 -0.477 U1/CLK SLICE_X39Y30 FDRE r U1/comptX_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X39Y30 FDRE (Prop_fdre_C_Q) 0.141 -0.336 r U1/comptX_reg[1]/Q net (fo=8, routed) 0.191 -0.144 U1/comptX_reg__0[1] SLICE_X39Y30 LUT3 (Prop_lut3_I0_O) 0.042 -0.102 r U1/comptX[2]_i_1/O net (fo=1, routed) 0.000 -0.102 U1/plusOp[2] SLICE_X39Y30 FDRE r U1/comptX_reg[2]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.851 -0.712 U1/CLK SLICE_X39Y30 FDRE r U1/comptX_reg[2]/C clock pessimism 0.235 -0.477 clock uncertainty 0.160 -0.317 SLICE_X39Y30 FDRE (Hold_fdre_C_D) 0.107 -0.210 U1/comptX_reg[2] ------------------------------------------------------------------- required time 0.210 arrival time -0.102 ------------------------------------------------------------------- slack 0.107 --------------------------------------------------------------------------------------------------- From Clock: clk_out1_clk_wiz_1 To Clock: clk_out1_clk_wiz_1_1 Setup : 0 Failing Endpoints, Worst Slack 35.149ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.063ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 35.149ns (required time - arrival time) Source: U1/comptY_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[0]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 4.145ns (logic 0.952ns (22.969%) route 3.193ns (77.031%)) Logic Levels: 4 (LUT4=1 LUT6=3) Clock Path Skew: -0.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.261ns = ( 38.739 - 40.000 ) Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.626ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.746 -0.613 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y31 FDRE (Prop_fdre_C_Q) 0.456 -0.157 r U1/comptY_reg[7]/Q net (fo=10, routed) 1.014 0.857 U1/comptY_reg__0[7] SLICE_X43Y31 LUT4 (Prop_lut4_I1_O) 0.124 0.981 r U1/vga_vs_OBUF_inst_i_2/O net (fo=3, routed) 0.540 1.521 U1/vga_vs_OBUF_inst_i_2_n_0 SLICE_X42Y31 LUT6 (Prop_lut6_I5_O) 0.124 1.645 r U1/comptY[9]_i_8/O net (fo=1, routed) 0.304 1.949 U1/comptY[9]_i_8_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.073 r U1/comptY[9]_i_5/O net (fo=1, routed) 0.650 2.723 U1/comptY[9]_i_5_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.847 r U1/comptY[9]_i_1/O net (fo=10, routed) 0.685 3.532 U1/comptY SLICE_X42Y32 FDRE r U1/comptY_reg[0]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 40.000 40.000 r L16 0.000 40.000 r H125MHz (IN) net (fo=0) 0.000 40.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.571 38.739 U1/CLK SLICE_X42Y32 FDRE r U1/comptY_reg[0]/C clock pessimism 0.626 39.365 clock uncertainty -0.160 39.205 SLICE_X42Y32 FDRE (Setup_fdre_C_R) -0.524 38.681 U1/comptY_reg[0] ------------------------------------------------------------------- required time 38.681 arrival time -3.532 ------------------------------------------------------------------- slack 35.149 Slack (MET) : 35.149ns (required time - arrival time) Source: U1/comptY_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[1]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 4.145ns (logic 0.952ns (22.969%) route 3.193ns (77.031%)) Logic Levels: 4 (LUT4=1 LUT6=3) Clock Path Skew: -0.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.261ns = ( 38.739 - 40.000 ) Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.626ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.746 -0.613 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y31 FDRE (Prop_fdre_C_Q) 0.456 -0.157 r U1/comptY_reg[7]/Q net (fo=10, routed) 1.014 0.857 U1/comptY_reg__0[7] SLICE_X43Y31 LUT4 (Prop_lut4_I1_O) 0.124 0.981 r U1/vga_vs_OBUF_inst_i_2/O net (fo=3, routed) 0.540 1.521 U1/vga_vs_OBUF_inst_i_2_n_0 SLICE_X42Y31 LUT6 (Prop_lut6_I5_O) 0.124 1.645 r U1/comptY[9]_i_8/O net (fo=1, routed) 0.304 1.949 U1/comptY[9]_i_8_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.073 r U1/comptY[9]_i_5/O net (fo=1, routed) 0.650 2.723 U1/comptY[9]_i_5_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.847 r U1/comptY[9]_i_1/O net (fo=10, routed) 0.685 3.532 U1/comptY SLICE_X42Y32 FDRE r U1/comptY_reg[1]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 40.000 40.000 r L16 0.000 40.000 r H125MHz (IN) net (fo=0) 0.000 40.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.571 38.739 U1/CLK SLICE_X42Y32 FDRE r U1/comptY_reg[1]/C clock pessimism 0.626 39.365 clock uncertainty -0.160 39.205 SLICE_X42Y32 FDRE (Setup_fdre_C_R) -0.524 38.681 U1/comptY_reg[1] ------------------------------------------------------------------- required time 38.681 arrival time -3.532 ------------------------------------------------------------------- slack 35.149 Slack (MET) : 35.149ns (required time - arrival time) Source: U1/comptY_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[2]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 4.145ns (logic 0.952ns (22.969%) route 3.193ns (77.031%)) Logic Levels: 4 (LUT4=1 LUT6=3) Clock Path Skew: -0.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.261ns = ( 38.739 - 40.000 ) Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.626ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.746 -0.613 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y31 FDRE (Prop_fdre_C_Q) 0.456 -0.157 r U1/comptY_reg[7]/Q net (fo=10, routed) 1.014 0.857 U1/comptY_reg__0[7] SLICE_X43Y31 LUT4 (Prop_lut4_I1_O) 0.124 0.981 r U1/vga_vs_OBUF_inst_i_2/O net (fo=3, routed) 0.540 1.521 U1/vga_vs_OBUF_inst_i_2_n_0 SLICE_X42Y31 LUT6 (Prop_lut6_I5_O) 0.124 1.645 r U1/comptY[9]_i_8/O net (fo=1, routed) 0.304 1.949 U1/comptY[9]_i_8_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.073 r U1/comptY[9]_i_5/O net (fo=1, routed) 0.650 2.723 U1/comptY[9]_i_5_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.847 r U1/comptY[9]_i_1/O net (fo=10, routed) 0.685 3.532 U1/comptY SLICE_X42Y32 FDRE r U1/comptY_reg[2]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 40.000 40.000 r L16 0.000 40.000 r H125MHz (IN) net (fo=0) 0.000 40.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.571 38.739 U1/CLK SLICE_X42Y32 FDRE r U1/comptY_reg[2]/C clock pessimism 0.626 39.365 clock uncertainty -0.160 39.205 SLICE_X42Y32 FDRE (Setup_fdre_C_R) -0.524 38.681 U1/comptY_reg[2] ------------------------------------------------------------------- required time 38.681 arrival time -3.532 ------------------------------------------------------------------- slack 35.149 Slack (MET) : 35.149ns (required time - arrival time) Source: U1/comptY_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[3]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 4.145ns (logic 0.952ns (22.969%) route 3.193ns (77.031%)) Logic Levels: 4 (LUT4=1 LUT6=3) Clock Path Skew: -0.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.261ns = ( 38.739 - 40.000 ) Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.626ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.746 -0.613 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y31 FDRE (Prop_fdre_C_Q) 0.456 -0.157 r U1/comptY_reg[7]/Q net (fo=10, routed) 1.014 0.857 U1/comptY_reg__0[7] SLICE_X43Y31 LUT4 (Prop_lut4_I1_O) 0.124 0.981 r U1/vga_vs_OBUF_inst_i_2/O net (fo=3, routed) 0.540 1.521 U1/vga_vs_OBUF_inst_i_2_n_0 SLICE_X42Y31 LUT6 (Prop_lut6_I5_O) 0.124 1.645 r U1/comptY[9]_i_8/O net (fo=1, routed) 0.304 1.949 U1/comptY[9]_i_8_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.073 r U1/comptY[9]_i_5/O net (fo=1, routed) 0.650 2.723 U1/comptY[9]_i_5_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.847 r U1/comptY[9]_i_1/O net (fo=10, routed) 0.685 3.532 U1/comptY SLICE_X42Y32 FDRE r U1/comptY_reg[3]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 40.000 40.000 r L16 0.000 40.000 r H125MHz (IN) net (fo=0) 0.000 40.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.571 38.739 U1/CLK SLICE_X42Y32 FDRE r U1/comptY_reg[3]/C clock pessimism 0.626 39.365 clock uncertainty -0.160 39.205 SLICE_X42Y32 FDRE (Setup_fdre_C_R) -0.524 38.681 U1/comptY_reg[3] ------------------------------------------------------------------- required time 38.681 arrival time -3.532 ------------------------------------------------------------------- slack 35.149 Slack (MET) : 35.149ns (required time - arrival time) Source: U1/comptY_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[5]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 4.145ns (logic 0.952ns (22.969%) route 3.193ns (77.031%)) Logic Levels: 4 (LUT4=1 LUT6=3) Clock Path Skew: -0.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.261ns = ( 38.739 - 40.000 ) Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.626ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.746 -0.613 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y31 FDRE (Prop_fdre_C_Q) 0.456 -0.157 r U1/comptY_reg[7]/Q net (fo=10, routed) 1.014 0.857 U1/comptY_reg__0[7] SLICE_X43Y31 LUT4 (Prop_lut4_I1_O) 0.124 0.981 r U1/vga_vs_OBUF_inst_i_2/O net (fo=3, routed) 0.540 1.521 U1/vga_vs_OBUF_inst_i_2_n_0 SLICE_X42Y31 LUT6 (Prop_lut6_I5_O) 0.124 1.645 r U1/comptY[9]_i_8/O net (fo=1, routed) 0.304 1.949 U1/comptY[9]_i_8_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.073 r U1/comptY[9]_i_5/O net (fo=1, routed) 0.650 2.723 U1/comptY[9]_i_5_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.847 r U1/comptY[9]_i_1/O net (fo=10, routed) 0.685 3.532 U1/comptY SLICE_X42Y32 FDRE r U1/comptY_reg[5]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 40.000 40.000 r L16 0.000 40.000 r H125MHz (IN) net (fo=0) 0.000 40.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.571 38.739 U1/CLK SLICE_X42Y32 FDRE r U1/comptY_reg[5]/C clock pessimism 0.626 39.365 clock uncertainty -0.160 39.205 SLICE_X42Y32 FDRE (Setup_fdre_C_R) -0.524 38.681 U1/comptY_reg[5] ------------------------------------------------------------------- required time 38.681 arrival time -3.532 ------------------------------------------------------------------- slack 35.149 Slack (MET) : 35.281ns (required time - arrival time) Source: U1/comptY_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[4]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 4.011ns (logic 0.952ns (23.735%) route 3.059ns (76.265%)) Logic Levels: 4 (LUT4=1 LUT6=3) Clock Path Skew: -0.024ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.263ns = ( 38.737 - 40.000 ) Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.626ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.746 -0.613 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y31 FDRE (Prop_fdre_C_Q) 0.456 -0.157 r U1/comptY_reg[7]/Q net (fo=10, routed) 1.014 0.857 U1/comptY_reg__0[7] SLICE_X43Y31 LUT4 (Prop_lut4_I1_O) 0.124 0.981 r U1/vga_vs_OBUF_inst_i_2/O net (fo=3, routed) 0.540 1.521 U1/vga_vs_OBUF_inst_i_2_n_0 SLICE_X42Y31 LUT6 (Prop_lut6_I5_O) 0.124 1.645 r U1/comptY[9]_i_8/O net (fo=1, routed) 0.304 1.949 U1/comptY[9]_i_8_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.073 r U1/comptY[9]_i_5/O net (fo=1, routed) 0.650 2.723 U1/comptY[9]_i_5_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.847 r U1/comptY[9]_i_1/O net (fo=10, routed) 0.552 3.398 U1/comptY SLICE_X42Y31 FDRE r U1/comptY_reg[4]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 40.000 40.000 r L16 0.000 40.000 r H125MHz (IN) net (fo=0) 0.000 40.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.569 38.737 U1/CLK SLICE_X42Y31 FDRE r U1/comptY_reg[4]/C clock pessimism 0.626 39.363 clock uncertainty -0.160 39.203 SLICE_X42Y31 FDRE (Setup_fdre_C_R) -0.524 38.679 U1/comptY_reg[4] ------------------------------------------------------------------- required time 38.679 arrival time -3.398 ------------------------------------------------------------------- slack 35.281 Slack (MET) : 35.427ns (required time - arrival time) Source: U1/comptY_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[6]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 3.961ns (logic 0.952ns (24.032%) route 3.009ns (75.968%)) Logic Levels: 4 (LUT4=1 LUT6=3) Clock Path Skew: -0.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.263ns = ( 38.737 - 40.000 ) Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.628ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.746 -0.613 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y31 FDRE (Prop_fdre_C_Q) 0.456 -0.157 r U1/comptY_reg[7]/Q net (fo=10, routed) 1.014 0.857 U1/comptY_reg__0[7] SLICE_X43Y31 LUT4 (Prop_lut4_I1_O) 0.124 0.981 r U1/vga_vs_OBUF_inst_i_2/O net (fo=3, routed) 0.540 1.521 U1/vga_vs_OBUF_inst_i_2_n_0 SLICE_X42Y31 LUT6 (Prop_lut6_I5_O) 0.124 1.645 r U1/comptY[9]_i_8/O net (fo=1, routed) 0.304 1.949 U1/comptY[9]_i_8_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.073 r U1/comptY[9]_i_5/O net (fo=1, routed) 0.650 2.723 U1/comptY[9]_i_5_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.847 r U1/comptY[9]_i_1/O net (fo=10, routed) 0.502 3.349 U1/comptY SLICE_X41Y31 FDRE r U1/comptY_reg[6]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 40.000 40.000 r L16 0.000 40.000 r H125MHz (IN) net (fo=0) 0.000 40.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.569 38.737 U1/CLK SLICE_X41Y31 FDRE r U1/comptY_reg[6]/C clock pessimism 0.628 39.365 clock uncertainty -0.160 39.205 SLICE_X41Y31 FDRE (Setup_fdre_C_R) -0.429 38.776 U1/comptY_reg[6] ------------------------------------------------------------------- required time 38.776 arrival time -3.349 ------------------------------------------------------------------- slack 35.427 Slack (MET) : 35.445ns (required time - arrival time) Source: U1/comptY_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[7]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 3.966ns (logic 0.952ns (24.006%) route 3.014ns (75.994%)) Logic Levels: 4 (LUT4=1 LUT6=3) Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.263ns = ( 38.737 - 40.000 ) Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.650ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.746 -0.613 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y31 FDRE (Prop_fdre_C_Q) 0.456 -0.157 r U1/comptY_reg[7]/Q net (fo=10, routed) 1.014 0.857 U1/comptY_reg__0[7] SLICE_X43Y31 LUT4 (Prop_lut4_I1_O) 0.124 0.981 r U1/vga_vs_OBUF_inst_i_2/O net (fo=3, routed) 0.540 1.521 U1/vga_vs_OBUF_inst_i_2_n_0 SLICE_X42Y31 LUT6 (Prop_lut6_I5_O) 0.124 1.645 r U1/comptY[9]_i_8/O net (fo=1, routed) 0.304 1.949 U1/comptY[9]_i_8_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.073 r U1/comptY[9]_i_5/O net (fo=1, routed) 0.650 2.723 U1/comptY[9]_i_5_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.847 r U1/comptY[9]_i_1/O net (fo=10, routed) 0.506 3.353 U1/comptY SLICE_X40Y31 FDRE r U1/comptY_reg[7]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 40.000 40.000 r L16 0.000 40.000 r H125MHz (IN) net (fo=0) 0.000 40.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.569 38.737 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[7]/C clock pessimism 0.650 39.387 clock uncertainty -0.160 39.227 SLICE_X40Y31 FDRE (Setup_fdre_C_R) -0.429 38.798 U1/comptY_reg[7] ------------------------------------------------------------------- required time 38.798 arrival time -3.353 ------------------------------------------------------------------- slack 35.445 Slack (MET) : 35.445ns (required time - arrival time) Source: U1/comptY_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[8]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 3.966ns (logic 0.952ns (24.006%) route 3.014ns (75.994%)) Logic Levels: 4 (LUT4=1 LUT6=3) Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.263ns = ( 38.737 - 40.000 ) Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.650ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.746 -0.613 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y31 FDRE (Prop_fdre_C_Q) 0.456 -0.157 r U1/comptY_reg[7]/Q net (fo=10, routed) 1.014 0.857 U1/comptY_reg__0[7] SLICE_X43Y31 LUT4 (Prop_lut4_I1_O) 0.124 0.981 r U1/vga_vs_OBUF_inst_i_2/O net (fo=3, routed) 0.540 1.521 U1/vga_vs_OBUF_inst_i_2_n_0 SLICE_X42Y31 LUT6 (Prop_lut6_I5_O) 0.124 1.645 r U1/comptY[9]_i_8/O net (fo=1, routed) 0.304 1.949 U1/comptY[9]_i_8_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.073 r U1/comptY[9]_i_5/O net (fo=1, routed) 0.650 2.723 U1/comptY[9]_i_5_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.847 r U1/comptY[9]_i_1/O net (fo=10, routed) 0.506 3.353 U1/comptY SLICE_X40Y31 FDRE r U1/comptY_reg[8]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 40.000 40.000 r L16 0.000 40.000 r H125MHz (IN) net (fo=0) 0.000 40.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.569 38.737 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[8]/C clock pessimism 0.650 39.387 clock uncertainty -0.160 39.227 SLICE_X40Y31 FDRE (Setup_fdre_C_R) -0.429 38.798 U1/comptY_reg[8] ------------------------------------------------------------------- required time 38.798 arrival time -3.353 ------------------------------------------------------------------- slack 35.445 Slack (MET) : 35.445ns (required time - arrival time) Source: U1/comptY_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[9]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 3.966ns (logic 0.952ns (24.006%) route 3.014ns (75.994%)) Logic Levels: 4 (LUT4=1 LUT6=3) Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.263ns = ( 38.737 - 40.000 ) Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.650ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.776 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -6.996 -4.220 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -2.460 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.359 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.746 -0.613 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y31 FDRE (Prop_fdre_C_Q) 0.456 -0.157 r U1/comptY_reg[7]/Q net (fo=10, routed) 1.014 0.857 U1/comptY_reg__0[7] SLICE_X43Y31 LUT4 (Prop_lut4_I1_O) 0.124 0.981 r U1/vga_vs_OBUF_inst_i_2/O net (fo=3, routed) 0.540 1.521 U1/vga_vs_OBUF_inst_i_2_n_0 SLICE_X42Y31 LUT6 (Prop_lut6_I5_O) 0.124 1.645 r U1/comptY[9]_i_8/O net (fo=1, routed) 0.304 1.949 U1/comptY[9]_i_8_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.073 r U1/comptY[9]_i_5/O net (fo=1, routed) 0.650 2.723 U1/comptY[9]_i_5_n_0 SLICE_X40Y30 LUT6 (Prop_lut6_I5_O) 0.124 2.847 r U1/comptY[9]_i_1/O net (fo=10, routed) 0.506 3.353 U1/comptY SLICE_X40Y31 FDRE r U1/comptY_reg[9]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 40.000 40.000 r L16 0.000 40.000 r H125MHz (IN) net (fo=0) 0.000 40.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 1.421 41.421 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.583 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.105 35.478 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 37.077 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 37.168 r U0/inst/clkout1_buf/O net (fo=21, routed) 1.569 38.737 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[9]/C clock pessimism 0.650 39.387 clock uncertainty -0.160 39.227 SLICE_X40Y31 FDRE (Setup_fdre_C_R) -0.429 38.798 U1/comptY_reg[9] ------------------------------------------------------------------- required time 38.798 arrival time -3.353 ------------------------------------------------------------------- slack 35.445 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.063ns (arrival time - required time) Source: U1/comptY_reg[6]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[8]/D (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 0.343ns (logic 0.189ns (55.030%) route 0.154ns (44.970%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.709ns Source Clock Delay (SCD): -0.474ns Clock Pessimism Removal (CPR): -0.248ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.587 -0.474 U1/CLK SLICE_X41Y31 FDRE r U1/comptY_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X41Y31 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptY_reg[6]/Q net (fo=11, routed) 0.154 -0.178 U1/comptY_reg__0[6] SLICE_X40Y31 LUT5 (Prop_lut5_I1_O) 0.048 -0.130 r U1/comptY[8]_i_1/O net (fo=1, routed) 0.000 -0.130 U1/plusOp__0[8] SLICE_X40Y31 FDRE r U1/comptY_reg[8]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.854 -0.709 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[8]/C clock pessimism 0.248 -0.461 clock uncertainty 0.160 -0.301 SLICE_X40Y31 FDRE (Hold_fdre_C_D) 0.107 -0.194 U1/comptY_reg[8] ------------------------------------------------------------------- required time 0.194 arrival time -0.130 ------------------------------------------------------------------- slack 0.063 Slack (MET) : 0.076ns (arrival time - required time) Source: U1/comptY_reg[6]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[9]/D (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 0.341ns (logic 0.186ns (54.474%) route 0.155ns (45.526%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.709ns Source Clock Delay (SCD): -0.474ns Clock Pessimism Removal (CPR): -0.248ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.587 -0.474 U1/CLK SLICE_X41Y31 FDRE r U1/comptY_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X41Y31 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptY_reg[6]/Q net (fo=11, routed) 0.155 -0.177 U1/comptY_reg__0[6] SLICE_X40Y31 LUT6 (Prop_lut6_I1_O) 0.045 -0.132 r U1/comptY[9]_i_3/O net (fo=1, routed) 0.000 -0.132 U1/plusOp__0[9] SLICE_X40Y31 FDRE r U1/comptY_reg[9]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.854 -0.709 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[9]/C clock pessimism 0.248 -0.461 clock uncertainty 0.160 -0.301 SLICE_X40Y31 FDRE (Hold_fdre_C_D) 0.092 -0.209 U1/comptY_reg[9] ------------------------------------------------------------------- required time 0.209 arrival time -0.132 ------------------------------------------------------------------- slack 0.076 Slack (MET) : 0.076ns (arrival time - required time) Source: U1/comptY_reg[6]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[7]/D (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 0.340ns (logic 0.186ns (54.634%) route 0.154ns (45.366%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.709ns Source Clock Delay (SCD): -0.474ns Clock Pessimism Removal (CPR): -0.248ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.587 -0.474 U1/CLK SLICE_X41Y31 FDRE r U1/comptY_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X41Y31 FDRE (Prop_fdre_C_Q) 0.141 -0.333 r U1/comptY_reg[6]/Q net (fo=11, routed) 0.154 -0.178 U1/comptY_reg__0[6] SLICE_X40Y31 LUT4 (Prop_lut4_I2_O) 0.045 -0.133 r U1/comptY[7]_i_1/O net (fo=1, routed) 0.000 -0.133 U1/plusOp__0[7] SLICE_X40Y31 FDRE r U1/comptY_reg[7]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.854 -0.709 U1/CLK SLICE_X40Y31 FDRE r U1/comptY_reg[7]/C clock pessimism 0.248 -0.461 clock uncertainty 0.160 -0.301 SLICE_X40Y31 FDRE (Hold_fdre_C_D) 0.091 -0.210 U1/comptY_reg[7] ------------------------------------------------------------------- required time 0.210 arrival time -0.133 ------------------------------------------------------------------- slack 0.076 Slack (MET) : 0.091ns (arrival time - required time) Source: U1/comptX_reg[8]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptX_reg[9]/D (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 0.382ns (logic 0.207ns (54.146%) route 0.175ns (45.854%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.714ns Source Clock Delay (SCD): -0.479ns Clock Pessimism Removal (CPR): -0.235ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.582 -0.479 U1/CLK SLICE_X38Y28 FDRE r U1/comptX_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X38Y28 FDRE (Prop_fdre_C_Q) 0.164 -0.315 r U1/comptX_reg[8]/Q net (fo=12, routed) 0.175 -0.140 U1/comptX_reg__0[8] SLICE_X38Y28 LUT5 (Prop_lut5_I0_O) 0.043 -0.097 r U1/comptX[9]_i_1/O net (fo=1, routed) 0.000 -0.097 U1/plusOp[9] SLICE_X38Y28 FDRE r U1/comptX_reg[9]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.849 -0.714 U1/CLK SLICE_X38Y28 FDRE r U1/comptX_reg[9]/C clock pessimism 0.235 -0.479 clock uncertainty 0.160 -0.319 SLICE_X38Y28 FDRE (Hold_fdre_C_D) 0.131 -0.188 U1/comptX_reg[9] ------------------------------------------------------------------- required time 0.188 arrival time -0.097 ------------------------------------------------------------------- slack 0.091 Slack (MET) : 0.093ns (arrival time - required time) Source: U1/comptY_reg[4]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[5]/D (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 0.389ns (logic 0.209ns (53.754%) route 0.180ns (46.246%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.708ns Source Clock Delay (SCD): -0.474ns Clock Pessimism Removal (CPR): -0.249ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.587 -0.474 U1/CLK SLICE_X42Y31 FDRE r U1/comptY_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X42Y31 FDRE (Prop_fdre_C_Q) 0.164 -0.310 r U1/comptY_reg[4]/Q net (fo=5, routed) 0.180 -0.130 U1/comptY_reg__0[4] SLICE_X42Y32 LUT6 (Prop_lut6_I0_O) 0.045 -0.085 r U1/comptY[5]_i_1/O net (fo=1, routed) 0.000 -0.085 U1/comptY[5]_i_1_n_0 SLICE_X42Y32 FDRE r U1/comptY_reg[5]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.855 -0.708 U1/CLK SLICE_X42Y32 FDRE r U1/comptY_reg[5]/C clock pessimism 0.249 -0.459 clock uncertainty 0.160 -0.299 SLICE_X42Y32 FDRE (Hold_fdre_C_D) 0.121 -0.178 U1/comptY_reg[5] ------------------------------------------------------------------- required time 0.178 arrival time -0.085 ------------------------------------------------------------------- slack 0.093 Slack (MET) : 0.094ns (arrival time - required time) Source: U1/comptX_reg[3]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptX_reg[5]/D (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 0.381ns (logic 0.186ns (48.823%) route 0.195ns (51.177%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.710ns Source Clock Delay (SCD): -0.477ns Clock Pessimism Removal (CPR): -0.269ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.584 -0.477 U1/CLK SLICE_X39Y30 FDRE r U1/comptX_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X39Y30 FDRE (Prop_fdre_C_Q) 0.141 -0.336 r U1/comptX_reg[3]/Q net (fo=6, routed) 0.195 -0.141 U1/comptX_reg__0[3] SLICE_X40Y30 LUT6 (Prop_lut6_I4_O) 0.045 -0.096 r U1/comptX[5]_i_1/O net (fo=1, routed) 0.000 -0.096 U1/plusOp[5] SLICE_X40Y30 FDRE r U1/comptX_reg[5]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.853 -0.710 U1/CLK SLICE_X40Y30 FDRE r U1/comptX_reg[5]/C clock pessimism 0.269 -0.441 clock uncertainty 0.160 -0.281 SLICE_X40Y30 FDRE (Hold_fdre_C_D) 0.091 -0.190 U1/comptX_reg[5] ------------------------------------------------------------------- required time 0.190 arrival time -0.096 ------------------------------------------------------------------- slack 0.094 Slack (MET) : 0.096ns (arrival time - required time) Source: U1/comptX_reg[6]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptX_reg[7]/D (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 0.363ns (logic 0.183ns (50.353%) route 0.180ns (49.647%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.714ns Source Clock Delay (SCD): -0.479ns Clock Pessimism Removal (CPR): -0.235ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.582 -0.479 U1/CLK SLICE_X39Y28 FDRE r U1/comptX_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X39Y28 FDRE (Prop_fdre_C_Q) 0.141 -0.338 r U1/comptX_reg[6]/Q net (fo=10, routed) 0.180 -0.157 U1/comptX_reg__0[6] SLICE_X39Y28 LUT3 (Prop_lut3_I0_O) 0.042 -0.115 r U1/comptX[7]_i_1/O net (fo=1, routed) 0.000 -0.115 U1/plusOp[7] SLICE_X39Y28 FDRE r U1/comptX_reg[7]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.849 -0.714 U1/CLK SLICE_X39Y28 FDRE r U1/comptX_reg[7]/C clock pessimism 0.235 -0.479 clock uncertainty 0.160 -0.319 SLICE_X39Y28 FDRE (Hold_fdre_C_D) 0.107 -0.212 U1/comptX_reg[7] ------------------------------------------------------------------- required time 0.212 arrival time -0.115 ------------------------------------------------------------------- slack 0.096 Slack (MET) : 0.099ns (arrival time - required time) Source: U1/comptY_reg[4]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptY_reg[4]/D (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 0.382ns (logic 0.207ns (54.146%) route 0.175ns (45.854%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.709ns Source Clock Delay (SCD): -0.474ns Clock Pessimism Removal (CPR): -0.235ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.587 -0.474 U1/CLK SLICE_X42Y31 FDRE r U1/comptY_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X42Y31 FDRE (Prop_fdre_C_Q) 0.164 -0.310 r U1/comptY_reg[4]/Q net (fo=5, routed) 0.175 -0.135 U1/comptY_reg__0[4] SLICE_X42Y31 LUT5 (Prop_lut5_I4_O) 0.043 -0.092 r U1/comptY[4]_i_1/O net (fo=2, routed) 0.000 -0.092 U1/comptY[4]_i_1_n_0 SLICE_X42Y31 FDRE r U1/comptY_reg[4]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.854 -0.709 U1/CLK SLICE_X42Y31 FDRE r U1/comptY_reg[4]/C clock pessimism 0.235 -0.474 clock uncertainty 0.160 -0.314 SLICE_X42Y31 FDRE (Hold_fdre_C_D) 0.123 -0.191 U1/comptY_reg[4] ------------------------------------------------------------------- required time 0.191 arrival time -0.092 ------------------------------------------------------------------- slack 0.099 Slack (MET) : 0.104ns (arrival time - required time) Source: U1/comptX_reg[8]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptX_reg[8]/D (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 0.384ns (logic 0.209ns (54.384%) route 0.175ns (45.616%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.714ns Source Clock Delay (SCD): -0.479ns Clock Pessimism Removal (CPR): -0.235ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.582 -0.479 U1/CLK SLICE_X38Y28 FDRE r U1/comptX_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X38Y28 FDRE (Prop_fdre_C_Q) 0.164 -0.315 r U1/comptX_reg[8]/Q net (fo=12, routed) 0.175 -0.140 U1/comptX_reg__0[8] SLICE_X38Y28 LUT4 (Prop_lut4_I3_O) 0.045 -0.095 r U1/comptX[8]_i_1/O net (fo=1, routed) 0.000 -0.095 U1/plusOp[8] SLICE_X38Y28 FDRE r U1/comptX_reg[8]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.849 -0.714 U1/CLK SLICE_X38Y28 FDRE r U1/comptX_reg[8]/C clock pessimism 0.235 -0.479 clock uncertainty 0.160 -0.319 SLICE_X38Y28 FDRE (Hold_fdre_C_D) 0.120 -0.199 U1/comptX_reg[8] ------------------------------------------------------------------- required time 0.199 arrival time -0.095 ------------------------------------------------------------------- slack 0.104 Slack (MET) : 0.107ns (arrival time - required time) Source: U1/comptX_reg[1]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: U1/comptX_reg[2]/D (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 0.374ns (logic 0.183ns (48.868%) route 0.191ns (51.132%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.712ns Source Clock Delay (SCD): -0.477ns Clock Pessimism Removal (CPR): -0.235ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.699 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.268 -1.568 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -1.086 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.060 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.584 -0.477 U1/CLK SLICE_X39Y30 FDRE r U1/comptX_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X39Y30 FDRE (Prop_fdre_C_Q) 0.141 -0.336 r U1/comptX_reg[1]/Q net (fo=8, routed) 0.191 -0.144 U1/comptX_reg__0[1] SLICE_X39Y30 LUT3 (Prop_lut3_I0_O) 0.042 -0.102 r U1/comptX[2]_i_1/O net (fo=1, routed) 0.000 -0.102 U1/plusOp[2] SLICE_X39Y30 FDRE r U1/comptX_reg[2]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1_1 rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 U0/inst/clk_in1 L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r U0/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.927 U0/inst/clk_in1_clk_wiz_1 MMCME2_ADV_X0Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.047 -2.120 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -1.592 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.563 r U0/inst/clkout1_buf/O net (fo=21, routed) 0.851 -0.712 U1/CLK SLICE_X39Y30 FDRE r U1/comptX_reg[2]/C clock pessimism 0.235 -0.477 clock uncertainty 0.160 -0.317 SLICE_X39Y30 FDRE (Hold_fdre_C_D) 0.107 -0.210 U1/comptX_reg[2] ------------------------------------------------------------------- required time 0.210 arrival time -0.102 ------------------------------------------------------------------- slack 0.107