Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
| Date         : Tue Jan 11 11:43:27 2022
| Host         : LAPTOP-6KRNTV69 running 64-bit Ubuntu 20.04 LTS
| Command      : report_drc -file VGA_top_drc_routed.rpt -pb VGA_top_drc_routed.pb -rpx VGA_top_drc_routed.rpx
| Design       : VGA_top
| Device       : xc7z010clg400-1
| Speed File   : -1
| Design State : Fully Routed
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Report DRC

Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS

1. REPORT SUMMARY
-----------------
            Netlist: netlist
          Floorplan: design_1
      Design limits: <entire design considered>
           Ruledeck: default
             Max violations: <unlimited>
             Violations found: 2
+----------+----------+--------------------+------------+
| Rule     | Severity | Description        | Violations |
+----------+----------+--------------------+------------+
| PDRC-153 | Warning  | Gated clock check  | 1          |
| ZPS7-1   | Warning  | PS7 block required | 1          |
+----------+----------+--------------------+------------+

2. REPORT DETAILS
-----------------
PDRC-153#1 Warning
Gated clock check  
Net UPD/resetPomme_reg_1 is a gated clock net sourced by a combinational pin UPD/state_reg[3]_LDC_i_1/O, cell UPD/state_reg[3]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
Related violations: <none>

ZPS7-1#1 Warning
PS7 block required  
The PS7 cell must be used in this Zynq design in order to enable correct default configuration.
Related violations: <none>