Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
| Date         : Tue Jan 11 11:41:28 2022
| Host         : LAPTOP-6KRNTV69 running 64-bit Ubuntu 20.04 LTS
| Command      : report_drc -file VGA_top_drc_opted.rpt -pb VGA_top_drc_opted.pb -rpx VGA_top_drc_opted.rpx
| Design       : VGA_top
| Device       : xc7z010clg400-1
| Speed File   : -1
| Design State : Synthesized
------------------------------------------------------------------------------------------------------------

Report DRC

Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS

1. REPORT SUMMARY
-----------------
            Netlist: netlist
          Floorplan: design_1
      Design limits: <entire design considered>
           Ruledeck: default
             Max violations: <unlimited>
             Violations found: 1
+--------+----------+--------------------+------------+
| Rule   | Severity | Description        | Violations |
+--------+----------+--------------------+------------+
| ZPS7-1 | Warning  | PS7 block required | 1          |
+--------+----------+--------------------+------------+

2. REPORT DETAILS
-----------------
ZPS7-1#1 Warning
PS7 block required  
The PS7 cell must be used in this Zynq design in order to enable correct default configuration.
Related violations: <none>