Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
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| Tool Version     : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
| Date             : Tue Jan 11 11:43:33 2022
| Host             : LAPTOP-6KRNTV69 running 64-bit Ubuntu 20.04 LTS
| Command          : report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx
| Design           : VGA_top
| Device           : xc7z010clg400-1
| Design State     : routed
| Grade            : commercial
| Process          : typical
| Characterization : Production
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Power Report

Table of Contents
-----------------
1. Summary
1.1 On-Chip Components
1.2 Power Supply Summary
1.3 Confidence Level
2. Settings
2.1 Environment
2.2 Clock Constraints
3. Detailed Reports
3.1 By Hierarchy

1. Summary
----------

+--------------------------+--------------+
| Total On-Chip Power (W)  | 0.298        |
| Design Power Budget (W)  | Unspecified* |
| Power Budget Margin (W)  | NA           |
| Dynamic (W)              | 0.202        |
| Device Static (W)        | 0.097        |
| Effective TJA (C/W)      | 11.5         |
| Max Ambient (C)          | 81.6         |
| Junction Temperature (C) | 28.4         |
| Confidence Level         | Low          |
| Setting File             | ---          |
| Simulation Activity File | ---          |
| Design Nets Matched      | NA           |
+--------------------------+--------------+
* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>


1.1 On-Chip Components
----------------------

+----------------+-----------+----------+-----------+-----------------+
| On-Chip        | Power (W) | Used     | Available | Utilization (%) |
+----------------+-----------+----------+-----------+-----------------+
| Clocks         |     0.005 |        5 |       --- |             --- |
| Slice Logic    |     0.005 |     3201 |       --- |             --- |
|   LUT as Logic |     0.004 |     1970 |     17600 |           11.19 |
|   CARRY4       |    <0.001 |      307 |      4400 |            6.98 |
|   Register     |    <0.001 |      353 |     35200 |            1.00 |
|   F7/F8 Muxes  |    <0.001 |       33 |     17600 |            0.19 |
|   Others       |     0.000 |       29 |       --- |             --- |
| Signals        |     0.007 |     2447 |       --- |             --- |
| Block RAM      |     0.068 |     22.5 |        60 |           37.50 |
| MMCM           |     0.115 |        1 |         2 |           50.00 |
| I/O            |     0.002 |       28 |       100 |           28.00 |
| Static Power   |     0.097 |          |           |                 |
| Total          |     0.298 |          |           |                 |
+----------------+-----------+----------+-----------+-----------------+


1.2 Power Supply Summary
------------------------

+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
| Source    | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A)  | Margin (A) |
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
| Vccint    |       1.000 |     0.084 |       0.080 |      0.005 |       NA    | Unspecified | NA         |
| Vccaux    |       1.800 |     0.070 |       0.064 |      0.006 |       NA    | Unspecified | NA         |
| Vcco33    |       3.300 |     0.001 |       0.000 |      0.001 |       NA    | Unspecified | NA         |
| Vcco25    |       2.500 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vcco18    |       1.800 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vcco15    |       1.500 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vcco135   |       1.350 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vcco12    |       1.200 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vccaux_io |       1.800 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vccbram   |       1.000 |     0.007 |       0.006 |      0.001 |       NA    | Unspecified | NA         |
| MGTAVcc   |       1.000 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| MGTAVtt   |       1.200 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| MGTVccaux |       1.800 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vccpint   |       1.000 |     0.018 |       0.000 |      0.018 |       NA    | Unspecified | NA         |
| Vccpaux   |       1.800 |     0.010 |       0.000 |      0.010 |       NA    | Unspecified | NA         |
| Vccpll    |       1.800 |     0.003 |       0.000 |      0.003 |       NA    | Unspecified | NA         |
| Vcco_ddr  |       1.500 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vcco_mio0 |       1.800 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vcco_mio1 |       1.800 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vccadc    |       1.800 |     0.020 |       0.000 |      0.020 |       NA    | Unspecified | NA         |
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+


1.3 Confidence Level
--------------------

+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
| User Input Data             | Confidence | Details                                                | Action                                                                                                     |
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
| Design implementation state | High       | Design is routed                                       |                                                                                                            |
| Clock nodes activity        | High       | User specified more than 95% of clocks                 |                                                                                                            |
| I/O nodes activity          | Low        | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view   |
| Internal nodes activity     | Medium     | User specified less than 25% of internal nodes         | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
| Device models               | High       | Device models are Production                           |                                                                                                            |
|                             |            |                                                        |                                                                                                            |
| Overall confidence level    | Low        |                                                        |                                                                                                            |
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+


2. Settings
-----------

2.1 Environment
---------------

+-----------------------+------------------------+
| Ambient Temp (C)      | 25.0                   |
| ThetaJA (C/W)         | 11.5                   |
| Airflow (LFM)         | 250                    |
| Heat Sink             | none                   |
| ThetaSA (C/W)         | 0.0                    |
| Board Selection       | medium (10"x10")       |
| # of Board Layers     | 8to11 (8 to 11 Layers) |
| Board Temperature (C) | 25.0                   |
+-----------------------+------------------------+


2.2 Clock Constraints
---------------------

+--------------------+----------------------------+-----------------+
| Clock              | Domain                     | Constraint (ns) |
+--------------------+----------------------------+-----------------+
| clk_out1_clk_wiz_0 | U0/inst/clk_out1_clk_wiz_0 |            40.0 |
| clkfbout_clk_wiz_0 | U0/inst/clkfbout_clk_wiz_0 |            40.0 |
| sys_clk_pin        | H125MHz                    |             8.0 |
+--------------------+----------------------------+-----------------+


3. Detailed Reports
-------------------

3.1 By Hierarchy
----------------

+---------------+-----------+
| Name          | Power (W) |
+---------------+-----------+
| VGA_top       |     0.202 |
|   APPLE       |     0.001 |
|   RAMCTRL     |     0.075 |
|     MAT_RAM   |     0.027 |
|     SNAKE_RAM |     0.048 |
|   U0          |     0.115 |
|     inst      |     0.115 |
|   UPD         |     0.007 |
+---------------+-----------+