Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
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| Tool Version     : Vivado v.2018.3 (win64) Build 2405991 Thu Dec  6 23:38:27 MST 2018
| Date             : Tue Dec  7 12:43:47 2021
| Host             : irb121-02-w running 64-bit major release  (build 9200)
| Command          : report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx
| Design           : VGA_top
| Device           : xc7z010clg400-1
| Design State     : routed
| Grade            : commercial
| Process          : typical
| Characterization : Production
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Power Report

Table of Contents
-----------------
1. Summary
1.1 On-Chip Components
1.2 Power Supply Summary
1.3 Confidence Level
2. Settings
2.1 Environment
2.2 Clock Constraints
3. Detailed Reports
3.1 By Hierarchy

1. Summary
----------

+--------------------------+--------------+
| Total On-Chip Power (W)  | 0.210        |
| Design Power Budget (W)  | Unspecified* |
| Power Budget Margin (W)  | NA           |
| Dynamic (W)              | 0.116        |
| Device Static (W)        | 0.094        |
| Effective TJA (C/W)      | 11.5         |
| Max Ambient (C)          | 82.6         |
| Junction Temperature (C) | 27.4         |
| Confidence Level         | Medium       |
| Setting File             | ---          |
| Simulation Activity File | ---          |
| Design Nets Matched      | NA           |
+--------------------------+--------------+
* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>


1.1 On-Chip Components
----------------------

+----------------+-----------+----------+-----------+-----------------+
| On-Chip        | Power (W) | Used     | Available | Utilization (%) |
+----------------+-----------+----------+-----------+-----------------+
| Clocks         |    <0.001 |        8 |       --- |             --- |
| Slice Logic    |    <0.001 |      272 |       --- |             --- |
|   LUT as Logic |    <0.001 |      168 |     17600 |            0.95 |
|   CARRY4       |    <0.001 |       34 |      4400 |            0.77 |
|   Register     |    <0.001 |       21 |     35200 |            0.06 |
|   Others       |     0.000 |        4 |       --- |             --- |
| Signals        |    <0.001 |      149 |       --- |             --- |
| MMCM           |     0.115 |        1 |         2 |           50.00 |
| I/O            |    <0.001 |       19 |       100 |           19.00 |
| Static Power   |     0.094 |          |           |                 |
| Total          |     0.210 |          |           |                 |
+----------------+-----------+----------+-----------+-----------------+


1.2 Power Supply Summary
------------------------

+-----------+-------------+-----------+-------------+------------+
| Source    | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
+-----------+-------------+-----------+-------------+------------+
| Vccint    |       1.000 |     0.004 |       0.001 |      0.004 |
| Vccaux    |       1.800 |     0.069 |       0.064 |      0.005 |
| Vcco33    |       3.300 |     0.001 |       0.000 |      0.001 |
| Vcco25    |       2.500 |     0.000 |       0.000 |      0.000 |
| Vcco18    |       1.800 |     0.000 |       0.000 |      0.000 |
| Vcco15    |       1.500 |     0.000 |       0.000 |      0.000 |
| Vcco135   |       1.350 |     0.000 |       0.000 |      0.000 |
| Vcco12    |       1.200 |     0.000 |       0.000 |      0.000 |
| Vccaux_io |       1.800 |     0.000 |       0.000 |      0.000 |
| Vccbram   |       1.000 |     0.000 |       0.000 |      0.000 |
| MGTAVcc   |       1.000 |     0.000 |       0.000 |      0.000 |
| MGTAVtt   |       1.200 |     0.000 |       0.000 |      0.000 |
| MGTVccaux |       1.800 |     0.000 |       0.000 |      0.000 |
| Vccpint   |       1.000 |     0.017 |       0.000 |      0.017 |
| Vccpaux   |       1.800 |     0.010 |       0.000 |      0.010 |
| Vccpll    |       1.800 |     0.003 |       0.000 |      0.003 |
| Vcco_ddr  |       1.500 |     0.000 |       0.000 |      0.000 |
| Vcco_mio0 |       1.800 |     0.000 |       0.000 |      0.000 |
| Vcco_mio1 |       1.800 |     0.000 |       0.000 |      0.000 |
| Vccadc    |       1.800 |     0.020 |       0.000 |      0.020 |
+-----------+-------------+-----------+-------------+------------+


1.3 Confidence Level
--------------------

+-----------------------------+------------+------------------------------------------------+------------------------------------------------------------------------------------------------------------+
| User Input Data             | Confidence | Details                                        | Action                                                                                                     |
+-----------------------------+------------+------------------------------------------------+------------------------------------------------------------------------------------------------------------+
| Design implementation state | High       | Design is routed                               |                                                                                                            |
| Clock nodes activity        | High       | User specified more than 95% of clocks         |                                                                                                            |
| I/O nodes activity          | High       | User specified more than 95% of inputs         |                                                                                                            |
| Internal nodes activity     | Medium     | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
| Device models               | High       | Device models are Production                   |                                                                                                            |
|                             |            |                                                |                                                                                                            |
| Overall confidence level    | Medium     |                                                |                                                                                                            |
+-----------------------------+------------+------------------------------------------------+------------------------------------------------------------------------------------------------------------+


2. Settings
-----------

2.1 Environment
---------------

+-----------------------+------------------------+
| Ambient Temp (C)      | 25.0                   |
| ThetaJA (C/W)         | 11.5                   |
| Airflow (LFM)         | 250                    |
| Heat Sink             | none                   |
| ThetaSA (C/W)         | 0.0                    |
| Board Selection       | medium (10"x10")       |
| # of Board Layers     | 8to11 (8 to 11 Layers) |
| Board Temperature (C) | 25.0                   |
+-----------------------+------------------------+


2.2 Clock Constraints
---------------------

+----------------------+----------------------------+-----------------+
| Clock                | Domain                     | Constraint (ns) |
+----------------------+----------------------------+-----------------+
| H125MHz              | H125MHz                    |             8.0 |
| clk_out1_clk_wiz_1   | U0/inst/clk_out1_clk_wiz_1 |            40.0 |
| clk_out1_clk_wiz_1_1 | U0/inst/clk_out1_clk_wiz_1 |            40.0 |
| clkfbout_clk_wiz_1   | U0/inst/clkfbout_clk_wiz_1 |            40.0 |
| clkfbout_clk_wiz_1_1 | U0/inst/clkfbout_clk_wiz_1 |            40.0 |
| sys_clk_pin          | H125MHz                    |             8.0 |
+----------------------+----------------------------+-----------------+


3. Detailed Reports
-------------------

3.1 By Hierarchy
----------------

+----------+-----------+
| Name     | Power (W) |
+----------+-----------+
| VGA_top  |     0.116 |
|   U0     |     0.115 |
|     inst |     0.115 |
+----------+-----------+