Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 | Date : Tue Dec 7 12:43:47 2021 | Host : irb121-02-w running 64-bit major release (build 9200) | Command : report_methodology -file VGA_top_methodology_drc_routed.rpt -pb VGA_top_methodology_drc_routed.pb -rpx VGA_top_methodology_drc_routed.rpx | Design : VGA_top | Device : xc7z010clg400-1 | Speed File : -1 | Design State : Fully Routed ----------------------------------------------------------------------------------------------------------------------------------------------------------- Report Methodology Table of Contents ----------------- 1. REPORT SUMMARY 2. REPORT DETAILS 1. REPORT SUMMARY ----------------- Netlist: netlist Floorplan: design_1 Design limits: Max violations: Violations found: 2 +----------+----------+------------------------------------------------+------------+ | Rule | Severity | Description | Violations | +----------+----------+------------------------------------------------+------------+ | TIMING-6 | Warning | No common primary clock between related clocks | 2 | +----------+----------+------------------------------------------------+------------+ 2. REPORT DETAILS ----------------- TIMING-6#1 Warning No common primary clock between related clocks The clocks clk_out1_clk_wiz_1 and clk_out1_clk_wiz_1_1 are related (timed together) but they have no common primary clock. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks clk_out1_clk_wiz_1] -to [get_clocks clk_out1_clk_wiz_1_1] Related violations: TIMING-6#2 Warning No common primary clock between related clocks The clocks clk_out1_clk_wiz_1_1 and clk_out1_clk_wiz_1 are related (timed together) but they have no common primary clock. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks clk_out1_clk_wiz_1_1] -to [get_clocks clk_out1_clk_wiz_1] Related violations: