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-- Company: 
-- Engineer: 
-- 
-- Create Date: 12/15/2021 02:06:27 PM
-- Design Name: 
-- Module Name: updateSnake - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

library ourTypes;
use ourTypes.types.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity updateSnake is
    Port ( inSnake : in pos;
           outSnake : out pos;
           inIndex : in unsigned(10 downto 0);
           outIndex : out unsigned(10 downto 0));
end updateSnake;

architecture Behavioral of updateSnake is
signal cSnake : pos;
begin
process(inSnake)
variable dir : direction;
begin
    case inSnake.dir is
        when gauche =>
            cSnake.X <= inSnake.X - 1;
            cSnake.Y <= inSnake.Y;
            cSnake.dir <= inSnake.dir;
            cSnake.isDefined <= inSnake.isDefined;
        when droite =>
            cSnake.X <= inSnake.X + 1;
            cSnake.Y <= inSnake.Y;
            cSnake.dir <= inSnake.dir;
            cSnake.isDefined <= inSnake.isDefined;
        when haut =>
            cSnake.X <= inSnake.X;
            cSnake.Y <= inSnake.Y - 1;
            cSnake.dir <= inSnake.dir;
            cSnake.isDefined <= inSnake.isDefined;
        when bas =>
            cSnake.X <= inSnake.X;
            cSnake.Y <= inSnake.Y + 1;
            cSnake.dir <= inSnake.dir;
            cSnake.isDefined <= inSnake.isDefined;
    end case;
end process;
outSnake <= cSnake;
outIndex <= inIndex + 1;
end Behavioral;