Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------ | Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 | Date : Tue Jan 11 11:41:58 2022 | Host : LAPTOP-6KRNTV69 running 64-bit Ubuntu 20.04 LTS | Command : report_control_sets -verbose -file VGA_top_control_sets_placed.rpt | Design : VGA_top | Device : xc7z010 ------------------------------------------------------------------------------------ Control Set Information Table of Contents ----------------- 1. Summary 2. Histogram 3. Flip-Flop Distribution 4. Detailed Control Set Information 1. Summary ---------- +----------------------------------------------------------+-------+ | Status | Count | +----------------------------------------------------------+-------+ | Total control sets | 30 | | Minimum number of control sets | 30 | | Addition due to synthesis replication | 0 | | Addition due to physical synthesis replication | 0 | | Unused register locations in slices containing registers | 151 | +----------------------------------------------------------+-------+ * Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers ** Run report_qor_suggestions for automated merging and remapping suggestions 2. Histogram ------------ +--------------------+-------+ | Fanout | Count | +--------------------+-------+ | Total control sets | 30 | | >= 0 to < 4 | 4 | | >= 4 to < 6 | 4 | | >= 6 to < 8 | 0 | | >= 8 to < 10 | 1 | | >= 10 to < 12 | 14 | | >= 12 to < 14 | 2 | | >= 14 to < 16 | 0 | | >= 16 | 5 | +--------------------+-------+ * Control sets can be remapped at either synth_design or opt_design 3. Flip-Flop Distribution ------------------------- +--------------+-----------------------+------------------------+-----------------+--------------+ | Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices | +--------------+-----------------------+------------------------+-----------------+--------------+ | No | No | No | 67 | 40 | | No | No | Yes | 49 | 17 | | No | Yes | No | 44 | 22 | | Yes | No | No | 122 | 59 | | Yes | No | Yes | 16 | 10 | | Yes | Yes | No | 55 | 24 | +--------------+-----------------------+------------------------+-----------------+--------------+ 4. Detailed Control Set Information ----------------------------------- +-----------------------+-------------------------------+------------------------------+------------------+----------------+--------------+ | Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | Bels / Slice | +-----------------------+-------------------------------+------------------------------+------------------+----------------+--------------+ | UPD/resetPomme_reg_1 | | UPD/resetPomme_reg_0 | 1 | 1 | 1.00 | | U0/inst/clk_out1 | | SNAKE/startUpdate_i_2_n_0 | 1 | 1 | 1.00 | | U0/inst/clk_out1 | | | 1 | 1 | 1.00 | | UPD_CLK_DIV/clk_out | | UPD/clear | 1 | 1 | 1.00 | | H125MHz_IBUF_BUFG | | SNAKE/ROMAddress_reg[9]_0[0] | 4 | 4 | 1.00 | | H125MHz_IBUF_BUFG | | UPD/resetPomme_reg_1 | 2 | 4 | 2.00 | | H125MHz_IBUF_BUFG | | UPD/resetPomme_reg_0 | 1 | 4 | 4.00 | | H125MHz_IBUF_BUFG | UPD/state[4]_i_1_n_0 | UPD/clear | 5 | 5 | 1.00 | | U0/inst/clk_out1 | APPLE/pommeHere0 | | 4 | 8 | 2.00 | | U0/inst/clk_out1 | | APPLE/colorOut[R][4]_i_1_n_0 | 3 | 10 | 3.33 | | H125MHz_IBUF_BUFG | RAMCTRL/SNAKE_RAM/E[0] | | 3 | 10 | 3.33 | | U0/inst/clk_out1 | SYNC/eqOp | SYNC/comptY | 4 | 10 | 2.50 | | H125MHz_IBUF_BUFG | UPD/dataOut[23]_i_1_n_0 | | 7 | 11 | 1.57 | | U0/inst/clk_out1 | | SYNC/clear | 5 | 11 | 2.20 | | H125MHz_IBUF_BUFG | UPD/nbOfEls[10]_i_2_n_0 | UPD/nbOfEls[10]_i_1_n_0 | 3 | 11 | 3.67 | | H125MHz_IBUF_BUFG | UPD/matDataOut[10]_i_2_n_0 | UPD/matDataOut[10]_i_1_n_0 | 5 | 11 | 2.20 | | H125MHz_IBUF_BUFG | UPD/address[10]_i_1__0_n_0 | | 5 | 11 | 2.20 | | H125MHz_IBUF_BUFG | UPD/dataOut[23]_i_1_n_0 | UPD/dataOut[16]_i_1_n_0 | 8 | 11 | 1.38 | | H125MHz_IBUF_BUFG | UPD/matAddress[10]_i_1__0_n_0 | | 7 | 11 | 1.57 | | H125MHz_IBUF_BUFG | UPD/updateIndex | UPD/clear | 5 | 11 | 2.20 | | H125MHz_IBUF_BUFG | APPLE/address0 | | 5 | 11 | 2.20 | | H125MHz_IBUF_BUFG | APPLE/matAddress0 | | 5 | 11 | 2.20 | | H125MHz_IBUF_BUFG | SNAKE/cCaseX0 | | 5 | 11 | 2.20 | | H125MHz_IBUF_BUFG | UPD/lSnake[Y][8]_i_2_n_0 | UPD/lSnake[Y][8]_i_1_n_0 | 4 | 12 | 3.00 | | U0/inst/clk_out1 | | UPD/SR[0] | 4 | 13 | 3.25 | | H125MHz_IBUF_BUFG | | UPD/SR[0] | 10 | 19 | 1.90 | | H125MHz_IBUF_BUFG | UPD/lSnake[Y][8]_i_2_n_0 | | 8 | 19 | 2.38 | | H125MHz_IBUF_BUFG | APPLE/randInd0 | | 10 | 19 | 1.90 | | U0/inst/clk_out1 | | UPD_CLK_DIV/temp[0]_i_2_n_0 | 7 | 25 | 3.57 | | H125MHz_IBUF_BUFG | | | 39 | 66 | 1.69 | +-----------------------+-------------------------------+------------------------------+------------------+----------------+--------------+