----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 12/21/2021 03:36:18 PM
-- Design Name: 
-- Module Name: spritesRom - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
	
use std.textio.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity spritesRom is
    generic( addressSize : integer;
             length : integer;
             dataSize : integer;
             fileName : string
    );
    Port ( address : in unsigned (addressSize-1 downto 0);
           data : out STD_LOGIC_VECTOR (dataSize-1 downto 0);
           clk : in STD_LOGIC);
end spritesRom;

architecture Behavioral of spritesRom is
type listData is array(0 to length-1) of std_logic_vector(dataSize-1 downto 0);

--code "emprunté" ici : https://vhdlwhiz.com/initialize-ram-from-file/
impure function init_ram_hex return listData is
  file text_file : text open read_mode is fileName;
  variable text_line : line;
  variable ram_content : listData;
begin
  for i in 0 to length-1 loop
    readline(text_file, text_line);
    hread(text_line, ram_content(i));
  end loop;
 
  return ram_content;
end function;

signal mem : listData := init_ram_hex;
begin
process(clk,address)
begin
    if(clk'event and clk = '1') then
        data <= mem(TO_INTEGER(address));
    end if;
end process;
end Behavioral;