Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------- | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 | Date : Tue Jan 4 12:21:25 2022 | Host : irb121-12-w running 64-bit major release (build 9200) | Command : report_clock_utilization -file VGA_top_clock_utilization_routed.rpt | Design : VGA_top | Device : 7z010-clg400 | Speed File : -1 PRODUCTION 1.11 2014-09-11 ------------------------------------------------------------------------------------- Clock Utilization Report Table of Contents ----------------- 1. Clock Primitive Utilization 2. Global Clock Resources 3. Global Clock Source Details 4. Local Clock Details 5. Clock Regions: Key Resource Utilization 6. Clock Regions : Global Clock Summary 7. Device Cell Placement Summary for Global Clock g0 8. Device Cell Placement Summary for Global Clock g1 9. Device Cell Placement Summary for Global Clock g2 10. Clock Region Cell Placement per Global Clock: Region X0Y0 11. Clock Region Cell Placement per Global Clock: Region X1Y0 12. Clock Region Cell Placement per Global Clock: Region X1Y1 1. Clock Primitive Utilization ------------------------------ +----------+------+-----------+-----+--------------+--------+ | Type | Used | Available | LOC | Clock Region | Pblock | +----------+------+-----------+-----+--------------+--------+ | BUFGCTRL | 3 | 32 | 0 | 0 | 0 | | BUFH | 0 | 48 | 0 | 0 | 0 | | BUFIO | 0 | 8 | 0 | 0 | 0 | | BUFMR | 0 | 4 | 0 | 0 | 0 | | BUFR | 0 | 8 | 0 | 0 | 0 | | MMCM | 1 | 2 | 0 | 0 | 0 | | PLL | 0 | 2 | 0 | 0 | 0 | +----------+------+-----------+-----+--------------+--------+ 2. Global Clock Resources ------------------------- +-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+--------------------+--------------------------+--------------------------------+ | Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | +-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+--------------------+--------------------------+--------------------------------+ | g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y16 | n/a | 3 | 184 | 0 | 8.000 | sys_clk_pin | H125MHz_IBUF_BUFG_inst/O | H125MHz_IBUF_BUFG | | g1 | src1 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 3 | 60 | 0 | 40.000 | clk_out1_clk_wiz_1 | U0/inst/clkout1_buf/O | U0/inst/clk_out1 | | g2 | src1 | BUFG/O | None | BUFGCTRL_X0Y1 | n/a | 1 | 1 | 0 | 40.000 | clkfbout_clk_wiz_1 | U0/inst/clkf_buf/O | U0/inst/clkfbout_buf_clk_wiz_1 | +-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+--------------------+--------------------------+--------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) 3. Global Clock Source Details ------------------------------ +-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------------+--------------------------------+----------------------------+ | Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | +-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------------+--------------------------------+----------------------------+ | src0 | g0 | IBUF/O | IOB_X0Y78 | IOB_X0Y78 | X1Y1 | 1 | 0 | 8.000 | sys_clk_pin | H125MHz_IBUF_inst/O | H125MHz_IBUF | | src1 | g1 | MMCME2_ADV/CLKOUT0 | None | MMCME2_ADV_X0Y0 | X1Y0 | 1 | 0 | 40.000 | clk_out1_clk_wiz_1 | U0/inst/mmcm_adv_inst/CLKOUT0 | U0/inst/clk_out1_clk_wiz_1 | | src1 | g2 | MMCME2_ADV/CLKFBOUT | None | MMCME2_ADV_X0Y0 | X1Y0 | 1 | 0 | 40.000 | clkfbout_clk_wiz_1 | U0/inst/mmcm_adv_inst/CLKFBOUT | U0/inst/clkfbout_clk_wiz_1 | +-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------------+--------------------------------+----------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) 4. Local Clock Details ---------------------- +----------+-----------------+------------+------------------+--------------+-------------+-----------------+--------------+-------+------------------+------------+ | Local Id | Driver Type/Pin | Constraint | Site/BEL | Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | +----------+-----------------+------------+------------------+--------------+-------------+-----------------+--------------+-------+------------------+------------|| | 0 | FDRE/Q | None | SLICE_X8Y34/A5FF | X0Y0 | 17 | 29 | | | UPD/update_reg/Q | UPD/update - Static - +----------+-----------------+------------+------------------+--------------+-------------+-----------------+--------------+-------+------------------+------------|| * Local Clocks in this context represents only clocks driven by non-global buffers ** Clock Loads column represents the clock pin loads (pin count) *** Non-Clock Loads column represents the non-clock pin loads (pin count) 5. Clock Regions: Key Resource Utilization ------------------------------------------ +-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ | | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ | Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ | X0Y0 | 2 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 76 | 1100 | 63 | 400 | 1 | 20 | 6 | 10 | 0 | 20 | | X1Y0 | 3 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 80 | 1100 | 29 | 350 | 3 | 40 | 12 | 20 | 0 | 20 | | X0Y1 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1100 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | | X1Y1 | 2 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 33 | 1100 | 8 | 350 | 0 | 40 | 0 | 20 | 0 | 20 | +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ * Global Clock column represents track count; while other columns represents cell counts 6. Clock Regions : Global Clock Summary --------------------------------------- All Modules +----+----+----+ | | X0 | X1 | +----+----+----+ | Y1 | 0 | 2 | | Y0 | 2 | 3 | +----+----+----+ 7. Device Cell Placement Summary for Global Clock g0 ---------------------------------------------------- +-----------+-----------------+-------------------+-------------+-------------+---------------+-------------+----------+----------------+----------+-------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-------------+-------------+---------------+-------------+----------+----------------+----------+-------------------+ | g0 | BUFG/O | n/a | sys_clk_pin | 8.000 | {0.000 4.000} | 156 | 0 | 1 | 0 | H125MHz_IBUF_BUFG | +-----------+-----------------+-------------------+-------------+-------------+---------------+-------------+----------+----------------+----------+-------------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+-----+-----+ | | X0 | X1 | +----+-----+-----+ | Y1 | 0 | 8 | | Y0 | 74 | 75 | +----+-----+-----+ 8. Device Cell Placement Summary for Global Clock g1 ---------------------------------------------------- +-----------+-----------------+-------------------+--------------------+-------------+----------------+-------------+----------+----------------+----------+------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+--------------------+-------------+----------------+-------------+----------+----------------+----------+------------------+ | g1 | BUFG/O | n/a | clk_out1_clk_wiz_1 | 40.000 | {0.000 20.000} | 60 | 0 | 0 | 0 | U0/inst/clk_out1 | +-----------+-----------------+-------------------+--------------------+-------------+----------------+-------------+----------+----------------+----------+------------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+-----+-----+ | | X0 | X1 | +----+-----+-----+ | Y1 | 0 | 25 | | Y0 | 10 | 25 | +----+-----+-----+ 9. Device Cell Placement Summary for Global Clock g2 ---------------------------------------------------- +-----------+-----------------+-------------------+--------------------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+--------------------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+ | g2 | BUFG/O | n/a | clkfbout_clk_wiz_1 | 40.000 | {0.000 20.000} | 0 | 0 | 1 | 0 | U0/inst/clkfbout_buf_clk_wiz_1 | +-----------+-----------------+-------------------+--------------------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+----+ | | X0 | X1 | +----+----+----+ | Y1 | 0 | 0 | | Y0 | 0 | 1 | +----+----+----+ 10. Clock Region Cell Placement per Global Clock: Region X0Y0 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------+ | g0 | n/a | BUFG/O | None | 74 | 0 | 66 | 0 | 7 | 0 | 0 | 0 | 0 | 0 | H125MHz_IBUF_BUFG | | g1 | n/a | BUFG/O | None | 10 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | U0/inst/clk_out1 | +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts 11. Clock Region Cell Placement per Global Clock: Region X1Y0 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+--------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+--------------------------------+ | g0 | n/a | BUFG/O | None | 75 | 0 | 55 | 0 | 15 | 0 | 0 | 1 | 0 | 0 | H125MHz_IBUF_BUFG | | g1 | n/a | BUFG/O | None | 25 | 0 | 25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | U0/inst/clk_out1 | | g2 | n/a | BUFG/O | None | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | U0/inst/clkfbout_buf_clk_wiz_1 | +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+--------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts 12. Clock Region Cell Placement per Global Clock: Region X1Y1 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------+ | g0 | n/a | BUFG/O | None | 8 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | H125MHz_IBUF_BUFG | | g1 | n/a | BUFG/O | None | 25 | 0 | 25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | U0/inst/clk_out1 | +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts # Location of BUFG Primitives set_property LOC BUFGCTRL_X0Y1 [get_cells U0/inst/clkf_buf] set_property LOC BUFGCTRL_X0Y0 [get_cells U0/inst/clkout1_buf] set_property LOC BUFGCTRL_X0Y16 [get_cells H125MHz_IBUF_BUFG_inst] # Location of IO Primitives which is load of clock spine # Location of clock ports set_property LOC IOB_X0Y78 [get_ports H125MHz] # Clock net "U0/inst/clk_out1" driven by instance "U0/inst/clkout1_buf" located at site "BUFGCTRL_X0Y0" #startgroup create_pblock {CLKAG_U0/inst/clk_out1} add_cells_to_pblock [get_pblocks {CLKAG_U0/inst/clk_out1}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="U0/inst/clk_out1"}]]] resize_pblock [get_pblocks {CLKAG_U0/inst/clk_out1}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1} #endgroup # Clock net "H125MHz_IBUF_BUFG" driven by instance "H125MHz_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y16" #startgroup create_pblock {CLKAG_H125MHz_IBUF_BUFG} add_cells_to_pblock [get_pblocks {CLKAG_H125MHz_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL && NAME!=U0/inst/mmcm_adv_inst} -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="H125MHz_IBUF_BUFG"}]]] resize_pblock [get_pblocks {CLKAG_H125MHz_IBUF_BUFG}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1} #endgroup