Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------ | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 | Date : Tue Jan 4 12:19:29 2022 | Host : irb121-12-w running 64-bit major release (build 9200) | Command : report_control_sets -verbose -file VGA_top_control_sets_placed.rpt | Design : VGA_top | Device : xc7z010 ------------------------------------------------------------------------------------ Control Set Information Table of Contents ----------------- 1. Summary 2. Histogram 3. Flip-Flop Distribution 4. Detailed Control Set Information 1. Summary ---------- +----------------------------------------------------------+-------+ | Status | Count | +----------------------------------------------------------+-------+ | Number of unique control sets | 31 | | Unused register locations in slices containing registers | 180 | +----------------------------------------------------------+-------+ 2. Histogram ------------ +--------+--------------+ | Fanout | Control Sets | +--------+--------------+ | 1 | 17 | | 3 | 2 | | 4 | 2 | | 10 | 2 | | 11 | 2 | | 13 | 1 | | 14 | 1 | | 16+ | 4 | +--------+--------------+ 3. Flip-Flop Distribution ------------------------- +--------------+-----------------------+------------------------+-----------------+--------------+ | Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices | +--------------+-----------------------+------------------------+-----------------+--------------+ | No | No | No | 71 | 29 | | No | No | Yes | 40 | 13 | | No | Yes | No | 34 | 21 | | Yes | No | No | 25 | 12 | | Yes | No | Yes | 32 | 18 | | Yes | Yes | No | 10 | 6 | +--------------+-----------------------+------------------------+-----------------+--------------+ 4. Detailed Control Set Information ----------------------------------- +----------------------------------+------------------------+---------------------------------------+------------------+----------------+ | Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | +----------------------------------+------------------------+---------------------------------------+------------------+----------------+ | U0/inst/clk_out1 | | SNAKE/startUpdate_i_2_n_0 | 1 | 1 | | UPD/dataOut_reg[19]_LDC_i_1_n_0 | | UPD/dataOut_reg[19]_LDC_i_2_n_0 | 1 | 1 | | UPD/dataOut_reg[18]_LDC_i_1_n_0 | | UPD/dataOut_reg[18]_LDC_i_2_n_0 | 1 | 1 | | UPD/dataOut_reg[1]_LDC_i_1_n_0 | | UPD/dataOut_reg[1]_LDC_i_2_n_0 | 1 | 1 | | UPD/dataOut_reg[4]_LDC_i_1_n_0 | | UPD/dataOut_reg[4]_LDC_i_2_n_0 | 1 | 1 | | UPD/dataOut_reg[21]_LDC_i_1_n_0 | | UPD/dataOut_reg[21]_LDC_i_2_n_0 | 1 | 1 | | UPD/dataOut_reg[20]_LDC_i_1_n_0 | | UPD/dataOut_reg[20]_LDC_i_2_n_0 | 1 | 1 | | H125MHz_IBUF_BUFG | UPD/dataOut[2]_i_1_n_0 | UPD/dataOut_reg[19]_LDC_i_1_n_0 | 1 | 1 | | H125MHz_IBUF_BUFG | UPD/dataOut[2]_i_1_n_0 | UPD/dataOut_reg[18]_LDC_i_1_n_0 | 1 | 1 | | H125MHz_IBUF_BUFG | UPD/dataOut[2]_i_1_n_0 | UPD/dataOut_reg[1]_LDC_i_1_n_0 | 1 | 1 | | H125MHz_IBUF_BUFG | UPD/dataOut[2]_i_1_n_0 | UPD/dataOut_reg[21]_LDC_i_2_n_0 | 1 | 1 | | H125MHz_IBUF_BUFG | UPD/dataOut[2]_i_1_n_0 | UPD/dataOut_reg[21]_LDC_i_1_n_0 | 1 | 1 | | H125MHz_IBUF_BUFG | UPD/dataOut[2]_i_1_n_0 | UPD/dataOut_reg[20]_LDC_i_2_n_0 | 1 | 1 | | H125MHz_IBUF_BUFG | UPD/dataOut[2]_i_1_n_0 | UPD/dataOut_reg[18]_LDC_i_2_n_0 | 1 | 1 | | H125MHz_IBUF_BUFG | UPD/dataOut[2]_i_1_n_0 | UPD/dataOut_reg[19]_LDC_i_2_n_0 | 1 | 1 | | H125MHz_IBUF_BUFG | UPD/dataOut[2]_i_1_n_0 | UPD/dataOut_reg[20]_LDC_i_1_n_0 | 1 | 1 | | H125MHz_IBUF_BUFG | UPD/dataOut[2]_i_1_n_0 | UPD/dataOut_reg[1]_LDC_i_2_n_0 | 1 | 1 | | H125MHz_IBUF_BUFG | UPD/dataOut[2]_i_1_n_0 | UPD/dataOut_reg[4]_LDC_i_1_n_0 | 1 | 3 | | H125MHz_IBUF_BUFG | UPD/dataOut[2]_i_1_n_0 | UPD/dataOut_reg[4]_LDC_i_2_n_0 | 1 | 3 | | H125MHz_IBUF_BUFG | | SNAKE/Q[0] | 4 | 4 | | H125MHz_IBUF_BUFG | UPD/update | | 2 | 4 | | U0/inst/clk_out1 | SYNC/eqOp | SYNC/comptY | 6 | 10 | | H125MHz_IBUF_BUFG | RAMCTRL/SNAKE_RAM/E[0] | | 3 | 10 | | U0/inst/clk_out1 | | SYNC/clear | 6 | 11 | | H125MHz_IBUF_BUFG | SNAKE/cCaseX0 | | 7 | 11 | | U0/inst/clk_out1 | | SNAKE/AR[0] | 4 | 13 | | H125MHz_IBUF_BUFG | | SNAKE/AR[0] | 6 | 14 | | H125MHz_IBUF_BUFG | UPD/dataOut[2]_i_1_n_0 | UPD/currentSnake_reg[dirY][0]_i_2_n_0 | 6 | 16 | | ~UPD/update | | | 5 | 17 | | U0/inst/clk_out1 | | UPD_CLK_DIV/temp[0]_i_2_n_0 | 7 | 25 | | H125MHz_IBUF_BUFG | | | 24 | 54 | +----------------------------------+------------------------+---------------------------------------+------------------+----------------+