Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
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| Tool Version     : Vivado v.2018.3 (win64) Build 2405991 Thu Dec  6 23:38:27 MST 2018
| Date             : Tue Jan  4 12:21:24 2022
| Host             : irb121-12-w running 64-bit major release  (build 9200)
| Command          : report_power -file VGA_top_power_routed.rpt -pb VGA_top_power_summary_routed.pb -rpx VGA_top_power_routed.rpx
| Design           : VGA_top
| Device           : xc7z010clg400-1
| Design State     : routed
| Grade            : commercial
| Process          : typical
| Characterization : Production
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Power Report

Table of Contents
-----------------
1. Summary
1.1 On-Chip Components
1.2 Power Supply Summary
1.3 Confidence Level
2. Settings
2.1 Environment
2.2 Clock Constraints
3. Detailed Reports
3.1 By Hierarchy

1. Summary
----------

+--------------------------+--------------+
| Total On-Chip Power (W)  | 0.298        |
| Design Power Budget (W)  | Unspecified* |
| Power Budget Margin (W)  | NA           |
| Dynamic (W)              | 0.201        |
| Device Static (W)        | 0.097        |
| Effective TJA (C/W)      | 11.5         |
| Max Ambient (C)          | 81.6         |
| Junction Temperature (C) | 28.4         |
| Confidence Level         | Medium       |
| Setting File             | ---          |
| Simulation Activity File | ---          |
| Design Nets Matched      | NA           |
+--------------------------+--------------+
* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>


1.1 On-Chip Components
----------------------

+----------------+-----------+----------+-----------+-----------------+
| On-Chip        | Power (W) | Used     | Available | Utilization (%) |
+----------------+-----------+----------+-----------+-----------------+
| Clocks         |     0.004 |        6 |       --- |             --- |
| Slice Logic    |     0.002 |     2313 |       --- |             --- |
|   LUT as Logic |     0.002 |     1491 |     17600 |            8.47 |
|   CARRY4       |    <0.001 |      266 |      4400 |            6.05 |
|   Register     |    <0.001 |      212 |     35200 |            0.60 |
|   F7/F8 Muxes  |    <0.001 |       20 |     17600 |            0.11 |
|   Others       |     0.000 |       26 |       --- |             --- |
| Signals        |     0.004 |     1918 |       --- |             --- |
| Block RAM      |     0.075 |     22.5 |        60 |           37.50 |
| MMCM           |     0.115 |        1 |         2 |           50.00 |
| I/O            |     0.002 |       24 |       100 |           24.00 |
| Static Power   |     0.097 |          |           |                 |
| Total          |     0.298 |          |           |                 |
+----------------+-----------+----------+-----------+-----------------+


1.2 Power Supply Summary
------------------------

+-----------+-------------+-----------+-------------+------------+
| Source    | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
+-----------+-------------+-----------+-------------+------------+
| Vccint    |       1.000 |     0.083 |       0.078 |      0.005 |
| Vccaux    |       1.800 |     0.070 |       0.064 |      0.006 |
| Vcco33    |       3.300 |     0.002 |       0.001 |      0.001 |
| Vcco25    |       2.500 |     0.000 |       0.000 |      0.000 |
| Vcco18    |       1.800 |     0.000 |       0.000 |      0.000 |
| Vcco15    |       1.500 |     0.000 |       0.000 |      0.000 |
| Vcco135   |       1.350 |     0.000 |       0.000 |      0.000 |
| Vcco12    |       1.200 |     0.000 |       0.000 |      0.000 |
| Vccaux_io |       1.800 |     0.000 |       0.000 |      0.000 |
| Vccbram   |       1.000 |     0.008 |       0.007 |      0.001 |
| MGTAVcc   |       1.000 |     0.000 |       0.000 |      0.000 |
| MGTAVtt   |       1.200 |     0.000 |       0.000 |      0.000 |
| MGTVccaux |       1.800 |     0.000 |       0.000 |      0.000 |
| Vccpint   |       1.000 |     0.018 |       0.000 |      0.018 |
| Vccpaux   |       1.800 |     0.010 |       0.000 |      0.010 |
| Vccpll    |       1.800 |     0.003 |       0.000 |      0.003 |
| Vcco_ddr  |       1.500 |     0.000 |       0.000 |      0.000 |
| Vcco_mio0 |       1.800 |     0.000 |       0.000 |      0.000 |
| Vcco_mio1 |       1.800 |     0.000 |       0.000 |      0.000 |
| Vccadc    |       1.800 |     0.020 |       0.000 |      0.020 |
+-----------+-------------+-----------+-------------+------------+


1.3 Confidence Level
--------------------

+-----------------------------+------------+-------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
| User Input Data             | Confidence | Details                                               | Action                                                                                                             |
+-----------------------------+------------+-------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
| Design implementation state | High       | Design is routed                                      |                                                                                                                    |
| Clock nodes activity        | Medium     | More than 5% of clocks are missing user specification | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view |
| I/O nodes activity          | Medium     | More than 5% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view           |
| Internal nodes activity     | Medium     | User specified less than 25% of internal nodes        | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views         |
| Device models               | High       | Device models are Production                          |                                                                                                                    |
|                             |            |                                                       |                                                                                                                    |
| Overall confidence level    | Medium     |                                                       |                                                                                                                    |
+-----------------------------+------------+-------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+


2. Settings
-----------

2.1 Environment
---------------

+-----------------------+------------------------+
| Ambient Temp (C)      | 25.0                   |
| ThetaJA (C/W)         | 11.5                   |
| Airflow (LFM)         | 250                    |
| Heat Sink             | none                   |
| ThetaSA (C/W)         | 0.0                    |
| Board Selection       | medium (10"x10")       |
| # of Board Layers     | 8to11 (8 to 11 Layers) |
| Board Temperature (C) | 25.0                   |
+-----------------------+------------------------+


2.2 Clock Constraints
---------------------

+--------------------+----------------------------+-----------------+
| Clock              | Domain                     | Constraint (ns) |
+--------------------+----------------------------+-----------------+
| clk_out1_clk_wiz_1 | U0/inst/clk_out1_clk_wiz_1 |            40.0 |
| clkfbout_clk_wiz_1 | U0/inst/clkfbout_clk_wiz_1 |            40.0 |
| sys_clk_pin        | H125MHz                    |             8.0 |
| sys_clk_pin        | H125MHz_IBUF_BUFG          |             8.0 |
+--------------------+----------------------------+-----------------+


3. Detailed Reports
-------------------

3.1 By Hierarchy
----------------

+---------------+-----------+
| Name          | Power (W) |
+---------------+-----------+
| VGA_top       |     0.201 |
|   RAMCTRL     |     0.080 |
|     MAT_RAM   |     0.031 |
|     SNAKE_RAM |     0.049 |
|   U0          |     0.115 |
|     inst      |     0.115 |
|   UPD         |     0.002 |
+---------------+-----------+