Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 | Date : Tue Jan 4 12:21:24 2022 | Host : irb121-12-w running 64-bit major release (build 9200) | Command : report_timing_summary -max_paths 10 -file VGA_top_timing_summary_routed.rpt -pb VGA_top_timing_summary_routed.pb -rpx VGA_top_timing_summary_routed.rpx -warn_on_violation | Design : VGA_top | Device : 7z010-clg400 | Speed File : -1 PRODUCTION 1.11 2014-09-11 -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Timing Summary Report ------------------------------------------------------------------------------------------------ | Timer Settings | -------------- ------------------------------------------------------------------------------------------------ Enable Multi Corner Analysis : Yes Enable Pessimism Removal : Yes Pessimism Removal Resolution : Nearest Common Node Enable Input Delay Default Clock : No Enable Preset / Clear Arcs : No Disable Flight Delays : No Ignore I/O Paths : No Timing Early Launch at Borrowing Latches : false Corner Analyze Analyze Name Max Paths Min Paths ------ --------- --------- Slow Yes Yes Fast Yes Yes check_timing report Table of Contents ----------------- 1. checking no_clock 2. checking constant_clock 3. checking pulse_width_clock 4. checking unconstrained_internal_endpoints 5. checking no_input_delay 6. checking no_output_delay 7. checking multiple_clock 8. checking generated_clocks 9. checking loops 10. checking partial_input_delay 11. checking partial_output_delay 12. checking latch_loops 1. checking no_clock -------------------- There is 1 register/latch pin with no clock driven by root clock pin: UPD/currentSnake_reg[X][4]/Q (HIGH) There is 1 register/latch pin with no clock driven by root clock pin: UPD/currentSnake_reg[X][5]/Q (HIGH) There is 1 register/latch pin with no clock driven by root clock pin: UPD/currentSnake_reg[X][6]/Q (HIGH) There is 1 register/latch pin with no clock driven by root clock pin: UPD/currentSnake_reg[X][7]/Q (HIGH) There is 1 register/latch pin with no clock driven by root clock pin: UPD/currentSnake_reg[dirX][1]/Q (HIGH) There is 1 register/latch pin with no clock driven by root clock pin: UPD/currentSnake_reg[dirY][0]/Q (HIGH) There are 23 register/latch pins with no clock driven by root clock pin: UPD/update_reg/Q (HIGH) 2. checking constant_clock -------------------------- There are 0 register/latch pins with constant_clock. 3. checking pulse_width_clock ----------------------------- There are 0 register/latch pins which need pulse_width check 4. checking unconstrained_internal_endpoints -------------------------------------------- There are 23 pins that are not constrained for maximum delay. (HIGH) There are 0 pins that are not constrained for maximum delay due to constant clock. 5. checking no_input_delay -------------------------- There is 1 input port with no input delay specified. (HIGH) There are 0 input ports with no input delay but user has a false path constraint. 6. checking no_output_delay --------------------------- There are 18 ports with no output delay specified. (HIGH) There are 0 ports with no output delay but user has a false path constraint There are 0 ports with no output delay but with a timing clock defined on it or propagating through it 7. checking multiple_clock -------------------------- There are 0 register/latch pins with multiple clocks. 8. checking generated_clocks ---------------------------- There are 0 generated clocks that are not connected to a clock source. 9. checking loops ----------------- There are 0 combinational loops in the design. 10. checking partial_input_delay -------------------------------- There are 0 input ports with partial input delay specified. 11. checking partial_output_delay --------------------------------- There are 0 ports with partial output delay specified. 12. checking latch_loops ------------------------ There are 0 combinational latch loops in the design through latch input ------------------------------------------------------------------------------------------------ | Design Timing Summary | --------------------- ------------------------------------------------------------------------------------------------ WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- -5.611 -86.314 22 1095 -0.025 -0.025 1 1095 2.000 0.000 0 250 Timing constraints are not met. ------------------------------------------------------------------------------------------------ | Clock Summary | ------------- ------------------------------------------------------------------------------------------------ Clock Waveform(ns) Period(ns) Frequency(MHz) ----- ------------ ---------- -------------- U0/inst/clk_in1 {0.000 4.000} 8.000 125.000 clk_out1_clk_wiz_1 {0.000 20.000} 40.000 25.000 clkfbout_clk_wiz_1 {0.000 20.000} 40.000 25.000 sys_clk_pin {0.000 4.000} 8.000 125.000 ------------------------------------------------------------------------------------------------ | Intra Clock Table | ----------------- ------------------------------------------------------------------------------------------------ Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- U0/inst/clk_in1 2.000 0.000 0 1 clk_out1_clk_wiz_1 31.915 0.000 0 78 0.218 0.000 0 78 19.500 0.000 0 62 clkfbout_clk_wiz_1 37.845 0.000 0 3 sys_clk_pin -5.611 -86.314 22 923 0.078 0.000 0 923 3.500 0.000 0 184 ------------------------------------------------------------------------------------------------ | Inter Clock Table | ----------------- ------------------------------------------------------------------------------------------------ From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- sys_clk_pin clk_out1_clk_wiz_1 1.397 0.000 0 13 0.418 0.000 0 13 clk_out1_clk_wiz_1 sys_clk_pin -3.437 -39.544 21 45 -0.025 -0.025 1 45 ------------------------------------------------------------------------------------------------ | Other Path Groups Table | ----------------------- ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- **async_default** clk_out1_clk_wiz_1 clk_out1_clk_wiz_1 34.529 0.000 0 25 1.220 0.000 0 25 **async_default** sys_clk_pin clk_out1_clk_wiz_1 2.088 0.000 0 1 0.745 0.000 0 1 **async_default** sys_clk_pin sys_clk_pin 4.029 0.000 0 32 0.841 0.000 0 32 ------------------------------------------------------------------------------------------------ | Timing Details | -------------- ------------------------------------------------------------------------------------------------ --------------------------------------------------------------------------------------------------- From Clock: U0/inst/clk_in1 To Clock: U0/inst/clk_in1 Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 2.000ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: U0/inst/clk_in1 Waveform(ns): { 0.000 4.000 } Period(ns): 8.000 Sources: { U0/inst/clk_in1 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a MMCME2_ADV/CLKIN1 n/a 1.249 8.000 6.751 MMCME2_ADV_X0Y0 U0/inst/mmcm_adv_inst/CLKIN1 Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 8.000 92.000 MMCME2_ADV_X0Y0 U0/inst/mmcm_adv_inst/CLKIN1 Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 4.000 2.000 MMCME2_ADV_X0Y0 U0/inst/mmcm_adv_inst/CLKIN1 Low Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 2.000 4.000 2.000 MMCME2_ADV_X0Y0 U0/inst/mmcm_adv_inst/CLKIN1 High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 4.000 2.000 MMCME2_ADV_X0Y0 U0/inst/mmcm_adv_inst/CLKIN1 High Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 2.000 4.000 2.000 MMCME2_ADV_X0Y0 U0/inst/mmcm_adv_inst/CLKIN1 --------------------------------------------------------------------------------------------------- From Clock: clk_out1_clk_wiz_1 To Clock: clk_out1_clk_wiz_1 Setup : 0 Failing Endpoints, Worst Slack 31.915ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.218ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 19.500ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 31.915ns (required time - arrival time) Source: SYNC/comptY_reg[9]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: SYNC/comptY_reg[0]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 7.463ns (logic 1.058ns (14.176%) route 6.405ns (85.824%)) Logic Levels: 3 (LUT5=1 LUT6=2) Clock Path Skew: -0.032ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.488ns = ( 41.488 - 40.000 ) Source Clock Delay (SCD): 1.659ns Clock Pessimism Removal (CPR): 0.139ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.656 1.659 SYNC/clk_out1 SLICE_X19Y26 FDRE r SYNC/comptY_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X19Y26 FDRE (Prop_fdre_C_Q) 0.456 2.115 r SYNC/comptY_reg[9]/Q net (fo=10, routed) 2.756 4.871 SYNC/comptY_reg__0[9] SLICE_X28Y23 LUT5 (Prop_lut5_I0_O) 0.150 5.021 r SYNC/comptY[9]_i_9/O net (fo=1, routed) 0.989 6.010 SYNC/comptY[9]_i_9_n_0 SLICE_X29Y25 LUT6 (Prop_lut6_I0_O) 0.328 6.338 r SYNC/comptY[9]_i_5/O net (fo=1, routed) 0.845 7.183 SYNC/comptY[9]_i_5_n_0 SLICE_X29Y25 LUT6 (Prop_lut6_I5_O) 0.124 7.307 r SYNC/comptY[9]_i_1/O net (fo=10, routed) 1.816 9.122 SYNC/comptY SLICE_X17Y26 FDRE r SYNC/comptY_reg[0]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.485 41.488 SYNC/clk_out1 SLICE_X17Y26 FDRE r SYNC/comptY_reg[0]/C clock pessimism 0.139 41.627 clock uncertainty -0.160 41.467 SLICE_X17Y26 FDRE (Setup_fdre_C_R) -0.429 41.038 SYNC/comptY_reg[0] ------------------------------------------------------------------- required time 41.038 arrival time -9.122 ------------------------------------------------------------------- slack 31.915 Slack (MET) : 32.277ns (required time - arrival time) Source: SYNC/comptY_reg[9]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: SYNC/comptY_reg[5]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 6.972ns (logic 1.058ns (15.176%) route 5.914ns (84.824%)) Logic Levels: 3 (LUT5=1 LUT6=2) Clock Path Skew: -0.067ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.487ns = ( 41.487 - 40.000 ) Source Clock Delay (SCD): 1.659ns Clock Pessimism Removal (CPR): 0.105ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.656 1.659 SYNC/clk_out1 SLICE_X19Y26 FDRE r SYNC/comptY_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X19Y26 FDRE (Prop_fdre_C_Q) 0.456 2.115 r SYNC/comptY_reg[9]/Q net (fo=10, routed) 2.756 4.871 SYNC/comptY_reg__0[9] SLICE_X28Y23 LUT5 (Prop_lut5_I0_O) 0.150 5.021 r SYNC/comptY[9]_i_9/O net (fo=1, routed) 0.989 6.010 SYNC/comptY[9]_i_9_n_0 SLICE_X29Y25 LUT6 (Prop_lut6_I0_O) 0.328 6.338 r SYNC/comptY[9]_i_5/O net (fo=1, routed) 0.845 7.183 SYNC/comptY[9]_i_5_n_0 SLICE_X29Y25 LUT6 (Prop_lut6_I5_O) 0.124 7.307 r SYNC/comptY[9]_i_1/O net (fo=10, routed) 1.324 8.631 SYNC/comptY SLICE_X20Y26 FDRE r SYNC/comptY_reg[5]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.484 41.487 SYNC/clk_out1 SLICE_X20Y26 FDRE r SYNC/comptY_reg[5]/C clock pessimism 0.105 41.592 clock uncertainty -0.160 41.432 SLICE_X20Y26 FDRE (Setup_fdre_C_R) -0.524 40.908 SYNC/comptY_reg[5] ------------------------------------------------------------------- required time 40.908 arrival time -8.631 ------------------------------------------------------------------- slack 32.277 Slack (MET) : 32.372ns (required time - arrival time) Source: SYNC/comptY_reg[9]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: SYNC/comptY_reg[3]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 6.972ns (logic 1.058ns (15.176%) route 5.914ns (84.824%)) Logic Levels: 3 (LUT5=1 LUT6=2) Clock Path Skew: -0.067ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.487ns = ( 41.487 - 40.000 ) Source Clock Delay (SCD): 1.659ns Clock Pessimism Removal (CPR): 0.105ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.656 1.659 SYNC/clk_out1 SLICE_X19Y26 FDRE r SYNC/comptY_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X19Y26 FDRE (Prop_fdre_C_Q) 0.456 2.115 r SYNC/comptY_reg[9]/Q net (fo=10, routed) 2.756 4.871 SYNC/comptY_reg__0[9] SLICE_X28Y23 LUT5 (Prop_lut5_I0_O) 0.150 5.021 r SYNC/comptY[9]_i_9/O net (fo=1, routed) 0.989 6.010 SYNC/comptY[9]_i_9_n_0 SLICE_X29Y25 LUT6 (Prop_lut6_I0_O) 0.328 6.338 r SYNC/comptY[9]_i_5/O net (fo=1, routed) 0.845 7.183 SYNC/comptY[9]_i_5_n_0 SLICE_X29Y25 LUT6 (Prop_lut6_I5_O) 0.124 7.307 r SYNC/comptY[9]_i_1/O net (fo=10, routed) 1.324 8.631 SYNC/comptY SLICE_X21Y26 FDRE r SYNC/comptY_reg[3]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.484 41.487 SYNC/clk_out1 SLICE_X21Y26 FDRE r SYNC/comptY_reg[3]/C clock pessimism 0.105 41.592 clock uncertainty -0.160 41.432 SLICE_X21Y26 FDRE (Setup_fdre_C_R) -0.429 41.003 SYNC/comptY_reg[3] ------------------------------------------------------------------- required time 41.003 arrival time -8.631 ------------------------------------------------------------------- slack 32.372 Slack (MET) : 32.372ns (required time - arrival time) Source: SYNC/comptY_reg[9]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: SYNC/comptY_reg[4]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 6.972ns (logic 1.058ns (15.176%) route 5.914ns (84.824%)) Logic Levels: 3 (LUT5=1 LUT6=2) Clock Path Skew: -0.067ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.487ns = ( 41.487 - 40.000 ) Source Clock Delay (SCD): 1.659ns Clock Pessimism Removal (CPR): 0.105ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.656 1.659 SYNC/clk_out1 SLICE_X19Y26 FDRE r SYNC/comptY_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X19Y26 FDRE (Prop_fdre_C_Q) 0.456 2.115 r SYNC/comptY_reg[9]/Q net (fo=10, routed) 2.756 4.871 SYNC/comptY_reg__0[9] SLICE_X28Y23 LUT5 (Prop_lut5_I0_O) 0.150 5.021 r SYNC/comptY[9]_i_9/O net (fo=1, routed) 0.989 6.010 SYNC/comptY[9]_i_9_n_0 SLICE_X29Y25 LUT6 (Prop_lut6_I0_O) 0.328 6.338 r SYNC/comptY[9]_i_5/O net (fo=1, routed) 0.845 7.183 SYNC/comptY[9]_i_5_n_0 SLICE_X29Y25 LUT6 (Prop_lut6_I5_O) 0.124 7.307 r SYNC/comptY[9]_i_1/O net (fo=10, routed) 1.324 8.631 SYNC/comptY SLICE_X21Y26 FDRE r SYNC/comptY_reg[4]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.484 41.487 SYNC/clk_out1 SLICE_X21Y26 FDRE r SYNC/comptY_reg[4]/C clock pessimism 0.105 41.592 clock uncertainty -0.160 41.432 SLICE_X21Y26 FDRE (Setup_fdre_C_R) -0.429 41.003 SYNC/comptY_reg[4] ------------------------------------------------------------------- required time 41.003 arrival time -8.631 ------------------------------------------------------------------- slack 32.372 Slack (MET) : 32.433ns (required time - arrival time) Source: SYNC/comptY_reg[9]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: SYNC/comptY_reg[6]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 6.945ns (logic 1.058ns (15.233%) route 5.887ns (84.767%)) Logic Levels: 3 (LUT5=1 LUT6=2) Clock Path Skew: -0.032ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.488ns = ( 41.488 - 40.000 ) Source Clock Delay (SCD): 1.659ns Clock Pessimism Removal (CPR): 0.139ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.656 1.659 SYNC/clk_out1 SLICE_X19Y26 FDRE r SYNC/comptY_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X19Y26 FDRE (Prop_fdre_C_Q) 0.456 2.115 r SYNC/comptY_reg[9]/Q net (fo=10, routed) 2.756 4.871 SYNC/comptY_reg__0[9] SLICE_X28Y23 LUT5 (Prop_lut5_I0_O) 0.150 5.021 r SYNC/comptY[9]_i_9/O net (fo=1, routed) 0.989 6.010 SYNC/comptY[9]_i_9_n_0 SLICE_X29Y25 LUT6 (Prop_lut6_I0_O) 0.328 6.338 r SYNC/comptY[9]_i_5/O net (fo=1, routed) 0.845 7.183 SYNC/comptY[9]_i_5_n_0 SLICE_X29Y25 LUT6 (Prop_lut6_I5_O) 0.124 7.307 r SYNC/comptY[9]_i_1/O net (fo=10, routed) 1.298 8.604 SYNC/comptY SLICE_X18Y26 FDRE r SYNC/comptY_reg[6]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.485 41.488 SYNC/clk_out1 SLICE_X18Y26 FDRE r SYNC/comptY_reg[6]/C clock pessimism 0.139 41.627 clock uncertainty -0.160 41.467 SLICE_X18Y26 FDRE (Setup_fdre_C_R) -0.429 41.038 SYNC/comptY_reg[6] ------------------------------------------------------------------- required time 41.038 arrival time -8.604 ------------------------------------------------------------------- slack 32.433 Slack (MET) : 32.460ns (required time - arrival time) Source: SYNC/comptY_reg[9]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: SYNC/comptY_reg[7]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 6.941ns (logic 1.058ns (15.243%) route 5.883ns (84.757%)) Logic Levels: 3 (LUT5=1 LUT6=2) Clock Path Skew: -0.010ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.488ns = ( 41.488 - 40.000 ) Source Clock Delay (SCD): 1.659ns Clock Pessimism Removal (CPR): 0.161ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.656 1.659 SYNC/clk_out1 SLICE_X19Y26 FDRE r SYNC/comptY_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X19Y26 FDRE (Prop_fdre_C_Q) 0.456 2.115 r SYNC/comptY_reg[9]/Q net (fo=10, routed) 2.756 4.871 SYNC/comptY_reg__0[9] SLICE_X28Y23 LUT5 (Prop_lut5_I0_O) 0.150 5.021 r SYNC/comptY[9]_i_9/O net (fo=1, routed) 0.989 6.010 SYNC/comptY[9]_i_9_n_0 SLICE_X29Y25 LUT6 (Prop_lut6_I0_O) 0.328 6.338 r SYNC/comptY[9]_i_5/O net (fo=1, routed) 0.845 7.183 SYNC/comptY[9]_i_5_n_0 SLICE_X29Y25 LUT6 (Prop_lut6_I5_O) 0.124 7.307 r SYNC/comptY[9]_i_1/O net (fo=10, routed) 1.293 8.600 SYNC/comptY SLICE_X19Y26 FDRE r SYNC/comptY_reg[7]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.485 41.488 SYNC/clk_out1 SLICE_X19Y26 FDRE r SYNC/comptY_reg[7]/C clock pessimism 0.161 41.649 clock uncertainty -0.160 41.489 SLICE_X19Y26 FDRE (Setup_fdre_C_R) -0.429 41.060 SYNC/comptY_reg[7] ------------------------------------------------------------------- required time 41.060 arrival time -8.600 ------------------------------------------------------------------- slack 32.460 Slack (MET) : 32.460ns (required time - arrival time) Source: SYNC/comptY_reg[9]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: SYNC/comptY_reg[8]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 6.941ns (logic 1.058ns (15.243%) route 5.883ns (84.757%)) Logic Levels: 3 (LUT5=1 LUT6=2) Clock Path Skew: -0.010ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.488ns = ( 41.488 - 40.000 ) Source Clock Delay (SCD): 1.659ns Clock Pessimism Removal (CPR): 0.161ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.656 1.659 SYNC/clk_out1 SLICE_X19Y26 FDRE r SYNC/comptY_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X19Y26 FDRE (Prop_fdre_C_Q) 0.456 2.115 r SYNC/comptY_reg[9]/Q net (fo=10, routed) 2.756 4.871 SYNC/comptY_reg__0[9] SLICE_X28Y23 LUT5 (Prop_lut5_I0_O) 0.150 5.021 r SYNC/comptY[9]_i_9/O net (fo=1, routed) 0.989 6.010 SYNC/comptY[9]_i_9_n_0 SLICE_X29Y25 LUT6 (Prop_lut6_I0_O) 0.328 6.338 r SYNC/comptY[9]_i_5/O net (fo=1, routed) 0.845 7.183 SYNC/comptY[9]_i_5_n_0 SLICE_X29Y25 LUT6 (Prop_lut6_I5_O) 0.124 7.307 r SYNC/comptY[9]_i_1/O net (fo=10, routed) 1.293 8.600 SYNC/comptY SLICE_X19Y26 FDRE r SYNC/comptY_reg[8]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.485 41.488 SYNC/clk_out1 SLICE_X19Y26 FDRE r SYNC/comptY_reg[8]/C clock pessimism 0.161 41.649 clock uncertainty -0.160 41.489 SLICE_X19Y26 FDRE (Setup_fdre_C_R) -0.429 41.060 SYNC/comptY_reg[8] ------------------------------------------------------------------- required time 41.060 arrival time -8.600 ------------------------------------------------------------------- slack 32.460 Slack (MET) : 32.460ns (required time - arrival time) Source: SYNC/comptY_reg[9]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: SYNC/comptY_reg[9]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 6.941ns (logic 1.058ns (15.243%) route 5.883ns (84.757%)) Logic Levels: 3 (LUT5=1 LUT6=2) Clock Path Skew: -0.010ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.488ns = ( 41.488 - 40.000 ) Source Clock Delay (SCD): 1.659ns Clock Pessimism Removal (CPR): 0.161ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.656 1.659 SYNC/clk_out1 SLICE_X19Y26 FDRE r SYNC/comptY_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X19Y26 FDRE (Prop_fdre_C_Q) 0.456 2.115 r SYNC/comptY_reg[9]/Q net (fo=10, routed) 2.756 4.871 SYNC/comptY_reg__0[9] SLICE_X28Y23 LUT5 (Prop_lut5_I0_O) 0.150 5.021 r SYNC/comptY[9]_i_9/O net (fo=1, routed) 0.989 6.010 SYNC/comptY[9]_i_9_n_0 SLICE_X29Y25 LUT6 (Prop_lut6_I0_O) 0.328 6.338 r SYNC/comptY[9]_i_5/O net (fo=1, routed) 0.845 7.183 SYNC/comptY[9]_i_5_n_0 SLICE_X29Y25 LUT6 (Prop_lut6_I5_O) 0.124 7.307 r SYNC/comptY[9]_i_1/O net (fo=10, routed) 1.293 8.600 SYNC/comptY SLICE_X19Y26 FDRE r SYNC/comptY_reg[9]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.485 41.488 SYNC/clk_out1 SLICE_X19Y26 FDRE r SYNC/comptY_reg[9]/C clock pessimism 0.161 41.649 clock uncertainty -0.160 41.489 SLICE_X19Y26 FDRE (Setup_fdre_C_R) -0.429 41.060 SYNC/comptY_reg[9] ------------------------------------------------------------------- required time 41.060 arrival time -8.600 ------------------------------------------------------------------- slack 32.460 Slack (MET) : 32.771ns (required time - arrival time) Source: SYNC/comptY_reg[9]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: SYNC/comptY_reg[1]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 6.605ns (logic 1.058ns (16.017%) route 5.547ns (83.983%)) Logic Levels: 3 (LUT5=1 LUT6=2) Clock Path Skew: -0.034ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.486ns = ( 41.486 - 40.000 ) Source Clock Delay (SCD): 1.659ns Clock Pessimism Removal (CPR): 0.139ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.656 1.659 SYNC/clk_out1 SLICE_X19Y26 FDRE r SYNC/comptY_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X19Y26 FDRE (Prop_fdre_C_Q) 0.456 2.115 r SYNC/comptY_reg[9]/Q net (fo=10, routed) 2.756 4.871 SYNC/comptY_reg__0[9] SLICE_X28Y23 LUT5 (Prop_lut5_I0_O) 0.150 5.021 r SYNC/comptY[9]_i_9/O net (fo=1, routed) 0.989 6.010 SYNC/comptY[9]_i_9_n_0 SLICE_X29Y25 LUT6 (Prop_lut6_I0_O) 0.328 6.338 r SYNC/comptY[9]_i_5/O net (fo=1, routed) 0.845 7.183 SYNC/comptY[9]_i_5_n_0 SLICE_X29Y25 LUT6 (Prop_lut6_I5_O) 0.124 7.307 r SYNC/comptY[9]_i_1/O net (fo=10, routed) 0.958 8.264 SYNC/comptY SLICE_X19Y25 FDRE r SYNC/comptY_reg[1]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.483 41.486 SYNC/clk_out1 SLICE_X19Y25 FDRE r SYNC/comptY_reg[1]/C clock pessimism 0.139 41.625 clock uncertainty -0.160 41.465 SLICE_X19Y25 FDRE (Setup_fdre_C_R) -0.429 41.036 SYNC/comptY_reg[1] ------------------------------------------------------------------- required time 41.036 arrival time -8.264 ------------------------------------------------------------------- slack 32.771 Slack (MET) : 32.771ns (required time - arrival time) Source: SYNC/comptY_reg[9]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: SYNC/comptY_reg[2]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 6.605ns (logic 1.058ns (16.017%) route 5.547ns (83.983%)) Logic Levels: 3 (LUT5=1 LUT6=2) Clock Path Skew: -0.034ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.486ns = ( 41.486 - 40.000 ) Source Clock Delay (SCD): 1.659ns Clock Pessimism Removal (CPR): 0.139ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.656 1.659 SYNC/clk_out1 SLICE_X19Y26 FDRE r SYNC/comptY_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X19Y26 FDRE (Prop_fdre_C_Q) 0.456 2.115 r SYNC/comptY_reg[9]/Q net (fo=10, routed) 2.756 4.871 SYNC/comptY_reg__0[9] SLICE_X28Y23 LUT5 (Prop_lut5_I0_O) 0.150 5.021 r SYNC/comptY[9]_i_9/O net (fo=1, routed) 0.989 6.010 SYNC/comptY[9]_i_9_n_0 SLICE_X29Y25 LUT6 (Prop_lut6_I0_O) 0.328 6.338 r SYNC/comptY[9]_i_5/O net (fo=1, routed) 0.845 7.183 SYNC/comptY[9]_i_5_n_0 SLICE_X29Y25 LUT6 (Prop_lut6_I5_O) 0.124 7.307 r SYNC/comptY[9]_i_1/O net (fo=10, routed) 0.958 8.264 SYNC/comptY SLICE_X19Y25 FDRE r SYNC/comptY_reg[2]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.483 41.486 SYNC/clk_out1 SLICE_X19Y25 FDRE r SYNC/comptY_reg[2]/C clock pessimism 0.139 41.625 clock uncertainty -0.160 41.465 SLICE_X19Y25 FDRE (Setup_fdre_C_R) -0.429 41.036 SYNC/comptY_reg[2] ------------------------------------------------------------------- required time 41.036 arrival time -8.264 ------------------------------------------------------------------- slack 32.771 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.218ns (arrival time - required time) Source: SYNC/comptX_reg[4]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: SYNC/comptX_reg[5]/D (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 0.310ns (logic 0.227ns (73.156%) route 0.083ns (26.844%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.821ns Source Clock Delay (SCD): 0.555ns Clock Pessimism Removal (CPR): 0.266ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.548 0.548 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.053 -0.506 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -0.024 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.002 r U0/inst/clkout1_buf/O net (fo=60, routed) 0.553 0.555 SYNC/clk_out1 SLICE_X29Y21 FDRE r SYNC/comptX_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X29Y21 FDRE (Prop_fdre_C_Q) 0.128 0.683 r SYNC/comptX_reg[4]/Q net (fo=10, routed) 0.083 0.766 SYNC/comptX_reg__0[4] SLICE_X29Y21 LUT6 (Prop_lut6_I0_O) 0.099 0.865 r SYNC/comptX[5]_i_1/O net (fo=1, routed) 0.000 0.865 SYNC/p_0_in[5] SLICE_X29Y21 FDRE r SYNC/comptX_reg[5]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O net (fo=60, routed) 0.819 0.821 SYNC/clk_out1 SLICE_X29Y21 FDRE r SYNC/comptX_reg[5]/C clock pessimism -0.266 0.555 SLICE_X29Y21 FDRE (Hold_fdre_C_D) 0.092 0.647 SYNC/comptX_reg[5] ------------------------------------------------------------------- required time -0.647 arrival time 0.865 ------------------------------------------------------------------- slack 0.218 Slack (MET) : 0.265ns (arrival time - required time) Source: SNAKE/startUpdate_reg/C (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: SNAKE/startUpdate_reg/D (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 0.356ns (logic 0.186ns (52.178%) route 0.170ns (47.822%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.830ns Source Clock Delay (SCD): 0.562ns Clock Pessimism Removal (CPR): 0.268ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.548 0.548 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.053 -0.506 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -0.024 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.002 r U0/inst/clkout1_buf/O net (fo=60, routed) 0.560 0.562 SNAKE/clk_out1 SLICE_X23Y44 FDCE r SNAKE/startUpdate_reg/C ------------------------------------------------------------------- ------------------- SLICE_X23Y44 FDCE (Prop_fdce_C_Q) 0.141 0.703 r SNAKE/startUpdate_reg/Q net (fo=4, routed) 0.170 0.873 SNAKE/startUpdate SLICE_X23Y44 LUT2 (Prop_lut2_I1_O) 0.045 0.918 r SNAKE/startUpdate_i_1/O net (fo=1, routed) 0.000 0.918 SNAKE/startUpdate_i_1_n_0 SLICE_X23Y44 FDCE r SNAKE/startUpdate_reg/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O net (fo=60, routed) 0.828 0.830 SNAKE/clk_out1 SLICE_X23Y44 FDCE r SNAKE/startUpdate_reg/C clock pessimism -0.268 0.562 SLICE_X23Y44 FDCE (Hold_fdce_C_D) 0.091 0.653 SNAKE/startUpdate_reg ------------------------------------------------------------------- required time -0.653 arrival time 0.918 ------------------------------------------------------------------- slack 0.265 Slack (MET) : 0.281ns (arrival time - required time) Source: UPD_CLK_DIV/temp_reg[22]/C (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: UPD_CLK_DIV/temp_reg[22]/D (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 0.386ns (logic 0.252ns (65.354%) route 0.134ns (34.646%)) Logic Levels: 1 (CARRY4=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.849ns Source Clock Delay (SCD): 0.582ns Clock Pessimism Removal (CPR): 0.267ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.548 0.548 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.053 -0.506 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -0.024 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.002 r U0/inst/clkout1_buf/O net (fo=60, routed) 0.580 0.582 UPD_CLK_DIV/clk_out1 SLICE_X40Y72 FDCE r UPD_CLK_DIV/temp_reg[22]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y72 FDCE (Prop_fdce_C_Q) 0.141 0.723 r UPD_CLK_DIV/temp_reg[22]/Q net (fo=4, routed) 0.134 0.856 UPD_CLK_DIV/temp_reg[22] SLICE_X40Y72 CARRY4 (Prop_carry4_S[2]_O[2]) 0.111 0.967 r UPD_CLK_DIV/temp_reg[20]_i_1/O[2] net (fo=1, routed) 0.000 0.967 UPD_CLK_DIV/temp_reg[20]_i_1_n_5 SLICE_X40Y72 FDCE r UPD_CLK_DIV/temp_reg[22]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O net (fo=60, routed) 0.847 0.849 UPD_CLK_DIV/clk_out1 SLICE_X40Y72 FDCE r UPD_CLK_DIV/temp_reg[22]/C clock pessimism -0.267 0.582 SLICE_X40Y72 FDCE (Hold_fdce_C_D) 0.105 0.687 UPD_CLK_DIV/temp_reg[22] ------------------------------------------------------------------- required time -0.687 arrival time 0.967 ------------------------------------------------------------------- slack 0.281 Slack (MET) : 0.288ns (arrival time - required time) Source: SYNC/comptY_reg[0]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: SYNC/comptY_reg[0]/D (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 0.379ns (logic 0.186ns (49.124%) route 0.193ns (50.876%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.818ns Source Clock Delay (SCD): 0.553ns Clock Pessimism Removal (CPR): 0.265ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.548 0.548 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.053 -0.506 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -0.024 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.002 r U0/inst/clkout1_buf/O net (fo=60, routed) 0.551 0.553 SYNC/clk_out1 SLICE_X17Y26 FDRE r SYNC/comptY_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X17Y26 FDRE (Prop_fdre_C_Q) 0.141 0.694 f SYNC/comptY_reg[0]/Q net (fo=58, routed) 0.193 0.886 SYNC/comptY_reg__0[0] SLICE_X17Y26 LUT1 (Prop_lut1_I0_O) 0.045 0.931 r SYNC/comptY[0]_i_1/O net (fo=1, routed) 0.000 0.931 SYNC/comptY[0]_i_1_n_0 SLICE_X17Y26 FDRE r SYNC/comptY_reg[0]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O net (fo=60, routed) 0.816 0.818 SYNC/clk_out1 SLICE_X17Y26 FDRE r SYNC/comptY_reg[0]/C clock pessimism -0.265 0.553 SLICE_X17Y26 FDRE (Hold_fdre_C_D) 0.091 0.644 SYNC/comptY_reg[0] ------------------------------------------------------------------- required time -0.644 arrival time 0.931 ------------------------------------------------------------------- slack 0.288 Slack (MET) : 0.292ns (arrival time - required time) Source: UPD_CLK_DIV/temp_reg[14]/C (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: UPD_CLK_DIV/temp_reg[14]/D (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 0.397ns (logic 0.252ns (63.525%) route 0.145ns (36.475%)) Logic Levels: 1 (CARRY4=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.851ns Source Clock Delay (SCD): 0.583ns Clock Pessimism Removal (CPR): 0.268ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.548 0.548 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.053 -0.506 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -0.024 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.002 r U0/inst/clkout1_buf/O net (fo=60, routed) 0.581 0.583 UPD_CLK_DIV/clk_out1 SLICE_X40Y70 FDCE r UPD_CLK_DIV/temp_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y70 FDCE (Prop_fdce_C_Q) 0.141 0.724 r UPD_CLK_DIV/temp_reg[14]/Q net (fo=4, routed) 0.145 0.868 UPD_CLK_DIV/temp_reg[14] SLICE_X40Y70 CARRY4 (Prop_carry4_S[2]_O[2]) 0.111 0.979 r UPD_CLK_DIV/temp_reg[12]_i_1/O[2] net (fo=1, routed) 0.000 0.979 UPD_CLK_DIV/temp_reg[12]_i_1_n_5 SLICE_X40Y70 FDCE r UPD_CLK_DIV/temp_reg[14]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O net (fo=60, routed) 0.849 0.851 UPD_CLK_DIV/clk_out1 SLICE_X40Y70 FDCE r UPD_CLK_DIV/temp_reg[14]/C clock pessimism -0.268 0.583 SLICE_X40Y70 FDCE (Hold_fdce_C_D) 0.105 0.688 UPD_CLK_DIV/temp_reg[14] ------------------------------------------------------------------- required time -0.688 arrival time 0.979 ------------------------------------------------------------------- slack 0.292 Slack (MET) : 0.292ns (arrival time - required time) Source: UPD_CLK_DIV/temp_reg[18]/C (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: UPD_CLK_DIV/temp_reg[18]/D (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 0.397ns (logic 0.252ns (63.515%) route 0.145ns (36.485%)) Logic Levels: 1 (CARRY4=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.850ns Source Clock Delay (SCD): 0.582ns Clock Pessimism Removal (CPR): 0.268ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.548 0.548 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.053 -0.506 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -0.024 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.002 r U0/inst/clkout1_buf/O net (fo=60, routed) 0.580 0.582 UPD_CLK_DIV/clk_out1 SLICE_X40Y71 FDCE r UPD_CLK_DIV/temp_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y71 FDCE (Prop_fdce_C_Q) 0.141 0.723 r UPD_CLK_DIV/temp_reg[18]/Q net (fo=3, routed) 0.145 0.867 UPD_CLK_DIV/temp_reg[18] SLICE_X40Y71 CARRY4 (Prop_carry4_S[2]_O[2]) 0.111 0.978 r UPD_CLK_DIV/temp_reg[16]_i_1/O[2] net (fo=1, routed) 0.000 0.978 UPD_CLK_DIV/temp_reg[16]_i_1_n_5 SLICE_X40Y71 FDCE r UPD_CLK_DIV/temp_reg[18]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O net (fo=60, routed) 0.848 0.850 UPD_CLK_DIV/clk_out1 SLICE_X40Y71 FDCE r UPD_CLK_DIV/temp_reg[18]/C clock pessimism -0.268 0.582 SLICE_X40Y71 FDCE (Hold_fdce_C_D) 0.105 0.687 UPD_CLK_DIV/temp_reg[18] ------------------------------------------------------------------- required time -0.687 arrival time 0.978 ------------------------------------------------------------------- slack 0.292 Slack (MET) : 0.293ns (arrival time - required time) Source: UPD_CLK_DIV/temp_reg[10]/C (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: UPD_CLK_DIV/temp_reg[10]/D (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 0.398ns (logic 0.252ns (63.360%) route 0.146ns (36.640%)) Logic Levels: 1 (CARRY4=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.852ns Source Clock Delay (SCD): 0.584ns Clock Pessimism Removal (CPR): 0.268ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.548 0.548 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.053 -0.506 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -0.024 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.002 r U0/inst/clkout1_buf/O net (fo=60, routed) 0.582 0.584 UPD_CLK_DIV/clk_out1 SLICE_X40Y69 FDCE r UPD_CLK_DIV/temp_reg[10]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y69 FDCE (Prop_fdce_C_Q) 0.141 0.725 r UPD_CLK_DIV/temp_reg[10]/Q net (fo=3, routed) 0.146 0.870 UPD_CLK_DIV/temp_reg[10] SLICE_X40Y69 CARRY4 (Prop_carry4_S[2]_O[2]) 0.111 0.981 r UPD_CLK_DIV/temp_reg[8]_i_1/O[2] net (fo=1, routed) 0.000 0.981 UPD_CLK_DIV/temp_reg[8]_i_1_n_5 SLICE_X40Y69 FDCE r UPD_CLK_DIV/temp_reg[10]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O net (fo=60, routed) 0.850 0.852 UPD_CLK_DIV/clk_out1 SLICE_X40Y69 FDCE r UPD_CLK_DIV/temp_reg[10]/C clock pessimism -0.268 0.584 SLICE_X40Y69 FDCE (Hold_fdce_C_D) 0.105 0.689 UPD_CLK_DIV/temp_reg[10] ------------------------------------------------------------------- required time -0.689 arrival time 0.981 ------------------------------------------------------------------- slack 0.293 Slack (MET) : 0.314ns (arrival time - required time) Source: UPD_CLK_DIV/temp_reg[22]/C (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: UPD_CLK_DIV/temp_reg[23]/D (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 0.419ns (logic 0.285ns (68.085%) route 0.134ns (31.915%)) Logic Levels: 1 (CARRY4=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.849ns Source Clock Delay (SCD): 0.582ns Clock Pessimism Removal (CPR): 0.267ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.548 0.548 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.053 -0.506 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -0.024 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.002 r U0/inst/clkout1_buf/O net (fo=60, routed) 0.580 0.582 UPD_CLK_DIV/clk_out1 SLICE_X40Y72 FDCE r UPD_CLK_DIV/temp_reg[22]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y72 FDCE (Prop_fdce_C_Q) 0.141 0.723 r UPD_CLK_DIV/temp_reg[22]/Q net (fo=4, routed) 0.134 0.856 UPD_CLK_DIV/temp_reg[22] SLICE_X40Y72 CARRY4 (Prop_carry4_S[2]_O[3]) 0.144 1.000 r UPD_CLK_DIV/temp_reg[20]_i_1/O[3] net (fo=1, routed) 0.000 1.000 UPD_CLK_DIV/temp_reg[20]_i_1_n_4 SLICE_X40Y72 FDCE r UPD_CLK_DIV/temp_reg[23]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O net (fo=60, routed) 0.847 0.849 UPD_CLK_DIV/clk_out1 SLICE_X40Y72 FDCE r UPD_CLK_DIV/temp_reg[23]/C clock pessimism -0.267 0.582 SLICE_X40Y72 FDCE (Hold_fdce_C_D) 0.105 0.687 UPD_CLK_DIV/temp_reg[23] ------------------------------------------------------------------- required time -0.687 arrival time 1.000 ------------------------------------------------------------------- slack 0.314 Slack (MET) : 0.325ns (arrival time - required time) Source: UPD_CLK_DIV/temp_reg[14]/C (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: UPD_CLK_DIV/temp_reg[15]/D (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 0.430ns (logic 0.285ns (66.326%) route 0.145ns (33.674%)) Logic Levels: 1 (CARRY4=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.851ns Source Clock Delay (SCD): 0.583ns Clock Pessimism Removal (CPR): 0.268ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.548 0.548 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.053 -0.506 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -0.024 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.002 r U0/inst/clkout1_buf/O net (fo=60, routed) 0.581 0.583 UPD_CLK_DIV/clk_out1 SLICE_X40Y70 FDCE r UPD_CLK_DIV/temp_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y70 FDCE (Prop_fdce_C_Q) 0.141 0.724 r UPD_CLK_DIV/temp_reg[14]/Q net (fo=4, routed) 0.145 0.868 UPD_CLK_DIV/temp_reg[14] SLICE_X40Y70 CARRY4 (Prop_carry4_S[2]_O[3]) 0.144 1.012 r UPD_CLK_DIV/temp_reg[12]_i_1/O[3] net (fo=1, routed) 0.000 1.012 UPD_CLK_DIV/temp_reg[12]_i_1_n_4 SLICE_X40Y70 FDCE r UPD_CLK_DIV/temp_reg[15]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O net (fo=60, routed) 0.849 0.851 UPD_CLK_DIV/clk_out1 SLICE_X40Y70 FDCE r UPD_CLK_DIV/temp_reg[15]/C clock pessimism -0.268 0.583 SLICE_X40Y70 FDCE (Hold_fdce_C_D) 0.105 0.688 UPD_CLK_DIV/temp_reg[15] ------------------------------------------------------------------- required time -0.688 arrival time 1.012 ------------------------------------------------------------------- slack 0.325 Slack (MET) : 0.325ns (arrival time - required time) Source: UPD_CLK_DIV/temp_reg[18]/C (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: UPD_CLK_DIV/temp_reg[19]/D (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 0.430ns (logic 0.285ns (66.316%) route 0.145ns (33.684%)) Logic Levels: 1 (CARRY4=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.850ns Source Clock Delay (SCD): 0.582ns Clock Pessimism Removal (CPR): 0.268ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.548 0.548 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.053 -0.506 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -0.024 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.002 r U0/inst/clkout1_buf/O net (fo=60, routed) 0.580 0.582 UPD_CLK_DIV/clk_out1 SLICE_X40Y71 FDCE r UPD_CLK_DIV/temp_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y71 FDCE (Prop_fdce_C_Q) 0.141 0.723 r UPD_CLK_DIV/temp_reg[18]/Q net (fo=3, routed) 0.145 0.867 UPD_CLK_DIV/temp_reg[18] SLICE_X40Y71 CARRY4 (Prop_carry4_S[2]_O[3]) 0.144 1.011 r UPD_CLK_DIV/temp_reg[16]_i_1/O[3] net (fo=1, routed) 0.000 1.011 UPD_CLK_DIV/temp_reg[16]_i_1_n_4 SLICE_X40Y71 FDCE r UPD_CLK_DIV/temp_reg[19]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O net (fo=60, routed) 0.848 0.850 UPD_CLK_DIV/clk_out1 SLICE_X40Y71 FDCE r UPD_CLK_DIV/temp_reg[19]/C clock pessimism -0.268 0.582 SLICE_X40Y71 FDCE (Hold_fdce_C_D) 0.105 0.687 UPD_CLK_DIV/temp_reg[19] ------------------------------------------------------------------- required time -0.687 arrival time 1.011 ------------------------------------------------------------------- slack 0.325 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk_out1_clk_wiz_1 Waveform(ns): { 0.000 20.000 } Period(ns): 40.000 Sources: { U0/inst/mmcm_adv_inst/CLKOUT0 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFG/I n/a 2.155 40.000 37.845 BUFGCTRL_X0Y0 U0/inst/clkout1_buf/I Min Period n/a MMCME2_ADV/CLKOUT0 n/a 1.249 40.000 38.751 MMCME2_ADV_X0Y0 U0/inst/mmcm_adv_inst/CLKOUT0 Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X27Y24 SYNC/comptX_reg[0]/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X27Y20 SYNC/comptX_reg[10]/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X27Y24 SYNC/comptX_reg[1]/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X29Y21 SYNC/comptX_reg[2]/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X28Y23 SYNC/comptX_reg[3]/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X29Y21 SYNC/comptX_reg[4]/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X29Y21 SYNC/comptX_reg[5]/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X29Y21 SYNC/comptX_reg[6]/C Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 40.000 173.360 MMCME2_ADV_X0Y0 U0/inst/mmcm_adv_inst/CLKOUT0 Low Pulse Width Fast FDCE/C n/a 0.500 20.000 19.500 SLICE_X40Y70 UPD_CLK_DIV/temp_reg[12]/C Low Pulse Width Fast FDCE/C n/a 0.500 20.000 19.500 SLICE_X40Y70 UPD_CLK_DIV/temp_reg[13]/C Low Pulse Width Fast FDCE/C n/a 0.500 20.000 19.500 SLICE_X40Y70 UPD_CLK_DIV/temp_reg[14]/C Low Pulse Width Fast FDCE/C n/a 0.500 20.000 19.500 SLICE_X40Y70 UPD_CLK_DIV/temp_reg[15]/C Low Pulse Width Fast FDCE/C n/a 0.500 20.000 19.500 SLICE_X40Y71 UPD_CLK_DIV/temp_reg[16]/C Low Pulse Width Fast FDCE/C n/a 0.500 20.000 19.500 SLICE_X40Y71 UPD_CLK_DIV/temp_reg[17]/C Low Pulse Width Fast FDCE/C n/a 0.500 20.000 19.500 SLICE_X40Y71 UPD_CLK_DIV/temp_reg[18]/C Low Pulse Width Fast FDCE/C n/a 0.500 20.000 19.500 SLICE_X40Y71 UPD_CLK_DIV/temp_reg[19]/C Low Pulse Width Fast FDCE/C n/a 0.500 20.000 19.500 SLICE_X40Y68 UPD_CLK_DIV/temp_reg[4]/C Low Pulse Width Fast FDCE/C n/a 0.500 20.000 19.500 SLICE_X40Y68 UPD_CLK_DIV/temp_reg[5]/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X27Y24 SYNC/comptX_reg[0]/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X27Y20 SYNC/comptX_reg[10]/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X27Y24 SYNC/comptX_reg[1]/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X29Y21 SYNC/comptX_reg[2]/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X28Y23 SYNC/comptX_reg[3]/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X29Y21 SYNC/comptX_reg[4]/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X29Y21 SYNC/comptX_reg[5]/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X29Y21 SYNC/comptX_reg[6]/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X27Y21 SYNC/comptX_reg[7]/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X26Y21 SYNC/comptX_reg[8]/C --------------------------------------------------------------------------------------------------- From Clock: clkfbout_clk_wiz_1 To Clock: clkfbout_clk_wiz_1 Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 37.845ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clkfbout_clk_wiz_1 Waveform(ns): { 0.000 20.000 } Period(ns): 40.000 Sources: { U0/inst/mmcm_adv_inst/CLKFBOUT } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFG/I n/a 2.155 40.000 37.845 BUFGCTRL_X0Y1 U0/inst/clkf_buf/I Min Period n/a MMCME2_ADV/CLKFBOUT n/a 1.249 40.000 38.751 MMCME2_ADV_X0Y0 U0/inst/mmcm_adv_inst/CLKFBOUT Min Period n/a MMCME2_ADV/CLKFBIN n/a 1.249 40.000 38.751 MMCME2_ADV_X0Y0 U0/inst/mmcm_adv_inst/CLKFBIN Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 40.000 60.000 MMCME2_ADV_X0Y0 U0/inst/mmcm_adv_inst/CLKFBIN Max Period n/a MMCME2_ADV/CLKFBOUT n/a 213.360 40.000 173.360 MMCME2_ADV_X0Y0 U0/inst/mmcm_adv_inst/CLKFBOUT --------------------------------------------------------------------------------------------------- From Clock: sys_clk_pin To Clock: sys_clk_pin Setup : 22 Failing Endpoints, Worst Slack -5.611ns, Total Violation -86.314ns Hold : 0 Failing Endpoints, Worst Slack 0.078ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 3.500ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (VIOLATED) : -5.611ns (required time - arrival time) Source: RAMCTRL/SNAKE_RAM/mem_reg_5_0/CLKBWRCLK (rising edge-triggered cell RAMB36E1 clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: SNAKE/ROMAddress_reg[9]/D (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: sys_clk_pin Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 13.483ns (logic 5.745ns (42.610%) route 7.738ns (57.390%)) Logic Levels: 12 (CARRY4=4 LUT2=2 LUT4=1 LUT6=5) Clock Path Skew: -0.202ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.883ns = ( 12.883 - 8.000 ) Source Clock Delay (SCD): 5.376ns Clock Pessimism Removal (CPR): 0.291ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O net (fo=1, routed) 2.076 3.567 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.707 5.376 RAMCTRL/SNAKE_RAM/H125MHz RAMB36_X1Y6 RAMB36E1 r RAMCTRL/SNAKE_RAM/mem_reg_5_0/CLKBWRCLK ------------------------------------------------------------------- ------------------- RAMB36_X1Y6 RAMB36E1 (Prop_ramb36e1_CLKBWRCLK_DOBDO[15]) 2.454 7.830 r RAMCTRL/SNAKE_RAM/mem_reg_5_0/DOBDO[15] net (fo=4, routed) 1.087 8.916 RAMCTRL/SNAKE_RAM/output_reg[4][4] SLICE_X23Y28 LUT2 (Prop_lut2_I0_O) 0.124 9.040 r RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_307/O net (fo=1, routed) 0.000 9.040 SYNC/ROMAddress[7]_i_108_0[1] SLICE_X23Y28 CARRY4 (Prop_carry4_S[1]_O[2]) 0.580 9.620 r SYNC/ROMAddress_reg[7]_i_252/O[2] net (fo=5, routed) 1.352 10.972 RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_40_1[1] SLICE_X22Y28 LUT4 (Prop_lut4_I3_O) 0.302 11.274 r RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_108/O net (fo=1, routed) 0.000 11.274 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_108_n_0 SLICE_X22Y28 CARRY4 (Prop_carry4_S[1]_O[3]) 0.640 11.914 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_40/O[3] net (fo=2, routed) 1.031 12.945 RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_40_n_4 SLICE_X15Y29 LUT6 (Prop_lut6_I0_O) 0.306 13.251 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_214/O net (fo=6, routed) 0.774 14.024 RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_214_n_0 SLICE_X10Y29 LUT2 (Prop_lut2_I1_O) 0.124 14.148 r RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_263/O net (fo=1, routed) 0.793 14.942 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_263_n_0 SLICE_X17Y28 LUT6 (Prop_lut6_I2_O) 0.124 15.066 r RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_128/O net (fo=1, routed) 0.658 15.724 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_128_n_0 SLICE_X16Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.848 f RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_46/O net (fo=1, routed) 0.559 16.407 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_46_n_0 SLICE_X16Y29 LUT6 (Prop_lut6_I5_O) 0.124 16.531 f RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_15/O net (fo=3, routed) 0.533 17.064 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_15_n_0 SLICE_X16Y29 LUT6 (Prop_lut6_I5_O) 0.124 17.188 r RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_2/O net (fo=1, routed) 0.951 18.139 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_2_n_0 SLICE_X20Y29 CARRY4 (Prop_carry4_DI[3]_CO[3]) 0.396 18.535 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_1/CO[3] net (fo=1, routed) 0.000 18.535 RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_1_n_0 SLICE_X20Y30 CARRY4 (Prop_carry4_CI_O[1]) 0.323 18.858 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_2/O[1] net (fo=1, routed) 0.000 18.858 SNAKE/D[9] SLICE_X20Y30 FDRE r SNAKE/ROMAddress_reg[9]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 8.000 8.000 r L16 0.000 8.000 r H125MHz (IN) net (fo=0) 0.000 8.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O net (fo=1, routed) 1.880 11.301 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.491 12.883 SNAKE/H125MHz SLICE_X20Y30 FDRE r SNAKE/ROMAddress_reg[9]/C clock pessimism 0.291 13.174 clock uncertainty -0.035 13.138 SLICE_X20Y30 FDRE (Setup_fdre_C_D) 0.109 13.247 SNAKE/ROMAddress_reg[9] ------------------------------------------------------------------- required time 13.247 arrival time -18.858 ------------------------------------------------------------------- slack -5.611 Slack (VIOLATED) : -5.507ns (required time - arrival time) Source: RAMCTRL/SNAKE_RAM/mem_reg_5_0/CLKBWRCLK (rising edge-triggered cell RAMB36E1 clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: SNAKE/ROMAddress_reg[8]/D (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: sys_clk_pin Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 13.379ns (logic 5.641ns (42.164%) route 7.738ns (57.836%)) Logic Levels: 12 (CARRY4=4 LUT2=2 LUT4=1 LUT6=5) Clock Path Skew: -0.202ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.883ns = ( 12.883 - 8.000 ) Source Clock Delay (SCD): 5.376ns Clock Pessimism Removal (CPR): 0.291ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O net (fo=1, routed) 2.076 3.567 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.707 5.376 RAMCTRL/SNAKE_RAM/H125MHz RAMB36_X1Y6 RAMB36E1 r RAMCTRL/SNAKE_RAM/mem_reg_5_0/CLKBWRCLK ------------------------------------------------------------------- ------------------- RAMB36_X1Y6 RAMB36E1 (Prop_ramb36e1_CLKBWRCLK_DOBDO[15]) 2.454 7.830 r RAMCTRL/SNAKE_RAM/mem_reg_5_0/DOBDO[15] net (fo=4, routed) 1.087 8.916 RAMCTRL/SNAKE_RAM/output_reg[4][4] SLICE_X23Y28 LUT2 (Prop_lut2_I0_O) 0.124 9.040 r RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_307/O net (fo=1, routed) 0.000 9.040 SYNC/ROMAddress[7]_i_108_0[1] SLICE_X23Y28 CARRY4 (Prop_carry4_S[1]_O[2]) 0.580 9.620 r SYNC/ROMAddress_reg[7]_i_252/O[2] net (fo=5, routed) 1.352 10.972 RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_40_1[1] SLICE_X22Y28 LUT4 (Prop_lut4_I3_O) 0.302 11.274 r RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_108/O net (fo=1, routed) 0.000 11.274 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_108_n_0 SLICE_X22Y28 CARRY4 (Prop_carry4_S[1]_O[3]) 0.640 11.914 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_40/O[3] net (fo=2, routed) 1.031 12.945 RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_40_n_4 SLICE_X15Y29 LUT6 (Prop_lut6_I0_O) 0.306 13.251 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_214/O net (fo=6, routed) 0.774 14.024 RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_214_n_0 SLICE_X10Y29 LUT2 (Prop_lut2_I1_O) 0.124 14.148 r RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_263/O net (fo=1, routed) 0.793 14.942 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_263_n_0 SLICE_X17Y28 LUT6 (Prop_lut6_I2_O) 0.124 15.066 r RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_128/O net (fo=1, routed) 0.658 15.724 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_128_n_0 SLICE_X16Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.848 f RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_46/O net (fo=1, routed) 0.559 16.407 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_46_n_0 SLICE_X16Y29 LUT6 (Prop_lut6_I5_O) 0.124 16.531 f RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_15/O net (fo=3, routed) 0.533 17.064 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_15_n_0 SLICE_X16Y29 LUT6 (Prop_lut6_I5_O) 0.124 17.188 r RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_2/O net (fo=1, routed) 0.951 18.139 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_2_n_0 SLICE_X20Y29 CARRY4 (Prop_carry4_DI[3]_CO[3]) 0.396 18.535 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_1/CO[3] net (fo=1, routed) 0.000 18.535 RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_1_n_0 SLICE_X20Y30 CARRY4 (Prop_carry4_CI_O[0]) 0.219 18.754 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_2/O[0] net (fo=1, routed) 0.000 18.754 SNAKE/D[8] SLICE_X20Y30 FDRE r SNAKE/ROMAddress_reg[8]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 8.000 8.000 r L16 0.000 8.000 r H125MHz (IN) net (fo=0) 0.000 8.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O net (fo=1, routed) 1.880 11.301 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.491 12.883 SNAKE/H125MHz SLICE_X20Y30 FDRE r SNAKE/ROMAddress_reg[8]/C clock pessimism 0.291 13.174 clock uncertainty -0.035 13.138 SLICE_X20Y30 FDRE (Setup_fdre_C_D) 0.109 13.247 SNAKE/ROMAddress_reg[8] ------------------------------------------------------------------- required time 13.247 arrival time -18.754 ------------------------------------------------------------------- slack -5.507 Slack (VIOLATED) : -4.950ns (required time - arrival time) Source: RAMCTRL/SNAKE_RAM/mem_reg_7_0/CLKBWRCLK (rising edge-triggered cell RAMB36E1 clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: SNAKE/ROMAddress_reg[5]/D (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: sys_clk_pin Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 12.824ns (logic 5.086ns (39.661%) route 7.738ns (60.339%)) Logic Levels: 12 (CARRY4=4 LUT3=1 LUT5=2 LUT6=5) Clock Path Skew: -0.200ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.883ns = ( 12.883 - 8.000 ) Source Clock Delay (SCD): 5.374ns Clock Pessimism Removal (CPR): 0.291ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O net (fo=1, routed) 2.076 3.567 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.705 5.374 RAMCTRL/SNAKE_RAM/H125MHz RAMB36_X2Y4 RAMB36E1 r RAMCTRL/SNAKE_RAM/mem_reg_7_0/CLKBWRCLK ------------------------------------------------------------------- ------------------- RAMB36_X2Y4 RAMB36E1 (Prop_ramb36e1_CLKBWRCLK_DOBDO[8]) 2.454 7.828 f RAMCTRL/SNAKE_RAM/mem_reg_7_0/DOBDO[8] net (fo=17, routed) 1.255 9.083 RAMCTRL/SNAKE_RAM/output_reg[6][2] SLICE_X31Y24 LUT3 (Prop_lut3_I1_O) 0.124 9.207 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_630/O net (fo=4, routed) 1.037 10.243 RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_630_n_0 SLICE_X25Y25 LUT5 (Prop_lut5_I3_O) 0.124 10.367 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_626/O net (fo=1, routed) 0.000 10.367 RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_626_n_0 SLICE_X25Y25 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.401 10.768 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_330/CO[3] net (fo=1, routed) 0.000 10.768 RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_330_n_0 SLICE_X25Y26 CARRY4 (Prop_carry4_CI_CO[0]) 0.271 11.039 f RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_114/CO[0] net (fo=1, routed) 0.820 11.859 RAMCTRL/SNAKE_RAM/SNAKE/snakeHere36_in SLICE_X25Y27 LUT5 (Prop_lut5_I2_O) 0.373 12.232 f RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_35/O net (fo=13, routed) 0.982 13.214 RAMCTRL/SNAKE_RAM/mem_reg_7_0_4 SLICE_X25Y27 LUT6 (Prop_lut6_I5_O) 0.124 13.338 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_10/O net (fo=10, routed) 0.705 14.043 RAMCTRL/SNAKE_RAM/mem_reg_8_0_4 SLICE_X25Y30 LUT6 (Prop_lut6_I2_O) 0.124 14.167 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_72/O net (fo=1, routed) 0.593 14.760 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_72_n_0 SLICE_X24Y29 LUT6 (Prop_lut6_I4_O) 0.124 14.884 f RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_27/O net (fo=2, routed) 0.761 15.645 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_27_n_0 SLICE_X19Y27 LUT6 (Prop_lut6_I3_O) 0.124 15.769 f RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_10/O net (fo=1, routed) 0.714 16.483 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_10_n_0 SLICE_X19Y28 LUT6 (Prop_lut6_I0_O) 0.124 16.607 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_2/O net (fo=1, routed) 0.871 17.479 RAMCTRL/SNAKE_RAM/SNAKE/p_11_out[3] SLICE_X20Y28 CARRY4 (Prop_carry4_DI[3]_CO[3]) 0.396 17.875 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_1/CO[3] net (fo=1, routed) 0.000 17.875 RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_1_n_0 SLICE_X20Y29 CARRY4 (Prop_carry4_CI_O[1]) 0.323 18.198 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_1/O[1] net (fo=1, routed) 0.000 18.198 SNAKE/D[5] SLICE_X20Y29 FDRE r SNAKE/ROMAddress_reg[5]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 8.000 8.000 r L16 0.000 8.000 r H125MHz (IN) net (fo=0) 0.000 8.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O net (fo=1, routed) 1.880 11.301 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.491 12.883 SNAKE/H125MHz SLICE_X20Y29 FDRE r SNAKE/ROMAddress_reg[5]/C clock pessimism 0.291 13.174 clock uncertainty -0.035 13.138 SLICE_X20Y29 FDRE (Setup_fdre_C_D) 0.109 13.247 SNAKE/ROMAddress_reg[5] ------------------------------------------------------------------- required time 13.247 arrival time -18.198 ------------------------------------------------------------------- slack -4.950 Slack (VIOLATED) : -4.942ns (required time - arrival time) Source: RAMCTRL/SNAKE_RAM/mem_reg_7_0/CLKBWRCLK (rising edge-triggered cell RAMB36E1 clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: SNAKE/ROMAddress_reg[7]/D (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: sys_clk_pin Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 12.816ns (logic 5.078ns (39.623%) route 7.738ns (60.377%)) Logic Levels: 12 (CARRY4=4 LUT3=1 LUT5=2 LUT6=5) Clock Path Skew: -0.200ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.883ns = ( 12.883 - 8.000 ) Source Clock Delay (SCD): 5.374ns Clock Pessimism Removal (CPR): 0.291ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O net (fo=1, routed) 2.076 3.567 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.705 5.374 RAMCTRL/SNAKE_RAM/H125MHz RAMB36_X2Y4 RAMB36E1 r RAMCTRL/SNAKE_RAM/mem_reg_7_0/CLKBWRCLK ------------------------------------------------------------------- ------------------- RAMB36_X2Y4 RAMB36E1 (Prop_ramb36e1_CLKBWRCLK_DOBDO[8]) 2.454 7.828 f RAMCTRL/SNAKE_RAM/mem_reg_7_0/DOBDO[8] net (fo=17, routed) 1.255 9.083 RAMCTRL/SNAKE_RAM/output_reg[6][2] SLICE_X31Y24 LUT3 (Prop_lut3_I1_O) 0.124 9.207 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_630/O net (fo=4, routed) 1.037 10.243 RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_630_n_0 SLICE_X25Y25 LUT5 (Prop_lut5_I3_O) 0.124 10.367 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_626/O net (fo=1, routed) 0.000 10.367 RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_626_n_0 SLICE_X25Y25 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.401 10.768 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_330/CO[3] net (fo=1, routed) 0.000 10.768 RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_330_n_0 SLICE_X25Y26 CARRY4 (Prop_carry4_CI_CO[0]) 0.271 11.039 f RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_114/CO[0] net (fo=1, routed) 0.820 11.859 RAMCTRL/SNAKE_RAM/SNAKE/snakeHere36_in SLICE_X25Y27 LUT5 (Prop_lut5_I2_O) 0.373 12.232 f RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_35/O net (fo=13, routed) 0.982 13.214 RAMCTRL/SNAKE_RAM/mem_reg_7_0_4 SLICE_X25Y27 LUT6 (Prop_lut6_I5_O) 0.124 13.338 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_10/O net (fo=10, routed) 0.705 14.043 RAMCTRL/SNAKE_RAM/mem_reg_8_0_4 SLICE_X25Y30 LUT6 (Prop_lut6_I2_O) 0.124 14.167 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_72/O net (fo=1, routed) 0.593 14.760 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_72_n_0 SLICE_X24Y29 LUT6 (Prop_lut6_I4_O) 0.124 14.884 f RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_27/O net (fo=2, routed) 0.761 15.645 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_27_n_0 SLICE_X19Y27 LUT6 (Prop_lut6_I3_O) 0.124 15.769 f RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_10/O net (fo=1, routed) 0.714 16.483 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_10_n_0 SLICE_X19Y28 LUT6 (Prop_lut6_I0_O) 0.124 16.607 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_2/O net (fo=1, routed) 0.871 17.479 RAMCTRL/SNAKE_RAM/SNAKE/p_11_out[3] SLICE_X20Y28 CARRY4 (Prop_carry4_DI[3]_CO[3]) 0.396 17.875 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_1/CO[3] net (fo=1, routed) 0.000 17.875 RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_1_n_0 SLICE_X20Y29 CARRY4 (Prop_carry4_CI_O[3]) 0.315 18.190 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_1/O[3] net (fo=1, routed) 0.000 18.190 SNAKE/D[7] SLICE_X20Y29 FDRE r SNAKE/ROMAddress_reg[7]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 8.000 8.000 r L16 0.000 8.000 r H125MHz (IN) net (fo=0) 0.000 8.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O net (fo=1, routed) 1.880 11.301 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.491 12.883 SNAKE/H125MHz SLICE_X20Y29 FDRE r SNAKE/ROMAddress_reg[7]/C clock pessimism 0.291 13.174 clock uncertainty -0.035 13.138 SLICE_X20Y29 FDRE (Setup_fdre_C_D) 0.109 13.247 SNAKE/ROMAddress_reg[7] ------------------------------------------------------------------- required time 13.247 arrival time -18.190 ------------------------------------------------------------------- slack -4.942 Slack (VIOLATED) : -4.866ns (required time - arrival time) Source: RAMCTRL/SNAKE_RAM/mem_reg_7_0/CLKBWRCLK (rising edge-triggered cell RAMB36E1 clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: SNAKE/ROMAddress_reg[6]/D (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: sys_clk_pin Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 12.740ns (logic 5.002ns (39.263%) route 7.738ns (60.737%)) Logic Levels: 12 (CARRY4=4 LUT3=1 LUT5=2 LUT6=5) Clock Path Skew: -0.200ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.883ns = ( 12.883 - 8.000 ) Source Clock Delay (SCD): 5.374ns Clock Pessimism Removal (CPR): 0.291ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O net (fo=1, routed) 2.076 3.567 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.705 5.374 RAMCTRL/SNAKE_RAM/H125MHz RAMB36_X2Y4 RAMB36E1 r RAMCTRL/SNAKE_RAM/mem_reg_7_0/CLKBWRCLK ------------------------------------------------------------------- ------------------- RAMB36_X2Y4 RAMB36E1 (Prop_ramb36e1_CLKBWRCLK_DOBDO[8]) 2.454 7.828 f RAMCTRL/SNAKE_RAM/mem_reg_7_0/DOBDO[8] net (fo=17, routed) 1.255 9.083 RAMCTRL/SNAKE_RAM/output_reg[6][2] SLICE_X31Y24 LUT3 (Prop_lut3_I1_O) 0.124 9.207 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_630/O net (fo=4, routed) 1.037 10.243 RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_630_n_0 SLICE_X25Y25 LUT5 (Prop_lut5_I3_O) 0.124 10.367 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_626/O net (fo=1, routed) 0.000 10.367 RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_626_n_0 SLICE_X25Y25 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.401 10.768 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_330/CO[3] net (fo=1, routed) 0.000 10.768 RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_330_n_0 SLICE_X25Y26 CARRY4 (Prop_carry4_CI_CO[0]) 0.271 11.039 f RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_114/CO[0] net (fo=1, routed) 0.820 11.859 RAMCTRL/SNAKE_RAM/SNAKE/snakeHere36_in SLICE_X25Y27 LUT5 (Prop_lut5_I2_O) 0.373 12.232 f RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_35/O net (fo=13, routed) 0.982 13.214 RAMCTRL/SNAKE_RAM/mem_reg_7_0_4 SLICE_X25Y27 LUT6 (Prop_lut6_I5_O) 0.124 13.338 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_10/O net (fo=10, routed) 0.705 14.043 RAMCTRL/SNAKE_RAM/mem_reg_8_0_4 SLICE_X25Y30 LUT6 (Prop_lut6_I2_O) 0.124 14.167 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_72/O net (fo=1, routed) 0.593 14.760 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_72_n_0 SLICE_X24Y29 LUT6 (Prop_lut6_I4_O) 0.124 14.884 f RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_27/O net (fo=2, routed) 0.761 15.645 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_27_n_0 SLICE_X19Y27 LUT6 (Prop_lut6_I3_O) 0.124 15.769 f RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_10/O net (fo=1, routed) 0.714 16.483 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_10_n_0 SLICE_X19Y28 LUT6 (Prop_lut6_I0_O) 0.124 16.607 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_2/O net (fo=1, routed) 0.871 17.479 RAMCTRL/SNAKE_RAM/SNAKE/p_11_out[3] SLICE_X20Y28 CARRY4 (Prop_carry4_DI[3]_CO[3]) 0.396 17.875 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_1/CO[3] net (fo=1, routed) 0.000 17.875 RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_1_n_0 SLICE_X20Y29 CARRY4 (Prop_carry4_CI_O[2]) 0.239 18.114 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_1/O[2] net (fo=1, routed) 0.000 18.114 SNAKE/D[6] SLICE_X20Y29 FDRE r SNAKE/ROMAddress_reg[6]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 8.000 8.000 r L16 0.000 8.000 r H125MHz (IN) net (fo=0) 0.000 8.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O net (fo=1, routed) 1.880 11.301 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.491 12.883 SNAKE/H125MHz SLICE_X20Y29 FDRE r SNAKE/ROMAddress_reg[6]/C clock pessimism 0.291 13.174 clock uncertainty -0.035 13.138 SLICE_X20Y29 FDRE (Setup_fdre_C_D) 0.109 13.247 SNAKE/ROMAddress_reg[6] ------------------------------------------------------------------- required time 13.247 arrival time -18.114 ------------------------------------------------------------------- slack -4.866 Slack (VIOLATED) : -4.846ns (required time - arrival time) Source: RAMCTRL/SNAKE_RAM/mem_reg_7_0/CLKBWRCLK (rising edge-triggered cell RAMB36E1 clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: SNAKE/ROMAddress_reg[4]/D (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: sys_clk_pin Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 12.720ns (logic 4.982ns (39.167%) route 7.738ns (60.833%)) Logic Levels: 12 (CARRY4=4 LUT3=1 LUT5=2 LUT6=5) Clock Path Skew: -0.200ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.883ns = ( 12.883 - 8.000 ) Source Clock Delay (SCD): 5.374ns Clock Pessimism Removal (CPR): 0.291ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O net (fo=1, routed) 2.076 3.567 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.705 5.374 RAMCTRL/SNAKE_RAM/H125MHz RAMB36_X2Y4 RAMB36E1 r RAMCTRL/SNAKE_RAM/mem_reg_7_0/CLKBWRCLK ------------------------------------------------------------------- ------------------- RAMB36_X2Y4 RAMB36E1 (Prop_ramb36e1_CLKBWRCLK_DOBDO[8]) 2.454 7.828 f RAMCTRL/SNAKE_RAM/mem_reg_7_0/DOBDO[8] net (fo=17, routed) 1.255 9.083 RAMCTRL/SNAKE_RAM/output_reg[6][2] SLICE_X31Y24 LUT3 (Prop_lut3_I1_O) 0.124 9.207 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_630/O net (fo=4, routed) 1.037 10.243 RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_630_n_0 SLICE_X25Y25 LUT5 (Prop_lut5_I3_O) 0.124 10.367 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_626/O net (fo=1, routed) 0.000 10.367 RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_626_n_0 SLICE_X25Y25 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.401 10.768 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_330/CO[3] net (fo=1, routed) 0.000 10.768 RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_330_n_0 SLICE_X25Y26 CARRY4 (Prop_carry4_CI_CO[0]) 0.271 11.039 f RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_114/CO[0] net (fo=1, routed) 0.820 11.859 RAMCTRL/SNAKE_RAM/SNAKE/snakeHere36_in SLICE_X25Y27 LUT5 (Prop_lut5_I2_O) 0.373 12.232 f RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_35/O net (fo=13, routed) 0.982 13.214 RAMCTRL/SNAKE_RAM/mem_reg_7_0_4 SLICE_X25Y27 LUT6 (Prop_lut6_I5_O) 0.124 13.338 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_10/O net (fo=10, routed) 0.705 14.043 RAMCTRL/SNAKE_RAM/mem_reg_8_0_4 SLICE_X25Y30 LUT6 (Prop_lut6_I2_O) 0.124 14.167 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_72/O net (fo=1, routed) 0.593 14.760 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_72_n_0 SLICE_X24Y29 LUT6 (Prop_lut6_I4_O) 0.124 14.884 f RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_27/O net (fo=2, routed) 0.761 15.645 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_27_n_0 SLICE_X19Y27 LUT6 (Prop_lut6_I3_O) 0.124 15.769 f RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_10/O net (fo=1, routed) 0.714 16.483 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_10_n_0 SLICE_X19Y28 LUT6 (Prop_lut6_I0_O) 0.124 16.607 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_2/O net (fo=1, routed) 0.871 17.479 RAMCTRL/SNAKE_RAM/SNAKE/p_11_out[3] SLICE_X20Y28 CARRY4 (Prop_carry4_DI[3]_CO[3]) 0.396 17.875 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_1/CO[3] net (fo=1, routed) 0.000 17.875 RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_1_n_0 SLICE_X20Y29 CARRY4 (Prop_carry4_CI_O[0]) 0.219 18.094 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_1/O[0] net (fo=1, routed) 0.000 18.094 SNAKE/D[4] SLICE_X20Y29 FDRE r SNAKE/ROMAddress_reg[4]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 8.000 8.000 r L16 0.000 8.000 r H125MHz (IN) net (fo=0) 0.000 8.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O net (fo=1, routed) 1.880 11.301 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.491 12.883 SNAKE/H125MHz SLICE_X20Y29 FDRE r SNAKE/ROMAddress_reg[4]/C clock pessimism 0.291 13.174 clock uncertainty -0.035 13.138 SLICE_X20Y29 FDRE (Setup_fdre_C_D) 0.109 13.247 SNAKE/ROMAddress_reg[4] ------------------------------------------------------------------- required time 13.247 arrival time -18.094 ------------------------------------------------------------------- slack -4.846 Slack (VIOLATED) : -4.073ns (required time - arrival time) Source: RAMCTRL/SNAKE_RAM/mem_reg_7_0/CLKBWRCLK (rising edge-triggered cell RAMB36E1 clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: SNAKE/ROMAddress_reg[3]/D (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: sys_clk_pin Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 11.945ns (logic 5.010ns (41.941%) route 6.935ns (58.059%)) Logic Levels: 11 (CARRY4=3 LUT3=1 LUT5=2 LUT6=5) Clock Path Skew: -0.201ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.882ns = ( 12.882 - 8.000 ) Source Clock Delay (SCD): 5.374ns Clock Pessimism Removal (CPR): 0.291ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O net (fo=1, routed) 2.076 3.567 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.705 5.374 RAMCTRL/SNAKE_RAM/H125MHz RAMB36_X2Y4 RAMB36E1 r RAMCTRL/SNAKE_RAM/mem_reg_7_0/CLKBWRCLK ------------------------------------------------------------------- ------------------- RAMB36_X2Y4 RAMB36E1 (Prop_ramb36e1_CLKBWRCLK_DOBDO[8]) 2.454 7.828 f RAMCTRL/SNAKE_RAM/mem_reg_7_0/DOBDO[8] net (fo=17, routed) 1.255 9.083 RAMCTRL/SNAKE_RAM/output_reg[6][2] SLICE_X31Y24 LUT3 (Prop_lut3_I1_O) 0.124 9.207 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_630/O net (fo=4, routed) 1.037 10.243 RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_630_n_0 SLICE_X25Y25 LUT5 (Prop_lut5_I3_O) 0.124 10.367 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_626/O net (fo=1, routed) 0.000 10.367 RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_626_n_0 SLICE_X25Y25 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.401 10.768 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_330/CO[3] net (fo=1, routed) 0.000 10.768 RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_330_n_0 SLICE_X25Y26 CARRY4 (Prop_carry4_CI_CO[0]) 0.271 11.039 f RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_114/CO[0] net (fo=1, routed) 0.820 11.859 RAMCTRL/SNAKE_RAM/SNAKE/snakeHere36_in SLICE_X25Y27 LUT5 (Prop_lut5_I2_O) 0.373 12.232 f RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_35/O net (fo=13, routed) 0.982 13.214 RAMCTRL/SNAKE_RAM/mem_reg_7_0_4 SLICE_X25Y27 LUT6 (Prop_lut6_I5_O) 0.124 13.338 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_10/O net (fo=10, routed) 0.533 13.871 RAMCTRL/SNAKE_RAM/mem_reg_8_0_4 SLICE_X18Y27 LUT6 (Prop_lut6_I5_O) 0.124 13.995 f RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_63/O net (fo=1, routed) 0.708 14.703 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_63_n_0 SLICE_X18Y27 LUT6 (Prop_lut6_I3_O) 0.124 14.827 f RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_19/O net (fo=1, routed) 0.736 15.564 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_19_n_0 SLICE_X20Y27 LUT6 (Prop_lut6_I0_O) 0.124 15.688 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_4/O net (fo=2, routed) 0.865 16.552 RAMCTRL/SNAKE_RAM/SNAKE/p_11_out[1] SLICE_X20Y28 LUT6 (Prop_lut6_I0_O) 0.124 16.676 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_8/O net (fo=1, routed) 0.000 16.676 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_8_n_0 SLICE_X20Y28 CARRY4 (Prop_carry4_S[1]_O[3]) 0.643 17.319 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_1/O[3] net (fo=1, routed) 0.000 17.319 SNAKE/D[3] SLICE_X20Y28 FDRE r SNAKE/ROMAddress_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 8.000 8.000 r L16 0.000 8.000 r H125MHz (IN) net (fo=0) 0.000 8.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O net (fo=1, routed) 1.880 11.301 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.490 12.882 SNAKE/H125MHz SLICE_X20Y28 FDRE r SNAKE/ROMAddress_reg[3]/C clock pessimism 0.291 13.173 clock uncertainty -0.035 13.137 SLICE_X20Y28 FDRE (Setup_fdre_C_D) 0.109 13.246 SNAKE/ROMAddress_reg[3] ------------------------------------------------------------------- required time 13.246 arrival time -17.319 ------------------------------------------------------------------- slack -4.073 Slack (VIOLATED) : -4.008ns (required time - arrival time) Source: RAMCTRL/SNAKE_RAM/mem_reg_7_0/CLKBWRCLK (rising edge-triggered cell RAMB36E1 clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: SNAKE/ROMAddress_reg[2]/D (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: sys_clk_pin Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 11.880ns (logic 4.945ns (41.623%) route 6.935ns (58.377%)) Logic Levels: 11 (CARRY4=3 LUT3=1 LUT5=2 LUT6=5) Clock Path Skew: -0.201ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.882ns = ( 12.882 - 8.000 ) Source Clock Delay (SCD): 5.374ns Clock Pessimism Removal (CPR): 0.291ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O net (fo=1, routed) 2.076 3.567 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.705 5.374 RAMCTRL/SNAKE_RAM/H125MHz RAMB36_X2Y4 RAMB36E1 r RAMCTRL/SNAKE_RAM/mem_reg_7_0/CLKBWRCLK ------------------------------------------------------------------- ------------------- RAMB36_X2Y4 RAMB36E1 (Prop_ramb36e1_CLKBWRCLK_DOBDO[8]) 2.454 7.828 f RAMCTRL/SNAKE_RAM/mem_reg_7_0/DOBDO[8] net (fo=17, routed) 1.255 9.083 RAMCTRL/SNAKE_RAM/output_reg[6][2] SLICE_X31Y24 LUT3 (Prop_lut3_I1_O) 0.124 9.207 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_630/O net (fo=4, routed) 1.037 10.243 RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_630_n_0 SLICE_X25Y25 LUT5 (Prop_lut5_I3_O) 0.124 10.367 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_626/O net (fo=1, routed) 0.000 10.367 RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_626_n_0 SLICE_X25Y25 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.401 10.768 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_330/CO[3] net (fo=1, routed) 0.000 10.768 RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_330_n_0 SLICE_X25Y26 CARRY4 (Prop_carry4_CI_CO[0]) 0.271 11.039 f RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_114/CO[0] net (fo=1, routed) 0.820 11.859 RAMCTRL/SNAKE_RAM/SNAKE/snakeHere36_in SLICE_X25Y27 LUT5 (Prop_lut5_I2_O) 0.373 12.232 f RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_35/O net (fo=13, routed) 0.982 13.214 RAMCTRL/SNAKE_RAM/mem_reg_7_0_4 SLICE_X25Y27 LUT6 (Prop_lut6_I5_O) 0.124 13.338 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_10/O net (fo=10, routed) 0.533 13.871 RAMCTRL/SNAKE_RAM/mem_reg_8_0_4 SLICE_X18Y27 LUT6 (Prop_lut6_I5_O) 0.124 13.995 f RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_63/O net (fo=1, routed) 0.708 14.703 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_63_n_0 SLICE_X18Y27 LUT6 (Prop_lut6_I3_O) 0.124 14.827 f RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_19/O net (fo=1, routed) 0.736 15.564 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_19_n_0 SLICE_X20Y27 LUT6 (Prop_lut6_I0_O) 0.124 15.688 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_4/O net (fo=2, routed) 0.865 16.552 RAMCTRL/SNAKE_RAM/SNAKE/p_11_out[1] SLICE_X20Y28 LUT6 (Prop_lut6_I0_O) 0.124 16.676 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_8/O net (fo=1, routed) 0.000 16.676 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_8_n_0 SLICE_X20Y28 CARRY4 (Prop_carry4_S[1]_O[2]) 0.578 17.254 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_1/O[2] net (fo=1, routed) 0.000 17.254 SNAKE/D[2] SLICE_X20Y28 FDRE r SNAKE/ROMAddress_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 8.000 8.000 r L16 0.000 8.000 r H125MHz (IN) net (fo=0) 0.000 8.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O net (fo=1, routed) 1.880 11.301 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.490 12.882 SNAKE/H125MHz SLICE_X20Y28 FDRE r SNAKE/ROMAddress_reg[2]/C clock pessimism 0.291 13.173 clock uncertainty -0.035 13.137 SLICE_X20Y28 FDRE (Setup_fdre_C_D) 0.109 13.246 SNAKE/ROMAddress_reg[2] ------------------------------------------------------------------- required time 13.246 arrival time -17.254 ------------------------------------------------------------------- slack -4.008 Slack (VIOLATED) : -3.881ns (required time - arrival time) Source: RAMCTRL/SNAKE_RAM/mem_reg_4_1/CLKBWRCLK (rising edge-triggered cell RAMB18E1 clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: SNAKE/ROMAddress_reg[4]/CE (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: sys_clk_pin Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 11.467ns (logic 4.091ns (35.675%) route 7.376ns (64.325%)) Logic Levels: 8 (CARRY4=2 LUT3=2 LUT4=1 LUT5=3) Clock Path Skew: -0.209ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.883ns = ( 12.883 - 8.000 ) Source Clock Delay (SCD): 5.383ns Clock Pessimism Removal (CPR): 0.291ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O net (fo=1, routed) 2.076 3.567 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.714 5.383 RAMCTRL/SNAKE_RAM/H125MHz RAMB18_X2Y14 RAMB18E1 r RAMCTRL/SNAKE_RAM/mem_reg_4_1/CLKBWRCLK ------------------------------------------------------------------- ------------------- RAMB18_X2Y14 RAMB18E1 (Prop_ramb18e1_CLKBWRCLK_DOBDO[0]) 2.454 7.837 f RAMCTRL/SNAKE_RAM/mem_reg_4_1/DOBDO[0] net (fo=12, routed) 0.816 8.653 RAMCTRL/SNAKE_RAM/output_reg[3][6] SLICE_X35Y35 LUT3 (Prop_lut3_I0_O) 0.124 8.777 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_363/O net (fo=1, routed) 0.782 9.560 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_363_n_0 SLICE_X35Y32 LUT5 (Prop_lut5_I1_O) 0.124 9.684 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_250/O net (fo=1, routed) 0.629 10.312 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_250_n_0 SLICE_X30Y32 CARRY4 (Prop_carry4_DI[3]_CO[3]) 0.396 10.708 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_114/CO[3] net (fo=1, routed) 0.000 10.708 RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_114_n_0 SLICE_X30Y33 CARRY4 (Prop_carry4_CI_CO[0]) 0.254 10.962 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_45/CO[0] net (fo=3, routed) 1.015 11.977 RAMCTRL/SNAKE_RAM/SNAKE/snakeHere534_in SLICE_X23Y32 LUT5 (Prop_lut5_I2_O) 0.367 12.344 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_21/O net (fo=19, routed) 1.243 13.587 RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_21_n_0 SLICE_X15Y32 LUT4 (Prop_lut4_I0_O) 0.124 13.711 f RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_7/O net (fo=10, routed) 0.963 14.674 RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_7_n_0 SLICE_X18Y34 LUT5 (Prop_lut5_I0_O) 0.124 14.798 f RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_3/O net (fo=2, routed) 0.898 15.696 RAMCTRL/SNAKE_RAM/mem_reg_9_0_4 SLICE_X18Y34 LUT3 (Prop_lut3_I2_O) 0.124 15.820 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_1/O net (fo=10, routed) 1.030 16.850 SNAKE/E[0] SLICE_X20Y29 FDRE r SNAKE/ROMAddress_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 8.000 8.000 r L16 0.000 8.000 r H125MHz (IN) net (fo=0) 0.000 8.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O net (fo=1, routed) 1.880 11.301 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.491 12.883 SNAKE/H125MHz SLICE_X20Y29 FDRE r SNAKE/ROMAddress_reg[4]/C clock pessimism 0.291 13.174 clock uncertainty -0.035 13.138 SLICE_X20Y29 FDRE (Setup_fdre_C_CE) -0.169 12.969 SNAKE/ROMAddress_reg[4] ------------------------------------------------------------------- required time 12.969 arrival time -16.850 ------------------------------------------------------------------- slack -3.881 Slack (VIOLATED) : -3.881ns (required time - arrival time) Source: RAMCTRL/SNAKE_RAM/mem_reg_4_1/CLKBWRCLK (rising edge-triggered cell RAMB18E1 clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: SNAKE/ROMAddress_reg[5]/CE (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: sys_clk_pin Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 11.467ns (logic 4.091ns (35.675%) route 7.376ns (64.325%)) Logic Levels: 8 (CARRY4=2 LUT3=2 LUT4=1 LUT5=3) Clock Path Skew: -0.209ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.883ns = ( 12.883 - 8.000 ) Source Clock Delay (SCD): 5.383ns Clock Pessimism Removal (CPR): 0.291ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O net (fo=1, routed) 2.076 3.567 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.714 5.383 RAMCTRL/SNAKE_RAM/H125MHz RAMB18_X2Y14 RAMB18E1 r RAMCTRL/SNAKE_RAM/mem_reg_4_1/CLKBWRCLK ------------------------------------------------------------------- ------------------- RAMB18_X2Y14 RAMB18E1 (Prop_ramb18e1_CLKBWRCLK_DOBDO[0]) 2.454 7.837 f RAMCTRL/SNAKE_RAM/mem_reg_4_1/DOBDO[0] net (fo=12, routed) 0.816 8.653 RAMCTRL/SNAKE_RAM/output_reg[3][6] SLICE_X35Y35 LUT3 (Prop_lut3_I0_O) 0.124 8.777 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_363/O net (fo=1, routed) 0.782 9.560 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_363_n_0 SLICE_X35Y32 LUT5 (Prop_lut5_I1_O) 0.124 9.684 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_250/O net (fo=1, routed) 0.629 10.312 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_250_n_0 SLICE_X30Y32 CARRY4 (Prop_carry4_DI[3]_CO[3]) 0.396 10.708 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_114/CO[3] net (fo=1, routed) 0.000 10.708 RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_114_n_0 SLICE_X30Y33 CARRY4 (Prop_carry4_CI_CO[0]) 0.254 10.962 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_45/CO[0] net (fo=3, routed) 1.015 11.977 RAMCTRL/SNAKE_RAM/SNAKE/snakeHere534_in SLICE_X23Y32 LUT5 (Prop_lut5_I2_O) 0.367 12.344 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_21/O net (fo=19, routed) 1.243 13.587 RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_21_n_0 SLICE_X15Y32 LUT4 (Prop_lut4_I0_O) 0.124 13.711 f RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_7/O net (fo=10, routed) 0.963 14.674 RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_7_n_0 SLICE_X18Y34 LUT5 (Prop_lut5_I0_O) 0.124 14.798 f RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_3/O net (fo=2, routed) 0.898 15.696 RAMCTRL/SNAKE_RAM/mem_reg_9_0_4 SLICE_X18Y34 LUT3 (Prop_lut3_I2_O) 0.124 15.820 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_1/O net (fo=10, routed) 1.030 16.850 SNAKE/E[0] SLICE_X20Y29 FDRE r SNAKE/ROMAddress_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 8.000 8.000 r L16 0.000 8.000 r H125MHz (IN) net (fo=0) 0.000 8.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O net (fo=1, routed) 1.880 11.301 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.491 12.883 SNAKE/H125MHz SLICE_X20Y29 FDRE r SNAKE/ROMAddress_reg[5]/C clock pessimism 0.291 13.174 clock uncertainty -0.035 13.138 SLICE_X20Y29 FDRE (Setup_fdre_C_CE) -0.169 12.969 SNAKE/ROMAddress_reg[5] ------------------------------------------------------------------- required time 12.969 arrival time -16.850 ------------------------------------------------------------------- slack -3.881 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.078ns (arrival time - required time) Source: UPD/dataOut_reg[13]/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: RAMCTRL/SNAKE_RAM/mem_reg_6_0/DIADI[13] (rising edge-triggered cell RAMB36E1 clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: sys_clk_pin Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 0.429ns (logic 0.141ns (32.829%) route 0.288ns (67.171%)) Logic Levels: 0 Clock Path Skew: 0.055ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.032ns Source Clock Delay (SCD): 1.478ns Clock Pessimism Removal (CPR): 0.499ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O net (fo=1, routed) 0.627 0.886 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.566 1.478 UPD/H125MHz SLICE_X26Y47 FDCE r UPD/dataOut_reg[13]/C ------------------------------------------------------------------- ------------------- SLICE_X26Y47 FDCE (Prop_fdce_C_Q) 0.141 1.619 r UPD/dataOut_reg[13]/Q net (fo=9, routed) 0.288 1.907 RAMCTRL/SNAKE_RAM/updateRAMDataOut[13] RAMB36_X1Y7 RAMB36E1 r RAMCTRL/SNAKE_RAM/mem_reg_6_0/DIADI[13] ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r H125MHz_IBUF_inst/O net (fo=1, routed) 0.683 1.130 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.159 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.873 2.032 RAMCTRL/SNAKE_RAM/H125MHz RAMB36_X1Y7 RAMB36E1 r RAMCTRL/SNAKE_RAM/mem_reg_6_0/CLKARDCLK clock pessimism -0.499 1.533 RAMB36_X1Y7 RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[13]) 0.296 1.829 RAMCTRL/SNAKE_RAM/mem_reg_6_0 ------------------------------------------------------------------- required time -1.829 arrival time 1.907 ------------------------------------------------------------------- slack 0.078 Slack (MET) : 0.088ns (arrival time - required time) Source: UPD/dataOut_reg[1]_P/C (rising edge-triggered cell FDPE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: RAMCTRL/SNAKE_RAM/mem_reg_2_0/DIADI[1] (rising edge-triggered cell RAMB36E1 clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: sys_clk_pin Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 0.443ns (logic 0.186ns (41.977%) route 0.257ns (58.023%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.059ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.025ns Source Clock Delay (SCD): 1.467ns Clock Pessimism Removal (CPR): 0.499ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O net (fo=1, routed) 0.627 0.886 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.555 1.467 UPD/H125MHz SLICE_X7Y25 FDPE r UPD/dataOut_reg[1]_P/C ------------------------------------------------------------------- ------------------- SLICE_X7Y25 FDPE (Prop_fdpe_C_Q) 0.141 1.608 r UPD/dataOut_reg[1]_P/Q net (fo=1, routed) 0.087 1.695 UPD/dataOut_reg[1]_P_n_0 SLICE_X6Y25 LUT3 (Prop_lut3_I0_O) 0.045 1.740 r UPD/mem_reg_1_0_i_3/O net (fo=9, routed) 0.170 1.910 RAMCTRL/SNAKE_RAM/updateRAMDataOut[1] RAMB36_X0Y5 RAMB36E1 r RAMCTRL/SNAKE_RAM/mem_reg_2_0/DIADI[1] ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r H125MHz_IBUF_inst/O net (fo=1, routed) 0.683 1.130 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.159 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.866 2.025 RAMCTRL/SNAKE_RAM/H125MHz RAMB36_X0Y5 RAMB36E1 r RAMCTRL/SNAKE_RAM/mem_reg_2_0/CLKARDCLK clock pessimism -0.499 1.526 RAMB36_X0Y5 RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[1]) 0.296 1.822 RAMCTRL/SNAKE_RAM/mem_reg_2_0 ------------------------------------------------------------------- required time -1.822 arrival time 1.910 ------------------------------------------------------------------- slack 0.088 Slack (MET) : 0.095ns (arrival time - required time) Source: RAMCTRL/clkCount_reg[22]/C (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: RAMCTRL/clkCount_reg[24]/D (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: sys_clk_pin Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 0.488ns (logic 0.373ns (76.423%) route 0.115ns (23.577%)) Logic Levels: 2 (CARRY4=2) Clock Path Skew: 0.263ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.985ns Source Clock Delay (SCD): 1.475ns Clock Pessimism Removal (CPR): 0.247ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O net (fo=1, routed) 0.627 0.886 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.563 1.475 RAMCTRL/H125MHz SLICE_X24Y49 FDRE r RAMCTRL/clkCount_reg[22]/C ------------------------------------------------------------------- ------------------- SLICE_X24Y49 FDRE (Prop_fdre_C_Q) 0.164 1.639 r RAMCTRL/clkCount_reg[22]/Q net (fo=1, routed) 0.114 1.753 RAMCTRL/clkCount_reg_n_0_[22] SLICE_X24Y49 CARRY4 (Prop_carry4_S[2]_CO[3]) 0.156 1.909 r RAMCTRL/clkCount_reg[23]_i_1/CO[3] net (fo=1, routed) 0.001 1.910 RAMCTRL/clkCount_reg[23]_i_1_n_0 SLICE_X24Y50 CARRY4 (Prop_carry4_CI_O[0]) 0.053 1.963 r RAMCTRL/clkCount_reg[27]_i_1/O[0] net (fo=2, routed) 0.000 1.963 RAMCTRL/sel0[24] SLICE_X24Y50 FDRE r RAMCTRL/clkCount_reg[24]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r H125MHz_IBUF_inst/O net (fo=1, routed) 0.683 1.130 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.159 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.826 1.985 RAMCTRL/H125MHz SLICE_X24Y50 FDRE r RAMCTRL/clkCount_reg[24]/C clock pessimism -0.247 1.738 SLICE_X24Y50 FDRE (Hold_fdre_C_D) 0.130 1.868 RAMCTRL/clkCount_reg[24] ------------------------------------------------------------------- required time -1.868 arrival time 1.963 ------------------------------------------------------------------- slack 0.095 Slack (MET) : 0.108ns (arrival time - required time) Source: RAMCTRL/clkCount_reg[22]/C (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: RAMCTRL/clkCount_reg[26]/D (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: sys_clk_pin Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 0.501ns (logic 0.386ns (77.035%) route 0.115ns (22.965%)) Logic Levels: 2 (CARRY4=2) Clock Path Skew: 0.263ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.985ns Source Clock Delay (SCD): 1.475ns Clock Pessimism Removal (CPR): 0.247ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O net (fo=1, routed) 0.627 0.886 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.563 1.475 RAMCTRL/H125MHz SLICE_X24Y49 FDRE r RAMCTRL/clkCount_reg[22]/C ------------------------------------------------------------------- ------------------- SLICE_X24Y49 FDRE (Prop_fdre_C_Q) 0.164 1.639 r RAMCTRL/clkCount_reg[22]/Q net (fo=1, routed) 0.114 1.753 RAMCTRL/clkCount_reg_n_0_[22] SLICE_X24Y49 CARRY4 (Prop_carry4_S[2]_CO[3]) 0.156 1.909 r RAMCTRL/clkCount_reg[23]_i_1/CO[3] net (fo=1, routed) 0.001 1.910 RAMCTRL/clkCount_reg[23]_i_1_n_0 SLICE_X24Y50 CARRY4 (Prop_carry4_CI_O[2]) 0.066 1.976 r RAMCTRL/clkCount_reg[27]_i_1/O[2] net (fo=2, routed) 0.000 1.976 RAMCTRL/sel0[26] SLICE_X24Y50 FDRE r RAMCTRL/clkCount_reg[26]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r H125MHz_IBUF_inst/O net (fo=1, routed) 0.683 1.130 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.159 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.826 1.985 RAMCTRL/H125MHz SLICE_X24Y50 FDRE r RAMCTRL/clkCount_reg[26]/C clock pessimism -0.247 1.738 SLICE_X24Y50 FDRE (Hold_fdre_C_D) 0.130 1.868 RAMCTRL/clkCount_reg[26] ------------------------------------------------------------------- required time -1.868 arrival time 1.976 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.111ns (arrival time - required time) Source: UPD/dataOut_reg[16]/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: RAMCTRL/SNAKE_RAM/mem_reg_3_0/DIPADIP[0] (rising edge-triggered cell RAMB36E1 clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: sys_clk_pin Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 0.491ns (logic 0.164ns (33.370%) route 0.327ns (66.630%)) Logic Levels: 0 Clock Path Skew: 0.084ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.035ns Source Clock Delay (SCD): 1.471ns Clock Pessimism Removal (CPR): 0.480ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O net (fo=1, routed) 0.627 0.886 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.559 1.471 UPD/H125MHz SLICE_X8Y29 FDCE r UPD/dataOut_reg[16]/C ------------------------------------------------------------------- ------------------- SLICE_X8Y29 FDCE (Prop_fdce_C_Q) 0.164 1.635 r UPD/dataOut_reg[16]/Q net (fo=9, routed) 0.327 1.962 RAMCTRL/SNAKE_RAM/updateRAMDataOut[16] RAMB36_X0Y7 RAMB36E1 r RAMCTRL/SNAKE_RAM/mem_reg_3_0/DIPADIP[0] ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r H125MHz_IBUF_inst/O net (fo=1, routed) 0.683 1.130 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.159 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.876 2.035 RAMCTRL/SNAKE_RAM/H125MHz RAMB36_X0Y7 RAMB36E1 r RAMCTRL/SNAKE_RAM/mem_reg_3_0/CLKARDCLK clock pessimism -0.480 1.555 RAMB36_X0Y7 RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIPADIP[0]) 0.296 1.851 RAMCTRL/SNAKE_RAM/mem_reg_3_0 ------------------------------------------------------------------- required time -1.851 arrival time 1.962 ------------------------------------------------------------------- slack 0.111 Slack (MET) : 0.116ns (arrival time - required time) Source: UPD/dataOut_reg[19]_P/C (rising edge-triggered cell FDPE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: RAMCTRL/SNAKE_RAM/mem_reg_2_1/DIADI[1] (rising edge-triggered cell RAMB18E1 clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: sys_clk_pin Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 0.470ns (logic 0.186ns (39.584%) route 0.284ns (60.416%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.057ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.030ns Source Clock Delay (SCD): 1.474ns Clock Pessimism Removal (CPR): 0.499ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O net (fo=1, routed) 0.627 0.886 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.562 1.474 UPD/H125MHz SLICE_X7Y32 FDPE r UPD/dataOut_reg[19]_P/C ------------------------------------------------------------------- ------------------- SLICE_X7Y32 FDPE (Prop_fdpe_C_Q) 0.141 1.615 r UPD/dataOut_reg[19]_P/Q net (fo=1, routed) 0.156 1.771 UPD/dataOut_reg[19]_P_n_0 SLICE_X7Y32 LUT3 (Prop_lut3_I0_O) 0.045 1.816 r UPD/mem_reg_1_1_i_3/O net (fo=9, routed) 0.128 1.944 RAMCTRL/SNAKE_RAM/updateRAMDataOut[19] RAMB18_X0Y13 RAMB18E1 r RAMCTRL/SNAKE_RAM/mem_reg_2_1/DIADI[1] ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r H125MHz_IBUF_inst/O net (fo=1, routed) 0.683 1.130 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.159 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.871 2.030 RAMCTRL/SNAKE_RAM/H125MHz RAMB18_X0Y13 RAMB18E1 r RAMCTRL/SNAKE_RAM/mem_reg_2_1/CLKARDCLK clock pessimism -0.499 1.531 RAMB18_X0Y13 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_DIADI[1]) 0.296 1.827 RAMCTRL/SNAKE_RAM/mem_reg_2_1 ------------------------------------------------------------------- required time -1.827 arrival time 1.944 ------------------------------------------------------------------- slack 0.116 Slack (MET) : 0.127ns (arrival time - required time) Source: UPD/index_reg[8]/C (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: RAMCTRL/SNAKE_RAM/mem_reg_1_1/ADDRARDADDR[11] (rising edge-triggered cell RAMB18E1 clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: sys_clk_pin Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 0.387ns (logic 0.141ns (36.448%) route 0.246ns (63.552%)) Logic Levels: 0 Clock Path Skew: 0.076ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.030ns Source Clock Delay (SCD): 1.474ns Clock Pessimism Removal (CPR): 0.480ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O net (fo=1, routed) 0.627 0.886 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.562 1.474 UPD/H125MHz SLICE_X9Y32 FDRE r UPD/index_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X9Y32 FDRE (Prop_fdre_C_Q) 0.141 1.615 r UPD/index_reg[8]/Q net (fo=24, routed) 0.246 1.861 RAMCTRL/SNAKE_RAM/Q[8] RAMB18_X0Y12 RAMB18E1 r RAMCTRL/SNAKE_RAM/mem_reg_1_1/ADDRARDADDR[11] ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r H125MHz_IBUF_inst/O net (fo=1, routed) 0.683 1.130 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.159 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.871 2.030 RAMCTRL/SNAKE_RAM/H125MHz RAMB18_X0Y12 RAMB18E1 r RAMCTRL/SNAKE_RAM/mem_reg_1_1/CLKARDCLK clock pessimism -0.480 1.550 RAMB18_X0Y12 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[11]) 0.183 1.733 RAMCTRL/SNAKE_RAM/mem_reg_1_1 ------------------------------------------------------------------- required time -1.733 arrival time 1.861 ------------------------------------------------------------------- slack 0.127 Slack (MET) : 0.127ns (arrival time - required time) Source: UPD/index_reg[8]/C (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: RAMCTRL/SNAKE_RAM/mem_reg_2_1/ADDRARDADDR[11] (rising edge-triggered cell RAMB18E1 clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: sys_clk_pin Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 0.387ns (logic 0.141ns (36.448%) route 0.246ns (63.552%)) Logic Levels: 0 Clock Path Skew: 0.076ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.030ns Source Clock Delay (SCD): 1.474ns Clock Pessimism Removal (CPR): 0.480ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O net (fo=1, routed) 0.627 0.886 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.562 1.474 UPD/H125MHz SLICE_X9Y32 FDRE r UPD/index_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X9Y32 FDRE (Prop_fdre_C_Q) 0.141 1.615 r UPD/index_reg[8]/Q net (fo=24, routed) 0.246 1.861 RAMCTRL/SNAKE_RAM/Q[8] RAMB18_X0Y13 RAMB18E1 r RAMCTRL/SNAKE_RAM/mem_reg_2_1/ADDRARDADDR[11] ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r H125MHz_IBUF_inst/O net (fo=1, routed) 0.683 1.130 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.159 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.871 2.030 RAMCTRL/SNAKE_RAM/H125MHz RAMB18_X0Y13 RAMB18E1 r RAMCTRL/SNAKE_RAM/mem_reg_2_1/CLKARDCLK clock pessimism -0.480 1.550 RAMB18_X0Y13 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[11]) 0.183 1.733 RAMCTRL/SNAKE_RAM/mem_reg_2_1 ------------------------------------------------------------------- required time -1.733 arrival time 1.861 ------------------------------------------------------------------- slack 0.127 Slack (MET) : 0.131ns (arrival time - required time) Source: RAMCTRL/clkCount_reg[22]/C (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: RAMCTRL/clkCount_reg[25]/D (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: sys_clk_pin Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 0.524ns (logic 0.409ns (78.043%) route 0.115ns (21.957%)) Logic Levels: 2 (CARRY4=2) Clock Path Skew: 0.263ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.985ns Source Clock Delay (SCD): 1.475ns Clock Pessimism Removal (CPR): 0.247ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O net (fo=1, routed) 0.627 0.886 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.563 1.475 RAMCTRL/H125MHz SLICE_X24Y49 FDRE r RAMCTRL/clkCount_reg[22]/C ------------------------------------------------------------------- ------------------- SLICE_X24Y49 FDRE (Prop_fdre_C_Q) 0.164 1.639 r RAMCTRL/clkCount_reg[22]/Q net (fo=1, routed) 0.114 1.753 RAMCTRL/clkCount_reg_n_0_[22] SLICE_X24Y49 CARRY4 (Prop_carry4_S[2]_CO[3]) 0.156 1.909 r RAMCTRL/clkCount_reg[23]_i_1/CO[3] net (fo=1, routed) 0.001 1.910 RAMCTRL/clkCount_reg[23]_i_1_n_0 SLICE_X24Y50 CARRY4 (Prop_carry4_CI_O[1]) 0.089 1.999 r RAMCTRL/clkCount_reg[27]_i_1/O[1] net (fo=2, routed) 0.000 1.999 RAMCTRL/sel0[25] SLICE_X24Y50 FDRE r RAMCTRL/clkCount_reg[25]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r H125MHz_IBUF_inst/O net (fo=1, routed) 0.683 1.130 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.159 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.826 1.985 RAMCTRL/H125MHz SLICE_X24Y50 FDRE r RAMCTRL/clkCount_reg[25]/C clock pessimism -0.247 1.738 SLICE_X24Y50 FDRE (Hold_fdre_C_D) 0.130 1.868 RAMCTRL/clkCount_reg[25] ------------------------------------------------------------------- required time -1.868 arrival time 1.999 ------------------------------------------------------------------- slack 0.131 Slack (MET) : 0.133ns (arrival time - required time) Source: RAMCTRL/clkCount_reg[22]/C (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: RAMCTRL/clkCount_reg[27]/D (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: sys_clk_pin Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 0.526ns (logic 0.411ns (78.126%) route 0.115ns (21.874%)) Logic Levels: 2 (CARRY4=2) Clock Path Skew: 0.263ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.985ns Source Clock Delay (SCD): 1.475ns Clock Pessimism Removal (CPR): 0.247ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O net (fo=1, routed) 0.627 0.886 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.563 1.475 RAMCTRL/H125MHz SLICE_X24Y49 FDRE r RAMCTRL/clkCount_reg[22]/C ------------------------------------------------------------------- ------------------- SLICE_X24Y49 FDRE (Prop_fdre_C_Q) 0.164 1.639 r RAMCTRL/clkCount_reg[22]/Q net (fo=1, routed) 0.114 1.753 RAMCTRL/clkCount_reg_n_0_[22] SLICE_X24Y49 CARRY4 (Prop_carry4_S[2]_CO[3]) 0.156 1.909 r RAMCTRL/clkCount_reg[23]_i_1/CO[3] net (fo=1, routed) 0.001 1.910 RAMCTRL/clkCount_reg[23]_i_1_n_0 SLICE_X24Y50 CARRY4 (Prop_carry4_CI_O[3]) 0.091 2.001 r RAMCTRL/clkCount_reg[27]_i_1/O[3] net (fo=2, routed) 0.000 2.001 RAMCTRL/sel0[27] SLICE_X24Y50 FDRE r RAMCTRL/clkCount_reg[27]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r H125MHz_IBUF_inst/O net (fo=1, routed) 0.683 1.130 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.159 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.826 1.985 RAMCTRL/H125MHz SLICE_X24Y50 FDRE r RAMCTRL/clkCount_reg[27]/C clock pessimism -0.247 1.738 SLICE_X24Y50 FDRE (Hold_fdre_C_D) 0.130 1.868 RAMCTRL/clkCount_reg[27] ------------------------------------------------------------------- required time -1.868 arrival time 2.001 ------------------------------------------------------------------- slack 0.133 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: sys_clk_pin Waveform(ns): { 0.000 4.000 } Period(ns): 8.000 Sources: { H125MHz } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 8.000 5.424 RAMB18_X0Y12 RAMCTRL/SNAKE_RAM/mem_reg_1_1/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 8.000 5.424 RAMB18_X0Y12 RAMCTRL/SNAKE_RAM/mem_reg_1_1/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 8.000 5.424 RAMB18_X1Y16 RAMCTRL/SNAKE_RAM/mem_reg_3_1/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 8.000 5.424 RAMB18_X1Y16 RAMCTRL/SNAKE_RAM/mem_reg_3_1/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 8.000 5.424 RAMB18_X1Y11 RAMCTRL/SNAKE_RAM/mem_reg_5_1/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 8.000 5.424 RAMB18_X1Y11 RAMCTRL/SNAKE_RAM/mem_reg_5_1/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 8.000 5.424 RAMB18_X2Y11 RAMCTRL/SNAKE_RAM/mem_reg_7_1/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 8.000 5.424 RAMB18_X2Y11 RAMCTRL/SNAKE_RAM/mem_reg_7_1/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 8.000 5.424 RAMB18_X2Y10 RAMCTRL/SNAKE_RAM/mem_reg_9_1/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 8.000 5.424 RAMB18_X2Y10 RAMCTRL/SNAKE_RAM/mem_reg_9_1/CLKBWRCLK Low Pulse Width Slow FDRE/C n/a 0.500 4.000 3.500 SLICE_X25Y44 RAMCTRL/clkCount_reg[0]/C Low Pulse Width Slow FDRE/C n/a 0.500 4.000 3.500 SLICE_X24Y46 RAMCTRL/clkCount_reg[10]/C Low Pulse Width Slow FDRE/C n/a 0.500 4.000 3.500 SLICE_X24Y46 RAMCTRL/clkCount_reg[11]/C Low Pulse Width Slow FDRE/C n/a 0.500 4.000 3.500 SLICE_X24Y47 RAMCTRL/clkCount_reg[12]/C Low Pulse Width Slow FDRE/C n/a 0.500 4.000 3.500 SLICE_X24Y47 RAMCTRL/clkCount_reg[13]/C Low Pulse Width Slow FDRE/C n/a 0.500 4.000 3.500 SLICE_X24Y47 RAMCTRL/clkCount_reg[14]/C Low Pulse Width Slow FDRE/C n/a 0.500 4.000 3.500 SLICE_X24Y47 RAMCTRL/clkCount_reg[15]/C Low Pulse Width Slow FDRE/C n/a 0.500 4.000 3.500 SLICE_X24Y48 RAMCTRL/clkCount_reg[16]/C Low Pulse Width Slow FDRE/C n/a 0.500 4.000 3.500 SLICE_X24Y48 RAMCTRL/clkCount_reg[17]/C Low Pulse Width Slow FDRE/C n/a 0.500 4.000 3.500 SLICE_X24Y48 RAMCTRL/clkCount_reg[18]/C High Pulse Width Slow FDCE/C n/a 0.500 4.000 3.500 SLICE_X28Y18 RAMCTRL/MAT_RAM/RAMCTRL/MAT_RAM/mem_reg_1_cooolgate_en_gate_1_cooolDelFlop/C High Pulse Width Fast FDCE/C n/a 0.500 4.000 3.500 SLICE_X28Y18 RAMCTRL/MAT_RAM/RAMCTRL/MAT_RAM/mem_reg_1_cooolgate_en_gate_1_cooolDelFlop/C High Pulse Width Slow FDCE/C n/a 0.500 4.000 3.500 SLICE_X32Y18 RAMCTRL/MAT_RAM/RAMCTRL/MAT_RAM/mem_reg_1_cooolgate_en_gate_2_cooolDelFlop/C High Pulse Width Fast FDCE/C n/a 0.500 4.000 3.500 SLICE_X32Y18 RAMCTRL/MAT_RAM/RAMCTRL/MAT_RAM/mem_reg_1_cooolgate_en_gate_2_cooolDelFlop/C High Pulse Width Fast FDRE/C n/a 0.500 4.000 3.500 SLICE_X36Y36 ROM/data_reg[14]/C High Pulse Width Slow FDRE/C n/a 0.500 4.000 3.500 SLICE_X39Y38 ROM/data_reg[15]/C High Pulse Width Slow FDRE/C n/a 0.500 4.000 3.500 SLICE_X35Y38 ROM/data_reg[17]/C High Pulse Width Slow FDRE/C n/a 0.500 4.000 3.500 SLICE_X38Y38 ROM/data_reg[20]/C High Pulse Width Fast FDRE/C n/a 0.500 4.000 3.500 SLICE_X38Y36 ROM/data_reg[21]/C High Pulse Width Fast FDRE/C n/a 0.500 4.000 3.500 SLICE_X39Y36 ROM/data_reg[22]/C --------------------------------------------------------------------------------------------------- From Clock: sys_clk_pin To Clock: clk_out1_clk_wiz_1 Setup : 0 Failing Endpoints, Worst Slack 1.397ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.418ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 1.397ns (required time - arrival time) Source: SNAKE/snakeHere_reg/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: SNAKE/snakeColor_reg[G][2]/D (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk_out1_clk_wiz_1 rise@40.000ns - sys_clk_pin rise@32.000ns) Data Path Delay: 2.462ns (logic 0.580ns (23.555%) route 1.882ns (76.445%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -3.764ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.576ns = ( 41.576 - 40.000 ) Source Clock Delay (SCD): 5.340ns = ( 37.340 - 32.000 ) Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 32.000 32.000 r L16 0.000 32.000 r H125MHz (IN) net (fo=0) 0.000 32.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.491 33.491 r H125MHz_IBUF_inst/O net (fo=1, routed) 2.076 35.567 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 35.668 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.672 37.340 SNAKE/H125MHz SLICE_X18Y36 FDCE r SNAKE/snakeHere_reg/C ------------------------------------------------------------------- ------------------- SLICE_X18Y36 FDCE (Prop_fdce_C_Q) 0.456 37.796 r SNAKE/snakeHere_reg/Q net (fo=14, routed) 1.882 39.679 SNAKE/snakeHere SLICE_X40Y38 LUT2 (Prop_lut2_I0_O) 0.124 39.803 r SNAKE/snakeColor[G][2]_i_1/O net (fo=1, routed) 0.000 39.803 SNAKE/snakeColor[G][2]_i_1_n_0 SLICE_X40Y38 FDCE r SNAKE/snakeColor_reg[G][2]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.573 41.576 SNAKE/clk_out1 SLICE_X40Y38 FDCE r SNAKE/snakeColor_reg[G][2]/C clock pessimism 0.000 41.576 clock uncertainty -0.406 41.170 SLICE_X40Y38 FDCE (Setup_fdce_C_D) 0.029 41.199 SNAKE/snakeColor_reg[G][2] ------------------------------------------------------------------- required time 41.199 arrival time -39.803 ------------------------------------------------------------------- slack 1.397 Slack (MET) : 1.415ns (required time - arrival time) Source: SNAKE/snakeHere_reg/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: SNAKE/snakeColor_reg[R][1]/D (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk_out1_clk_wiz_1 rise@40.000ns - sys_clk_pin rise@32.000ns) Data Path Delay: 2.490ns (logic 0.608ns (24.414%) route 1.882ns (75.586%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -3.764ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.576ns = ( 41.576 - 40.000 ) Source Clock Delay (SCD): 5.340ns = ( 37.340 - 32.000 ) Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 32.000 32.000 r L16 0.000 32.000 r H125MHz (IN) net (fo=0) 0.000 32.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.491 33.491 r H125MHz_IBUF_inst/O net (fo=1, routed) 2.076 35.567 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 35.668 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.672 37.340 SNAKE/H125MHz SLICE_X18Y36 FDCE r SNAKE/snakeHere_reg/C ------------------------------------------------------------------- ------------------- SLICE_X18Y36 FDCE (Prop_fdce_C_Q) 0.456 37.796 r SNAKE/snakeHere_reg/Q net (fo=14, routed) 1.882 39.679 SNAKE/snakeHere SLICE_X40Y38 LUT2 (Prop_lut2_I0_O) 0.152 39.831 r SNAKE/snakeColor[R][1]_i_1/O net (fo=1, routed) 0.000 39.831 SNAKE/snakeColor[R][1]_i_1_n_0 SLICE_X40Y38 FDCE r SNAKE/snakeColor_reg[R][1]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.573 41.576 SNAKE/clk_out1 SLICE_X40Y38 FDCE r SNAKE/snakeColor_reg[R][1]/C clock pessimism 0.000 41.576 clock uncertainty -0.406 41.170 SLICE_X40Y38 FDCE (Setup_fdce_C_D) 0.075 41.245 SNAKE/snakeColor_reg[R][1] ------------------------------------------------------------------- required time 41.245 arrival time -39.831 ------------------------------------------------------------------- slack 1.415 Slack (MET) : 1.545ns (required time - arrival time) Source: SNAKE/snakeHere_reg/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: SNAKE/snakeColor_reg[G][5]/D (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk_out1_clk_wiz_1 rise@40.000ns - sys_clk_pin rise@32.000ns) Data Path Delay: 2.314ns (logic 0.580ns (25.068%) route 1.734ns (74.932%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -3.766ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.574ns = ( 41.574 - 40.000 ) Source Clock Delay (SCD): 5.340ns = ( 37.340 - 32.000 ) Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 32.000 32.000 r L16 0.000 32.000 r H125MHz (IN) net (fo=0) 0.000 32.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.491 33.491 r H125MHz_IBUF_inst/O net (fo=1, routed) 2.076 35.567 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 35.668 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.672 37.340 SNAKE/H125MHz SLICE_X18Y36 FDCE r SNAKE/snakeHere_reg/C ------------------------------------------------------------------- ------------------- SLICE_X18Y36 FDCE (Prop_fdce_C_Q) 0.456 37.796 r SNAKE/snakeHere_reg/Q net (fo=14, routed) 1.734 39.530 SNAKE/snakeHere SLICE_X40Y36 LUT2 (Prop_lut2_I0_O) 0.124 39.654 r SNAKE/snakeColor[G][5]_i_1/O net (fo=1, routed) 0.000 39.654 SNAKE/snakeColor[G][5]_i_1_n_0 SLICE_X40Y36 FDCE r SNAKE/snakeColor_reg[G][5]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.571 41.574 SNAKE/clk_out1 SLICE_X40Y36 FDCE r SNAKE/snakeColor_reg[G][5]/C clock pessimism 0.000 41.574 clock uncertainty -0.406 41.168 SLICE_X40Y36 FDCE (Setup_fdce_C_D) 0.031 41.199 SNAKE/snakeColor_reg[G][5] ------------------------------------------------------------------- required time 41.199 arrival time -39.654 ------------------------------------------------------------------- slack 1.545 Slack (MET) : 1.561ns (required time - arrival time) Source: SNAKE/snakeHere_reg/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: SNAKE/snakeColor_reg[R][3]/D (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk_out1_clk_wiz_1 rise@40.000ns - sys_clk_pin rise@32.000ns) Data Path Delay: 2.342ns (logic 0.608ns (25.964%) route 1.734ns (74.036%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -3.766ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.574ns = ( 41.574 - 40.000 ) Source Clock Delay (SCD): 5.340ns = ( 37.340 - 32.000 ) Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 32.000 32.000 r L16 0.000 32.000 r H125MHz (IN) net (fo=0) 0.000 32.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.491 33.491 r H125MHz_IBUF_inst/O net (fo=1, routed) 2.076 35.567 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 35.668 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.672 37.340 SNAKE/H125MHz SLICE_X18Y36 FDCE r SNAKE/snakeHere_reg/C ------------------------------------------------------------------- ------------------- SLICE_X18Y36 FDCE (Prop_fdce_C_Q) 0.456 37.796 r SNAKE/snakeHere_reg/Q net (fo=14, routed) 1.734 39.530 SNAKE/snakeHere SLICE_X40Y36 LUT2 (Prop_lut2_I0_O) 0.152 39.682 r SNAKE/snakeColor[R][3]_i_1/O net (fo=1, routed) 0.000 39.682 SNAKE/snakeColor[R][3]_i_1_n_0 SLICE_X40Y36 FDCE r SNAKE/snakeColor_reg[R][3]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.571 41.574 SNAKE/clk_out1 SLICE_X40Y36 FDCE r SNAKE/snakeColor_reg[R][3]/C clock pessimism 0.000 41.574 clock uncertainty -0.406 41.168 SLICE_X40Y36 FDCE (Setup_fdce_C_D) 0.075 41.243 SNAKE/snakeColor_reg[R][3] ------------------------------------------------------------------- required time 41.243 arrival time -39.682 ------------------------------------------------------------------- slack 1.561 Slack (MET) : 1.639ns (required time - arrival time) Source: SNAKE/snakeHere_reg/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: SNAKE/snakeColor_reg[G][4]/D (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk_out1_clk_wiz_1 rise@40.000ns - sys_clk_pin rise@32.000ns) Data Path Delay: 2.220ns (logic 0.580ns (26.131%) route 1.640ns (73.869%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -3.765ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.575ns = ( 41.575 - 40.000 ) Source Clock Delay (SCD): 5.340ns = ( 37.340 - 32.000 ) Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 32.000 32.000 r L16 0.000 32.000 r H125MHz (IN) net (fo=0) 0.000 32.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.491 33.491 r H125MHz_IBUF_inst/O net (fo=1, routed) 2.076 35.567 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 35.668 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.672 37.340 SNAKE/H125MHz SLICE_X18Y36 FDCE r SNAKE/snakeHere_reg/C ------------------------------------------------------------------- ------------------- SLICE_X18Y36 FDCE (Prop_fdce_C_Q) 0.456 37.796 r SNAKE/snakeHere_reg/Q net (fo=14, routed) 1.640 39.436 SNAKE/snakeHere SLICE_X37Y38 LUT2 (Prop_lut2_I0_O) 0.124 39.560 r SNAKE/snakeColor[G][4]_i_1/O net (fo=1, routed) 0.000 39.560 SNAKE/snakeColor[G][4]_i_1_n_0 SLICE_X37Y38 FDCE r SNAKE/snakeColor_reg[G][4]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.572 41.575 SNAKE/clk_out1 SLICE_X37Y38 FDCE r SNAKE/snakeColor_reg[G][4]/C clock pessimism 0.000 41.575 clock uncertainty -0.406 41.169 SLICE_X37Y38 FDCE (Setup_fdce_C_D) 0.029 41.198 SNAKE/snakeColor_reg[G][4] ------------------------------------------------------------------- required time 41.198 arrival time -39.560 ------------------------------------------------------------------- slack 1.639 Slack (MET) : 1.691ns (required time - arrival time) Source: SNAKE/snakeHere_reg/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: SNAKE/snakeColor_reg[R][2]/D (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk_out1_clk_wiz_1 rise@40.000ns - sys_clk_pin rise@32.000ns) Data Path Delay: 2.214ns (logic 0.574ns (25.931%) route 1.640ns (74.069%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -3.765ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.575ns = ( 41.575 - 40.000 ) Source Clock Delay (SCD): 5.340ns = ( 37.340 - 32.000 ) Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 32.000 32.000 r L16 0.000 32.000 r H125MHz (IN) net (fo=0) 0.000 32.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.491 33.491 r H125MHz_IBUF_inst/O net (fo=1, routed) 2.076 35.567 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 35.668 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.672 37.340 SNAKE/H125MHz SLICE_X18Y36 FDCE r SNAKE/snakeHere_reg/C ------------------------------------------------------------------- ------------------- SLICE_X18Y36 FDCE (Prop_fdce_C_Q) 0.456 37.796 r SNAKE/snakeHere_reg/Q net (fo=14, routed) 1.640 39.436 SNAKE/snakeHere SLICE_X37Y38 LUT2 (Prop_lut2_I0_O) 0.118 39.554 r SNAKE/snakeColor[R][2]_i_1/O net (fo=1, routed) 0.000 39.554 SNAKE/snakeColor[R][2]_i_1_n_0 SLICE_X37Y38 FDCE r SNAKE/snakeColor_reg[R][2]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.572 41.575 SNAKE/clk_out1 SLICE_X37Y38 FDCE r SNAKE/snakeColor_reg[R][2]/C clock pessimism 0.000 41.575 clock uncertainty -0.406 41.169 SLICE_X37Y38 FDCE (Setup_fdce_C_D) 0.075 41.244 SNAKE/snakeColor_reg[R][2] ------------------------------------------------------------------- required time 41.244 arrival time -39.554 ------------------------------------------------------------------- slack 1.691 Slack (MET) : 1.722ns (required time - arrival time) Source: SNAKE/snakeHere_reg/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: SNAKE/snakeColor_reg[B][1]/D (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk_out1_clk_wiz_1 rise@40.000ns - sys_clk_pin rise@32.000ns) Data Path Delay: 2.134ns (logic 0.580ns (27.176%) route 1.554ns (72.824%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -3.767ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.573ns = ( 41.573 - 40.000 ) Source Clock Delay (SCD): 5.340ns = ( 37.340 - 32.000 ) Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 32.000 32.000 r L16 0.000 32.000 r H125MHz (IN) net (fo=0) 0.000 32.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.491 33.491 r H125MHz_IBUF_inst/O net (fo=1, routed) 2.076 35.567 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 35.668 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.672 37.340 SNAKE/H125MHz SLICE_X18Y36 FDCE r SNAKE/snakeHere_reg/C ------------------------------------------------------------------- ------------------- SLICE_X18Y36 FDCE (Prop_fdce_C_Q) 0.456 37.796 r SNAKE/snakeHere_reg/Q net (fo=14, routed) 1.554 39.351 SNAKE/snakeHere SLICE_X37Y36 LUT2 (Prop_lut2_I0_O) 0.124 39.475 r SNAKE/snakeColor[B][1]_i_1/O net (fo=1, routed) 0.000 39.475 SNAKE/snakeColor[B][1]_i_1_n_0 SLICE_X37Y36 FDCE r SNAKE/snakeColor_reg[B][1]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.570 41.573 SNAKE/clk_out1 SLICE_X37Y36 FDCE r SNAKE/snakeColor_reg[B][1]/C clock pessimism 0.000 41.573 clock uncertainty -0.406 41.167 SLICE_X37Y36 FDCE (Setup_fdce_C_D) 0.029 41.196 SNAKE/snakeColor_reg[B][1] ------------------------------------------------------------------- required time 41.196 arrival time -39.475 ------------------------------------------------------------------- slack 1.722 Slack (MET) : 1.725ns (required time - arrival time) Source: SNAKE/snakeHere_reg/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: SNAKE/snakeColor_reg[G][1]/D (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk_out1_clk_wiz_1 rise@40.000ns - sys_clk_pin rise@32.000ns) Data Path Delay: 2.133ns (logic 0.580ns (27.189%) route 1.553ns (72.811%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -3.767ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.573ns = ( 41.573 - 40.000 ) Source Clock Delay (SCD): 5.340ns = ( 37.340 - 32.000 ) Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 32.000 32.000 r L16 0.000 32.000 r H125MHz (IN) net (fo=0) 0.000 32.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.491 33.491 r H125MHz_IBUF_inst/O net (fo=1, routed) 2.076 35.567 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 35.668 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.672 37.340 SNAKE/H125MHz SLICE_X18Y36 FDCE r SNAKE/snakeHere_reg/C ------------------------------------------------------------------- ------------------- SLICE_X18Y36 FDCE (Prop_fdce_C_Q) 0.456 37.796 r SNAKE/snakeHere_reg/Q net (fo=14, routed) 1.553 39.350 SNAKE/snakeHere SLICE_X37Y36 LUT2 (Prop_lut2_I0_O) 0.124 39.474 r SNAKE/snakeColor[G][1]_i_1/O net (fo=1, routed) 0.000 39.474 SNAKE/snakeColor[G][1]_i_1_n_0 SLICE_X37Y36 FDCE r SNAKE/snakeColor_reg[G][1]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.570 41.573 SNAKE/clk_out1 SLICE_X37Y36 FDCE r SNAKE/snakeColor_reg[G][1]/C clock pessimism 0.000 41.573 clock uncertainty -0.406 41.167 SLICE_X37Y36 FDCE (Setup_fdce_C_D) 0.031 41.198 SNAKE/snakeColor_reg[G][1] ------------------------------------------------------------------- required time 41.198 arrival time -39.474 ------------------------------------------------------------------- slack 1.725 Slack (MET) : 1.740ns (required time - arrival time) Source: SNAKE/snakeHere_reg/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: SNAKE/snakeColor_reg[G][0]/D (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk_out1_clk_wiz_1 rise@40.000ns - sys_clk_pin rise@32.000ns) Data Path Delay: 2.162ns (logic 0.608ns (28.119%) route 1.554ns (71.881%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -3.767ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.573ns = ( 41.573 - 40.000 ) Source Clock Delay (SCD): 5.340ns = ( 37.340 - 32.000 ) Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 32.000 32.000 r L16 0.000 32.000 r H125MHz (IN) net (fo=0) 0.000 32.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.491 33.491 r H125MHz_IBUF_inst/O net (fo=1, routed) 2.076 35.567 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 35.668 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.672 37.340 SNAKE/H125MHz SLICE_X18Y36 FDCE r SNAKE/snakeHere_reg/C ------------------------------------------------------------------- ------------------- SLICE_X18Y36 FDCE (Prop_fdce_C_Q) 0.456 37.796 r SNAKE/snakeHere_reg/Q net (fo=14, routed) 1.554 39.351 SNAKE/snakeHere SLICE_X37Y36 LUT2 (Prop_lut2_I0_O) 0.152 39.503 r SNAKE/snakeColor[G][0]_i_1/O net (fo=1, routed) 0.000 39.503 SNAKE/snakeColor[G][0]_i_1_n_0 SLICE_X37Y36 FDCE r SNAKE/snakeColor_reg[G][0]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.570 41.573 SNAKE/clk_out1 SLICE_X37Y36 FDCE r SNAKE/snakeColor_reg[G][0]/C clock pessimism 0.000 41.573 clock uncertainty -0.406 41.167 SLICE_X37Y36 FDCE (Setup_fdce_C_D) 0.075 41.242 SNAKE/snakeColor_reg[G][0] ------------------------------------------------------------------- required time 41.242 arrival time -39.503 ------------------------------------------------------------------- slack 1.740 Slack (MET) : 1.741ns (required time - arrival time) Source: SNAKE/snakeHere_reg/C (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: SNAKE/snakeColor_reg[R][4]/D (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk_out1_clk_wiz_1 rise@40.000ns - sys_clk_pin rise@32.000ns) Data Path Delay: 2.161ns (logic 0.608ns (28.132%) route 1.553ns (71.868%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -3.767ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.573ns = ( 41.573 - 40.000 ) Source Clock Delay (SCD): 5.340ns = ( 37.340 - 32.000 ) Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 32.000 32.000 r L16 0.000 32.000 r H125MHz (IN) net (fo=0) 0.000 32.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.491 33.491 r H125MHz_IBUF_inst/O net (fo=1, routed) 2.076 35.567 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 35.668 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.672 37.340 SNAKE/H125MHz SLICE_X18Y36 FDCE r SNAKE/snakeHere_reg/C ------------------------------------------------------------------- ------------------- SLICE_X18Y36 FDCE (Prop_fdce_C_Q) 0.456 37.796 r SNAKE/snakeHere_reg/Q net (fo=14, routed) 1.553 39.350 SNAKE/snakeHere SLICE_X37Y36 LUT2 (Prop_lut2_I0_O) 0.152 39.502 r SNAKE/snakeColor[R][4]_i_1/O net (fo=1, routed) 0.000 39.502 SNAKE/snakeColor[R][4]_i_1_n_0 SLICE_X37Y36 FDCE r SNAKE/snakeColor_reg[R][4]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.570 41.573 SNAKE/clk_out1 SLICE_X37Y36 FDCE r SNAKE/snakeColor_reg[R][4]/C clock pessimism 0.000 41.573 clock uncertainty -0.406 41.167 SLICE_X37Y36 FDCE (Setup_fdce_C_D) 0.075 41.242 SNAKE/snakeColor_reg[R][4] ------------------------------------------------------------------- required time 41.242 arrival time -39.502 ------------------------------------------------------------------- slack 1.741 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.418ns (arrival time - required time) Source: ROM/data_reg[14]/C (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: SNAKE/snakeColor_reg[G][1]/D (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 0.273ns (logic 0.186ns (68.212%) route 0.087ns (31.788%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.644ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.856ns Source Clock Delay (SCD): 1.500ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O net (fo=1, routed) 0.627 0.886 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.588 1.500 ROM/H125MHz SLICE_X36Y36 FDRE r ROM/data_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X36Y36 FDRE (Prop_fdre_C_Q) 0.141 1.641 r ROM/data_reg[14]/Q net (fo=1, routed) 0.087 1.727 SNAKE/spritesROMData[4] SLICE_X37Y36 LUT2 (Prop_lut2_I1_O) 0.045 1.772 r SNAKE/snakeColor[G][1]_i_1/O net (fo=1, routed) 0.000 1.772 SNAKE/snakeColor[G][1]_i_1_n_0 SLICE_X37Y36 FDCE r SNAKE/snakeColor_reg[G][1]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O net (fo=60, routed) 0.854 0.856 SNAKE/clk_out1 SLICE_X37Y36 FDCE r SNAKE/snakeColor_reg[G][1]/C clock pessimism 0.000 0.856 clock uncertainty 0.406 1.262 SLICE_X37Y36 FDCE (Hold_fdce_C_D) 0.092 1.354 SNAKE/snakeColor_reg[G][1] ------------------------------------------------------------------- required time -1.354 arrival time 1.772 ------------------------------------------------------------------- slack 0.418 Slack (MET) : 0.470ns (arrival time - required time) Source: ROM/data_reg[9]/C (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: SNAKE/snakeColor_reg[B][1]/D (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 0.322ns (logic 0.186ns (57.733%) route 0.136ns (42.267%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.645ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.856ns Source Clock Delay (SCD): 1.501ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O net (fo=1, routed) 0.627 0.886 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.589 1.501 ROM/H125MHz SLICE_X37Y37 FDRE r ROM/data_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X37Y37 FDRE (Prop_fdre_C_Q) 0.141 1.642 r ROM/data_reg[9]/Q net (fo=1, routed) 0.136 1.778 SNAKE/spritesROMData[1] SLICE_X37Y36 LUT2 (Prop_lut2_I1_O) 0.045 1.823 r SNAKE/snakeColor[B][1]_i_1/O net (fo=1, routed) 0.000 1.823 SNAKE/snakeColor[B][1]_i_1_n_0 SLICE_X37Y36 FDCE r SNAKE/snakeColor_reg[B][1]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O net (fo=60, routed) 0.854 0.856 SNAKE/clk_out1 SLICE_X37Y36 FDCE r SNAKE/snakeColor_reg[B][1]/C clock pessimism 0.000 0.856 clock uncertainty 0.406 1.262 SLICE_X37Y36 FDCE (Hold_fdce_C_D) 0.091 1.353 SNAKE/snakeColor_reg[B][1] ------------------------------------------------------------------- required time -1.353 arrival time 1.823 ------------------------------------------------------------------- slack 0.470 Slack (MET) : 0.485ns (arrival time - required time) Source: ROM/data_reg[7]/C (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: SNAKE/snakeColor_reg[A][7]/D (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 0.340ns (logic 0.186ns (54.731%) route 0.154ns (45.269%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.642ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.858ns Source Clock Delay (SCD): 1.500ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O net (fo=1, routed) 0.627 0.886 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.588 1.500 ROM/H125MHz SLICE_X39Y36 FDRE r ROM/data_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X39Y36 FDRE (Prop_fdre_C_Q) 0.141 1.641 r ROM/data_reg[7]/Q net (fo=1, routed) 0.154 1.795 SNAKE/spritesROMData[0] SLICE_X40Y36 LUT2 (Prop_lut2_I1_O) 0.045 1.840 r SNAKE/snakeColor[A][7]_i_1/O net (fo=1, routed) 0.000 1.840 SNAKE/snakeColor[A][7]_i_1_n_0 SLICE_X40Y36 FDCE r SNAKE/snakeColor_reg[A][7]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O net (fo=60, routed) 0.856 0.858 SNAKE/clk_out1 SLICE_X40Y36 FDCE r SNAKE/snakeColor_reg[A][7]/C clock pessimism 0.000 0.858 clock uncertainty 0.406 1.264 SLICE_X40Y36 FDCE (Hold_fdce_C_D) 0.091 1.355 SNAKE/snakeColor_reg[A][7] ------------------------------------------------------------------- required time -1.355 arrival time 1.840 ------------------------------------------------------------------- slack 0.485 Slack (MET) : 0.537ns (arrival time - required time) Source: ROM/data_reg[15]/C (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: SNAKE/snakeColor_reg[G][2]/D (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 0.393ns (logic 0.186ns (47.328%) route 0.207ns (52.672%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.641ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.861ns Source Clock Delay (SCD): 1.502ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O net (fo=1, routed) 0.627 0.886 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.590 1.502 ROM/H125MHz SLICE_X39Y38 FDRE r ROM/data_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X39Y38 FDRE (Prop_fdre_C_Q) 0.141 1.643 r ROM/data_reg[15]/Q net (fo=1, routed) 0.207 1.850 SNAKE/spritesROMData[5] SLICE_X40Y38 LUT2 (Prop_lut2_I1_O) 0.045 1.895 r SNAKE/snakeColor[G][2]_i_1/O net (fo=1, routed) 0.000 1.895 SNAKE/snakeColor[G][2]_i_1_n_0 SLICE_X40Y38 FDCE r SNAKE/snakeColor_reg[G][2]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O net (fo=60, routed) 0.859 0.861 SNAKE/clk_out1 SLICE_X40Y38 FDCE r SNAKE/snakeColor_reg[G][2]/C clock pessimism 0.000 0.861 clock uncertainty 0.406 1.267 SLICE_X40Y38 FDCE (Hold_fdce_C_D) 0.091 1.358 SNAKE/snakeColor_reg[G][2] ------------------------------------------------------------------- required time -1.358 arrival time 1.895 ------------------------------------------------------------------- slack 0.537 Slack (MET) : 0.570ns (arrival time - required time) Source: ROM/data_reg[21]/C (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: SNAKE/snakeColor_reg[R][2]/D (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 0.442ns (logic 0.210ns (47.481%) route 0.232ns (52.519%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.641ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.859ns Source Clock Delay (SCD): 1.500ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O net (fo=1, routed) 0.627 0.886 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.588 1.500 ROM/H125MHz SLICE_X38Y36 FDRE r ROM/data_reg[21]/C ------------------------------------------------------------------- ------------------- SLICE_X38Y36 FDRE (Prop_fdre_C_Q) 0.164 1.664 r ROM/data_reg[21]/Q net (fo=1, routed) 0.232 1.896 SNAKE/spritesROMData[10] SLICE_X37Y38 LUT2 (Prop_lut2_I1_O) 0.046 1.942 r SNAKE/snakeColor[R][2]_i_1/O net (fo=1, routed) 0.000 1.942 SNAKE/snakeColor[R][2]_i_1_n_0 SLICE_X37Y38 FDCE r SNAKE/snakeColor_reg[R][2]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O net (fo=60, routed) 0.857 0.859 SNAKE/clk_out1 SLICE_X37Y38 FDCE r SNAKE/snakeColor_reg[R][2]/C clock pessimism 0.000 0.859 clock uncertainty 0.406 1.265 SLICE_X37Y38 FDCE (Hold_fdce_C_D) 0.107 1.372 SNAKE/snakeColor_reg[R][2] ------------------------------------------------------------------- required time -1.372 arrival time 1.942 ------------------------------------------------------------------- slack 0.570 Slack (MET) : 0.594ns (arrival time - required time) Source: ROM/data_reg[18]/C (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: SNAKE/snakeColor_reg[G][5]/D (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 0.451ns (logic 0.186ns (41.243%) route 0.265ns (58.757%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.641ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.858ns Source Clock Delay (SCD): 1.499ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O net (fo=1, routed) 0.627 0.886 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.587 1.499 ROM/H125MHz SLICE_X39Y33 FDRE r ROM/data_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X39Y33 FDRE (Prop_fdre_C_Q) 0.141 1.640 r ROM/data_reg[18]/Q net (fo=1, routed) 0.265 1.905 SNAKE/spritesROMData[8] SLICE_X40Y36 LUT2 (Prop_lut2_I1_O) 0.045 1.950 r SNAKE/snakeColor[G][5]_i_1/O net (fo=1, routed) 0.000 1.950 SNAKE/snakeColor[G][5]_i_1_n_0 SLICE_X40Y36 FDCE r SNAKE/snakeColor_reg[G][5]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O net (fo=60, routed) 0.856 0.858 SNAKE/clk_out1 SLICE_X40Y36 FDCE r SNAKE/snakeColor_reg[G][5]/C clock pessimism 0.000 0.858 clock uncertainty 0.406 1.264 SLICE_X40Y36 FDCE (Hold_fdce_C_D) 0.092 1.356 SNAKE/snakeColor_reg[G][5] ------------------------------------------------------------------- required time -1.356 arrival time 1.950 ------------------------------------------------------------------- slack 0.594 Slack (MET) : 0.595ns (arrival time - required time) Source: ROM/data_reg[16]/C (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: SNAKE/snakeColor_reg[G][3]/D (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 0.466ns (logic 0.183ns (39.248%) route 0.283ns (60.752%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.642ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.858ns Source Clock Delay (SCD): 1.500ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O net (fo=1, routed) 0.627 0.886 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.588 1.500 ROM/H125MHz SLICE_X39Y34 FDRE r ROM/data_reg[16]/C ------------------------------------------------------------------- ------------------- SLICE_X39Y34 FDRE (Prop_fdre_C_Q) 0.141 1.641 r ROM/data_reg[16]/Q net (fo=1, routed) 0.283 1.924 SNAKE/spritesROMData[6] SLICE_X40Y36 LUT2 (Prop_lut2_I1_O) 0.042 1.966 r SNAKE/snakeColor[G][3]_i_1/O net (fo=1, routed) 0.000 1.966 SNAKE/snakeColor[G][3]_i_1_n_0 SLICE_X40Y36 FDCE r SNAKE/snakeColor_reg[G][3]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O net (fo=60, routed) 0.856 0.858 SNAKE/clk_out1 SLICE_X40Y36 FDCE r SNAKE/snakeColor_reg[G][3]/C clock pessimism 0.000 0.858 clock uncertainty 0.406 1.264 SLICE_X40Y36 FDCE (Hold_fdce_C_D) 0.107 1.371 SNAKE/snakeColor_reg[G][3] ------------------------------------------------------------------- required time -1.371 arrival time 1.966 ------------------------------------------------------------------- slack 0.595 Slack (MET) : 0.607ns (arrival time - required time) Source: ROM/data_reg[13]/C (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: SNAKE/snakeColor_reg[G][0]/D (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 0.502ns (logic 0.187ns (37.223%) route 0.315ns (62.777%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.618ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.856ns Source Clock Delay (SCD): 1.474ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O net (fo=1, routed) 0.627 0.886 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.562 1.474 ROM/H125MHz SLICE_X35Y37 FDRE r ROM/data_reg[13]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y37 FDRE (Prop_fdre_C_Q) 0.141 1.615 r ROM/data_reg[13]/Q net (fo=1, routed) 0.315 1.930 SNAKE/spritesROMData[3] SLICE_X37Y36 LUT2 (Prop_lut2_I1_O) 0.046 1.976 r SNAKE/snakeColor[G][0]_i_1/O net (fo=1, routed) 0.000 1.976 SNAKE/snakeColor[G][0]_i_1_n_0 SLICE_X37Y36 FDCE r SNAKE/snakeColor_reg[G][0]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O net (fo=60, routed) 0.854 0.856 SNAKE/clk_out1 SLICE_X37Y36 FDCE r SNAKE/snakeColor_reg[G][0]/C clock pessimism 0.000 0.856 clock uncertainty 0.406 1.262 SLICE_X37Y36 FDCE (Hold_fdce_C_D) 0.107 1.369 SNAKE/snakeColor_reg[G][0] ------------------------------------------------------------------- required time -1.369 arrival time 1.976 ------------------------------------------------------------------- slack 0.607 Slack (MET) : 0.645ns (arrival time - required time) Source: ROM/data_reg[17]/C (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: SNAKE/snakeColor_reg[G][4]/D (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 0.527ns (logic 0.186ns (35.324%) route 0.341ns (64.676%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.616ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.859ns Source Clock Delay (SCD): 1.475ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O net (fo=1, routed) 0.627 0.886 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.563 1.475 ROM/H125MHz SLICE_X35Y38 FDRE r ROM/data_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y38 FDRE (Prop_fdre_C_Q) 0.141 1.616 r ROM/data_reg[17]/Q net (fo=1, routed) 0.341 1.956 SNAKE/spritesROMData[7] SLICE_X37Y38 LUT2 (Prop_lut2_I1_O) 0.045 2.001 r SNAKE/snakeColor[G][4]_i_1/O net (fo=1, routed) 0.000 2.001 SNAKE/snakeColor[G][4]_i_1_n_0 SLICE_X37Y38 FDCE r SNAKE/snakeColor_reg[G][4]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O net (fo=60, routed) 0.857 0.859 SNAKE/clk_out1 SLICE_X37Y38 FDCE r SNAKE/snakeColor_reg[G][4]/C clock pessimism 0.000 0.859 clock uncertainty 0.406 1.265 SLICE_X37Y38 FDCE (Hold_fdce_C_D) 0.091 1.356 SNAKE/snakeColor_reg[G][4] ------------------------------------------------------------------- required time -1.356 arrival time 2.001 ------------------------------------------------------------------- slack 0.645 Slack (MET) : 0.648ns (arrival time - required time) Source: ROM/data_reg[22]/C (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: SNAKE/snakeColor_reg[R][3]/D (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out1_clk_wiz_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 0.519ns (logic 0.186ns (35.838%) route 0.333ns (64.162%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.642ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.858ns Source Clock Delay (SCD): 1.500ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O net (fo=1, routed) 0.627 0.886 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.588 1.500 ROM/H125MHz SLICE_X39Y36 FDRE r ROM/data_reg[22]/C ------------------------------------------------------------------- ------------------- SLICE_X39Y36 FDRE (Prop_fdre_C_Q) 0.141 1.641 r ROM/data_reg[22]/Q net (fo=1, routed) 0.333 1.974 SNAKE/spritesROMData[11] SLICE_X40Y36 LUT2 (Prop_lut2_I1_O) 0.045 2.019 r SNAKE/snakeColor[R][3]_i_1/O net (fo=1, routed) 0.000 2.019 SNAKE/snakeColor[R][3]_i_1_n_0 SLICE_X40Y36 FDCE r SNAKE/snakeColor_reg[R][3]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O net (fo=60, routed) 0.856 0.858 SNAKE/clk_out1 SLICE_X40Y36 FDCE r SNAKE/snakeColor_reg[R][3]/C clock pessimism 0.000 0.858 clock uncertainty 0.406 1.264 SLICE_X40Y36 FDCE (Hold_fdce_C_D) 0.107 1.371 SNAKE/snakeColor_reg[R][3] ------------------------------------------------------------------- required time -1.371 arrival time 2.019 ------------------------------------------------------------------- slack 0.648 --------------------------------------------------------------------------------------------------- From Clock: clk_out1_clk_wiz_1 To Clock: sys_clk_pin Setup : 21 Failing Endpoints, Worst Slack -3.437ns, Total Violation -39.544ns Hold : 1 Failing Endpoint , Worst Slack -0.025ns, Total Violation -0.025ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (VIOLATED) : -3.437ns (required time - arrival time) Source: SYNC/comptX_reg[4]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: SNAKE/ROMAddress_reg[9]/D (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: sys_clk_pin Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (sys_clk_pin rise@8.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 14.360ns (logic 3.985ns (27.750%) route 10.375ns (72.250%)) Logic Levels: 13 (CARRY4=4 LUT2=1 LUT3=1 LUT4=1 LUT6=6) Clock Path Skew: 3.220ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.883ns = ( 12.883 - 8.000 ) Source Clock Delay (SCD): 1.663ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.660 1.663 SYNC/clk_out1 SLICE_X29Y21 FDRE r SYNC/comptX_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X29Y21 FDRE (Prop_fdre_C_Q) 0.419 2.082 r SYNC/comptX_reg[4]/Q net (fo=10, routed) 1.606 3.688 SYNC/comptX_reg__0[4] SLICE_X28Y20 LUT3 (Prop_lut3_I1_O) 0.299 3.987 r SYNC/comptY[9]_i_4/O net (fo=10, routed) 1.071 5.058 SYNC/comptY[9]_i_4_n_0 SLICE_X27Y24 LUT6 (Prop_lut6_I4_O) 0.124 5.182 r SYNC/ROMAddress[7]_i_113/O net (fo=54, routed) 1.047 6.229 SYNC/Xi[0] SLICE_X23Y28 CARRY4 (Prop_carry4_DI[0]_O[2]) 0.556 6.785 r SYNC/ROMAddress_reg[7]_i_252/O[2] net (fo=5, routed) 1.352 8.137 RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_40_1[1] SLICE_X22Y28 LUT4 (Prop_lut4_I3_O) 0.302 8.439 r RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_108/O net (fo=1, routed) 0.000 8.439 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_108_n_0 SLICE_X22Y28 CARRY4 (Prop_carry4_S[1]_O[3]) 0.640 9.079 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_40/O[3] net (fo=2, routed) 1.031 10.110 RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_40_n_4 SLICE_X15Y29 LUT6 (Prop_lut6_I0_O) 0.306 10.416 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_214/O net (fo=6, routed) 0.774 11.189 RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_214_n_0 SLICE_X10Y29 LUT2 (Prop_lut2_I1_O) 0.124 11.313 r RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_263/O net (fo=1, routed) 0.793 12.107 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_263_n_0 SLICE_X17Y28 LUT6 (Prop_lut6_I2_O) 0.124 12.231 r RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_128/O net (fo=1, routed) 0.658 12.889 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_128_n_0 SLICE_X16Y29 LUT6 (Prop_lut6_I5_O) 0.124 13.013 f RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_46/O net (fo=1, routed) 0.559 13.572 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_46_n_0 SLICE_X16Y29 LUT6 (Prop_lut6_I5_O) 0.124 13.696 f RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_15/O net (fo=3, routed) 0.533 14.229 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_15_n_0 SLICE_X16Y29 LUT6 (Prop_lut6_I5_O) 0.124 14.353 r RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_2/O net (fo=1, routed) 0.951 15.304 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_2_n_0 SLICE_X20Y29 CARRY4 (Prop_carry4_DI[3]_CO[3]) 0.396 15.700 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_1/CO[3] net (fo=1, routed) 0.000 15.700 RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_1_n_0 SLICE_X20Y30 CARRY4 (Prop_carry4_CI_O[1]) 0.323 16.023 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_2/O[1] net (fo=1, routed) 0.000 16.023 SNAKE/D[9] SLICE_X20Y30 FDRE r SNAKE/ROMAddress_reg[9]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 8.000 8.000 r L16 0.000 8.000 r H125MHz (IN) net (fo=0) 0.000 8.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O net (fo=1, routed) 1.880 11.301 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.491 12.883 SNAKE/H125MHz SLICE_X20Y30 FDRE r SNAKE/ROMAddress_reg[9]/C clock pessimism 0.000 12.883 clock uncertainty -0.406 12.477 SLICE_X20Y30 FDRE (Setup_fdre_C_D) 0.109 12.586 SNAKE/ROMAddress_reg[9] ------------------------------------------------------------------- required time 12.586 arrival time -16.023 ------------------------------------------------------------------- slack -3.437 Slack (VIOLATED) : -3.333ns (required time - arrival time) Source: SYNC/comptX_reg[4]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: SNAKE/ROMAddress_reg[8]/D (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: sys_clk_pin Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (sys_clk_pin rise@8.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 14.256ns (logic 3.881ns (27.223%) route 10.375ns (72.777%)) Logic Levels: 13 (CARRY4=4 LUT2=1 LUT3=1 LUT4=1 LUT6=6) Clock Path Skew: 3.220ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.883ns = ( 12.883 - 8.000 ) Source Clock Delay (SCD): 1.663ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.660 1.663 SYNC/clk_out1 SLICE_X29Y21 FDRE r SYNC/comptX_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X29Y21 FDRE (Prop_fdre_C_Q) 0.419 2.082 r SYNC/comptX_reg[4]/Q net (fo=10, routed) 1.606 3.688 SYNC/comptX_reg__0[4] SLICE_X28Y20 LUT3 (Prop_lut3_I1_O) 0.299 3.987 r SYNC/comptY[9]_i_4/O net (fo=10, routed) 1.071 5.058 SYNC/comptY[9]_i_4_n_0 SLICE_X27Y24 LUT6 (Prop_lut6_I4_O) 0.124 5.182 r SYNC/ROMAddress[7]_i_113/O net (fo=54, routed) 1.047 6.229 SYNC/Xi[0] SLICE_X23Y28 CARRY4 (Prop_carry4_DI[0]_O[2]) 0.556 6.785 r SYNC/ROMAddress_reg[7]_i_252/O[2] net (fo=5, routed) 1.352 8.137 RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_40_1[1] SLICE_X22Y28 LUT4 (Prop_lut4_I3_O) 0.302 8.439 r RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_108/O net (fo=1, routed) 0.000 8.439 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_108_n_0 SLICE_X22Y28 CARRY4 (Prop_carry4_S[1]_O[3]) 0.640 9.079 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_40/O[3] net (fo=2, routed) 1.031 10.110 RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_40_n_4 SLICE_X15Y29 LUT6 (Prop_lut6_I0_O) 0.306 10.416 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_214/O net (fo=6, routed) 0.774 11.189 RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_214_n_0 SLICE_X10Y29 LUT2 (Prop_lut2_I1_O) 0.124 11.313 r RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_263/O net (fo=1, routed) 0.793 12.107 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_263_n_0 SLICE_X17Y28 LUT6 (Prop_lut6_I2_O) 0.124 12.231 r RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_128/O net (fo=1, routed) 0.658 12.889 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_128_n_0 SLICE_X16Y29 LUT6 (Prop_lut6_I5_O) 0.124 13.013 f RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_46/O net (fo=1, routed) 0.559 13.572 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_46_n_0 SLICE_X16Y29 LUT6 (Prop_lut6_I5_O) 0.124 13.696 f RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_15/O net (fo=3, routed) 0.533 14.229 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_15_n_0 SLICE_X16Y29 LUT6 (Prop_lut6_I5_O) 0.124 14.353 r RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_2/O net (fo=1, routed) 0.951 15.304 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_2_n_0 SLICE_X20Y29 CARRY4 (Prop_carry4_DI[3]_CO[3]) 0.396 15.700 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_1/CO[3] net (fo=1, routed) 0.000 15.700 RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_1_n_0 SLICE_X20Y30 CARRY4 (Prop_carry4_CI_O[0]) 0.219 15.919 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_2/O[0] net (fo=1, routed) 0.000 15.919 SNAKE/D[8] SLICE_X20Y30 FDRE r SNAKE/ROMAddress_reg[8]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 8.000 8.000 r L16 0.000 8.000 r H125MHz (IN) net (fo=0) 0.000 8.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O net (fo=1, routed) 1.880 11.301 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.491 12.883 SNAKE/H125MHz SLICE_X20Y30 FDRE r SNAKE/ROMAddress_reg[8]/C clock pessimism 0.000 12.883 clock uncertainty -0.406 12.477 SLICE_X20Y30 FDRE (Setup_fdre_C_D) 0.109 12.586 SNAKE/ROMAddress_reg[8] ------------------------------------------------------------------- required time 12.586 arrival time -15.919 ------------------------------------------------------------------- slack -3.333 Slack (VIOLATED) : -2.495ns (required time - arrival time) Source: SYNC/comptX_reg[4]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: SNAKE/ROMAddress_reg[7]/D (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: sys_clk_pin Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (sys_clk_pin rise@8.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 13.418ns (logic 3.618ns (26.963%) route 9.800ns (73.037%)) Logic Levels: 12 (CARRY4=3 LUT2=1 LUT3=1 LUT4=1 LUT5=1 LUT6=5) Clock Path Skew: 3.220ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.883ns = ( 12.883 - 8.000 ) Source Clock Delay (SCD): 1.663ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.660 1.663 SYNC/clk_out1 SLICE_X29Y21 FDRE r SYNC/comptX_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X29Y21 FDRE (Prop_fdre_C_Q) 0.419 2.082 r SYNC/comptX_reg[4]/Q net (fo=10, routed) 1.606 3.688 SYNC/comptX_reg__0[4] SLICE_X28Y20 LUT3 (Prop_lut3_I1_O) 0.299 3.987 r SYNC/comptY[9]_i_4/O net (fo=10, routed) 1.071 5.058 SYNC/comptY[9]_i_4_n_0 SLICE_X27Y24 LUT6 (Prop_lut6_I4_O) 0.124 5.182 r SYNC/ROMAddress[7]_i_113/O net (fo=54, routed) 1.047 6.229 SYNC/Xi[0] SLICE_X23Y28 CARRY4 (Prop_carry4_DI[0]_O[2]) 0.556 6.785 r SYNC/ROMAddress_reg[7]_i_252/O[2] net (fo=5, routed) 1.352 8.137 RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_40_1[1] SLICE_X22Y28 LUT4 (Prop_lut4_I3_O) 0.302 8.439 r RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_108/O net (fo=1, routed) 0.000 8.439 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_108_n_0 SLICE_X22Y28 CARRY4 (Prop_carry4_S[1]_O[3]) 0.640 9.079 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_40/O[3] net (fo=2, routed) 1.031 10.110 RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_40_n_4 SLICE_X15Y29 LUT6 (Prop_lut6_I0_O) 0.306 10.416 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_214/O net (fo=6, routed) 0.774 11.189 RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_214_n_0 SLICE_X10Y29 LUT2 (Prop_lut2_I1_O) 0.124 11.313 r RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_263/O net (fo=1, routed) 0.793 12.107 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_263_n_0 SLICE_X17Y28 LUT6 (Prop_lut6_I2_O) 0.124 12.231 f RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_128/O net (fo=1, routed) 0.658 12.889 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_128_n_0 SLICE_X16Y29 LUT6 (Prop_lut6_I5_O) 0.124 13.013 r RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_46/O net (fo=1, routed) 0.559 13.572 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_46_n_0 SLICE_X16Y29 LUT6 (Prop_lut6_I5_O) 0.124 13.696 r RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_15/O net (fo=3, routed) 0.909 14.605 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_15_n_0 SLICE_X20Y29 LUT5 (Prop_lut5_I3_O) 0.124 14.729 r RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_7/O net (fo=1, routed) 0.000 14.729 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_7_n_0 SLICE_X20Y29 CARRY4 (Prop_carry4_S[2]_O[3]) 0.352 15.081 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_1/O[3] net (fo=1, routed) 0.000 15.081 SNAKE/D[7] SLICE_X20Y29 FDRE r SNAKE/ROMAddress_reg[7]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 8.000 8.000 r L16 0.000 8.000 r H125MHz (IN) net (fo=0) 0.000 8.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O net (fo=1, routed) 1.880 11.301 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.491 12.883 SNAKE/H125MHz SLICE_X20Y29 FDRE r SNAKE/ROMAddress_reg[7]/C clock pessimism 0.000 12.883 clock uncertainty -0.406 12.477 SLICE_X20Y29 FDRE (Setup_fdre_C_D) 0.109 12.586 SNAKE/ROMAddress_reg[7] ------------------------------------------------------------------- required time 12.586 arrival time -15.081 ------------------------------------------------------------------- slack -2.495 Slack (VIOLATED) : -2.393ns (required time - arrival time) Source: SYNC/comptX_reg[4]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: SNAKE/ROMAddress_reg[6]/D (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: sys_clk_pin Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (sys_clk_pin rise@8.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 13.316ns (logic 3.516ns (26.403%) route 9.800ns (73.597%)) Logic Levels: 12 (CARRY4=3 LUT2=1 LUT3=1 LUT4=1 LUT5=1 LUT6=5) Clock Path Skew: 3.220ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.883ns = ( 12.883 - 8.000 ) Source Clock Delay (SCD): 1.663ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.660 1.663 SYNC/clk_out1 SLICE_X29Y21 FDRE r SYNC/comptX_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X29Y21 FDRE (Prop_fdre_C_Q) 0.419 2.082 r SYNC/comptX_reg[4]/Q net (fo=10, routed) 1.606 3.688 SYNC/comptX_reg__0[4] SLICE_X28Y20 LUT3 (Prop_lut3_I1_O) 0.299 3.987 r SYNC/comptY[9]_i_4/O net (fo=10, routed) 1.071 5.058 SYNC/comptY[9]_i_4_n_0 SLICE_X27Y24 LUT6 (Prop_lut6_I4_O) 0.124 5.182 r SYNC/ROMAddress[7]_i_113/O net (fo=54, routed) 1.047 6.229 SYNC/Xi[0] SLICE_X23Y28 CARRY4 (Prop_carry4_DI[0]_O[2]) 0.556 6.785 r SYNC/ROMAddress_reg[7]_i_252/O[2] net (fo=5, routed) 1.352 8.137 RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_40_1[1] SLICE_X22Y28 LUT4 (Prop_lut4_I3_O) 0.302 8.439 r RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_108/O net (fo=1, routed) 0.000 8.439 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_108_n_0 SLICE_X22Y28 CARRY4 (Prop_carry4_S[1]_O[3]) 0.640 9.079 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_40/O[3] net (fo=2, routed) 1.031 10.110 RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_40_n_4 SLICE_X15Y29 LUT6 (Prop_lut6_I0_O) 0.306 10.416 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_214/O net (fo=6, routed) 0.774 11.189 RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_214_n_0 SLICE_X10Y29 LUT2 (Prop_lut2_I1_O) 0.124 11.313 r RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_263/O net (fo=1, routed) 0.793 12.107 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_263_n_0 SLICE_X17Y28 LUT6 (Prop_lut6_I2_O) 0.124 12.231 f RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_128/O net (fo=1, routed) 0.658 12.889 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_128_n_0 SLICE_X16Y29 LUT6 (Prop_lut6_I5_O) 0.124 13.013 r RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_46/O net (fo=1, routed) 0.559 13.572 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_46_n_0 SLICE_X16Y29 LUT6 (Prop_lut6_I5_O) 0.124 13.696 r RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_15/O net (fo=3, routed) 0.909 14.605 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_15_n_0 SLICE_X20Y29 LUT5 (Prop_lut5_I3_O) 0.124 14.729 r RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_7/O net (fo=1, routed) 0.000 14.729 RAMCTRL/SNAKE_RAM/ROMAddress[7]_i_7_n_0 SLICE_X20Y29 CARRY4 (Prop_carry4_S[2]_O[2]) 0.250 14.979 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_1/O[2] net (fo=1, routed) 0.000 14.979 SNAKE/D[6] SLICE_X20Y29 FDRE r SNAKE/ROMAddress_reg[6]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 8.000 8.000 r L16 0.000 8.000 r H125MHz (IN) net (fo=0) 0.000 8.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O net (fo=1, routed) 1.880 11.301 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.491 12.883 SNAKE/H125MHz SLICE_X20Y29 FDRE r SNAKE/ROMAddress_reg[6]/C clock pessimism 0.000 12.883 clock uncertainty -0.406 12.477 SLICE_X20Y29 FDRE (Setup_fdre_C_D) 0.109 12.586 SNAKE/ROMAddress_reg[6] ------------------------------------------------------------------- required time 12.586 arrival time -14.979 ------------------------------------------------------------------- slack -2.393 Slack (VIOLATED) : -2.382ns (required time - arrival time) Source: SYNC/comptX_reg[10]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: SNAKE/ROMAddress_reg[5]/D (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: sys_clk_pin Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (sys_clk_pin rise@8.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 13.305ns (logic 3.333ns (25.050%) route 9.972ns (74.950%)) Logic Levels: 14 (CARRY4=4 LUT2=1 LUT5=3 LUT6=6) Clock Path Skew: 3.220ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.883ns = ( 12.883 - 8.000 ) Source Clock Delay (SCD): 1.663ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.660 1.663 SYNC/clk_out1 SLICE_X27Y20 FDRE r SYNC/comptX_reg[10]/C ------------------------------------------------------------------- ------------------- SLICE_X27Y20 FDRE (Prop_fdre_C_Q) 0.456 2.119 f SYNC/comptX_reg[10]/Q net (fo=19, routed) 1.176 3.295 SYNC/comptX_reg__0[10] SLICE_X26Y20 LUT2 (Prop_lut2_I1_O) 0.124 3.419 f SYNC/cCaseX[0]_i_3/O net (fo=2, routed) 1.479 4.898 SYNC/cCaseX[0]_i_3_n_0 SLICE_X26Y25 LUT6 (Prop_lut6_I1_O) 0.124 5.022 r SYNC/cCaseX[1]_i_2/O net (fo=1, routed) 0.586 5.608 SYNC/cCaseX[1]_i_2_n_0 SLICE_X26Y25 LUT5 (Prop_lut5_I4_O) 0.124 5.732 r SYNC/cCaseX[1]_i_1/O net (fo=55, routed) 1.269 7.001 RAMCTRL/SNAKE_RAM/Xi[5] SLICE_X31Y25 LUT5 (Prop_lut5_I1_O) 0.124 7.125 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_618/O net (fo=1, routed) 0.000 7.125 RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_618_n_0 SLICE_X31Y25 CARRY4 (Prop_carry4_S[2]_CO[3]) 0.398 7.523 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_327/CO[3] net (fo=1, routed) 0.000 7.523 RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_327_n_0 SLICE_X31Y26 CARRY4 (Prop_carry4_CI_CO[0]) 0.271 7.794 f RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_113/CO[0] net (fo=1, routed) 0.836 8.630 RAMCTRL/SNAKE_RAM/SNAKE/snakeHere5 SLICE_X25Y27 LUT5 (Prop_lut5_I1_O) 0.373 9.003 f RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_35/O net (fo=13, routed) 0.982 9.985 RAMCTRL/SNAKE_RAM/mem_reg_7_0_4 SLICE_X25Y27 LUT6 (Prop_lut6_I5_O) 0.124 10.109 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_10/O net (fo=10, routed) 0.705 10.814 RAMCTRL/SNAKE_RAM/mem_reg_8_0_4 SLICE_X25Y30 LUT6 (Prop_lut6_I2_O) 0.124 10.938 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_72/O net (fo=1, routed) 0.593 11.531 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_72_n_0 SLICE_X24Y29 LUT6 (Prop_lut6_I4_O) 0.124 11.655 f RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_27/O net (fo=2, routed) 0.761 12.416 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_27_n_0 SLICE_X19Y27 LUT6 (Prop_lut6_I3_O) 0.124 12.540 f RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_10/O net (fo=1, routed) 0.714 13.254 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_10_n_0 SLICE_X19Y28 LUT6 (Prop_lut6_I0_O) 0.124 13.378 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_2/O net (fo=1, routed) 0.871 14.249 RAMCTRL/SNAKE_RAM/SNAKE/p_11_out[3] SLICE_X20Y28 CARRY4 (Prop_carry4_DI[3]_CO[3]) 0.396 14.645 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_1/CO[3] net (fo=1, routed) 0.000 14.645 RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_1_n_0 SLICE_X20Y29 CARRY4 (Prop_carry4_CI_O[1]) 0.323 14.968 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_1/O[1] net (fo=1, routed) 0.000 14.968 SNAKE/D[5] SLICE_X20Y29 FDRE r SNAKE/ROMAddress_reg[5]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 8.000 8.000 r L16 0.000 8.000 r H125MHz (IN) net (fo=0) 0.000 8.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O net (fo=1, routed) 1.880 11.301 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.491 12.883 SNAKE/H125MHz SLICE_X20Y29 FDRE r SNAKE/ROMAddress_reg[5]/C clock pessimism 0.000 12.883 clock uncertainty -0.406 12.477 SLICE_X20Y29 FDRE (Setup_fdre_C_D) 0.109 12.586 SNAKE/ROMAddress_reg[5] ------------------------------------------------------------------- required time 12.586 arrival time -14.968 ------------------------------------------------------------------- slack -2.382 Slack (VIOLATED) : -2.278ns (required time - arrival time) Source: SYNC/comptX_reg[10]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: SNAKE/ROMAddress_reg[4]/D (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: sys_clk_pin Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (sys_clk_pin rise@8.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 13.201ns (logic 3.229ns (24.459%) route 9.972ns (75.541%)) Logic Levels: 14 (CARRY4=4 LUT2=1 LUT5=3 LUT6=6) Clock Path Skew: 3.220ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.883ns = ( 12.883 - 8.000 ) Source Clock Delay (SCD): 1.663ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.660 1.663 SYNC/clk_out1 SLICE_X27Y20 FDRE r SYNC/comptX_reg[10]/C ------------------------------------------------------------------- ------------------- SLICE_X27Y20 FDRE (Prop_fdre_C_Q) 0.456 2.119 f SYNC/comptX_reg[10]/Q net (fo=19, routed) 1.176 3.295 SYNC/comptX_reg__0[10] SLICE_X26Y20 LUT2 (Prop_lut2_I1_O) 0.124 3.419 f SYNC/cCaseX[0]_i_3/O net (fo=2, routed) 1.479 4.898 SYNC/cCaseX[0]_i_3_n_0 SLICE_X26Y25 LUT6 (Prop_lut6_I1_O) 0.124 5.022 r SYNC/cCaseX[1]_i_2/O net (fo=1, routed) 0.586 5.608 SYNC/cCaseX[1]_i_2_n_0 SLICE_X26Y25 LUT5 (Prop_lut5_I4_O) 0.124 5.732 r SYNC/cCaseX[1]_i_1/O net (fo=55, routed) 1.269 7.001 RAMCTRL/SNAKE_RAM/Xi[5] SLICE_X31Y25 LUT5 (Prop_lut5_I1_O) 0.124 7.125 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_618/O net (fo=1, routed) 0.000 7.125 RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_618_n_0 SLICE_X31Y25 CARRY4 (Prop_carry4_S[2]_CO[3]) 0.398 7.523 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_327/CO[3] net (fo=1, routed) 0.000 7.523 RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_327_n_0 SLICE_X31Y26 CARRY4 (Prop_carry4_CI_CO[0]) 0.271 7.794 f RAMCTRL/SNAKE_RAM/ROMAddress_reg[9]_i_113/CO[0] net (fo=1, routed) 0.836 8.630 RAMCTRL/SNAKE_RAM/SNAKE/snakeHere5 SLICE_X25Y27 LUT5 (Prop_lut5_I1_O) 0.373 9.003 f RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_35/O net (fo=13, routed) 0.982 9.985 RAMCTRL/SNAKE_RAM/mem_reg_7_0_4 SLICE_X25Y27 LUT6 (Prop_lut6_I5_O) 0.124 10.109 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_10/O net (fo=10, routed) 0.705 10.814 RAMCTRL/SNAKE_RAM/mem_reg_8_0_4 SLICE_X25Y30 LUT6 (Prop_lut6_I2_O) 0.124 10.938 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_72/O net (fo=1, routed) 0.593 11.531 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_72_n_0 SLICE_X24Y29 LUT6 (Prop_lut6_I4_O) 0.124 11.655 f RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_27/O net (fo=2, routed) 0.761 12.416 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_27_n_0 SLICE_X19Y27 LUT6 (Prop_lut6_I3_O) 0.124 12.540 f RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_10/O net (fo=1, routed) 0.714 13.254 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_10_n_0 SLICE_X19Y28 LUT6 (Prop_lut6_I0_O) 0.124 13.378 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_2/O net (fo=1, routed) 0.871 14.249 RAMCTRL/SNAKE_RAM/SNAKE/p_11_out[3] SLICE_X20Y28 CARRY4 (Prop_carry4_DI[3]_CO[3]) 0.396 14.645 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_1/CO[3] net (fo=1, routed) 0.000 14.645 RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_1_n_0 SLICE_X20Y29 CARRY4 (Prop_carry4_CI_O[0]) 0.219 14.864 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[7]_i_1/O[0] net (fo=1, routed) 0.000 14.864 SNAKE/D[4] SLICE_X20Y29 FDRE r SNAKE/ROMAddress_reg[4]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 8.000 8.000 r L16 0.000 8.000 r H125MHz (IN) net (fo=0) 0.000 8.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O net (fo=1, routed) 1.880 11.301 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.491 12.883 SNAKE/H125MHz SLICE_X20Y29 FDRE r SNAKE/ROMAddress_reg[4]/C clock pessimism 0.000 12.883 clock uncertainty -0.406 12.477 SLICE_X20Y29 FDRE (Setup_fdre_C_D) 0.109 12.586 SNAKE/ROMAddress_reg[4] ------------------------------------------------------------------- required time 12.586 arrival time -14.864 ------------------------------------------------------------------- slack -2.278 Slack (VIOLATED) : -1.898ns (required time - arrival time) Source: SYNC/comptX_reg[4]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: SNAKE/ROMAddress_reg[3]/D (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: sys_clk_pin Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (sys_clk_pin rise@8.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 12.820ns (logic 2.983ns (23.268%) route 9.837ns (76.732%)) Logic Levels: 12 (CARRY4=3 LUT3=1 LUT4=1 LUT5=3 LUT6=4) Clock Path Skew: 3.219ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.882ns = ( 12.882 - 8.000 ) Source Clock Delay (SCD): 1.663ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.660 1.663 SYNC/clk_out1 SLICE_X29Y21 FDRE r SYNC/comptX_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X29Y21 FDRE (Prop_fdre_C_Q) 0.419 2.082 r SYNC/comptX_reg[4]/Q net (fo=10, routed) 1.606 3.688 SYNC/comptX_reg__0[4] SLICE_X28Y20 LUT3 (Prop_lut3_I1_O) 0.299 3.987 r SYNC/comptY[9]_i_4/O net (fo=10, routed) 1.017 5.004 SYNC/comptY[9]_i_4_n_0 SLICE_X27Y20 LUT5 (Prop_lut5_I4_O) 0.124 5.128 r SYNC/cCaseX[3]_i_1/O net (fo=55, routed) 1.817 6.945 RAMCTRL/SNAKE_RAM/Xi[7] SLICE_X11Y30 LUT6 (Prop_lut6_I0_O) 0.124 7.069 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_376/O net (fo=1, routed) 0.394 7.463 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_376_n_0 SLICE_X13Y29 LUT6 (Prop_lut6_I0_O) 0.124 7.587 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_275/O net (fo=1, routed) 0.000 7.587 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_275_n_0 SLICE_X13Y29 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.401 7.988 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_125/CO[3] net (fo=1, routed) 0.000 7.988 RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_125_n_0 SLICE_X13Y30 CARRY4 (Prop_carry4_CI_CO[0]) 0.271 8.259 f RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_49/CO[0] net (fo=1, routed) 0.844 9.104 RAMCTRL/SNAKE_RAM/SNAKE/snakeHere524_in SLICE_X14Y28 LUT5 (Prop_lut5_I2_O) 0.373 9.477 f RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_14/O net (fo=25, routed) 1.167 10.644 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_14_n_0 SLICE_X18Y33 LUT6 (Prop_lut6_I0_O) 0.124 10.768 f RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_26/O net (fo=11, routed) 1.228 11.996 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_26_n_0 SLICE_X20Y26 LUT5 (Prop_lut5_I0_O) 0.124 12.120 f RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_16/O net (fo=1, routed) 0.900 13.020 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_16_n_0 SLICE_X21Y28 LUT6 (Prop_lut6_I2_O) 0.124 13.144 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_3/O net (fo=2, routed) 0.864 14.007 RAMCTRL/SNAKE_RAM/SNAKE/p_11_out[2] SLICE_X20Y28 LUT4 (Prop_lut4_I0_O) 0.124 14.131 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_7/O net (fo=1, routed) 0.000 14.131 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_7_n_0 SLICE_X20Y28 CARRY4 (Prop_carry4_S[2]_O[3]) 0.352 14.483 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_1/O[3] net (fo=1, routed) 0.000 14.483 SNAKE/D[3] SLICE_X20Y28 FDRE r SNAKE/ROMAddress_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 8.000 8.000 r L16 0.000 8.000 r H125MHz (IN) net (fo=0) 0.000 8.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O net (fo=1, routed) 1.880 11.301 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.490 12.882 SNAKE/H125MHz SLICE_X20Y28 FDRE r SNAKE/ROMAddress_reg[3]/C clock pessimism 0.000 12.882 clock uncertainty -0.406 12.476 SLICE_X20Y28 FDRE (Setup_fdre_C_D) 0.109 12.585 SNAKE/ROMAddress_reg[3] ------------------------------------------------------------------- required time 12.585 arrival time -14.483 ------------------------------------------------------------------- slack -1.898 Slack (VIOLATED) : -1.833ns (required time - arrival time) Source: SYNC/comptX_reg[4]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: SNAKE/ROMAddress_reg[2]/D (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: sys_clk_pin Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (sys_clk_pin rise@8.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 12.755ns (logic 3.209ns (25.158%) route 9.546ns (74.842%)) Logic Levels: 12 (CARRY4=3 LUT3=1 LUT5=2 LUT6=6) Clock Path Skew: 3.219ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.882ns = ( 12.882 - 8.000 ) Source Clock Delay (SCD): 1.663ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.660 1.663 SYNC/clk_out1 SLICE_X29Y21 FDRE r SYNC/comptX_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X29Y21 FDRE (Prop_fdre_C_Q) 0.419 2.082 r SYNC/comptX_reg[4]/Q net (fo=10, routed) 1.606 3.688 SYNC/comptX_reg__0[4] SLICE_X28Y20 LUT3 (Prop_lut3_I1_O) 0.299 3.987 r SYNC/comptY[9]_i_4/O net (fo=10, routed) 1.017 5.004 SYNC/comptY[9]_i_4_n_0 SLICE_X27Y20 LUT5 (Prop_lut5_I4_O) 0.124 5.128 r SYNC/cCaseX[3]_i_1/O net (fo=55, routed) 1.817 6.945 RAMCTRL/SNAKE_RAM/Xi[7] SLICE_X11Y30 LUT6 (Prop_lut6_I0_O) 0.124 7.069 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_376/O net (fo=1, routed) 0.394 7.463 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_376_n_0 SLICE_X13Y29 LUT6 (Prop_lut6_I0_O) 0.124 7.587 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_275/O net (fo=1, routed) 0.000 7.587 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_275_n_0 SLICE_X13Y29 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.401 7.988 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_125/CO[3] net (fo=1, routed) 0.000 7.988 RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_125_n_0 SLICE_X13Y30 CARRY4 (Prop_carry4_CI_CO[0]) 0.271 8.259 f RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_49/CO[0] net (fo=1, routed) 0.844 9.104 RAMCTRL/SNAKE_RAM/SNAKE/snakeHere524_in SLICE_X14Y28 LUT5 (Prop_lut5_I2_O) 0.373 9.477 f RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_14/O net (fo=25, routed) 1.167 10.644 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_14_n_0 SLICE_X18Y33 LUT6 (Prop_lut6_I0_O) 0.124 10.768 f RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_26/O net (fo=11, routed) 1.099 11.867 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_26_n_0 SLICE_X18Y27 LUT6 (Prop_lut6_I0_O) 0.124 11.991 f RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_19/O net (fo=1, routed) 0.736 12.728 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_19_n_0 SLICE_X20Y27 LUT6 (Prop_lut6_I0_O) 0.124 12.852 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_4/O net (fo=2, routed) 0.865 13.716 RAMCTRL/SNAKE_RAM/SNAKE/p_11_out[1] SLICE_X20Y28 LUT6 (Prop_lut6_I0_O) 0.124 13.840 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_8/O net (fo=1, routed) 0.000 13.840 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_8_n_0 SLICE_X20Y28 CARRY4 (Prop_carry4_S[1]_O[2]) 0.578 14.418 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_1/O[2] net (fo=1, routed) 0.000 14.418 SNAKE/D[2] SLICE_X20Y28 FDRE r SNAKE/ROMAddress_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 8.000 8.000 r L16 0.000 8.000 r H125MHz (IN) net (fo=0) 0.000 8.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O net (fo=1, routed) 1.880 11.301 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.490 12.882 SNAKE/H125MHz SLICE_X20Y28 FDRE r SNAKE/ROMAddress_reg[2]/C clock pessimism 0.000 12.882 clock uncertainty -0.406 12.476 SLICE_X20Y28 FDRE (Setup_fdre_C_D) 0.109 12.585 SNAKE/ROMAddress_reg[2] ------------------------------------------------------------------- required time 12.585 arrival time -14.418 ------------------------------------------------------------------- slack -1.833 Slack (VIOLATED) : -1.756ns (required time - arrival time) Source: SYNC/comptX_reg[4]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: SNAKE/ROMAddress_reg[4]/CE (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: sys_clk_pin Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (sys_clk_pin rise@8.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 12.401ns (logic 2.507ns (20.216%) route 9.894ns (79.784%)) Logic Levels: 10 (CARRY4=2 LUT3=2 LUT4=1 LUT5=3 LUT6=2) Clock Path Skew: 3.220ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.883ns = ( 12.883 - 8.000 ) Source Clock Delay (SCD): 1.663ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.660 1.663 SYNC/clk_out1 SLICE_X29Y21 FDRE r SYNC/comptX_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X29Y21 FDRE (Prop_fdre_C_Q) 0.419 2.082 r SYNC/comptX_reg[4]/Q net (fo=10, routed) 1.606 3.688 SYNC/comptX_reg__0[4] SLICE_X28Y20 LUT3 (Prop_lut3_I1_O) 0.299 3.987 r SYNC/comptY[9]_i_4/O net (fo=10, routed) 1.017 5.004 SYNC/comptY[9]_i_4_n_0 SLICE_X27Y20 LUT5 (Prop_lut5_I4_O) 0.124 5.128 r SYNC/cCaseX[3]_i_1/O net (fo=55, routed) 1.817 6.945 RAMCTRL/SNAKE_RAM/Xi[7] SLICE_X11Y30 LUT6 (Prop_lut6_I0_O) 0.124 7.069 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_376/O net (fo=1, routed) 0.394 7.463 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_376_n_0 SLICE_X13Y29 LUT6 (Prop_lut6_I0_O) 0.124 7.587 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_275/O net (fo=1, routed) 0.000 7.587 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_275_n_0 SLICE_X13Y29 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.401 7.988 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_125/CO[3] net (fo=1, routed) 0.000 7.988 RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_125_n_0 SLICE_X13Y30 CARRY4 (Prop_carry4_CI_CO[0]) 0.271 8.259 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_49/CO[0] net (fo=1, routed) 0.844 9.104 RAMCTRL/SNAKE_RAM/SNAKE/snakeHere524_in SLICE_X14Y28 LUT5 (Prop_lut5_I2_O) 0.373 9.477 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_14/O net (fo=25, routed) 1.325 10.802 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_14_n_0 SLICE_X15Y32 LUT4 (Prop_lut4_I3_O) 0.124 10.926 f RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_7/O net (fo=10, routed) 0.963 11.889 RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_7_n_0 SLICE_X18Y34 LUT5 (Prop_lut5_I0_O) 0.124 12.013 f RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_3/O net (fo=2, routed) 0.898 12.910 RAMCTRL/SNAKE_RAM/mem_reg_9_0_4 SLICE_X18Y34 LUT3 (Prop_lut3_I2_O) 0.124 13.034 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_1/O net (fo=10, routed) 1.030 14.064 SNAKE/E[0] SLICE_X20Y29 FDRE r SNAKE/ROMAddress_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 8.000 8.000 r L16 0.000 8.000 r H125MHz (IN) net (fo=0) 0.000 8.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O net (fo=1, routed) 1.880 11.301 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.491 12.883 SNAKE/H125MHz SLICE_X20Y29 FDRE r SNAKE/ROMAddress_reg[4]/C clock pessimism 0.000 12.883 clock uncertainty -0.406 12.477 SLICE_X20Y29 FDRE (Setup_fdre_C_CE) -0.169 12.308 SNAKE/ROMAddress_reg[4] ------------------------------------------------------------------- required time 12.308 arrival time -14.064 ------------------------------------------------------------------- slack -1.756 Slack (VIOLATED) : -1.756ns (required time - arrival time) Source: SYNC/comptX_reg[4]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: SNAKE/ROMAddress_reg[5]/CE (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: sys_clk_pin Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (sys_clk_pin rise@8.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 12.401ns (logic 2.507ns (20.216%) route 9.894ns (79.784%)) Logic Levels: 10 (CARRY4=2 LUT3=2 LUT4=1 LUT5=3 LUT6=2) Clock Path Skew: 3.220ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.883ns = ( 12.883 - 8.000 ) Source Clock Delay (SCD): 1.663ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.660 1.663 SYNC/clk_out1 SLICE_X29Y21 FDRE r SYNC/comptX_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X29Y21 FDRE (Prop_fdre_C_Q) 0.419 2.082 r SYNC/comptX_reg[4]/Q net (fo=10, routed) 1.606 3.688 SYNC/comptX_reg__0[4] SLICE_X28Y20 LUT3 (Prop_lut3_I1_O) 0.299 3.987 r SYNC/comptY[9]_i_4/O net (fo=10, routed) 1.017 5.004 SYNC/comptY[9]_i_4_n_0 SLICE_X27Y20 LUT5 (Prop_lut5_I4_O) 0.124 5.128 r SYNC/cCaseX[3]_i_1/O net (fo=55, routed) 1.817 6.945 RAMCTRL/SNAKE_RAM/Xi[7] SLICE_X11Y30 LUT6 (Prop_lut6_I0_O) 0.124 7.069 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_376/O net (fo=1, routed) 0.394 7.463 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_376_n_0 SLICE_X13Y29 LUT6 (Prop_lut6_I0_O) 0.124 7.587 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_275/O net (fo=1, routed) 0.000 7.587 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_275_n_0 SLICE_X13Y29 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.401 7.988 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_125/CO[3] net (fo=1, routed) 0.000 7.988 RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_125_n_0 SLICE_X13Y30 CARRY4 (Prop_carry4_CI_CO[0]) 0.271 8.259 r RAMCTRL/SNAKE_RAM/ROMAddress_reg[3]_i_49/CO[0] net (fo=1, routed) 0.844 9.104 RAMCTRL/SNAKE_RAM/SNAKE/snakeHere524_in SLICE_X14Y28 LUT5 (Prop_lut5_I2_O) 0.373 9.477 r RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_14/O net (fo=25, routed) 1.325 10.802 RAMCTRL/SNAKE_RAM/ROMAddress[3]_i_14_n_0 SLICE_X15Y32 LUT4 (Prop_lut4_I3_O) 0.124 10.926 f RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_7/O net (fo=10, routed) 0.963 11.889 RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_7_n_0 SLICE_X18Y34 LUT5 (Prop_lut5_I0_O) 0.124 12.013 f RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_3/O net (fo=2, routed) 0.898 12.910 RAMCTRL/SNAKE_RAM/mem_reg_9_0_4 SLICE_X18Y34 LUT3 (Prop_lut3_I2_O) 0.124 13.034 r RAMCTRL/SNAKE_RAM/ROMAddress[9]_i_1/O net (fo=10, routed) 1.030 14.064 SNAKE/E[0] SLICE_X20Y29 FDRE r SNAKE/ROMAddress_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 8.000 8.000 r L16 0.000 8.000 r H125MHz (IN) net (fo=0) 0.000 8.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O net (fo=1, routed) 1.880 11.301 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.491 12.883 SNAKE/H125MHz SLICE_X20Y29 FDRE r SNAKE/ROMAddress_reg[5]/C clock pessimism 0.000 12.883 clock uncertainty -0.406 12.477 SLICE_X20Y29 FDRE (Setup_fdre_C_CE) -0.169 12.308 SNAKE/ROMAddress_reg[5] ------------------------------------------------------------------- required time 12.308 arrival time -14.064 ------------------------------------------------------------------- slack -1.756 Min Delay Paths -------------------------------------------------------------------------------------- Slack (VIOLATED) : -0.025ns (arrival time - required time) Source: SYNC/comptY_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: SNAKE/cCaseY_reg[3]/D (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: sys_clk_pin Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (sys_clk_pin rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 4.437ns (logic 0.467ns (10.525%) route 3.970ns (89.475%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 3.838ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 5.326ns Source Clock Delay (SCD): 1.488ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.490 1.490 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.177 -1.687 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 -0.088 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 0.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.485 1.488 SYNC/clk_out1 SLICE_X19Y26 FDRE r SYNC/comptY_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X19Y26 FDRE (Prop_fdre_C_Q) 0.367 1.855 r SYNC/comptY_reg[7]/Q net (fo=11, routed) 1.151 3.007 SYNC/comptY_reg__0[7] SLICE_X27Y27 LUT6 (Prop_lut6_I4_O) 0.100 3.107 r SYNC/cCaseY[3]_i_1/O net (fo=55, routed) 2.819 5.925 SNAKE/Yi[3] SLICE_X20Y23 FDRE r SNAKE/cCaseY_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O net (fo=1, routed) 2.076 3.567 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.658 5.326 SNAKE/H125MHz SLICE_X20Y23 FDRE r SNAKE/cCaseY_reg[3]/C clock pessimism 0.000 5.326 clock uncertainty 0.406 5.732 SLICE_X20Y23 FDRE (Hold_fdre_C_D) 0.218 5.950 SNAKE/cCaseY_reg[3] ------------------------------------------------------------------- required time -5.950 arrival time 5.925 ------------------------------------------------------------------- slack -0.025 Slack (MET) : 0.106ns (arrival time - required time) Source: SYNC/comptX_reg[8]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: SNAKE/cCaseX_reg[1]/D (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: sys_clk_pin Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (sys_clk_pin rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 4.547ns (logic 0.467ns (10.271%) route 4.080ns (89.729%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 3.843ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 5.333ns Source Clock Delay (SCD): 1.490ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.490 1.490 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.177 -1.687 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 -0.088 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 0.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.487 1.490 SYNC/clk_out1 SLICE_X26Y21 FDRE r SYNC/comptX_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X26Y21 FDRE (Prop_fdre_C_Q) 0.367 1.857 r SYNC/comptX_reg[8]/Q net (fo=22, routed) 1.161 3.019 SYNC/comptX_reg__0[8] SLICE_X26Y25 LUT5 (Prop_lut5_I2_O) 0.100 3.119 r SYNC/cCaseX[1]_i_1/O net (fo=55, routed) 2.918 6.037 SNAKE/Xi[1] SLICE_X29Y19 FDRE r SNAKE/cCaseX_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O net (fo=1, routed) 2.076 3.567 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.665 5.333 SNAKE/H125MHz SLICE_X29Y19 FDRE r SNAKE/cCaseX_reg[1]/C clock pessimism 0.000 5.333 clock uncertainty 0.406 5.739 SLICE_X29Y19 FDRE (Hold_fdre_C_D) 0.192 5.931 SNAKE/cCaseX_reg[1] ------------------------------------------------------------------- required time -5.931 arrival time 6.037 ------------------------------------------------------------------- slack 0.106 Slack (MET) : 0.128ns (arrival time - required time) Source: SYNC/comptX_reg[6]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: SNAKE/cCaseX_reg[2]/D (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: sys_clk_pin Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (sys_clk_pin rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 4.568ns (logic 0.467ns (10.224%) route 4.101ns (89.776%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 3.842ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 5.332ns Source Clock Delay (SCD): 1.490ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.490 1.490 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.177 -1.687 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 -0.088 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 0.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.487 1.490 SYNC/clk_out1 SLICE_X29Y21 FDRE r SYNC/comptX_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X29Y21 FDRE (Prop_fdre_C_Q) 0.367 1.857 r SYNC/comptX_reg[6]/Q net (fo=13, routed) 1.123 2.980 SYNC/comptX_reg__0[6] SLICE_X27Y20 LUT6 (Prop_lut6_I4_O) 0.100 3.080 r SYNC/cCaseX[2]_i_1/O net (fo=55, routed) 2.978 6.058 SNAKE/Xi[2] SLICE_X18Y20 FDRE r SNAKE/cCaseX_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O net (fo=1, routed) 2.076 3.567 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.664 5.332 SNAKE/H125MHz SLICE_X18Y20 FDRE r SNAKE/cCaseX_reg[2]/C clock pessimism 0.000 5.332 clock uncertainty 0.406 5.738 SLICE_X18Y20 FDRE (Hold_fdre_C_D) 0.192 5.930 SNAKE/cCaseX_reg[2] ------------------------------------------------------------------- required time -5.930 arrival time 6.058 ------------------------------------------------------------------- slack 0.128 Slack (MET) : 0.159ns (arrival time - required time) Source: SYNC/comptY_reg[9]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: SNAKE/cCaseY_reg[2]/D (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: sys_clk_pin Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (sys_clk_pin rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 4.598ns (logic 0.467ns (10.156%) route 4.131ns (89.844%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 3.838ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 5.326ns Source Clock Delay (SCD): 1.488ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.490 1.490 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.177 -1.687 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 -0.088 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 0.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.485 1.488 SYNC/clk_out1 SLICE_X19Y26 FDRE r SYNC/comptY_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X19Y26 FDRE (Prop_fdre_C_Q) 0.367 1.855 f SYNC/comptY_reg[9]/Q net (fo=10, routed) 1.330 3.185 SYNC/comptY_reg__0[9] SLICE_X25Y27 LUT6 (Prop_lut6_I5_O) 0.100 3.285 r SYNC/cCaseY[2]_i_1/O net (fo=55, routed) 2.801 6.087 SNAKE/Yi[2] SLICE_X21Y23 FDRE r SNAKE/cCaseY_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O net (fo=1, routed) 2.076 3.567 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.658 5.326 SNAKE/H125MHz SLICE_X21Y23 FDRE r SNAKE/cCaseY_reg[2]/C clock pessimism 0.000 5.326 clock uncertainty 0.406 5.732 SLICE_X21Y23 FDRE (Hold_fdre_C_D) 0.196 5.928 SNAKE/cCaseY_reg[2] ------------------------------------------------------------------- required time -5.928 arrival time 6.087 ------------------------------------------------------------------- slack 0.159 Slack (MET) : 0.219ns (arrival time - required time) Source: SYNC/comptX_reg[8]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: SNAKE/cCaseX_reg[5]/D (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: sys_clk_pin Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (sys_clk_pin rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 4.663ns (logic 0.467ns (10.015%) route 4.196ns (89.985%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 3.846ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 5.336ns Source Clock Delay (SCD): 1.490ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.490 1.490 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.177 -1.687 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 -0.088 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 0.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.487 1.490 SYNC/clk_out1 SLICE_X26Y21 FDRE r SYNC/comptX_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X26Y21 FDRE (Prop_fdre_C_Q) 0.367 1.857 r SYNC/comptX_reg[8]/Q net (fo=22, routed) 0.935 2.792 SYNC/comptX_reg__0[8] SLICE_X30Y21 LUT5 (Prop_lut5_I4_O) 0.100 2.892 r SYNC/cCaseX[5]_i_2/O net (fo=46, routed) 3.261 6.153 SNAKE/Xi[5] SLICE_X18Y17 FDRE r SNAKE/cCaseX_reg[5]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O net (fo=1, routed) 2.076 3.567 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.668 5.336 SNAKE/H125MHz SLICE_X18Y17 FDRE r SNAKE/cCaseX_reg[5]/C clock pessimism 0.000 5.336 clock uncertainty 0.406 5.742 SLICE_X18Y17 FDRE (Hold_fdre_C_D) 0.192 5.934 SNAKE/cCaseX_reg[5] ------------------------------------------------------------------- required time -5.934 arrival time 6.153 ------------------------------------------------------------------- slack 0.219 Slack (MET) : 0.223ns (arrival time - required time) Source: SYNC/comptX_reg[8]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: SNAKE/cCaseX_reg[3]/D (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: sys_clk_pin Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (sys_clk_pin rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 4.667ns (logic 0.467ns (10.007%) route 4.200ns (89.993%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 3.846ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 5.336ns Source Clock Delay (SCD): 1.490ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.490 1.490 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.177 -1.687 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 -0.088 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 0.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.487 1.490 SYNC/clk_out1 SLICE_X26Y21 FDRE r SYNC/comptX_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X26Y21 FDRE (Prop_fdre_C_Q) 0.367 1.857 r SYNC/comptX_reg[8]/Q net (fo=22, routed) 1.126 2.983 SYNC/comptX_reg__0[8] SLICE_X27Y20 LUT5 (Prop_lut5_I1_O) 0.100 3.083 r SYNC/cCaseX[3]_i_1/O net (fo=55, routed) 3.074 6.157 SNAKE/Xi[3] SLICE_X29Y17 FDRE r SNAKE/cCaseX_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O net (fo=1, routed) 2.076 3.567 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.668 5.336 SNAKE/H125MHz SLICE_X29Y17 FDRE r SNAKE/cCaseX_reg[3]/C clock pessimism 0.000 5.336 clock uncertainty 0.406 5.742 SLICE_X29Y17 FDRE (Hold_fdre_C_D) 0.192 5.934 SNAKE/cCaseX_reg[3] ------------------------------------------------------------------- required time -5.934 arrival time 6.157 ------------------------------------------------------------------- slack 0.223 Slack (MET) : 0.239ns (arrival time - required time) Source: SYNC/comptY_reg[8]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: SNAKE/cCaseY_reg[1]/D (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: sys_clk_pin Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (sys_clk_pin rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 4.663ns (logic 0.578ns (12.397%) route 4.085ns (87.603%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 3.838ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 5.326ns Source Clock Delay (SCD): 1.488ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.490 1.490 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.177 -1.687 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 -0.088 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 0.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.485 1.488 SYNC/clk_out1 SLICE_X19Y26 FDRE r SYNC/comptY_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X19Y26 FDRE (Prop_fdre_C_Q) 0.337 1.825 r SYNC/comptY_reg[8]/Q net (fo=10, routed) 1.069 2.895 SYNC/comptY_reg__0[8] SLICE_X21Y26 LUT6 (Prop_lut6_I4_O) 0.241 3.136 r SYNC/cCaseY[1]_i_1/O net (fo=55, routed) 3.015 6.151 SNAKE/Yi[1] SLICE_X21Y23 FDRE r SNAKE/cCaseY_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O net (fo=1, routed) 2.076 3.567 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.658 5.326 SNAKE/H125MHz SLICE_X21Y23 FDRE r SNAKE/cCaseY_reg[1]/C clock pessimism 0.000 5.326 clock uncertainty 0.406 5.732 SLICE_X21Y23 FDRE (Hold_fdre_C_D) 0.180 5.912 SNAKE/cCaseY_reg[1] ------------------------------------------------------------------- required time -5.912 arrival time 6.151 ------------------------------------------------------------------- slack 0.239 Slack (MET) : 0.275ns (arrival time - required time) Source: SYNC/comptY_reg[5]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: SNAKE/cCaseY_reg[4]/D (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: sys_clk_pin Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (sys_clk_pin rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 4.719ns (logic 0.518ns (10.976%) route 4.201ns (89.024%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 3.839ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 5.326ns Source Clock Delay (SCD): 1.487ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.490 1.490 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.177 -1.687 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 -0.088 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 0.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.484 1.487 SYNC/clk_out1 SLICE_X20Y26 FDRE r SYNC/comptY_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y26 FDRE (Prop_fdre_C_Q) 0.418 1.905 r SYNC/comptY_reg[5]/Q net (fo=13, routed) 1.194 3.099 SYNC/comptY_reg__0[5] SLICE_X23Y31 LUT6 (Prop_lut6_I3_O) 0.100 3.199 r SYNC/cCaseY[4]_i_1/O net (fo=55, routed) 3.007 6.207 SNAKE/Yi[4] SLICE_X21Y23 FDRE r SNAKE/cCaseY_reg[4]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O net (fo=1, routed) 2.076 3.567 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.658 5.326 SNAKE/H125MHz SLICE_X21Y23 FDRE r SNAKE/cCaseY_reg[4]/C clock pessimism 0.000 5.326 clock uncertainty 0.406 5.732 SLICE_X21Y23 FDRE (Hold_fdre_C_D) 0.199 5.931 SNAKE/cCaseY_reg[4] ------------------------------------------------------------------- required time -5.931 arrival time 6.207 ------------------------------------------------------------------- slack 0.275 Slack (MET) : 0.326ns (arrival time - required time) Source: SYNC/comptY_reg[3]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: SNAKE/cCaseY_reg[0]/D (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: sys_clk_pin Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (sys_clk_pin rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 4.794ns (logic 0.467ns (9.742%) route 4.327ns (90.258%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 3.839ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 5.326ns Source Clock Delay (SCD): 1.487ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.490 1.490 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.177 -1.687 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 -0.088 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 0.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.484 1.487 SYNC/clk_out1 SLICE_X21Y26 FDRE r SYNC/comptY_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X21Y26 FDRE (Prop_fdre_C_Q) 0.367 1.854 r SYNC/comptY_reg[3]/Q net (fo=8, routed) 1.209 3.064 SYNC/comptY_reg__0[3] SLICE_X20Y27 LUT6 (Prop_lut6_I4_O) 0.100 3.164 r SYNC/cCaseY[0]_i_1/O net (fo=55, routed) 3.117 6.281 SNAKE/Yi[0] SLICE_X20Y23 FDRE r SNAKE/cCaseY_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O net (fo=1, routed) 2.076 3.567 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.658 5.326 SNAKE/H125MHz SLICE_X20Y23 FDRE r SNAKE/cCaseY_reg[0]/C clock pessimism 0.000 5.326 clock uncertainty 0.406 5.732 SLICE_X20Y23 FDRE (Hold_fdre_C_D) 0.223 5.955 SNAKE/cCaseY_reg[0] ------------------------------------------------------------------- required time -5.955 arrival time 6.281 ------------------------------------------------------------------- slack 0.326 Slack (MET) : 0.337ns (arrival time - required time) Source: SYNC/comptX_reg[8]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: SNAKE/cCaseX_reg[4]/D (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: sys_clk_pin Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (sys_clk_pin rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 4.777ns (logic 0.467ns (9.775%) route 4.310ns (90.225%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 3.843ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 5.333ns Source Clock Delay (SCD): 1.490ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.490 1.490 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.177 -1.687 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 -0.088 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 0.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.487 1.490 SYNC/clk_out1 SLICE_X26Y21 FDRE r SYNC/comptX_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X26Y21 FDRE (Prop_fdre_C_Q) 0.367 1.857 r SYNC/comptX_reg[8]/Q net (fo=22, routed) 1.138 2.995 SYNC/comptX_reg__0[8] SLICE_X30Y25 LUT5 (Prop_lut5_I3_O) 0.100 3.095 r SYNC/cCaseX[4]_i_1/O net (fo=55, routed) 3.172 6.268 SNAKE/Xi[4] SLICE_X18Y19 FDRE r SNAKE/cCaseX_reg[4]/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O net (fo=1, routed) 2.076 3.567 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.665 5.333 SNAKE/H125MHz SLICE_X18Y19 FDRE r SNAKE/cCaseX_reg[4]/C clock pessimism 0.000 5.333 clock uncertainty 0.406 5.739 SLICE_X18Y19 FDRE (Hold_fdre_C_D) 0.192 5.931 SNAKE/cCaseX_reg[4] ------------------------------------------------------------------- required time -5.931 arrival time 6.268 ------------------------------------------------------------------- slack 0.337 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: clk_out1_clk_wiz_1 To Clock: clk_out1_clk_wiz_1 Setup : 0 Failing Endpoints, Worst Slack 34.529ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 1.220ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 34.529ns (required time - arrival time) Source: UPD_CLK_DIV/temp_reg[2]/C (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: UPD_CLK_DIV/temp_reg[0]/CLR (recovery check against rising-edge clock clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 4.896ns (logic 1.831ns (37.397%) route 3.065ns (62.603%)) Logic Levels: 5 (CARRY4=3 LUT2=1 LUT3=1) Clock Path Skew: -0.010ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.561ns = ( 41.561 - 40.000 ) Source Clock Delay (SCD): 1.737ns Clock Pessimism Removal (CPR): 0.166ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.734 1.737 UPD_CLK_DIV/clk_out1 SLICE_X40Y67 FDCE r UPD_CLK_DIV/temp_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y67 FDCE (Prop_fdce_C_Q) 0.456 2.193 f UPD_CLK_DIV/temp_reg[2]/Q net (fo=4, routed) 1.200 3.393 UPD_CLK_DIV/temp_reg[2] SLICE_X42Y69 LUT3 (Prop_lut3_I0_O) 0.124 3.517 r UPD_CLK_DIV/temp[0]_i_14/O net (fo=1, routed) 0.000 3.517 UPD_CLK_DIV/temp[0]_i_14_n_0 SLICE_X42Y69 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 4.030 r UPD_CLK_DIV/temp_reg[0]_i_6/CO[3] net (fo=1, routed) 0.000 4.030 UPD_CLK_DIV/temp_reg[0]_i_6_n_0 SLICE_X42Y70 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 4.147 r UPD_CLK_DIV/temp_reg[0]_i_5/CO[3] net (fo=1, routed) 0.000 4.147 UPD_CLK_DIV/temp_reg[0]_i_5_n_0 SLICE_X42Y71 CARRY4 (Prop_carry4_CI_CO[0]) 0.254 4.401 f UPD_CLK_DIV/temp_reg[0]_i_4/CO[0] net (fo=1, routed) 0.685 5.086 UPD_CLK_DIV/temp_reg[0]_i_4_n_3 SLICE_X43Y71 LUT2 (Prop_lut2_I0_O) 0.367 5.453 f UPD_CLK_DIV/temp[0]_i_2/O net (fo=25, routed) 1.180 6.633 UPD_CLK_DIV/temp[0]_i_2_n_0 SLICE_X40Y67 FDCE f UPD_CLK_DIV/temp_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.558 41.561 UPD_CLK_DIV/clk_out1 SLICE_X40Y67 FDCE r UPD_CLK_DIV/temp_reg[0]/C clock pessimism 0.166 41.727 clock uncertainty -0.160 41.567 SLICE_X40Y67 FDCE (Recov_fdce_C_CLR) -0.405 41.162 UPD_CLK_DIV/temp_reg[0] ------------------------------------------------------------------- required time 41.162 arrival time -6.633 ------------------------------------------------------------------- slack 34.529 Slack (MET) : 34.529ns (required time - arrival time) Source: UPD_CLK_DIV/temp_reg[2]/C (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: UPD_CLK_DIV/temp_reg[1]/CLR (recovery check against rising-edge clock clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 4.896ns (logic 1.831ns (37.397%) route 3.065ns (62.603%)) Logic Levels: 5 (CARRY4=3 LUT2=1 LUT3=1) Clock Path Skew: -0.010ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.561ns = ( 41.561 - 40.000 ) Source Clock Delay (SCD): 1.737ns Clock Pessimism Removal (CPR): 0.166ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.734 1.737 UPD_CLK_DIV/clk_out1 SLICE_X40Y67 FDCE r UPD_CLK_DIV/temp_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y67 FDCE (Prop_fdce_C_Q) 0.456 2.193 f UPD_CLK_DIV/temp_reg[2]/Q net (fo=4, routed) 1.200 3.393 UPD_CLK_DIV/temp_reg[2] SLICE_X42Y69 LUT3 (Prop_lut3_I0_O) 0.124 3.517 r UPD_CLK_DIV/temp[0]_i_14/O net (fo=1, routed) 0.000 3.517 UPD_CLK_DIV/temp[0]_i_14_n_0 SLICE_X42Y69 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 4.030 r UPD_CLK_DIV/temp_reg[0]_i_6/CO[3] net (fo=1, routed) 0.000 4.030 UPD_CLK_DIV/temp_reg[0]_i_6_n_0 SLICE_X42Y70 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 4.147 r UPD_CLK_DIV/temp_reg[0]_i_5/CO[3] net (fo=1, routed) 0.000 4.147 UPD_CLK_DIV/temp_reg[0]_i_5_n_0 SLICE_X42Y71 CARRY4 (Prop_carry4_CI_CO[0]) 0.254 4.401 f UPD_CLK_DIV/temp_reg[0]_i_4/CO[0] net (fo=1, routed) 0.685 5.086 UPD_CLK_DIV/temp_reg[0]_i_4_n_3 SLICE_X43Y71 LUT2 (Prop_lut2_I0_O) 0.367 5.453 f UPD_CLK_DIV/temp[0]_i_2/O net (fo=25, routed) 1.180 6.633 UPD_CLK_DIV/temp[0]_i_2_n_0 SLICE_X40Y67 FDCE f UPD_CLK_DIV/temp_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.558 41.561 UPD_CLK_DIV/clk_out1 SLICE_X40Y67 FDCE r UPD_CLK_DIV/temp_reg[1]/C clock pessimism 0.166 41.727 clock uncertainty -0.160 41.567 SLICE_X40Y67 FDCE (Recov_fdce_C_CLR) -0.405 41.162 UPD_CLK_DIV/temp_reg[1] ------------------------------------------------------------------- required time 41.162 arrival time -6.633 ------------------------------------------------------------------- slack 34.529 Slack (MET) : 34.529ns (required time - arrival time) Source: UPD_CLK_DIV/temp_reg[2]/C (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: UPD_CLK_DIV/temp_reg[2]/CLR (recovery check against rising-edge clock clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 4.896ns (logic 1.831ns (37.397%) route 3.065ns (62.603%)) Logic Levels: 5 (CARRY4=3 LUT2=1 LUT3=1) Clock Path Skew: -0.010ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.561ns = ( 41.561 - 40.000 ) Source Clock Delay (SCD): 1.737ns Clock Pessimism Removal (CPR): 0.166ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.734 1.737 UPD_CLK_DIV/clk_out1 SLICE_X40Y67 FDCE r UPD_CLK_DIV/temp_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y67 FDCE (Prop_fdce_C_Q) 0.456 2.193 f UPD_CLK_DIV/temp_reg[2]/Q net (fo=4, routed) 1.200 3.393 UPD_CLK_DIV/temp_reg[2] SLICE_X42Y69 LUT3 (Prop_lut3_I0_O) 0.124 3.517 r UPD_CLK_DIV/temp[0]_i_14/O net (fo=1, routed) 0.000 3.517 UPD_CLK_DIV/temp[0]_i_14_n_0 SLICE_X42Y69 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 4.030 r UPD_CLK_DIV/temp_reg[0]_i_6/CO[3] net (fo=1, routed) 0.000 4.030 UPD_CLK_DIV/temp_reg[0]_i_6_n_0 SLICE_X42Y70 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 4.147 r UPD_CLK_DIV/temp_reg[0]_i_5/CO[3] net (fo=1, routed) 0.000 4.147 UPD_CLK_DIV/temp_reg[0]_i_5_n_0 SLICE_X42Y71 CARRY4 (Prop_carry4_CI_CO[0]) 0.254 4.401 f UPD_CLK_DIV/temp_reg[0]_i_4/CO[0] net (fo=1, routed) 0.685 5.086 UPD_CLK_DIV/temp_reg[0]_i_4_n_3 SLICE_X43Y71 LUT2 (Prop_lut2_I0_O) 0.367 5.453 f UPD_CLK_DIV/temp[0]_i_2/O net (fo=25, routed) 1.180 6.633 UPD_CLK_DIV/temp[0]_i_2_n_0 SLICE_X40Y67 FDCE f UPD_CLK_DIV/temp_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.558 41.561 UPD_CLK_DIV/clk_out1 SLICE_X40Y67 FDCE r UPD_CLK_DIV/temp_reg[2]/C clock pessimism 0.166 41.727 clock uncertainty -0.160 41.567 SLICE_X40Y67 FDCE (Recov_fdce_C_CLR) -0.405 41.162 UPD_CLK_DIV/temp_reg[2] ------------------------------------------------------------------- required time 41.162 arrival time -6.633 ------------------------------------------------------------------- slack 34.529 Slack (MET) : 34.529ns (required time - arrival time) Source: UPD_CLK_DIV/temp_reg[2]/C (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: UPD_CLK_DIV/temp_reg[3]/CLR (recovery check against rising-edge clock clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 4.896ns (logic 1.831ns (37.397%) route 3.065ns (62.603%)) Logic Levels: 5 (CARRY4=3 LUT2=1 LUT3=1) Clock Path Skew: -0.010ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.561ns = ( 41.561 - 40.000 ) Source Clock Delay (SCD): 1.737ns Clock Pessimism Removal (CPR): 0.166ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.734 1.737 UPD_CLK_DIV/clk_out1 SLICE_X40Y67 FDCE r UPD_CLK_DIV/temp_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y67 FDCE (Prop_fdce_C_Q) 0.456 2.193 f UPD_CLK_DIV/temp_reg[2]/Q net (fo=4, routed) 1.200 3.393 UPD_CLK_DIV/temp_reg[2] SLICE_X42Y69 LUT3 (Prop_lut3_I0_O) 0.124 3.517 r UPD_CLK_DIV/temp[0]_i_14/O net (fo=1, routed) 0.000 3.517 UPD_CLK_DIV/temp[0]_i_14_n_0 SLICE_X42Y69 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 4.030 r UPD_CLK_DIV/temp_reg[0]_i_6/CO[3] net (fo=1, routed) 0.000 4.030 UPD_CLK_DIV/temp_reg[0]_i_6_n_0 SLICE_X42Y70 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 4.147 r UPD_CLK_DIV/temp_reg[0]_i_5/CO[3] net (fo=1, routed) 0.000 4.147 UPD_CLK_DIV/temp_reg[0]_i_5_n_0 SLICE_X42Y71 CARRY4 (Prop_carry4_CI_CO[0]) 0.254 4.401 f UPD_CLK_DIV/temp_reg[0]_i_4/CO[0] net (fo=1, routed) 0.685 5.086 UPD_CLK_DIV/temp_reg[0]_i_4_n_3 SLICE_X43Y71 LUT2 (Prop_lut2_I0_O) 0.367 5.453 f UPD_CLK_DIV/temp[0]_i_2/O net (fo=25, routed) 1.180 6.633 UPD_CLK_DIV/temp[0]_i_2_n_0 SLICE_X40Y67 FDCE f UPD_CLK_DIV/temp_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.558 41.561 UPD_CLK_DIV/clk_out1 SLICE_X40Y67 FDCE r UPD_CLK_DIV/temp_reg[3]/C clock pessimism 0.166 41.727 clock uncertainty -0.160 41.567 SLICE_X40Y67 FDCE (Recov_fdce_C_CLR) -0.405 41.162 UPD_CLK_DIV/temp_reg[3] ------------------------------------------------------------------- required time 41.162 arrival time -6.633 ------------------------------------------------------------------- slack 34.529 Slack (MET) : 34.595ns (required time - arrival time) Source: UPD_CLK_DIV/temp_reg[2]/C (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: UPD_CLK_DIV/temp_reg[4]/CLR (recovery check against rising-edge clock clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 4.804ns (logic 1.831ns (38.114%) route 2.973ns (61.886%)) Logic Levels: 5 (CARRY4=3 LUT2=1 LUT3=1) Clock Path Skew: -0.036ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.559ns = ( 41.559 - 40.000 ) Source Clock Delay (SCD): 1.737ns Clock Pessimism Removal (CPR): 0.142ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.734 1.737 UPD_CLK_DIV/clk_out1 SLICE_X40Y67 FDCE r UPD_CLK_DIV/temp_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y67 FDCE (Prop_fdce_C_Q) 0.456 2.193 f UPD_CLK_DIV/temp_reg[2]/Q net (fo=4, routed) 1.200 3.393 UPD_CLK_DIV/temp_reg[2] SLICE_X42Y69 LUT3 (Prop_lut3_I0_O) 0.124 3.517 r UPD_CLK_DIV/temp[0]_i_14/O net (fo=1, routed) 0.000 3.517 UPD_CLK_DIV/temp[0]_i_14_n_0 SLICE_X42Y69 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 4.030 r UPD_CLK_DIV/temp_reg[0]_i_6/CO[3] net (fo=1, routed) 0.000 4.030 UPD_CLK_DIV/temp_reg[0]_i_6_n_0 SLICE_X42Y70 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 4.147 r UPD_CLK_DIV/temp_reg[0]_i_5/CO[3] net (fo=1, routed) 0.000 4.147 UPD_CLK_DIV/temp_reg[0]_i_5_n_0 SLICE_X42Y71 CARRY4 (Prop_carry4_CI_CO[0]) 0.254 4.401 f UPD_CLK_DIV/temp_reg[0]_i_4/CO[0] net (fo=1, routed) 0.685 5.086 UPD_CLK_DIV/temp_reg[0]_i_4_n_3 SLICE_X43Y71 LUT2 (Prop_lut2_I0_O) 0.367 5.453 f UPD_CLK_DIV/temp[0]_i_2/O net (fo=25, routed) 1.088 6.541 UPD_CLK_DIV/temp[0]_i_2_n_0 SLICE_X40Y68 FDCE f UPD_CLK_DIV/temp_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.556 41.559 UPD_CLK_DIV/clk_out1 SLICE_X40Y68 FDCE r UPD_CLK_DIV/temp_reg[4]/C clock pessimism 0.142 41.701 clock uncertainty -0.160 41.541 SLICE_X40Y68 FDCE (Recov_fdce_C_CLR) -0.405 41.136 UPD_CLK_DIV/temp_reg[4] ------------------------------------------------------------------- required time 41.136 arrival time -6.541 ------------------------------------------------------------------- slack 34.595 Slack (MET) : 34.595ns (required time - arrival time) Source: UPD_CLK_DIV/temp_reg[2]/C (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: UPD_CLK_DIV/temp_reg[5]/CLR (recovery check against rising-edge clock clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 4.804ns (logic 1.831ns (38.114%) route 2.973ns (61.886%)) Logic Levels: 5 (CARRY4=3 LUT2=1 LUT3=1) Clock Path Skew: -0.036ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.559ns = ( 41.559 - 40.000 ) Source Clock Delay (SCD): 1.737ns Clock Pessimism Removal (CPR): 0.142ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.734 1.737 UPD_CLK_DIV/clk_out1 SLICE_X40Y67 FDCE r UPD_CLK_DIV/temp_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y67 FDCE (Prop_fdce_C_Q) 0.456 2.193 f UPD_CLK_DIV/temp_reg[2]/Q net (fo=4, routed) 1.200 3.393 UPD_CLK_DIV/temp_reg[2] SLICE_X42Y69 LUT3 (Prop_lut3_I0_O) 0.124 3.517 r UPD_CLK_DIV/temp[0]_i_14/O net (fo=1, routed) 0.000 3.517 UPD_CLK_DIV/temp[0]_i_14_n_0 SLICE_X42Y69 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 4.030 r UPD_CLK_DIV/temp_reg[0]_i_6/CO[3] net (fo=1, routed) 0.000 4.030 UPD_CLK_DIV/temp_reg[0]_i_6_n_0 SLICE_X42Y70 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 4.147 r UPD_CLK_DIV/temp_reg[0]_i_5/CO[3] net (fo=1, routed) 0.000 4.147 UPD_CLK_DIV/temp_reg[0]_i_5_n_0 SLICE_X42Y71 CARRY4 (Prop_carry4_CI_CO[0]) 0.254 4.401 f UPD_CLK_DIV/temp_reg[0]_i_4/CO[0] net (fo=1, routed) 0.685 5.086 UPD_CLK_DIV/temp_reg[0]_i_4_n_3 SLICE_X43Y71 LUT2 (Prop_lut2_I0_O) 0.367 5.453 f UPD_CLK_DIV/temp[0]_i_2/O net (fo=25, routed) 1.088 6.541 UPD_CLK_DIV/temp[0]_i_2_n_0 SLICE_X40Y68 FDCE f UPD_CLK_DIV/temp_reg[5]/CLR ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.556 41.559 UPD_CLK_DIV/clk_out1 SLICE_X40Y68 FDCE r UPD_CLK_DIV/temp_reg[5]/C clock pessimism 0.142 41.701 clock uncertainty -0.160 41.541 SLICE_X40Y68 FDCE (Recov_fdce_C_CLR) -0.405 41.136 UPD_CLK_DIV/temp_reg[5] ------------------------------------------------------------------- required time 41.136 arrival time -6.541 ------------------------------------------------------------------- slack 34.595 Slack (MET) : 34.595ns (required time - arrival time) Source: UPD_CLK_DIV/temp_reg[2]/C (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: UPD_CLK_DIV/temp_reg[6]/CLR (recovery check against rising-edge clock clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 4.804ns (logic 1.831ns (38.114%) route 2.973ns (61.886%)) Logic Levels: 5 (CARRY4=3 LUT2=1 LUT3=1) Clock Path Skew: -0.036ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.559ns = ( 41.559 - 40.000 ) Source Clock Delay (SCD): 1.737ns Clock Pessimism Removal (CPR): 0.142ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.734 1.737 UPD_CLK_DIV/clk_out1 SLICE_X40Y67 FDCE r UPD_CLK_DIV/temp_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y67 FDCE (Prop_fdce_C_Q) 0.456 2.193 f UPD_CLK_DIV/temp_reg[2]/Q net (fo=4, routed) 1.200 3.393 UPD_CLK_DIV/temp_reg[2] SLICE_X42Y69 LUT3 (Prop_lut3_I0_O) 0.124 3.517 r UPD_CLK_DIV/temp[0]_i_14/O net (fo=1, routed) 0.000 3.517 UPD_CLK_DIV/temp[0]_i_14_n_0 SLICE_X42Y69 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 4.030 r UPD_CLK_DIV/temp_reg[0]_i_6/CO[3] net (fo=1, routed) 0.000 4.030 UPD_CLK_DIV/temp_reg[0]_i_6_n_0 SLICE_X42Y70 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 4.147 r UPD_CLK_DIV/temp_reg[0]_i_5/CO[3] net (fo=1, routed) 0.000 4.147 UPD_CLK_DIV/temp_reg[0]_i_5_n_0 SLICE_X42Y71 CARRY4 (Prop_carry4_CI_CO[0]) 0.254 4.401 f UPD_CLK_DIV/temp_reg[0]_i_4/CO[0] net (fo=1, routed) 0.685 5.086 UPD_CLK_DIV/temp_reg[0]_i_4_n_3 SLICE_X43Y71 LUT2 (Prop_lut2_I0_O) 0.367 5.453 f UPD_CLK_DIV/temp[0]_i_2/O net (fo=25, routed) 1.088 6.541 UPD_CLK_DIV/temp[0]_i_2_n_0 SLICE_X40Y68 FDCE f UPD_CLK_DIV/temp_reg[6]/CLR ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.556 41.559 UPD_CLK_DIV/clk_out1 SLICE_X40Y68 FDCE r UPD_CLK_DIV/temp_reg[6]/C clock pessimism 0.142 41.701 clock uncertainty -0.160 41.541 SLICE_X40Y68 FDCE (Recov_fdce_C_CLR) -0.405 41.136 UPD_CLK_DIV/temp_reg[6] ------------------------------------------------------------------- required time 41.136 arrival time -6.541 ------------------------------------------------------------------- slack 34.595 Slack (MET) : 34.595ns (required time - arrival time) Source: UPD_CLK_DIV/temp_reg[2]/C (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: UPD_CLK_DIV/temp_reg[7]/CLR (recovery check against rising-edge clock clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 4.804ns (logic 1.831ns (38.114%) route 2.973ns (61.886%)) Logic Levels: 5 (CARRY4=3 LUT2=1 LUT3=1) Clock Path Skew: -0.036ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.559ns = ( 41.559 - 40.000 ) Source Clock Delay (SCD): 1.737ns Clock Pessimism Removal (CPR): 0.142ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.734 1.737 UPD_CLK_DIV/clk_out1 SLICE_X40Y67 FDCE r UPD_CLK_DIV/temp_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y67 FDCE (Prop_fdce_C_Q) 0.456 2.193 f UPD_CLK_DIV/temp_reg[2]/Q net (fo=4, routed) 1.200 3.393 UPD_CLK_DIV/temp_reg[2] SLICE_X42Y69 LUT3 (Prop_lut3_I0_O) 0.124 3.517 r UPD_CLK_DIV/temp[0]_i_14/O net (fo=1, routed) 0.000 3.517 UPD_CLK_DIV/temp[0]_i_14_n_0 SLICE_X42Y69 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 4.030 r UPD_CLK_DIV/temp_reg[0]_i_6/CO[3] net (fo=1, routed) 0.000 4.030 UPD_CLK_DIV/temp_reg[0]_i_6_n_0 SLICE_X42Y70 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 4.147 r UPD_CLK_DIV/temp_reg[0]_i_5/CO[3] net (fo=1, routed) 0.000 4.147 UPD_CLK_DIV/temp_reg[0]_i_5_n_0 SLICE_X42Y71 CARRY4 (Prop_carry4_CI_CO[0]) 0.254 4.401 f UPD_CLK_DIV/temp_reg[0]_i_4/CO[0] net (fo=1, routed) 0.685 5.086 UPD_CLK_DIV/temp_reg[0]_i_4_n_3 SLICE_X43Y71 LUT2 (Prop_lut2_I0_O) 0.367 5.453 f UPD_CLK_DIV/temp[0]_i_2/O net (fo=25, routed) 1.088 6.541 UPD_CLK_DIV/temp[0]_i_2_n_0 SLICE_X40Y68 FDCE f UPD_CLK_DIV/temp_reg[7]/CLR ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.556 41.559 UPD_CLK_DIV/clk_out1 SLICE_X40Y68 FDCE r UPD_CLK_DIV/temp_reg[7]/C clock pessimism 0.142 41.701 clock uncertainty -0.160 41.541 SLICE_X40Y68 FDCE (Recov_fdce_C_CLR) -0.405 41.136 UPD_CLK_DIV/temp_reg[7] ------------------------------------------------------------------- required time 41.136 arrival time -6.541 ------------------------------------------------------------------- slack 34.595 Slack (MET) : 34.643ns (required time - arrival time) Source: UPD_CLK_DIV/temp_reg[2]/C (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: UPD_CLK_DIV/temp_reg[10]/CLR (recovery check against rising-edge clock clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 4.755ns (logic 1.831ns (38.506%) route 2.924ns (61.493%)) Logic Levels: 5 (CARRY4=3 LUT2=1 LUT3=1) Clock Path Skew: -0.037ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.558ns = ( 41.558 - 40.000 ) Source Clock Delay (SCD): 1.737ns Clock Pessimism Removal (CPR): 0.142ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.734 1.737 UPD_CLK_DIV/clk_out1 SLICE_X40Y67 FDCE r UPD_CLK_DIV/temp_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y67 FDCE (Prop_fdce_C_Q) 0.456 2.193 f UPD_CLK_DIV/temp_reg[2]/Q net (fo=4, routed) 1.200 3.393 UPD_CLK_DIV/temp_reg[2] SLICE_X42Y69 LUT3 (Prop_lut3_I0_O) 0.124 3.517 r UPD_CLK_DIV/temp[0]_i_14/O net (fo=1, routed) 0.000 3.517 UPD_CLK_DIV/temp[0]_i_14_n_0 SLICE_X42Y69 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 4.030 r UPD_CLK_DIV/temp_reg[0]_i_6/CO[3] net (fo=1, routed) 0.000 4.030 UPD_CLK_DIV/temp_reg[0]_i_6_n_0 SLICE_X42Y70 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 4.147 r UPD_CLK_DIV/temp_reg[0]_i_5/CO[3] net (fo=1, routed) 0.000 4.147 UPD_CLK_DIV/temp_reg[0]_i_5_n_0 SLICE_X42Y71 CARRY4 (Prop_carry4_CI_CO[0]) 0.254 4.401 f UPD_CLK_DIV/temp_reg[0]_i_4/CO[0] net (fo=1, routed) 0.685 5.086 UPD_CLK_DIV/temp_reg[0]_i_4_n_3 SLICE_X43Y71 LUT2 (Prop_lut2_I0_O) 0.367 5.453 f UPD_CLK_DIV/temp[0]_i_2/O net (fo=25, routed) 1.039 6.492 UPD_CLK_DIV/temp[0]_i_2_n_0 SLICE_X40Y69 FDCE f UPD_CLK_DIV/temp_reg[10]/CLR ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.555 41.558 UPD_CLK_DIV/clk_out1 SLICE_X40Y69 FDCE r UPD_CLK_DIV/temp_reg[10]/C clock pessimism 0.142 41.700 clock uncertainty -0.160 41.540 SLICE_X40Y69 FDCE (Recov_fdce_C_CLR) -0.405 41.135 UPD_CLK_DIV/temp_reg[10] ------------------------------------------------------------------- required time 41.135 arrival time -6.492 ------------------------------------------------------------------- slack 34.643 Slack (MET) : 34.643ns (required time - arrival time) Source: UPD_CLK_DIV/temp_reg[2]/C (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: UPD_CLK_DIV/temp_reg[11]/CLR (recovery check against rising-edge clock clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 40.000ns (clk_out1_clk_wiz_1 rise@40.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 4.755ns (logic 1.831ns (38.506%) route 2.924ns (61.493%)) Logic Levels: 5 (CARRY4=3 LUT2=1 LUT3=1) Clock Path Skew: -0.037ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.558ns = ( 41.558 - 40.000 ) Source Clock Delay (SCD): 1.737ns Clock Pessimism Removal (CPR): 0.142ns Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.680 1.680 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.538 -1.858 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.760 -0.098 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 0.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.734 1.737 UPD_CLK_DIV/clk_out1 SLICE_X40Y67 FDCE r UPD_CLK_DIV/temp_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y67 FDCE (Prop_fdce_C_Q) 0.456 2.193 f UPD_CLK_DIV/temp_reg[2]/Q net (fo=4, routed) 1.200 3.393 UPD_CLK_DIV/temp_reg[2] SLICE_X42Y69 LUT3 (Prop_lut3_I0_O) 0.124 3.517 r UPD_CLK_DIV/temp[0]_i_14/O net (fo=1, routed) 0.000 3.517 UPD_CLK_DIV/temp[0]_i_14_n_0 SLICE_X42Y69 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.513 4.030 r UPD_CLK_DIV/temp_reg[0]_i_6/CO[3] net (fo=1, routed) 0.000 4.030 UPD_CLK_DIV/temp_reg[0]_i_6_n_0 SLICE_X42Y70 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 4.147 r UPD_CLK_DIV/temp_reg[0]_i_5/CO[3] net (fo=1, routed) 0.000 4.147 UPD_CLK_DIV/temp_reg[0]_i_5_n_0 SLICE_X42Y71 CARRY4 (Prop_carry4_CI_CO[0]) 0.254 4.401 f UPD_CLK_DIV/temp_reg[0]_i_4/CO[0] net (fo=1, routed) 0.685 5.086 UPD_CLK_DIV/temp_reg[0]_i_4_n_3 SLICE_X43Y71 LUT2 (Prop_lut2_I0_O) 0.367 5.453 f UPD_CLK_DIV/temp[0]_i_2/O net (fo=25, routed) 1.039 6.492 UPD_CLK_DIV/temp[0]_i_2_n_0 SLICE_X40Y69 FDCE f UPD_CLK_DIV/temp_reg[11]/CLR ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.555 41.558 UPD_CLK_DIV/clk_out1 SLICE_X40Y69 FDCE r UPD_CLK_DIV/temp_reg[11]/C clock pessimism 0.142 41.700 clock uncertainty -0.160 41.540 SLICE_X40Y69 FDCE (Recov_fdce_C_CLR) -0.405 41.135 UPD_CLK_DIV/temp_reg[11] ------------------------------------------------------------------- required time 41.135 arrival time -6.492 ------------------------------------------------------------------- slack 34.643 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 1.220ns (arrival time - required time) Source: UPD_CLK_DIV/temp_reg[24]/C (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: UPD_CLK_DIV/temp_reg[16]/CLR (removal check against rising-edge clock clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 1.144ns (logic 0.407ns (35.576%) route 0.737ns (64.424%)) Logic Levels: 2 (CARRY4=1 LUT2=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.850ns Source Clock Delay (SCD): 0.580ns Clock Pessimism Removal (CPR): 0.254ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.548 0.548 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.053 -0.506 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -0.024 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.002 r U0/inst/clkout1_buf/O net (fo=60, routed) 0.578 0.580 UPD_CLK_DIV/clk_out1 SLICE_X40Y73 FDCE r UPD_CLK_DIV/temp_reg[24]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y73 FDCE (Prop_fdce_C_Q) 0.141 0.721 r UPD_CLK_DIV/temp_reg[24]/Q net (fo=4, routed) 0.245 0.966 UPD_CLK_DIV/temp_reg[24] SLICE_X42Y71 CARRY4 (Prop_carry4_S[0]_CO[0]) 0.142 1.108 f UPD_CLK_DIV/temp_reg[0]_i_4/CO[0] net (fo=1, routed) 0.219 1.328 UPD_CLK_DIV/temp_reg[0]_i_4_n_3 SLICE_X43Y71 LUT2 (Prop_lut2_I0_O) 0.124 1.452 f UPD_CLK_DIV/temp[0]_i_2/O net (fo=25, routed) 0.272 1.724 UPD_CLK_DIV/temp[0]_i_2_n_0 SLICE_X40Y71 FDCE f UPD_CLK_DIV/temp_reg[16]/CLR ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O net (fo=60, routed) 0.848 0.850 UPD_CLK_DIV/clk_out1 SLICE_X40Y71 FDCE r UPD_CLK_DIV/temp_reg[16]/C clock pessimism -0.254 0.596 SLICE_X40Y71 FDCE (Remov_fdce_C_CLR) -0.092 0.504 UPD_CLK_DIV/temp_reg[16] ------------------------------------------------------------------- required time -0.504 arrival time 1.724 ------------------------------------------------------------------- slack 1.220 Slack (MET) : 1.220ns (arrival time - required time) Source: UPD_CLK_DIV/temp_reg[24]/C (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: UPD_CLK_DIV/temp_reg[17]/CLR (removal check against rising-edge clock clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 1.144ns (logic 0.407ns (35.576%) route 0.737ns (64.424%)) Logic Levels: 2 (CARRY4=1 LUT2=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.850ns Source Clock Delay (SCD): 0.580ns Clock Pessimism Removal (CPR): 0.254ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.548 0.548 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.053 -0.506 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -0.024 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.002 r U0/inst/clkout1_buf/O net (fo=60, routed) 0.578 0.580 UPD_CLK_DIV/clk_out1 SLICE_X40Y73 FDCE r UPD_CLK_DIV/temp_reg[24]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y73 FDCE (Prop_fdce_C_Q) 0.141 0.721 r UPD_CLK_DIV/temp_reg[24]/Q net (fo=4, routed) 0.245 0.966 UPD_CLK_DIV/temp_reg[24] SLICE_X42Y71 CARRY4 (Prop_carry4_S[0]_CO[0]) 0.142 1.108 f UPD_CLK_DIV/temp_reg[0]_i_4/CO[0] net (fo=1, routed) 0.219 1.328 UPD_CLK_DIV/temp_reg[0]_i_4_n_3 SLICE_X43Y71 LUT2 (Prop_lut2_I0_O) 0.124 1.452 f UPD_CLK_DIV/temp[0]_i_2/O net (fo=25, routed) 0.272 1.724 UPD_CLK_DIV/temp[0]_i_2_n_0 SLICE_X40Y71 FDCE f UPD_CLK_DIV/temp_reg[17]/CLR ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O net (fo=60, routed) 0.848 0.850 UPD_CLK_DIV/clk_out1 SLICE_X40Y71 FDCE r UPD_CLK_DIV/temp_reg[17]/C clock pessimism -0.254 0.596 SLICE_X40Y71 FDCE (Remov_fdce_C_CLR) -0.092 0.504 UPD_CLK_DIV/temp_reg[17] ------------------------------------------------------------------- required time -0.504 arrival time 1.724 ------------------------------------------------------------------- slack 1.220 Slack (MET) : 1.220ns (arrival time - required time) Source: UPD_CLK_DIV/temp_reg[24]/C (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: UPD_CLK_DIV/temp_reg[18]/CLR (removal check against rising-edge clock clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 1.144ns (logic 0.407ns (35.576%) route 0.737ns (64.424%)) Logic Levels: 2 (CARRY4=1 LUT2=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.850ns Source Clock Delay (SCD): 0.580ns Clock Pessimism Removal (CPR): 0.254ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.548 0.548 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.053 -0.506 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -0.024 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.002 r U0/inst/clkout1_buf/O net (fo=60, routed) 0.578 0.580 UPD_CLK_DIV/clk_out1 SLICE_X40Y73 FDCE r UPD_CLK_DIV/temp_reg[24]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y73 FDCE (Prop_fdce_C_Q) 0.141 0.721 r UPD_CLK_DIV/temp_reg[24]/Q net (fo=4, routed) 0.245 0.966 UPD_CLK_DIV/temp_reg[24] SLICE_X42Y71 CARRY4 (Prop_carry4_S[0]_CO[0]) 0.142 1.108 f UPD_CLK_DIV/temp_reg[0]_i_4/CO[0] net (fo=1, routed) 0.219 1.328 UPD_CLK_DIV/temp_reg[0]_i_4_n_3 SLICE_X43Y71 LUT2 (Prop_lut2_I0_O) 0.124 1.452 f UPD_CLK_DIV/temp[0]_i_2/O net (fo=25, routed) 0.272 1.724 UPD_CLK_DIV/temp[0]_i_2_n_0 SLICE_X40Y71 FDCE f UPD_CLK_DIV/temp_reg[18]/CLR ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O net (fo=60, routed) 0.848 0.850 UPD_CLK_DIV/clk_out1 SLICE_X40Y71 FDCE r UPD_CLK_DIV/temp_reg[18]/C clock pessimism -0.254 0.596 SLICE_X40Y71 FDCE (Remov_fdce_C_CLR) -0.092 0.504 UPD_CLK_DIV/temp_reg[18] ------------------------------------------------------------------- required time -0.504 arrival time 1.724 ------------------------------------------------------------------- slack 1.220 Slack (MET) : 1.220ns (arrival time - required time) Source: UPD_CLK_DIV/temp_reg[24]/C (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: UPD_CLK_DIV/temp_reg[19]/CLR (removal check against rising-edge clock clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 1.144ns (logic 0.407ns (35.576%) route 0.737ns (64.424%)) Logic Levels: 2 (CARRY4=1 LUT2=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.850ns Source Clock Delay (SCD): 0.580ns Clock Pessimism Removal (CPR): 0.254ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.548 0.548 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.053 -0.506 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -0.024 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.002 r U0/inst/clkout1_buf/O net (fo=60, routed) 0.578 0.580 UPD_CLK_DIV/clk_out1 SLICE_X40Y73 FDCE r UPD_CLK_DIV/temp_reg[24]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y73 FDCE (Prop_fdce_C_Q) 0.141 0.721 r UPD_CLK_DIV/temp_reg[24]/Q net (fo=4, routed) 0.245 0.966 UPD_CLK_DIV/temp_reg[24] SLICE_X42Y71 CARRY4 (Prop_carry4_S[0]_CO[0]) 0.142 1.108 f UPD_CLK_DIV/temp_reg[0]_i_4/CO[0] net (fo=1, routed) 0.219 1.328 UPD_CLK_DIV/temp_reg[0]_i_4_n_3 SLICE_X43Y71 LUT2 (Prop_lut2_I0_O) 0.124 1.452 f UPD_CLK_DIV/temp[0]_i_2/O net (fo=25, routed) 0.272 1.724 UPD_CLK_DIV/temp[0]_i_2_n_0 SLICE_X40Y71 FDCE f UPD_CLK_DIV/temp_reg[19]/CLR ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O net (fo=60, routed) 0.848 0.850 UPD_CLK_DIV/clk_out1 SLICE_X40Y71 FDCE r UPD_CLK_DIV/temp_reg[19]/C clock pessimism -0.254 0.596 SLICE_X40Y71 FDCE (Remov_fdce_C_CLR) -0.092 0.504 UPD_CLK_DIV/temp_reg[19] ------------------------------------------------------------------- required time -0.504 arrival time 1.724 ------------------------------------------------------------------- slack 1.220 Slack (MET) : 1.228ns (arrival time - required time) Source: UPD_CLK_DIV/temp_reg[24]/C (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: UPD_CLK_DIV/temp_reg[20]/CLR (removal check against rising-edge clock clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 1.151ns (logic 0.407ns (35.369%) route 0.744ns (64.631%)) Logic Levels: 2 (CARRY4=1 LUT2=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.849ns Source Clock Delay (SCD): 0.580ns Clock Pessimism Removal (CPR): 0.254ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.548 0.548 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.053 -0.506 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -0.024 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.002 r U0/inst/clkout1_buf/O net (fo=60, routed) 0.578 0.580 UPD_CLK_DIV/clk_out1 SLICE_X40Y73 FDCE r UPD_CLK_DIV/temp_reg[24]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y73 FDCE (Prop_fdce_C_Q) 0.141 0.721 r UPD_CLK_DIV/temp_reg[24]/Q net (fo=4, routed) 0.245 0.966 UPD_CLK_DIV/temp_reg[24] SLICE_X42Y71 CARRY4 (Prop_carry4_S[0]_CO[0]) 0.142 1.108 f UPD_CLK_DIV/temp_reg[0]_i_4/CO[0] net (fo=1, routed) 0.219 1.328 UPD_CLK_DIV/temp_reg[0]_i_4_n_3 SLICE_X43Y71 LUT2 (Prop_lut2_I0_O) 0.124 1.452 f UPD_CLK_DIV/temp[0]_i_2/O net (fo=25, routed) 0.279 1.730 UPD_CLK_DIV/temp[0]_i_2_n_0 SLICE_X40Y72 FDCE f UPD_CLK_DIV/temp_reg[20]/CLR ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O net (fo=60, routed) 0.847 0.849 UPD_CLK_DIV/clk_out1 SLICE_X40Y72 FDCE r UPD_CLK_DIV/temp_reg[20]/C clock pessimism -0.254 0.595 SLICE_X40Y72 FDCE (Remov_fdce_C_CLR) -0.092 0.503 UPD_CLK_DIV/temp_reg[20] ------------------------------------------------------------------- required time -0.503 arrival time 1.730 ------------------------------------------------------------------- slack 1.228 Slack (MET) : 1.228ns (arrival time - required time) Source: UPD_CLK_DIV/temp_reg[24]/C (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: UPD_CLK_DIV/temp_reg[21]/CLR (removal check against rising-edge clock clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 1.151ns (logic 0.407ns (35.369%) route 0.744ns (64.631%)) Logic Levels: 2 (CARRY4=1 LUT2=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.849ns Source Clock Delay (SCD): 0.580ns Clock Pessimism Removal (CPR): 0.254ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.548 0.548 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.053 -0.506 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -0.024 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.002 r U0/inst/clkout1_buf/O net (fo=60, routed) 0.578 0.580 UPD_CLK_DIV/clk_out1 SLICE_X40Y73 FDCE r UPD_CLK_DIV/temp_reg[24]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y73 FDCE (Prop_fdce_C_Q) 0.141 0.721 r UPD_CLK_DIV/temp_reg[24]/Q net (fo=4, routed) 0.245 0.966 UPD_CLK_DIV/temp_reg[24] SLICE_X42Y71 CARRY4 (Prop_carry4_S[0]_CO[0]) 0.142 1.108 f UPD_CLK_DIV/temp_reg[0]_i_4/CO[0] net (fo=1, routed) 0.219 1.328 UPD_CLK_DIV/temp_reg[0]_i_4_n_3 SLICE_X43Y71 LUT2 (Prop_lut2_I0_O) 0.124 1.452 f UPD_CLK_DIV/temp[0]_i_2/O net (fo=25, routed) 0.279 1.730 UPD_CLK_DIV/temp[0]_i_2_n_0 SLICE_X40Y72 FDCE f UPD_CLK_DIV/temp_reg[21]/CLR ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O net (fo=60, routed) 0.847 0.849 UPD_CLK_DIV/clk_out1 SLICE_X40Y72 FDCE r UPD_CLK_DIV/temp_reg[21]/C clock pessimism -0.254 0.595 SLICE_X40Y72 FDCE (Remov_fdce_C_CLR) -0.092 0.503 UPD_CLK_DIV/temp_reg[21] ------------------------------------------------------------------- required time -0.503 arrival time 1.730 ------------------------------------------------------------------- slack 1.228 Slack (MET) : 1.228ns (arrival time - required time) Source: UPD_CLK_DIV/temp_reg[24]/C (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: UPD_CLK_DIV/temp_reg[22]/CLR (removal check against rising-edge clock clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 1.151ns (logic 0.407ns (35.369%) route 0.744ns (64.631%)) Logic Levels: 2 (CARRY4=1 LUT2=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.849ns Source Clock Delay (SCD): 0.580ns Clock Pessimism Removal (CPR): 0.254ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.548 0.548 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.053 -0.506 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -0.024 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.002 r U0/inst/clkout1_buf/O net (fo=60, routed) 0.578 0.580 UPD_CLK_DIV/clk_out1 SLICE_X40Y73 FDCE r UPD_CLK_DIV/temp_reg[24]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y73 FDCE (Prop_fdce_C_Q) 0.141 0.721 r UPD_CLK_DIV/temp_reg[24]/Q net (fo=4, routed) 0.245 0.966 UPD_CLK_DIV/temp_reg[24] SLICE_X42Y71 CARRY4 (Prop_carry4_S[0]_CO[0]) 0.142 1.108 f UPD_CLK_DIV/temp_reg[0]_i_4/CO[0] net (fo=1, routed) 0.219 1.328 UPD_CLK_DIV/temp_reg[0]_i_4_n_3 SLICE_X43Y71 LUT2 (Prop_lut2_I0_O) 0.124 1.452 f UPD_CLK_DIV/temp[0]_i_2/O net (fo=25, routed) 0.279 1.730 UPD_CLK_DIV/temp[0]_i_2_n_0 SLICE_X40Y72 FDCE f UPD_CLK_DIV/temp_reg[22]/CLR ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O net (fo=60, routed) 0.847 0.849 UPD_CLK_DIV/clk_out1 SLICE_X40Y72 FDCE r UPD_CLK_DIV/temp_reg[22]/C clock pessimism -0.254 0.595 SLICE_X40Y72 FDCE (Remov_fdce_C_CLR) -0.092 0.503 UPD_CLK_DIV/temp_reg[22] ------------------------------------------------------------------- required time -0.503 arrival time 1.730 ------------------------------------------------------------------- slack 1.228 Slack (MET) : 1.228ns (arrival time - required time) Source: UPD_CLK_DIV/temp_reg[24]/C (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: UPD_CLK_DIV/temp_reg[23]/CLR (removal check against rising-edge clock clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 1.151ns (logic 0.407ns (35.369%) route 0.744ns (64.631%)) Logic Levels: 2 (CARRY4=1 LUT2=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.849ns Source Clock Delay (SCD): 0.580ns Clock Pessimism Removal (CPR): 0.254ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.548 0.548 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.053 -0.506 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -0.024 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.002 r U0/inst/clkout1_buf/O net (fo=60, routed) 0.578 0.580 UPD_CLK_DIV/clk_out1 SLICE_X40Y73 FDCE r UPD_CLK_DIV/temp_reg[24]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y73 FDCE (Prop_fdce_C_Q) 0.141 0.721 r UPD_CLK_DIV/temp_reg[24]/Q net (fo=4, routed) 0.245 0.966 UPD_CLK_DIV/temp_reg[24] SLICE_X42Y71 CARRY4 (Prop_carry4_S[0]_CO[0]) 0.142 1.108 f UPD_CLK_DIV/temp_reg[0]_i_4/CO[0] net (fo=1, routed) 0.219 1.328 UPD_CLK_DIV/temp_reg[0]_i_4_n_3 SLICE_X43Y71 LUT2 (Prop_lut2_I0_O) 0.124 1.452 f UPD_CLK_DIV/temp[0]_i_2/O net (fo=25, routed) 0.279 1.730 UPD_CLK_DIV/temp[0]_i_2_n_0 SLICE_X40Y72 FDCE f UPD_CLK_DIV/temp_reg[23]/CLR ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O net (fo=60, routed) 0.847 0.849 UPD_CLK_DIV/clk_out1 SLICE_X40Y72 FDCE r UPD_CLK_DIV/temp_reg[23]/C clock pessimism -0.254 0.595 SLICE_X40Y72 FDCE (Remov_fdce_C_CLR) -0.092 0.503 UPD_CLK_DIV/temp_reg[23] ------------------------------------------------------------------- required time -0.503 arrival time 1.730 ------------------------------------------------------------------- slack 1.228 Slack (MET) : 1.228ns (arrival time - required time) Source: UPD_CLK_DIV/temp_reg[24]/C (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: UPD_CLK_DIV/temp_reg[12]/CLR (removal check against rising-edge clock clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 1.153ns (logic 0.407ns (35.306%) route 0.746ns (64.694%)) Logic Levels: 2 (CARRY4=1 LUT2=1) Clock Path Skew: 0.017ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.851ns Source Clock Delay (SCD): 0.580ns Clock Pessimism Removal (CPR): 0.254ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.548 0.548 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.053 -0.506 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -0.024 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.002 r U0/inst/clkout1_buf/O net (fo=60, routed) 0.578 0.580 UPD_CLK_DIV/clk_out1 SLICE_X40Y73 FDCE r UPD_CLK_DIV/temp_reg[24]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y73 FDCE (Prop_fdce_C_Q) 0.141 0.721 r UPD_CLK_DIV/temp_reg[24]/Q net (fo=4, routed) 0.245 0.966 UPD_CLK_DIV/temp_reg[24] SLICE_X42Y71 CARRY4 (Prop_carry4_S[0]_CO[0]) 0.142 1.108 f UPD_CLK_DIV/temp_reg[0]_i_4/CO[0] net (fo=1, routed) 0.219 1.328 UPD_CLK_DIV/temp_reg[0]_i_4_n_3 SLICE_X43Y71 LUT2 (Prop_lut2_I0_O) 0.124 1.452 f UPD_CLK_DIV/temp[0]_i_2/O net (fo=25, routed) 0.281 1.732 UPD_CLK_DIV/temp[0]_i_2_n_0 SLICE_X40Y70 FDCE f UPD_CLK_DIV/temp_reg[12]/CLR ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O net (fo=60, routed) 0.849 0.851 UPD_CLK_DIV/clk_out1 SLICE_X40Y70 FDCE r UPD_CLK_DIV/temp_reg[12]/C clock pessimism -0.254 0.597 SLICE_X40Y70 FDCE (Remov_fdce_C_CLR) -0.092 0.505 UPD_CLK_DIV/temp_reg[12] ------------------------------------------------------------------- required time -0.505 arrival time 1.732 ------------------------------------------------------------------- slack 1.228 Slack (MET) : 1.228ns (arrival time - required time) Source: UPD_CLK_DIV/temp_reg[24]/C (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: UPD_CLK_DIV/temp_reg[13]/CLR (removal check against rising-edge clock clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - clk_out1_clk_wiz_1 rise@0.000ns) Data Path Delay: 1.153ns (logic 0.407ns (35.306%) route 0.746ns (64.694%)) Logic Levels: 2 (CARRY4=1 LUT2=1) Clock Path Skew: 0.017ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.851ns Source Clock Delay (SCD): 0.580ns Clock Pessimism Removal (CPR): 0.254ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.548 0.548 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.053 -0.506 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.482 -0.024 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.002 r U0/inst/clkout1_buf/O net (fo=60, routed) 0.578 0.580 UPD_CLK_DIV/clk_out1 SLICE_X40Y73 FDCE r UPD_CLK_DIV/temp_reg[24]/C ------------------------------------------------------------------- ------------------- SLICE_X40Y73 FDCE (Prop_fdce_C_Q) 0.141 0.721 r UPD_CLK_DIV/temp_reg[24]/Q net (fo=4, routed) 0.245 0.966 UPD_CLK_DIV/temp_reg[24] SLICE_X42Y71 CARRY4 (Prop_carry4_S[0]_CO[0]) 0.142 1.108 f UPD_CLK_DIV/temp_reg[0]_i_4/CO[0] net (fo=1, routed) 0.219 1.328 UPD_CLK_DIV/temp_reg[0]_i_4_n_3 SLICE_X43Y71 LUT2 (Prop_lut2_I0_O) 0.124 1.452 f UPD_CLK_DIV/temp[0]_i_2/O net (fo=25, routed) 0.281 1.732 UPD_CLK_DIV/temp[0]_i_2_n_0 SLICE_X40Y70 FDCE f UPD_CLK_DIV/temp_reg[13]/CLR ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O net (fo=60, routed) 0.849 0.851 UPD_CLK_DIV/clk_out1 SLICE_X40Y70 FDCE r UPD_CLK_DIV/temp_reg[13]/C clock pessimism -0.254 0.597 SLICE_X40Y70 FDCE (Remov_fdce_C_CLR) -0.092 0.505 UPD_CLK_DIV/temp_reg[13] ------------------------------------------------------------------- required time -0.505 arrival time 1.732 ------------------------------------------------------------------- slack 1.228 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: sys_clk_pin To Clock: clk_out1_clk_wiz_1 Setup : 0 Failing Endpoints, Worst Slack 2.088ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.745ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 2.088ns (required time - arrival time) Source: SNAKE/request_reg/C (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: SNAKE/startUpdate_reg/CLR (recovery check against rising-edge clock clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.000ns (clk_out1_clk_wiz_1 rise@40.000ns - sys_clk_pin rise@32.000ns) Data Path Delay: 1.259ns (logic 0.580ns (46.066%) route 0.679ns (53.934%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -3.842ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.498ns = ( 41.498 - 40.000 ) Source Clock Delay (SCD): 5.340ns = ( 37.340 - 32.000 ) Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 32.000 32.000 r L16 0.000 32.000 r H125MHz (IN) net (fo=0) 0.000 32.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.491 33.491 r H125MHz_IBUF_inst/O net (fo=1, routed) 2.076 35.567 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 35.668 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.672 37.340 SNAKE/H125MHz SLICE_X22Y44 FDRE r SNAKE/request_reg/C ------------------------------------------------------------------- ------------------- SLICE_X22Y44 FDRE (Prop_fdre_C_Q) 0.456 37.796 f SNAKE/request_reg/Q net (fo=5, routed) 0.292 38.088 SNAKE/dataRequest SLICE_X23Y44 LUT2 (Prop_lut2_I1_O) 0.124 38.212 f SNAKE/startUpdate_i_2/O net (fo=1, routed) 0.387 38.599 SNAKE/startUpdate_i_2_n_0 SLICE_X23Y44 FDCE f SNAKE/startUpdate_reg/CLR ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 40.000 40.000 r BUFGCTRL_X0Y16 BUFG 0.000 40.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.490 41.490 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.177 38.313 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.599 39.912 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 40.003 r U0/inst/clkout1_buf/O net (fo=60, routed) 1.495 41.498 SNAKE/clk_out1 SLICE_X23Y44 FDCE r SNAKE/startUpdate_reg/C clock pessimism 0.000 41.498 clock uncertainty -0.406 41.092 SLICE_X23Y44 FDCE (Recov_fdce_C_CLR) -0.405 40.687 SNAKE/startUpdate_reg ------------------------------------------------------------------- required time 40.687 arrival time -38.599 ------------------------------------------------------------------- slack 2.088 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.745ns (arrival time - required time) Source: SNAKE/request_reg/C (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: SNAKE/startUpdate_reg/CLR (removal check against rising-edge clock clk_out1_clk_wiz_1 {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_1 rise@0.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 0.415ns (logic 0.186ns (44.813%) route 0.229ns (55.187%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.644ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.830ns Source Clock Delay (SCD): 1.474ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.406ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.313ns Phase Error (PE): 0.246ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O net (fo=1, routed) 0.627 0.886 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.562 1.474 SNAKE/H125MHz SLICE_X22Y44 FDRE r SNAKE/request_reg/C ------------------------------------------------------------------- ------------------- SLICE_X22Y44 FDRE (Prop_fdre_C_Q) 0.141 1.615 f SNAKE/request_reg/Q net (fo=5, routed) 0.110 1.725 SNAKE/dataRequest SLICE_X23Y44 LUT2 (Prop_lut2_I1_O) 0.045 1.770 f SNAKE/startUpdate_i_2/O net (fo=1, routed) 0.119 1.889 SNAKE/startUpdate_i_2_n_0 SLICE_X23Y44 FDCE f SNAKE/startUpdate_reg/CLR ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.814 0.814 U0/inst/clk_in1 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.369 -0.555 r U0/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.528 -0.027 U0/inst/clk_out1_clk_wiz_1 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.002 r U0/inst/clkout1_buf/O net (fo=60, routed) 0.828 0.830 SNAKE/clk_out1 SLICE_X23Y44 FDCE r SNAKE/startUpdate_reg/C clock pessimism 0.000 0.830 clock uncertainty 0.406 1.236 SLICE_X23Y44 FDCE (Remov_fdce_C_CLR) -0.092 1.144 SNAKE/startUpdate_reg ------------------------------------------------------------------- required time -1.144 arrival time 1.889 ------------------------------------------------------------------- slack 0.745 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: sys_clk_pin To Clock: sys_clk_pin Setup : 0 Failing Endpoints, Worst Slack 4.029ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.841ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.029ns (required time - arrival time) Source: UPD/update_reg/C (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: UPD/dataOut_reg[13]/CLR (recovery check against rising-edge clock sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.000ns (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 3.371ns (logic 0.773ns (22.929%) route 2.598ns (77.071%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.160ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.895ns = ( 12.895 - 8.000 ) Source Clock Delay (SCD): 5.345ns Clock Pessimism Removal (CPR): 0.291ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O net (fo=1, routed) 2.076 3.567 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.677 5.345 UPD/H125MHz SLICE_X8Y34 FDRE r UPD/update_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y34 FDRE (Prop_fdre_C_Q) 0.478 5.823 r UPD/update_reg/Q net (fo=46, routed) 0.804 6.627 UPD/update SLICE_X9Y33 LUT1 (Prop_lut1_I0_O) 0.295 6.922 f UPD/currentSnake_reg[dirY][0]_i_2/O net (fo=16, routed) 1.794 8.717 UPD/currentSnake_reg[dirY][0]_i_2_n_0 SLICE_X26Y47 FDCE f UPD/dataOut_reg[13]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 8.000 8.000 r L16 0.000 8.000 r H125MHz (IN) net (fo=0) 0.000 8.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O net (fo=1, routed) 1.880 11.301 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.503 12.895 UPD/H125MHz SLICE_X26Y47 FDCE r UPD/dataOut_reg[13]/C clock pessimism 0.291 13.186 clock uncertainty -0.035 13.150 SLICE_X26Y47 FDCE (Recov_fdce_C_CLR) -0.405 12.745 UPD/dataOut_reg[13] ------------------------------------------------------------------- required time 12.745 arrival time -8.717 ------------------------------------------------------------------- slack 4.029 Slack (MET) : 4.166ns (required time - arrival time) Source: UPD/update_reg/C (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: UPD/dataOut_reg[10]/CLR (recovery check against rising-edge clock sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.000ns (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 3.233ns (logic 0.773ns (23.911%) route 2.460ns (76.089%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.161ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.894ns = ( 12.894 - 8.000 ) Source Clock Delay (SCD): 5.345ns Clock Pessimism Removal (CPR): 0.291ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O net (fo=1, routed) 2.076 3.567 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.677 5.345 UPD/H125MHz SLICE_X8Y34 FDRE r UPD/update_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y34 FDRE (Prop_fdre_C_Q) 0.478 5.823 r UPD/update_reg/Q net (fo=46, routed) 0.804 6.627 UPD/update SLICE_X9Y33 LUT1 (Prop_lut1_I0_O) 0.295 6.922 f UPD/currentSnake_reg[dirY][0]_i_2/O net (fo=16, routed) 1.656 8.578 UPD/currentSnake_reg[dirY][0]_i_2_n_0 SLICE_X26Y46 FDCE f UPD/dataOut_reg[10]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 8.000 8.000 r L16 0.000 8.000 r H125MHz (IN) net (fo=0) 0.000 8.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O net (fo=1, routed) 1.880 11.301 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.502 12.894 UPD/H125MHz SLICE_X26Y46 FDCE r UPD/dataOut_reg[10]/C clock pessimism 0.291 13.185 clock uncertainty -0.035 13.149 SLICE_X26Y46 FDCE (Recov_fdce_C_CLR) -0.405 12.744 UPD/dataOut_reg[10] ------------------------------------------------------------------- required time 12.744 arrival time -8.578 ------------------------------------------------------------------- slack 4.166 Slack (MET) : 4.166ns (required time - arrival time) Source: UPD/update_reg/C (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: UPD/dataOut_reg[11]/CLR (recovery check against rising-edge clock sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.000ns (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 3.233ns (logic 0.773ns (23.911%) route 2.460ns (76.089%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.161ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.894ns = ( 12.894 - 8.000 ) Source Clock Delay (SCD): 5.345ns Clock Pessimism Removal (CPR): 0.291ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O net (fo=1, routed) 2.076 3.567 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.677 5.345 UPD/H125MHz SLICE_X8Y34 FDRE r UPD/update_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y34 FDRE (Prop_fdre_C_Q) 0.478 5.823 r UPD/update_reg/Q net (fo=46, routed) 0.804 6.627 UPD/update SLICE_X9Y33 LUT1 (Prop_lut1_I0_O) 0.295 6.922 f UPD/currentSnake_reg[dirY][0]_i_2/O net (fo=16, routed) 1.656 8.578 UPD/currentSnake_reg[dirY][0]_i_2_n_0 SLICE_X26Y46 FDCE f UPD/dataOut_reg[11]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 8.000 8.000 r L16 0.000 8.000 r H125MHz (IN) net (fo=0) 0.000 8.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O net (fo=1, routed) 1.880 11.301 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.502 12.894 UPD/H125MHz SLICE_X26Y46 FDCE r UPD/dataOut_reg[11]/C clock pessimism 0.291 13.185 clock uncertainty -0.035 13.149 SLICE_X26Y46 FDCE (Recov_fdce_C_CLR) -0.405 12.744 UPD/dataOut_reg[11] ------------------------------------------------------------------- required time 12.744 arrival time -8.578 ------------------------------------------------------------------- slack 4.166 Slack (MET) : 4.166ns (required time - arrival time) Source: UPD/update_reg/C (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: UPD/dataOut_reg[12]/CLR (recovery check against rising-edge clock sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.000ns (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 3.233ns (logic 0.773ns (23.911%) route 2.460ns (76.089%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.161ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.894ns = ( 12.894 - 8.000 ) Source Clock Delay (SCD): 5.345ns Clock Pessimism Removal (CPR): 0.291ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O net (fo=1, routed) 2.076 3.567 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.677 5.345 UPD/H125MHz SLICE_X8Y34 FDRE r UPD/update_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y34 FDRE (Prop_fdre_C_Q) 0.478 5.823 r UPD/update_reg/Q net (fo=46, routed) 0.804 6.627 UPD/update SLICE_X9Y33 LUT1 (Prop_lut1_I0_O) 0.295 6.922 f UPD/currentSnake_reg[dirY][0]_i_2/O net (fo=16, routed) 1.656 8.578 UPD/currentSnake_reg[dirY][0]_i_2_n_0 SLICE_X26Y46 FDCE f UPD/dataOut_reg[12]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 8.000 8.000 r L16 0.000 8.000 r H125MHz (IN) net (fo=0) 0.000 8.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O net (fo=1, routed) 1.880 11.301 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.502 12.894 UPD/H125MHz SLICE_X26Y46 FDCE r UPD/dataOut_reg[12]/C clock pessimism 0.291 13.185 clock uncertainty -0.035 13.149 SLICE_X26Y46 FDCE (Recov_fdce_C_CLR) -0.405 12.744 UPD/dataOut_reg[12] ------------------------------------------------------------------- required time 12.744 arrival time -8.578 ------------------------------------------------------------------- slack 4.166 Slack (MET) : 4.166ns (required time - arrival time) Source: UPD/update_reg/C (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: UPD/dataOut_reg[9]/CLR (recovery check against rising-edge clock sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.000ns (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 3.233ns (logic 0.773ns (23.911%) route 2.460ns (76.089%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.161ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.894ns = ( 12.894 - 8.000 ) Source Clock Delay (SCD): 5.345ns Clock Pessimism Removal (CPR): 0.291ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O net (fo=1, routed) 2.076 3.567 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.677 5.345 UPD/H125MHz SLICE_X8Y34 FDRE r UPD/update_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y34 FDRE (Prop_fdre_C_Q) 0.478 5.823 r UPD/update_reg/Q net (fo=46, routed) 0.804 6.627 UPD/update SLICE_X9Y33 LUT1 (Prop_lut1_I0_O) 0.295 6.922 f UPD/currentSnake_reg[dirY][0]_i_2/O net (fo=16, routed) 1.656 8.578 UPD/currentSnake_reg[dirY][0]_i_2_n_0 SLICE_X26Y46 FDCE f UPD/dataOut_reg[9]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 8.000 8.000 r L16 0.000 8.000 r H125MHz (IN) net (fo=0) 0.000 8.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O net (fo=1, routed) 1.880 11.301 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.502 12.894 UPD/H125MHz SLICE_X26Y46 FDCE r UPD/dataOut_reg[9]/C clock pessimism 0.291 13.185 clock uncertainty -0.035 13.149 SLICE_X26Y46 FDCE (Recov_fdce_C_CLR) -0.405 12.744 UPD/dataOut_reg[9] ------------------------------------------------------------------- required time 12.744 arrival time -8.578 ------------------------------------------------------------------- slack 4.166 Slack (MET) : 4.315ns (required time - arrival time) Source: UPD/update_reg/C (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: UPD/dataOut_reg[5]/CLR (recovery check against rising-edge clock sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.000ns (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 3.085ns (logic 0.773ns (25.061%) route 2.312ns (74.939%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.161ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.894ns = ( 12.894 - 8.000 ) Source Clock Delay (SCD): 5.345ns Clock Pessimism Removal (CPR): 0.291ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O net (fo=1, routed) 2.076 3.567 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.677 5.345 UPD/H125MHz SLICE_X8Y34 FDRE r UPD/update_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y34 FDRE (Prop_fdre_C_Q) 0.478 5.823 r UPD/update_reg/Q net (fo=46, routed) 0.804 6.627 UPD/update SLICE_X9Y33 LUT1 (Prop_lut1_I0_O) 0.295 6.922 f UPD/currentSnake_reg[dirY][0]_i_2/O net (fo=16, routed) 1.508 8.430 UPD/currentSnake_reg[dirY][0]_i_2_n_0 SLICE_X26Y45 FDCE f UPD/dataOut_reg[5]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 8.000 8.000 r L16 0.000 8.000 r H125MHz (IN) net (fo=0) 0.000 8.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O net (fo=1, routed) 1.880 11.301 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.502 12.894 UPD/H125MHz SLICE_X26Y45 FDCE r UPD/dataOut_reg[5]/C clock pessimism 0.291 13.185 clock uncertainty -0.035 13.149 SLICE_X26Y45 FDCE (Recov_fdce_C_CLR) -0.405 12.744 UPD/dataOut_reg[5] ------------------------------------------------------------------- required time 12.744 arrival time -8.430 ------------------------------------------------------------------- slack 4.315 Slack (MET) : 4.315ns (required time - arrival time) Source: UPD/update_reg/C (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: UPD/dataOut_reg[6]/CLR (recovery check against rising-edge clock sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.000ns (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 3.085ns (logic 0.773ns (25.061%) route 2.312ns (74.939%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.161ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.894ns = ( 12.894 - 8.000 ) Source Clock Delay (SCD): 5.345ns Clock Pessimism Removal (CPR): 0.291ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O net (fo=1, routed) 2.076 3.567 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.677 5.345 UPD/H125MHz SLICE_X8Y34 FDRE r UPD/update_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y34 FDRE (Prop_fdre_C_Q) 0.478 5.823 r UPD/update_reg/Q net (fo=46, routed) 0.804 6.627 UPD/update SLICE_X9Y33 LUT1 (Prop_lut1_I0_O) 0.295 6.922 f UPD/currentSnake_reg[dirY][0]_i_2/O net (fo=16, routed) 1.508 8.430 UPD/currentSnake_reg[dirY][0]_i_2_n_0 SLICE_X26Y45 FDCE f UPD/dataOut_reg[6]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 8.000 8.000 r L16 0.000 8.000 r H125MHz (IN) net (fo=0) 0.000 8.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O net (fo=1, routed) 1.880 11.301 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.502 12.894 UPD/H125MHz SLICE_X26Y45 FDCE r UPD/dataOut_reg[6]/C clock pessimism 0.291 13.185 clock uncertainty -0.035 13.149 SLICE_X26Y45 FDCE (Recov_fdce_C_CLR) -0.405 12.744 UPD/dataOut_reg[6] ------------------------------------------------------------------- required time 12.744 arrival time -8.430 ------------------------------------------------------------------- slack 4.315 Slack (MET) : 4.315ns (required time - arrival time) Source: UPD/update_reg/C (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: UPD/dataOut_reg[7]/CLR (recovery check against rising-edge clock sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.000ns (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 3.085ns (logic 0.773ns (25.061%) route 2.312ns (74.939%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.161ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.894ns = ( 12.894 - 8.000 ) Source Clock Delay (SCD): 5.345ns Clock Pessimism Removal (CPR): 0.291ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O net (fo=1, routed) 2.076 3.567 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.677 5.345 UPD/H125MHz SLICE_X8Y34 FDRE r UPD/update_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y34 FDRE (Prop_fdre_C_Q) 0.478 5.823 r UPD/update_reg/Q net (fo=46, routed) 0.804 6.627 UPD/update SLICE_X9Y33 LUT1 (Prop_lut1_I0_O) 0.295 6.922 f UPD/currentSnake_reg[dirY][0]_i_2/O net (fo=16, routed) 1.508 8.430 UPD/currentSnake_reg[dirY][0]_i_2_n_0 SLICE_X26Y45 FDCE f UPD/dataOut_reg[7]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 8.000 8.000 r L16 0.000 8.000 r H125MHz (IN) net (fo=0) 0.000 8.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O net (fo=1, routed) 1.880 11.301 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.502 12.894 UPD/H125MHz SLICE_X26Y45 FDCE r UPD/dataOut_reg[7]/C clock pessimism 0.291 13.185 clock uncertainty -0.035 13.149 SLICE_X26Y45 FDCE (Recov_fdce_C_CLR) -0.405 12.744 UPD/dataOut_reg[7] ------------------------------------------------------------------- required time 12.744 arrival time -8.430 ------------------------------------------------------------------- slack 4.315 Slack (MET) : 4.319ns (required time - arrival time) Source: UPD/update_reg/C (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: UPD/dataOut_reg[2]/CLR (recovery check against rising-edge clock sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.000ns (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 3.080ns (logic 0.773ns (25.096%) route 2.307ns (74.904%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.161ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.894ns = ( 12.894 - 8.000 ) Source Clock Delay (SCD): 5.345ns Clock Pessimism Removal (CPR): 0.291ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O net (fo=1, routed) 2.076 3.567 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.677 5.345 UPD/H125MHz SLICE_X8Y34 FDRE r UPD/update_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y34 FDRE (Prop_fdre_C_Q) 0.478 5.823 r UPD/update_reg/Q net (fo=46, routed) 0.804 6.627 UPD/update SLICE_X9Y33 LUT1 (Prop_lut1_I0_O) 0.295 6.922 f UPD/currentSnake_reg[dirY][0]_i_2/O net (fo=16, routed) 1.503 8.425 UPD/currentSnake_reg[dirY][0]_i_2_n_0 SLICE_X27Y45 FDCE f UPD/dataOut_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 8.000 8.000 r L16 0.000 8.000 r H125MHz (IN) net (fo=0) 0.000 8.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O net (fo=1, routed) 1.880 11.301 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.502 12.894 UPD/H125MHz SLICE_X27Y45 FDCE r UPD/dataOut_reg[2]/C clock pessimism 0.291 13.185 clock uncertainty -0.035 13.149 SLICE_X27Y45 FDCE (Recov_fdce_C_CLR) -0.405 12.744 UPD/dataOut_reg[2] ------------------------------------------------------------------- required time 12.744 arrival time -8.425 ------------------------------------------------------------------- slack 4.319 Slack (MET) : 4.353ns (required time - arrival time) Source: UPD/update_reg/C (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: UPD/dataOut_reg[20]_P/PRE (recovery check against rising-edge clock sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.000ns (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 3.188ns (logic 0.773ns (24.251%) route 2.415ns (75.749%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.065ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.889ns = ( 12.889 - 8.000 ) Source Clock Delay (SCD): 5.345ns Clock Pessimism Removal (CPR): 0.391ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.491 1.491 r H125MHz_IBUF_inst/O net (fo=1, routed) 2.076 3.567 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 3.668 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.677 5.345 UPD/H125MHz SLICE_X8Y34 FDRE r UPD/update_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y34 FDRE (Prop_fdre_C_Q) 0.478 5.823 r UPD/update_reg/Q net (fo=46, routed) 1.437 7.260 UPD/update SLICE_X6Y28 LUT2 (Prop_lut2_I1_O) 0.295 7.555 f UPD/dataOut_reg[20]_LDC_i_1/O net (fo=2, routed) 0.977 8.533 UPD/dataOut_reg[20]_LDC_i_1_n_0 SLICE_X7Y28 FDPE f UPD/dataOut_reg[20]_P/PRE ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 8.000 8.000 r L16 0.000 8.000 r H125MHz (IN) net (fo=0) 0.000 8.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 1.421 9.421 r H125MHz_IBUF_inst/O net (fo=1, routed) 1.880 11.301 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.392 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 1.497 12.889 UPD/H125MHz SLICE_X7Y28 FDPE r UPD/dataOut_reg[20]_P/C clock pessimism 0.391 13.280 clock uncertainty -0.035 13.245 SLICE_X7Y28 FDPE (Recov_fdpe_C_PRE) -0.359 12.886 UPD/dataOut_reg[20]_P ------------------------------------------------------------------- required time 12.886 arrival time -8.533 ------------------------------------------------------------------- slack 4.353 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.841ns (arrival time - required time) Source: UPD/update_reg/C (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: UPD/dataOut_reg[22]/CLR (removal check against rising-edge clock sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 0.785ns (logic 0.246ns (31.332%) route 0.539ns (68.668%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.986ns Source Clock Delay (SCD): 1.476ns Clock Pessimism Removal (CPR): 0.499ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O net (fo=1, routed) 0.627 0.886 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.564 1.476 UPD/H125MHz SLICE_X8Y34 FDRE r UPD/update_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y34 FDRE (Prop_fdre_C_Q) 0.148 1.624 r UPD/update_reg/Q net (fo=46, routed) 0.357 1.981 UPD/update SLICE_X9Y33 LUT1 (Prop_lut1_I0_O) 0.098 2.079 f UPD/currentSnake_reg[dirY][0]_i_2/O net (fo=16, routed) 0.182 2.261 UPD/currentSnake_reg[dirY][0]_i_2_n_0 SLICE_X8Y31 FDCE f UPD/dataOut_reg[22]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r H125MHz_IBUF_inst/O net (fo=1, routed) 0.683 1.130 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.159 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.827 1.986 UPD/H125MHz SLICE_X8Y31 FDCE r UPD/dataOut_reg[22]/C clock pessimism -0.499 1.487 SLICE_X8Y31 FDCE (Remov_fdce_C_CLR) -0.067 1.420 UPD/dataOut_reg[22] ------------------------------------------------------------------- required time -1.420 arrival time 2.261 ------------------------------------------------------------------- slack 0.841 Slack (MET) : 0.841ns (arrival time - required time) Source: UPD/update_reg/C (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: UPD/dataOut_reg[23]/CLR (removal check against rising-edge clock sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 0.785ns (logic 0.246ns (31.332%) route 0.539ns (68.668%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.986ns Source Clock Delay (SCD): 1.476ns Clock Pessimism Removal (CPR): 0.499ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O net (fo=1, routed) 0.627 0.886 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.564 1.476 UPD/H125MHz SLICE_X8Y34 FDRE r UPD/update_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y34 FDRE (Prop_fdre_C_Q) 0.148 1.624 r UPD/update_reg/Q net (fo=46, routed) 0.357 1.981 UPD/update SLICE_X9Y33 LUT1 (Prop_lut1_I0_O) 0.098 2.079 f UPD/currentSnake_reg[dirY][0]_i_2/O net (fo=16, routed) 0.182 2.261 UPD/currentSnake_reg[dirY][0]_i_2_n_0 SLICE_X8Y31 FDCE f UPD/dataOut_reg[23]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r H125MHz_IBUF_inst/O net (fo=1, routed) 0.683 1.130 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.159 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.827 1.986 UPD/H125MHz SLICE_X8Y31 FDCE r UPD/dataOut_reg[23]/C clock pessimism -0.499 1.487 SLICE_X8Y31 FDCE (Remov_fdce_C_CLR) -0.067 1.420 UPD/dataOut_reg[23] ------------------------------------------------------------------- required time -1.420 arrival time 2.261 ------------------------------------------------------------------- slack 0.841 Slack (MET) : 0.920ns (arrival time - required time) Source: UPD/update_reg/C (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: UPD/dataOut_reg[14]/CLR (removal check against rising-edge clock sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 0.862ns (logic 0.246ns (28.546%) route 0.616ns (71.454%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.009ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.984ns Source Clock Delay (SCD): 1.476ns Clock Pessimism Removal (CPR): 0.499ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O net (fo=1, routed) 0.627 0.886 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.564 1.476 UPD/H125MHz SLICE_X8Y34 FDRE r UPD/update_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y34 FDRE (Prop_fdre_C_Q) 0.148 1.624 r UPD/update_reg/Q net (fo=46, routed) 0.357 1.981 UPD/update SLICE_X9Y33 LUT1 (Prop_lut1_I0_O) 0.098 2.079 f UPD/currentSnake_reg[dirY][0]_i_2/O net (fo=16, routed) 0.259 2.337 UPD/currentSnake_reg[dirY][0]_i_2_n_0 SLICE_X8Y29 FDCE f UPD/dataOut_reg[14]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r H125MHz_IBUF_inst/O net (fo=1, routed) 0.683 1.130 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.159 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.825 1.984 UPD/H125MHz SLICE_X8Y29 FDCE r UPD/dataOut_reg[14]/C clock pessimism -0.499 1.485 SLICE_X8Y29 FDCE (Remov_fdce_C_CLR) -0.067 1.418 UPD/dataOut_reg[14] ------------------------------------------------------------------- required time -1.418 arrival time 2.337 ------------------------------------------------------------------- slack 0.920 Slack (MET) : 0.920ns (arrival time - required time) Source: UPD/update_reg/C (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: UPD/dataOut_reg[15]/CLR (removal check against rising-edge clock sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 0.862ns (logic 0.246ns (28.546%) route 0.616ns (71.454%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.009ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.984ns Source Clock Delay (SCD): 1.476ns Clock Pessimism Removal (CPR): 0.499ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O net (fo=1, routed) 0.627 0.886 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.564 1.476 UPD/H125MHz SLICE_X8Y34 FDRE r UPD/update_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y34 FDRE (Prop_fdre_C_Q) 0.148 1.624 r UPD/update_reg/Q net (fo=46, routed) 0.357 1.981 UPD/update SLICE_X9Y33 LUT1 (Prop_lut1_I0_O) 0.098 2.079 f UPD/currentSnake_reg[dirY][0]_i_2/O net (fo=16, routed) 0.259 2.337 UPD/currentSnake_reg[dirY][0]_i_2_n_0 SLICE_X8Y29 FDCE f UPD/dataOut_reg[15]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r H125MHz_IBUF_inst/O net (fo=1, routed) 0.683 1.130 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.159 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.825 1.984 UPD/H125MHz SLICE_X8Y29 FDCE r UPD/dataOut_reg[15]/C clock pessimism -0.499 1.485 SLICE_X8Y29 FDCE (Remov_fdce_C_CLR) -0.067 1.418 UPD/dataOut_reg[15] ------------------------------------------------------------------- required time -1.418 arrival time 2.337 ------------------------------------------------------------------- slack 0.920 Slack (MET) : 0.920ns (arrival time - required time) Source: UPD/update_reg/C (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: UPD/dataOut_reg[16]/CLR (removal check against rising-edge clock sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 0.862ns (logic 0.246ns (28.546%) route 0.616ns (71.454%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.009ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.984ns Source Clock Delay (SCD): 1.476ns Clock Pessimism Removal (CPR): 0.499ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O net (fo=1, routed) 0.627 0.886 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.564 1.476 UPD/H125MHz SLICE_X8Y34 FDRE r UPD/update_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y34 FDRE (Prop_fdre_C_Q) 0.148 1.624 r UPD/update_reg/Q net (fo=46, routed) 0.357 1.981 UPD/update SLICE_X9Y33 LUT1 (Prop_lut1_I0_O) 0.098 2.079 f UPD/currentSnake_reg[dirY][0]_i_2/O net (fo=16, routed) 0.259 2.337 UPD/currentSnake_reg[dirY][0]_i_2_n_0 SLICE_X8Y29 FDCE f UPD/dataOut_reg[16]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r H125MHz_IBUF_inst/O net (fo=1, routed) 0.683 1.130 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.159 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.825 1.984 UPD/H125MHz SLICE_X8Y29 FDCE r UPD/dataOut_reg[16]/C clock pessimism -0.499 1.485 SLICE_X8Y29 FDCE (Remov_fdce_C_CLR) -0.067 1.418 UPD/dataOut_reg[16] ------------------------------------------------------------------- required time -1.418 arrival time 2.337 ------------------------------------------------------------------- slack 0.920 Slack (MET) : 0.924ns (arrival time - required time) Source: UPD/update_reg/C (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: UPD/dataOut_reg[17]/PRE (removal check against rising-edge clock sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 0.862ns (logic 0.246ns (28.546%) route 0.616ns (71.454%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.009ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.984ns Source Clock Delay (SCD): 1.476ns Clock Pessimism Removal (CPR): 0.499ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O net (fo=1, routed) 0.627 0.886 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.564 1.476 UPD/H125MHz SLICE_X8Y34 FDRE r UPD/update_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y34 FDRE (Prop_fdre_C_Q) 0.148 1.624 r UPD/update_reg/Q net (fo=46, routed) 0.357 1.981 UPD/update SLICE_X9Y33 LUT1 (Prop_lut1_I0_O) 0.098 2.079 f UPD/currentSnake_reg[dirY][0]_i_2/O net (fo=16, routed) 0.259 2.337 UPD/currentSnake_reg[dirY][0]_i_2_n_0 SLICE_X8Y29 FDPE f UPD/dataOut_reg[17]/PRE ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r H125MHz_IBUF_inst/O net (fo=1, routed) 0.683 1.130 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.159 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.825 1.984 UPD/H125MHz SLICE_X8Y29 FDPE r UPD/dataOut_reg[17]/C clock pessimism -0.499 1.485 SLICE_X8Y29 FDPE (Remov_fdpe_C_PRE) -0.071 1.414 UPD/dataOut_reg[17] ------------------------------------------------------------------- required time -1.414 arrival time 2.337 ------------------------------------------------------------------- slack 0.924 Slack (MET) : 0.974ns (arrival time - required time) Source: UPD/update_reg/C (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: UPD/dataOut_reg[19]_P/PRE (removal check against rising-edge clock sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 0.910ns (logic 0.246ns (27.026%) route 0.664ns (72.974%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.031ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.987ns Source Clock Delay (SCD): 1.476ns Clock Pessimism Removal (CPR): 0.480ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O net (fo=1, routed) 0.627 0.886 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.564 1.476 UPD/H125MHz SLICE_X8Y34 FDRE r UPD/update_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y34 FDRE (Prop_fdre_C_Q) 0.148 1.624 r UPD/update_reg/Q net (fo=46, routed) 0.533 2.157 UPD/update SLICE_X7Y32 LUT2 (Prop_lut2_I1_O) 0.098 2.255 f UPD/dataOut_reg[19]_LDC_i_1/O net (fo=2, routed) 0.131 2.386 UPD/dataOut_reg[19]_LDC_i_1_n_0 SLICE_X7Y32 FDPE f UPD/dataOut_reg[19]_P/PRE ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r H125MHz_IBUF_inst/O net (fo=1, routed) 0.683 1.130 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.159 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.828 1.987 UPD/H125MHz SLICE_X7Y32 FDPE r UPD/dataOut_reg[19]_P/C clock pessimism -0.480 1.507 SLICE_X7Y32 FDPE (Remov_fdpe_C_PRE) -0.095 1.412 UPD/dataOut_reg[19]_P ------------------------------------------------------------------- required time -1.412 arrival time 2.386 ------------------------------------------------------------------- slack 0.974 Slack (MET) : 0.987ns (arrival time - required time) Source: UPD/update_reg/C (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: UPD/dataOut_reg[19]_C/CLR (removal check against rising-edge clock sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 0.932ns (logic 0.246ns (26.401%) route 0.686ns (73.599%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.987ns Source Clock Delay (SCD): 1.476ns Clock Pessimism Removal (CPR): 0.499ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O net (fo=1, routed) 0.627 0.886 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.564 1.476 UPD/H125MHz SLICE_X8Y34 FDRE r UPD/update_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y34 FDRE (Prop_fdre_C_Q) 0.148 1.624 r UPD/update_reg/Q net (fo=46, routed) 0.502 2.126 UPD/update SLICE_X7Y32 LUT2 (Prop_lut2_I1_O) 0.098 2.224 f UPD/dataOut_reg[19]_LDC_i_2/O net (fo=2, routed) 0.184 2.408 UPD/dataOut_reg[19]_LDC_i_2_n_0 SLICE_X8Y32 FDCE f UPD/dataOut_reg[19]_C/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r H125MHz_IBUF_inst/O net (fo=1, routed) 0.683 1.130 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.159 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.828 1.987 UPD/H125MHz SLICE_X8Y32 FDCE r UPD/dataOut_reg[19]_C/C clock pessimism -0.499 1.488 SLICE_X8Y32 FDCE (Remov_fdce_C_CLR) -0.067 1.421 UPD/dataOut_reg[19]_C ------------------------------------------------------------------- required time -1.421 arrival time 2.408 ------------------------------------------------------------------- slack 0.987 Slack (MET) : 0.994ns (arrival time - required time) Source: UPD/update_reg/C (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: UPD/dataOut_reg[0]_C/CLR (removal check against rising-edge clock sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 0.935ns (logic 0.246ns (26.298%) route 0.689ns (73.702%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.008ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.983ns Source Clock Delay (SCD): 1.476ns Clock Pessimism Removal (CPR): 0.499ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O net (fo=1, routed) 0.627 0.886 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.564 1.476 UPD/H125MHz SLICE_X8Y34 FDRE r UPD/update_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y34 FDRE (Prop_fdre_C_Q) 0.148 1.624 r UPD/update_reg/Q net (fo=46, routed) 0.415 2.039 UPD/update SLICE_X6Y27 LUT2 (Prop_lut2_I1_O) 0.098 2.137 f UPD/dataOut_reg[4]_LDC_i_2/O net (fo=4, routed) 0.274 2.411 UPD/dataOut_reg[4]_LDC_i_2_n_0 SLICE_X8Y28 FDCE f UPD/dataOut_reg[0]_C/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r H125MHz_IBUF_inst/O net (fo=1, routed) 0.683 1.130 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.159 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.824 1.983 UPD/H125MHz SLICE_X8Y28 FDCE r UPD/dataOut_reg[0]_C/C clock pessimism -0.499 1.484 SLICE_X8Y28 FDCE (Remov_fdce_C_CLR) -0.067 1.417 UPD/dataOut_reg[0]_C ------------------------------------------------------------------- required time -1.417 arrival time 2.411 ------------------------------------------------------------------- slack 0.994 Slack (MET) : 0.994ns (arrival time - required time) Source: UPD/update_reg/C (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: UPD/dataOut_reg[3]_C/CLR (removal check against rising-edge clock sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 0.935ns (logic 0.246ns (26.298%) route 0.689ns (73.702%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.008ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.983ns Source Clock Delay (SCD): 1.476ns Clock Pessimism Removal (CPR): 0.499ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 0.259 0.259 r H125MHz_IBUF_inst/O net (fo=1, routed) 0.627 0.886 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.912 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.564 1.476 UPD/H125MHz SLICE_X8Y34 FDRE r UPD/update_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y34 FDRE (Prop_fdre_C_Q) 0.148 1.624 r UPD/update_reg/Q net (fo=46, routed) 0.415 2.039 UPD/update SLICE_X6Y27 LUT2 (Prop_lut2_I1_O) 0.098 2.137 f UPD/dataOut_reg[4]_LDC_i_2/O net (fo=4, routed) 0.274 2.411 UPD/dataOut_reg[4]_LDC_i_2_n_0 SLICE_X8Y28 FDCE f UPD/dataOut_reg[3]_C/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r L16 0.000 0.000 r H125MHz (IN) net (fo=0) 0.000 0.000 H125MHz L16 IBUF (Prop_ibuf_I_O) 0.447 0.447 r H125MHz_IBUF_inst/O net (fo=1, routed) 0.683 1.130 H125MHz_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.159 r H125MHz_IBUF_BUFG_inst/O net (fo=184, routed) 0.824 1.983 UPD/H125MHz SLICE_X8Y28 FDCE r UPD/dataOut_reg[3]_C/C clock pessimism -0.499 1.484 SLICE_X8Y28 FDCE (Remov_fdce_C_CLR) -0.067 1.417 UPD/dataOut_reg[3]_C ------------------------------------------------------------------- required time -1.417 arrival time 2.411 ------------------------------------------------------------------- slack 0.994