Device Usage Page (usage_statistics_webtalk.html)

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software_version_and_target_device
betaFALSE build_version2405991
date_generatedTue Jan 4 12:21:35 2022 os_platformWIN64
product_versionVivado v2018.3 (64-bit) project_id5587c47a25864f30a941d919a4588f42
project_iteration49 random_id5c5083d208095dd793a4532428ca92e6
registration_id174121763_1777493939_210660961_260 route_designTRUE
target_devicexc7z010 target_familyzynq
target_packageclg400 target_speed-1
tool_flowVivado

user_environment
cpu_nameIntel(R) Core(TM) i7-10700 CPU @ 2.90GHz cpu_speed2904 MHz
os_nameMicrosoft Windows 8 or later , 64-bit os_releasemajor release (build 9200)
system_ram16.000 GB total_processors1

vivado_usage
gui_handlers
abstractcombinedpanel_add_element=9 abstractcombinedpanel_remove_selected_elements=2 abstractfileview_close=1 abstractfileview_reload=2
addsrcwizard_specify_or_create_constraint_files=1 basedialog_cancel=59 basedialog_close=1 basedialog_no=3
basedialog_ok=474 basedialog_yes=4 cmdmsgdialog_ok=2 confirmsavetexteditsdialog_no=1
constraintschooserpanel_add_files=2 coretreetablepanel_core_tree_table=24 createnewdiagramdialog_design_name=1 createsrcfiledialog_file_name=5
definemodulesdialog_define_modules_and_specify_io_ports=95 filesetpanel_file_set_panel_tree=209 flownavigatortreepanel_flow_navigator_tree=261 fpgachooser_fpga_table=1
gettingstartedview_create_new_project=2 gettingstartedview_open_project=1 hcodeeditor_blank_operations=17 hcodeeditor_close=3
hcodeeditor_commands_to_fold_text=2 hcodeeditor_diff_with=8 hcodeeditor_search_text_combo_box=20 hinputhandler_indent_selection=1
hinputhandler_toggle_line_comments=40 hinputhandler_unindent_selection=2 hpopuptitle_close=1 logmonitor_monitor=3
msgtreepanel_manage_suppression=1 msgtreepanel_message_view_tree=137 msgview_clear_messages_resulting_from_user_executed=4 msgview_critical_warnings=2
msgview_error_messages=4 msgview_information_messages=3 msgview_warning_messages=11 netlisttreeview_netlist_tree=4
numjobschooser_number_of_jobs=3 pacommandnames_auto_connect_target=18 pacommandnames_auto_update_hier=15 pacommandnames_goto_implemented_design=2
pacommandnames_goto_netlist_design=1 pacommandnames_log_window=1 pacommandnames_message_window=2 pacommandnames_open_hardware_manager=2
pacommandnames_recustomize_core=1 pacommandnames_run_bitgen=45 pacommandnames_run_implementation=8 pacommandnames_src_disable=1
paviews_code=7 paviews_device=3 paviews_ip_catalog=2 paviews_project_summary=26
paviews_schematic=10 programdebugtab_program_device=1 programdebugtab_refresh_device=2 programfpgadialog_program=51
progressdialog_background=5 progressdialog_cancel=5 projectnamechooser_project_name=1 projecttab_reload=9
rdicommands_copy=1 rdicommands_delete=8 removesourcesdialog_also_delete=2 rungadget_show_warning_and_error_messages_in_messages=2
saveprojectutils_dont_save=8 saveprojectutils_save=6 schematicview_previous=10 simpleoutputproductdialog_generate_output_products_immediately=4
specifylibrarydialog_library_name=1 srcchooserpanel_add_directories=2 srcchooserpanel_add_hdl_and_netlist_files_to_your_project=3 srcchooserpanel_add_or_create_source_file=1
srcchooserpanel_create_file=6 srcfileproppanels_type=4 srcfiletypecombobox_source_file_type=4 srcmenu_ip_documentation=6
srcmenu_ip_hierarchy=10 srcmenu_set_library=1 stalerundialog_no=1 syntheticagettingstartedview_recent_projects=4
syntheticastatemonitor_cancel=7 taskbanner_close=19
java_command_handlers
addsources=11 autoconnecttarget=18 coreview=4 createblockdesign=3
customizecore=5 editdelete=9 editpaste=3 editundo=1
fliptoviewtaskrtlanalysis=1 launchprogramfpga=51 newproject=2 openhardwaremanager=74
openproject=1 openrecenttarget=24 programdevice=50 recustomizecore=3
runbitgen=54 runimplementation=68 runschematic=7 runsynthesis=114
savefileproxyhandler=3 setsourceenabled=1 showview=35 viewtaskimplementation=8
viewtaskrtlanalysis=7 viewtasksynthesis=2
other_data
guimode=6
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=2 export_simulation_ies=2
export_simulation_modelsim=2 export_simulation_questa=2 export_simulation_riviera=2 export_simulation_vcs=2
export_simulation_xsim=2 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=0 simulator_language=VHDL srcsetcount=13 synthesisstrategy=Vivado Synthesis Defaults
target_language=VHDL target_simulator=XSim totalimplruns=1 totalsynthesisruns=1

unisim_transformation
post_unisim_transformation
bufg=2 carry4=266 fdce=62 fdpe=10
fdre=114 fdse=1 gnd=11 ibuf=2
ldce=23 lut1=12 lut2=275 lut3=323
lut4=365 lut5=358 lut6=447 mmcme2_adv=1
muxf7=19 muxf8=1 obuf=21 obuft=1
ramb18e1=9 ramb36e1=18 vcc=11
pre_unisim_transformation
bufg=2 carry4=266 fdce=62 fdpe=10
fdre=114 fdse=1 gnd=11 ibuf=3
ldce=23 lut1=12 lut2=275 lut3=323
lut4=365 lut5=358 lut6=447 mmcme2_adv=1
muxf7=19 muxf8=1 obuf=21 obuft=1
ramb18e1=9 ramb36e1=18 vcc=11

power_opt_design
command_line_options_spo
-cell_types=default::all -clocks=default::[not_specified] -exclude_cells=default::[not_specified] -include_cells=default::[not_specified]
usage
bram_ports_augmented=0 bram_ports_newly_gated=25 bram_ports_total=54 flow_state=default
slice_registers_augmented=0 slice_registers_newly_gated=0 slice_registers_total=187 srls_augmented=0
srls_newly_gated=0 srls_total=0

ip_statistics
clk_wiz_v6_0_2_0_0/1
clkin1_period=8.000 clkin2_period=10.000 clock_mgr_type=NA component_name=clk_wiz_1
core_container=NA enable_axi=0 feedback_source=FDBK_AUTO feedback_type=SINGLE
iptotal=1 manual_override=false num_out_clk=1 primitive=MMCM
use_dyn_phase_shift=false use_dyn_reconfig=false use_inclk_stopped=false use_inclk_switchover=false
use_locked=false use_max_i_jitter=false use_min_o_jitter=false use_phase_alignment=true
use_power_down=false use_reset=false

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -internal=default::[not_specified] -internal_only=default::[not_specified] -messages=default::[not_specified]
-name=default::[not_specified] -no_waivers=default::[not_specified] -return_string=default::[not_specified] -ruledecks=default::[not_specified]
-upgrade_cw=default::[not_specified] -waived=default::[not_specified]
results
pdrc-153=6 zps7-1=1

report_methodology
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-slack_lesser_than=default::[not_specified] -waived=default::[not_specified]
results
lutar-1=14 synth-6=26 timing-16=21 timing-18=5
timing-20=23 timing-27=1 timing-4=1 timing-6=2
timing-7=2

report_power
command_line_options
-advisory=default::[not_specified] -append=default::[not_specified] -file=[specified] -format=default::text
-hier=default::power -hierarchical_depth=default::4 -l=default::[not_specified] -name=default::[not_specified]
-no_propagation=default::[not_specified] -return_string=default::[not_specified] -rpx=[specified] -verbose=default::[not_specified]
-vid=default::[not_specified] -xpe=default::[not_specified]
usage
airflow=250 (LFM) ambient_temp=25.0 (C) bi-dir_toggle=12.500000 bidir_output_enable=1.000000
board_layers=8to11 (8 to 11 Layers) board_selection=medium (10"x10") bram=0.074844 clocks=0.003860
confidence_level_clock_activity=Medium confidence_level_design_state=High confidence_level_device_models=High confidence_level_internal_activity=Medium
confidence_level_io_activity=Medium confidence_level_overall=Medium customer=TBD customer_class=TBD
devstatic=0.096510 die=xc7z010clg400-1 dsp_output_toggle=12.500000 dynamic=0.201475
effective_thetaja=11.5 enable_probability=0.990000 family=zynq ff_toggle=12.500000
flow_state=routed heatsink=none i/o=0.001879 input_toggle=12.500000
junction_temp=28.4 (C) logic=0.002055 mgtavcc_dynamic_current=0.000000 mgtavcc_static_current=0.000000
mgtavcc_total_current=0.000000 mgtavcc_voltage=1.000000 mgtavtt_dynamic_current=0.000000 mgtavtt_static_current=0.000000
mgtavtt_total_current=0.000000 mgtavtt_voltage=1.200000 mgtvccaux_dynamic_current=0.000000 mgtvccaux_static_current=0.000000
mgtvccaux_total_current=0.000000 mgtvccaux_voltage=1.800000 mmcm=0.115225 netlist_net_matched=NA
off-chip_power=0.000000 on-chip_power=0.297985 output_enable=1.000000 output_load=5.000000
output_toggle=12.500000 package=clg400 pct_clock_constrained=1.000000 pct_inputs_defined=50
platform=nt64 process=typical ram_enable=50.000000 ram_write=50.000000
read_saif=False set/reset_probability=0.000000 signal_rate=False signals=0.003612
simulation_file=None speedgrade=-1 static_prob=False temp_grade=commercial
thetajb=9.3 (C/W) thetasa=0.0 (C/W) toggle_rate=False user_board_temp=25.0 (C)
user_effective_thetaja=11.5 user_junc_temp=28.4 (C) user_thetajb=9.3 (C/W) user_thetasa=0.0 (C/W)
vccadc_dynamic_current=0.000000 vccadc_static_current=0.020000 vccadc_total_current=0.020000 vccadc_voltage=1.800000
vccaux_dynamic_current=0.064022 vccaux_io_dynamic_current=0.000000 vccaux_io_static_current=0.000000 vccaux_io_total_current=0.000000
vccaux_io_voltage=1.800000 vccaux_static_current=0.005617 vccaux_total_current=0.069639 vccaux_voltage=1.800000
vccbram_dynamic_current=0.006550 vccbram_static_current=0.001052 vccbram_total_current=0.007602 vccbram_voltage=1.000000
vccint_dynamic_current=0.078006 vccint_static_current=0.004501 vccint_total_current=0.082507 vccint_voltage=1.000000
vcco12_dynamic_current=0.000000 vcco12_static_current=0.000000 vcco12_total_current=0.000000 vcco12_voltage=1.200000
vcco135_dynamic_current=0.000000 vcco135_static_current=0.000000 vcco135_total_current=0.000000 vcco135_voltage=1.350000
vcco15_dynamic_current=0.000000 vcco15_static_current=0.000000 vcco15_total_current=0.000000 vcco15_voltage=1.500000
vcco18_dynamic_current=0.000000 vcco18_static_current=0.000000 vcco18_total_current=0.000000 vcco18_voltage=1.800000
vcco25_dynamic_current=0.000000 vcco25_static_current=0.000000 vcco25_total_current=0.000000 vcco25_voltage=2.500000
vcco33_dynamic_current=0.000509 vcco33_static_current=0.001000 vcco33_total_current=0.001509 vcco33_voltage=3.300000
vcco_ddr_dynamic_current=0.000000 vcco_ddr_static_current=0.000000 vcco_ddr_total_current=0.000000 vcco_ddr_voltage=1.500000
vcco_mio0_dynamic_current=0.000000 vcco_mio0_static_current=0.000000 vcco_mio0_total_current=0.000000 vcco_mio0_voltage=1.800000
vcco_mio1_dynamic_current=0.000000 vcco_mio1_static_current=0.000000 vcco_mio1_total_current=0.000000 vcco_mio1_voltage=1.800000
vccpaux_dynamic_current=0.000000 vccpaux_static_current=0.010330 vccpaux_total_current=0.010330 vccpaux_voltage=1.800000
vccpint_dynamic_current=0.000000 vccpint_static_current=0.017552 vccpint_total_current=0.017552 vccpint_voltage=1.000000
vccpll_dynamic_current=0.000000 vccpll_static_current=0.003000 vccpll_total_current=0.003000 vccpll_voltage=1.800000
version=2018.3

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=3 bufgctrl_util_percentage=9.38
bufhce_available=48 bufhce_fixed=0 bufhce_used=0 bufhce_util_percentage=0.00
bufio_available=8 bufio_fixed=0 bufio_used=0 bufio_util_percentage=0.00
bufmrce_available=4 bufmrce_fixed=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=8 bufr_fixed=0 bufr_used=0 bufr_util_percentage=0.00
mmcme2_adv_available=2 mmcme2_adv_fixed=0 mmcme2_adv_used=1 mmcme2_adv_util_percentage=50.00
plle2_adv_available=2 plle2_adv_fixed=0 plle2_adv_used=0 plle2_adv_util_percentage=0.00
dsp
dsps_available=80 dsps_fixed=0 dsps_used=0 dsps_util_percentage=0.00
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=0 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=60 block_ram_tile_fixed=0 block_ram_tile_used=22.5 block_ram_tile_util_percentage=37.50
ramb18_available=120 ramb18_fixed=0 ramb18_used=9 ramb18_util_percentage=7.50
ramb18e1_only_used=9 ramb36_fifo_available=60 ramb36_fifo_fixed=0 ramb36_fifo_used=18
ramb36_fifo_util_percentage=30.00 ramb36e1_only_used=18
primitives
bufg_functional_category=Clock bufg_used=3 carry4_functional_category=CarryLogic carry4_used=266
fdce_functional_category=Flop & Latch fdce_used=64 fdpe_functional_category=Flop & Latch fdpe_used=10
fdre_functional_category=Flop & Latch fdre_used=114 fdse_functional_category=Flop & Latch fdse_used=1
ibuf_functional_category=IO ibuf_used=2 ldce_functional_category=Flop & Latch ldce_used=23
lut1_functional_category=LUT lut1_used=12 lut2_functional_category=LUT lut2_used=275
lut3_functional_category=LUT lut3_used=332 lut4_functional_category=LUT lut4_used=365
lut5_functional_category=LUT lut5_used=358 lut6_functional_category=LUT lut6_used=447
mmcme2_adv_functional_category=Clock mmcme2_adv_used=1 muxf7_functional_category=MuxFx muxf7_used=19
muxf8_functional_category=MuxFx muxf8_used=1 obuf_functional_category=IO obuf_used=21
obuft_functional_category=IO obuft_used=1 ramb18e1_functional_category=Block Memory ramb18e1_used=9
ramb36e1_functional_category=Block Memory ramb36e1_used=18
slice_logic
f7_muxes_available=8800 f7_muxes_fixed=0 f7_muxes_used=19 f7_muxes_util_percentage=0.22
f8_muxes_available=4400 f8_muxes_fixed=0 f8_muxes_used=1 f8_muxes_util_percentage=0.02
lut_as_logic_available=17600 lut_as_logic_fixed=0 lut_as_logic_used=1491 lut_as_logic_util_percentage=8.47
lut_as_memory_available=6000 lut_as_memory_fixed=0 lut_as_memory_used=0 lut_as_memory_util_percentage=0.00
register_as_flip_flop_available=35200 register_as_flip_flop_fixed=0 register_as_flip_flop_used=189 register_as_flip_flop_util_percentage=0.54
register_as_latch_available=35200 register_as_latch_fixed=0 register_as_latch_used=23 register_as_latch_util_percentage=0.07
slice_luts_available=17600 slice_luts_fixed=0 slice_luts_used=1491 slice_luts_util_percentage=8.47
slice_registers_available=35200 slice_registers_fixed=0 slice_registers_used=212 slice_registers_util_percentage=0.60
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=0 lut_as_logic_available=17600 lut_as_logic_fixed=0
lut_as_logic_used=1491 lut_as_logic_util_percentage=8.47 lut_as_memory_available=6000 lut_as_memory_fixed=0
lut_as_memory_used=0 lut_as_memory_util_percentage=0.00 lut_as_shift_register_fixed=0 lut_as_shift_register_used=0
lut_in_front_of_the_register_is_unused_fixed=0 lut_in_front_of_the_register_is_unused_used=21 lut_in_front_of_the_register_is_used_fixed=21 lut_in_front_of_the_register_is_used_used=26
register_driven_from_outside_the_slice_fixed=26 register_driven_from_outside_the_slice_used=47 register_driven_from_within_the_slice_fixed=47 register_driven_from_within_the_slice_used=165
slice_available=4400 slice_fixed=0 slice_registers_available=35200 slice_registers_fixed=0
slice_registers_used=212 slice_registers_util_percentage=0.60 slice_used=541 slice_util_percentage=12.30
slicel_fixed=0 slicel_used=361 slicem_fixed=0 slicem_used=180
unique_control_sets_available=4400 unique_control_sets_fixed=4400 unique_control_sets_used=31 unique_control_sets_util_percentage=0.70
using_o5_and_o6_fixed=0.70 using_o5_and_o6_used=298 using_o5_output_only_fixed=298 using_o5_output_only_used=0
using_o6_output_only_fixed=0 using_o6_output_only_used=1193
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=0 bscane2_util_percentage=0.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=0 xadc_used=0 xadc_util_percentage=0.00

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -directive=default::default -fanout_limit=default::10000 -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified] -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] -max_bram=default::-1 -max_bram_cascade_height=default::-1 -max_dsp=default::-1
-max_uram=default::-1 -max_uram_cascade_height=default::-1 -mode=default::default -name=default::[not_specified]
-no_lc=default::[not_specified] -no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified] -part=xc7z010clg400-1
-resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] -seu_protect=default::none -sfcu=default::[not_specified] -shreg_min_size=default::3
-top=VGA_top -verilog_define=default::[not_specified]
usage
elapsed=00:00:46s hls_ip=0 memory_gain=613.590MB memory_peak=976.145MB